Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlxge/qls_hw.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/12.0/sys/dev/qlxge/qls_hw.h 326255 2017-11-27 14:52:40Z pfg $ 30 */ 31 /* 32 * File: qls_hw.h 33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 34 */ 35 #ifndef _QLS_HW_H_ 36 #define _QLS_HW_H_ 37 38 #define Q8_MAX_NUM_MULTICAST_ADDRS 32 39 #define Q8_MAC_ADDR_LEN 6 40 41 #define BIT_0 (0x1 << 0) 42 #define BIT_1 (0x1 << 1) 43 #define BIT_2 (0x1 << 2) 44 #define BIT_3 (0x1 << 3) 45 #define BIT_4 (0x1 << 4) 46 #define BIT_5 (0x1 << 5) 47 #define BIT_6 (0x1 << 6) 48 #define BIT_7 (0x1 << 7) 49 #define BIT_8 (0x1 << 8) 50 #define BIT_9 (0x1 << 9) 51 #define BIT_10 (0x1 << 10) 52 #define BIT_11 (0x1 << 11) 53 #define BIT_12 (0x1 << 12) 54 #define BIT_13 (0x1 << 13) 55 #define BIT_14 (0x1 << 14) 56 #define BIT_15 (0x1 << 15) 57 #define BIT_16 (0x1 << 16) 58 #define BIT_17 (0x1 << 17) 59 #define BIT_18 (0x1 << 18) 60 #define BIT_19 (0x1 << 19) 61 #define BIT_20 (0x1 << 20) 62 #define BIT_21 (0x1 << 21) 63 #define BIT_22 (0x1 << 22) 64 #define BIT_23 (0x1 << 23) 65 #define BIT_24 (0x1 << 24) 66 #define BIT_25 (0x1 << 25) 67 #define BIT_11 (0x1 << 11) 68 #define BIT_12 (0x1 << 12) 69 #define BIT_13 (0x1 << 13) 70 #define BIT_14 (0x1 << 14) 71 #define BIT_15 (0x1 << 15) 72 #define BIT_16 (0x1 << 16) 73 #define BIT_17 (0x1 << 17) 74 #define BIT_18 (0x1 << 18) 75 #define BIT_19 (0x1 << 19) 76 #define BIT_20 (0x1 << 20) 77 #define BIT_21 (0x1 << 21) 78 #define BIT_22 (0x1 << 22) 79 #define BIT_23 (0x1 << 23) 80 #define BIT_24 (0x1 << 24) 81 #define BIT_25 (0x1 << 25) 82 #define BIT_26 (0x1 << 26) 83 #define BIT_27 (0x1 << 27) 84 #define BIT_28 (0x1 << 28) 85 #define BIT_29 (0x1 << 29) 86 #define BIT_30 (0x1 << 30) 87 #define BIT_31 (0x1 << 31) 88 89 90 /* 91 * Firmware Interface 92 */ 93 94 /********************************************************************* 95 * Work Queue Register Map 96 *********************************************************************/ 97 #define Q81_WRKQ_INDEX_REG 0x00 98 #define Q81_WRKQ_CONS_INDEX_MASK 0xFFFF0000 99 #define Q81_WRKQ_PROD_INDEX_MASK 0x0000FFFF 100 #define Q81_WRKQ_VALID_REG 0x04 101 #define Q81_WRKQ_VALID_ONQ BIT_25 102 #define Q81_WRKQ_VALID_V BIT_4 103 104 /********************************************************************* 105 * Completion Queue Register Map 106 *********************************************************************/ 107 #define Q81_COMPQ_INDEX_REG 0x00 108 #define Q81_COMPQ_PROD_INDEX_MASK 0xFFFF0000 109 #define Q81_COMPQ_CONS_INDEX_MASK 0x0000FFFF 110 #define Q81_COMPQ_VALID_REG 0x04 111 #define Q81_COMPQ_VALID_V BIT_4 112 #define Q81_LRGBQ_INDEX_REG 0x18 113 #define Q81_LRGBQ_CONS_INDEX_MASK 0xFFFF0000 114 #define Q81_LRGBQ_PROD_INDEX_MASK 0x0000FFFF 115 #define Q81_SMBQ_INDEX_REG 0x1C 116 #define Q81_SMBQ_CONS_INDEX_MASK 0xFFFF0000 117 #define Q81_SMBQ_PROD_INDEX_MASK 0x0000FFFF 118 119 /********************************************************************* 120 * Control Register Definitions 121 * (Access, Function Specific, Shared via Semaphore, Control by MPI FW) 122 *********************************************************************/ 123 #define Q81_CTL_PROC_ADDR 0x00 /* R/W - Y - */ 124 #define Q81_CTL_PROC_DATA 0x04 /* R/W - Y - */ 125 #define Q81_CTL_SYSTEM 0x08 /* MWR - - - */ 126 #define Q81_CTL_RESET 0x0C /* MWR Y - - */ 127 #define Q81_CTL_FUNC_SPECIFIC 0x10 /* MWR Y - - */ 128 #define Q81_CTL_HOST_CMD_STATUS 0x14 /* R/W Y - - */ 129 #define Q81_CTL_LED 0x18 /* R/W Y - Y */ 130 #define Q81_CTL_ICB_ACCESS_ADDR_LO 0x20 /* R/W - Y - */ 131 #define Q81_CTL_ICB_ACCESS_ADDR_HI 0x24 /* R/W - Y - */ 132 #define Q81_CTL_CONFIG 0x28 /* MWR - - - */ 133 #define Q81_CTL_STATUS 0x30 /* MWR Y - - */ 134 #define Q81_CTL_INTR_ENABLE 0x34 /* MWR Y - - */ 135 #define Q81_CTL_INTR_MASK 0x38 /* MWR Y - - */ 136 #define Q81_CTL_INTR_STATUS1 0x3C /* RO Y - - */ 137 #define Q81_CTL_INTR_STATUS2 0x40 /* RO Y - - */ 138 #define Q81_CTL_INTR_STATUS3 0x44 /* RO Y - - */ 139 #define Q81_CTL_INTR_STATUS4 0x48 /* RO Y - - */ 140 #define Q81_CTL_REV_ID 0x4C /* RO - - - */ 141 #define Q81_CTL_FATAL_ERR_STATUS 0x54 /* RO Y - - */ 142 #define Q81_CTL_COR_ECC_ERR_COUNTER 0x60 /* RO Y - - */ 143 #define Q81_CTL_SEMAPHORE 0x64 /* MWR Y - - */ 144 #define Q81_CTL_GPIO1 0x68 /* MWR Y - - */ 145 #define Q81_CTL_GPIO2 0x6C /* MWR Y - - */ 146 #define Q81_CTL_GPIO3 0x70 /* MWR Y - - */ 147 #define Q81_CTL_XGMAC_ADDR 0x78 /* R/W Y Y - */ 148 #define Q81_CTL_XGMAC_DATA 0x7C /* R/W Y Y Y */ 149 #define Q81_CTL_NIC_ENH_TX_SCHD 0x80 /* R/W Y - Y */ 150 #define Q81_CTL_CNA_ENH_TX_SCHD 0x84 /* R/W Y - Y */ 151 #define Q81_CTL_FLASH_ADDR 0x88 /* R/W - Y - */ 152 #define Q81_CTL_FLASH_DATA 0x8C /* R/W - Y - */ 153 #define Q81_CTL_STOP_CQ_PROCESSING 0x90 /* MWR Y - - */ 154 #define Q81_CTL_MAC_PROTO_ADDR_INDEX 0xA8 /* R/W - Y - */ 155 #define Q81_CTL_MAC_PROTO_ADDR_DATA 0xAC /* R/W - Y - */ 156 #define Q81_CTL_COS_DEF_CQ1 0xB0 /* R/W Y - - */ 157 #define Q81_CTL_COS_DEF_CQ2 0xB4 /* R/W Y - - */ 158 #define Q81_CTL_ETHERTYPE_SKIP_1 0xB8 /* R/W Y - - */ 159 #define Q81_CTL_ETHERTYPE_SKIP_2 0xBC /* R/W Y - - */ 160 #define Q81_CTL_SPLIT_HDR 0xC0 /* R/W Y - - */ 161 #define Q81_CTL_NIC_PAUSE_THRES 0xC8 /* R/W Y - Y */ 162 #define Q81_CTL_NIC_RCV_CONFIG 0xD4 /* MWR Y - Y */ 163 #define Q81_CTL_COS_TAGS_IN_NIC_FIFO 0xDC /* R/W Y - Y */ 164 #define Q81_CTL_MGMT_RCV_CONFIG 0xE0 /* MWR Y - Y */ 165 #define Q81_CTL_ROUTING_INDEX 0xE4 /* R/W Y Y - */ 166 #define Q81_CTL_ROUTING_DATA 0xE8 /* R/W Y Y - */ 167 #define Q81_CTL_XG_SERDES_ADDR 0xF0 /* R/W Y Y Y */ 168 #define Q81_CTL_XG_SERDES_DATA 0xF4 /* R/W Y Y Y */ 169 #define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ 170 #define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ 171 172 173 /* 174 * Process Address Register (0x00) 175 */ 176 #define Q81_CTL_PROC_ADDR_RDY BIT_31 177 #define Q81_CTL_PROC_ADDR_READ BIT_30 178 #define Q81_CTL_PROC_ADDR_ERR BIT_29 179 #define Q81_CTL_PROC_ADDR_MPI_RISC (0x00 << 16) 180 #define Q81_CTL_PROC_ADDR_MDE (0x01 << 16) 181 #define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) 182 #define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) 183 184 185 /* 186 * System Register (0x08) 187 */ 188 #define Q81_CTL_SYSTEM_MASK_SHIFT 16 189 #define Q81_CTL_SYSTEM_ENABLE_VQM_WR BIT_5 190 #define Q81_CTL_SYSTEM_ENABLE_DWC BIT_4 191 #define Q81_CTL_SYSTEM_ENABLE_DA_SINGLE_THRD BIT_3 192 #define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2 193 #define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1 194 #define Q81_CTL_SYSTEM_ENABLE_EFE BIT_0 195 196 /* 197 * Reset Register (0x0C) 198 */ 199 #define Q81_CTL_RESET_MASK_SHIFT 16 200 #define Q81_CTL_RESET_FUNC BIT_15 201 #define Q81_CTL_RESET_RR_SHIFT 1 202 203 /* 204 * Function Specific Control Register (0x10) 205 */ 206 #define Q81_CTL_FUNC_SPECIFIC_MASK_SHIFT 16 207 208 #define Q81_CTL_FUNC_SPECIFIC_FE BIT_15 209 #define Q81_CTL_FUNC_SPECIFIC_STE BIT_13 210 #define Q81_CTL_FUNC_SPECIFIC_DSB BIT_12 211 #define Q81_CTL_FUNC_SPECIFIC_SH BIT_11 212 213 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK (0x7 << 8) 214 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K (0x1 << 8) 215 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K (0x2 << 8) 216 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K (0x3 << 8) 217 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K (0x6 << 8) 218 219 #define Q81_CTL_FUNC_SPECIFIC_EPC_O BIT_7 220 #define Q81_CTL_FUNC_SPECIFIC_EPC_I BIT_6 221 #define Q81_CTL_FUNC_SPECIFIC_EC BIT_5 222 #define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST (0x00 << 3) 223 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ (0x01 << 3) 224 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ (0x02 << 3) 225 #define Q81_CTL_FUNC_SPECIFIC_DBL_128 (0x03 << 3) 226 #define Q81_CTL_FUNC_SPECIFIC_DBRST_256 0x00 227 #define Q81_CTL_FUNC_SPECIFIC_DBRST_512 0x01 228 #define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 229 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 230 231 232 /* 233 * Host Command/Status Register (0x14) 234 */ 235 #define Q81_CTL_HCS_CMD_NOP (0x00 << 28) 236 #define Q81_CTL_HCS_CMD_SET_RISC_RESET (0x01 << 28) 237 #define Q81_CTL_HCS_CMD_CLR_RISC_RESET (0x02 << 28) 238 #define Q81_CTL_HCS_CMD_SET_RISC_PAUSE (0x03 << 28) 239 #define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE (0x04 << 28) 240 #define Q81_CTL_HCS_CMD_SET_HTR_INTR (0x05 << 28) 241 #define Q81_CTL_HCS_CMD_CLR_HTR_INTR (0x06 << 28) 242 #define Q81_CTL_HCS_CMD_SET_PARITY_EN (0x07 << 28) 243 #define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY (0x08 << 28) 244 #define Q81_CTL_HCS_CMD_CLR_BAD_PARITY (0x09 << 28) 245 #define Q81_CTL_HCS_CMD_CLR_RTH_INTR (0x0A << 28) 246 247 #define Q81_CTL_HCS_CMD_PAR_SHIFT 22 248 #define Q81_CTL_HCS_RISC_PAUSED BIT_10 249 #define Q81_CTL_HCS_HTR_INTR BIT_9 250 #define Q81_CTL_HCS_RISC_RESET BIT_8 251 #define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F 252 253 254 /* 255 * Configuration Register (0x28) 256 */ 257 #define Q81_CTL_CONFIG_MASK_SHIFT 16 258 #define Q81_CTL_CONFIG_Q_NUM_SHIFT 8 259 #define Q81_CTL_CONFIG_Q_NUM_MASK (0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT) 260 #define Q81_CTL_CONFIG_DCQ BIT_7 261 #define Q81_CTL_CONFIG_LCQ BIT_6 262 #define Q81_CTL_CONFIG_LE BIT_5 263 #define Q81_CTL_CONFIG_DR BIT_3 264 #define Q81_CTL_CONFIG_LR BIT_2 265 #define Q81_CTL_CONFIG_DRQ BIT_1 266 #define Q81_CTL_CONFIG_LRQ BIT_0 267 268 269 /* 270 * Status Register (0x30) 271 */ 272 #define Q81_CTL_STATUS_MASK_SHIFT 16 273 #define Q81_CTL_STATUS_NFE BIT_12 274 #define Q81_CTL_STATUS_F3E BIT_11 275 #define Q81_CTL_STATUS_F2E BIT_10 276 #define Q81_CTL_STATUS_F1E BIT_9 277 #define Q81_CTL_STATUS_F0E BIT_8 278 #define Q81_CTL_STATUS_FUNC_SHIFT 6 279 #define Q81_CTL_STATUS_PI1 BIT_5 280 #define Q81_CTL_STATUS_PI0 BIT_4 281 #define Q81_CTL_STATUS_PL1 BIT_3 282 #define Q81_CTL_STATUS_PL0 BIT_2 283 #define Q81_CTL_STATUS_PI BIT_1 284 #define Q81_CTL_STATUS_FE BIT_0 285 286 /* 287 * Interrupt Enable Register (0x34) 288 */ 289 #define Q81_CTL_INTRE_MASK_SHIFT 16 290 #define Q81_CTL_INTRE_EN BIT_15 291 #define Q81_CTL_INTRE_EI BIT_14 292 #define Q81_CTL_INTRE_IHD BIT_13 293 #define Q81_CTL_INTRE_RTYPE_MASK (0x3 << 8) 294 #define Q81_CTL_INTRE_RTYPE_ENABLE (0x1 << 8) 295 #define Q81_CTL_INTRE_RTYPE_DISABLE (0x2 << 8) 296 #define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD (0x3 << 8) 297 #define Q81_CTL_INTRE_HOST_INTR_MASK 0x7F 298 299 /* 300 * Interrupt Mask Register (0x38) 301 */ 302 #define Q81_CTL_INTRM_MASK_SHIFT 16 303 #define Q81_CTL_INTRM_MC BIT_7 304 #define Q81_CTL_INTRM_LSC BIT_6 305 #define Q81_CTL_INTRM_LH1 BIT_4 306 #define Q81_CTL_INTRM_HL1 BIT_3 307 #define Q81_CTL_INTRM_LH0 BIT_2 308 #define Q81_CTL_INTRM_HL0 BIT_1 309 #define Q81_CTL_INTRM_PI BIT_0 310 311 /* 312 * Interrupt Status 1 Register (0x3C) 313 */ 314 #define Q81_CTL_INTRS1_COMPQ(i) (0x1 << i) 315 316 /* 317 * Interrupt Status 2 Register (0x40) 318 */ 319 #define Q81_CTL_INTRS2_COMPQ(i) (0x1 << i) 320 321 /* 322 * Interrupt Status 3 Register (0x44) 323 */ 324 #define Q81_CTL_INTRS3_COMPQ(i) (0x1 << i) 325 326 /* 327 * Interrupt Status 4 Register (0x48) 328 */ 329 #define Q81_CTL_INTRS4_COMPQ(i) (0x1 << i) 330 331 /* 332 * Revision ID Register (0x4C) 333 */ 334 #define Q81_CTL_REV_ID_CHIP_REV_MASK (0xF << 28) 335 #define Q81_CTL_REV_ID_XGMAC_RCV_MASK (0xF << 16) 336 #define Q81_CTL_REV_ID_XGMAC_ROLL_MASK (0xF << 8) 337 #define Q81_CTL_REV_ID_NIC_REV_MASK (0xF << 4) 338 #define Q81_CTL_REV_ID_NIC_ROLL_MASK (0xF << 0) 339 340 /* 341 * Semaphore Register (0x64) 342 */ 343 344 #define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV 0xC0000000 345 346 #define Q81_CTL_SEM_MASK_RIDX_DATAREG 0x30000000 347 348 #define Q81_CTL_SEM_MASK_FLASH 0x03000000 349 350 #define Q81_CTL_SEM_MASK_MAC_SERDES 0x00C00000 351 352 #define Q81_CTL_SEM_MASK_ICB 0x00300000 353 354 #define Q81_CTL_SEM_MASK_XGMAC1 0x000C0000 355 356 #define Q81_CTL_SEM_MASK_XGMAC0 0x00030000 357 358 #define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV 0x4000 359 #define Q81_CTL_SEM_SET_RIDX_DATAREG 0x1000 360 #define Q81_CTL_SEM_SET_FLASH 0x0100 361 #define Q81_CTL_SEM_SET_MAC_SERDES 0x0040 362 #define Q81_CTL_SEM_SET_ICB 0x0010 363 #define Q81_CTL_SEM_SET_XGMAC1 0x0004 364 #define Q81_CTL_SEM_SET_XGMAC0 0x0001 365 366 367 /* 368 * Flash Address Register (0x88) 369 */ 370 #define Q81_CTL_FLASH_ADDR_RDY BIT_31 371 #define Q81_CTL_FLASH_ADDR_R BIT_30 372 #define Q81_CTL_FLASH_ADDR_ERR BIT_29 373 #define Q81_CTL_FLASH_ADDR_MASK 0x7FFFFF 374 375 /* 376 * Stop CQ Processing Register (0x90) 377 */ 378 #define Q81_CTL_STOP_CQ_MASK_SHIFT 16 379 #define Q81_CTL_STOP_CQ_EN BIT_15 380 #define Q81_CTL_STOP_CQ_RQ_STARTQ (0x1 << 8) 381 #define Q81_CTL_STOP_CQ_RQ_STOPQ (0x2 << 8) 382 #define Q81_CTL_STOP_CQ_RQ_READ (0x3 << 8) 383 #define Q81_CTL_STOP_CQ_MASK 0x7F 384 385 /* 386 * MAC Protocol Address Index Register (0xA8) 387 */ 388 #define Q81_CTL_MAC_PROTO_AI_MW BIT_31 389 #define Q81_CTL_MAC_PROTO_AI_MR BIT_30 390 #define Q81_CTL_MAC_PROTO_AI_E BIT_27 391 #define Q81_CTL_MAC_PROTO_AI_RS BIT_26 392 #define Q81_CTL_MAC_PROTO_AI_ADR BIT_25 393 #define Q81_CTL_MAC_PROTO_AI_TYPE_SHIFT 16 394 #define Q81_CTL_MAC_PROTO_AI_TYPE_MASK 0xF0000 395 #define Q81_CTL_MAC_PROTO_AI_IDX_SHIFT 4 396 #define Q81_CTL_MAC_PROTO_AI_IDX_MASK 0xFFF0 397 #define Q81_CTL_MAC_PROTO_AI_OFF_MASK 0xF 398 399 #define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC (0 << 16) 400 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST (1 << 16) 401 #define Q81_CTL_MAC_PROTO_AI_TYPE_VLAN (2 << 16) 402 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST_FILTER (3 << 16) 403 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_MAC (5 << 16) 404 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMMT_VLAN (6 << 16) 405 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV4 (7 << 16) 406 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV6 (8 << 16) 407 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_PORT (9 << 16) /* TCP/UDP Port */ 408 409 /* 410 * CAM MAC offset 2 definitions 411 */ 412 #define Q81_CAM_MAC_OFF2_ROUTE_FC 0x00000000 413 #define Q81_CAM_MAC_OFF2_ROUTE_NIC 0x00000001 414 #define Q81_CAM_MAC_OFF2_FUNC_SHIFT 2 415 #define Q81_CAM_MAC_OFF2_RV 0x00000010 416 #define Q81_CAM_MAC_OFF2_CQID_SHIFT 5 417 #define Q81_CAM_MAC_OFF2_SH 0x00008000 418 #define Q81_CAM_MAC_OFF2_MHT 0x40000000 419 #define Q81_CAM_MAC_OFF2_VLD 0x80000000 420 421 /* 422 * NIC Pause Threshold Register (0xC8) 423 */ 424 #define Q81_CTL_NIC_PAUSE_THRES_PAUSE_SHIFT 16 425 #define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT 0 426 427 /* 428 * NIC Receive Configuration Register (0xD4) 429 */ 430 #define Q81_CTL_NIC_RCVC_MASK_SHIFT 16 431 #define Q81_CTL_NIC_RCVC_DCQ_SHIFT 8 432 #define Q81_CTL_NIC_RCVC_DCQ_MASK 0x7F00 433 #define Q81_CTL_NIC_RCVC_DTP BIT_5 434 #define Q81_CTL_NIC_RCVC_R4T BIT_4 435 #define Q81_CTL_NIC_RCVC_RV BIT_3 436 #define Q81_CTL_NIC_RCVC_VLAN_ALL (0x0 << 1) 437 #define Q81_CTL_NIC_RCVC_VLAN_ONLY (0x1 << 1) 438 #define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN (0x2 << 1) 439 #define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) 440 #define Q81_CTL_NIC_RCVC_PPE BIT_0 441 442 443 /* 444 * Routing Index Register (0xE4) 445 */ 446 #define Q81_CTL_RI_MW BIT_31 447 #define Q81_CTL_RI_MR BIT_30 448 #define Q81_CTL_RI_E BIT_27 449 #define Q81_CTL_RI_RS BIT_26 450 451 #define Q81_CTL_RI_DST_RSS (0x00 << 20) 452 #define Q81_CTL_RI_DST_CAMQ (0x01 << 20) 453 #define Q81_CTL_RI_DST_COSQ (0x02 << 20) 454 #define Q81_CTL_RI_DST_DFLTQ (0x03 << 20) 455 #define Q81_CTL_RI_DST_DESTQ (0x04 << 20) 456 #define Q81_CTL_RI_DST_DROP (0x07 << 20) 457 458 #define Q81_CTL_RI_TYPE_RTMASK (0x00 << 16) 459 #define Q81_CTL_RI_TYPE_RTINVMASK (0x01 << 16) 460 #define Q81_CTL_RI_TYPE_NICQMASK (0x02 << 16) 461 #define Q81_CTL_RI_TYPE_NICQINVMASK (0x03 << 16) 462 463 /* these indices for the Routing Index Register are user defined */ 464 #define Q81_CTL_RI_IDX_ALL_ERROR (0x00 << 8) 465 #define Q81_CTL_RI_IDX_MAC_ERROR (0x00 << 8) 466 #define Q81_CTL_RI_IDX_IPCSUM_ERROR (0x01 << 8) 467 #define Q81_CTL_RI_IDX_TCPCSUM_ERROR (0x02 << 8) 468 #define Q81_CTL_RI_IDX_BCAST (0x03 << 8) 469 #define Q81_CTL_RI_IDX_MCAST_MATCH (0x04 << 8) 470 #define Q81_CTL_RI_IDX_ALLMULTI (0x05 << 8) 471 #define Q81_CTL_RI_IDX_RSS_MATCH (0x08 << 8) 472 #define Q81_CTL_RI_IDX_RSS_IPV4 (0x08 << 8) 473 #define Q81_CTL_RI_IDX_RSS_IPV6 (0x09 << 8) 474 #define Q81_CTL_RI_IDX_RSS_TCPV4 (0x0A << 8) 475 #define Q81_CTL_RI_IDX_RSS_TCPV6 (0x0B << 8) 476 #define Q81_CTL_RI_IDX_CAM_HIT (0x0C << 8) 477 #define Q81_CTL_RI_IDX_PROMISCUOUS (0x0F << 8) 478 479 /* Routing Masks to be loaded into Routing Data Register */ 480 #define Q81_CTL_RD_BCAST BIT_0 481 #define Q81_CTL_RD_MCAST BIT_1 482 #define Q81_CTL_RD_MCAST_MATCH BIT_2 483 #define Q81_CTL_RD_MCAST_REG_MATCH BIT_3 484 #define Q81_CTL_RD_MCAST_HASH_MATCH BIT_4 485 #define Q81_CTL_RD_CAM_HIT BIT_7 486 #define Q81_CTL_RD_CAM_BIT0 BIT_8 487 #define Q81_CTL_RD_CAM_BIT1 BIT_9 488 #define Q81_CTL_RD_VLAN_TAG_PRESENT BIT_10 489 #define Q81_CTL_RD_VLAN_MATCH BIT_11 490 #define Q81_CTL_RD_VLAN_FILTER_PASS BIT_12 491 #define Q81_CTL_RD_SKIP_ETHERTYPE_1 BIT_13 492 #define Q81_CTL_RD_SKIP_ETHERTYPE_2 BIT_14 493 #define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15 494 #define Q81_CTL_RD_802_3_PKT BIT_16 495 #define Q81_CTL_RD_LLDP_PKT BIT_17 496 #define Q81_CTL_RD_TUNNELED_PKT BIT_18 497 #define Q81_CTL_RD_ERROR_PKT BIT_22 498 #define Q81_CTL_RD_VALID_PKT BIT_23 499 #define Q81_CTL_RD_TCP_UDP_CSUM_ERR BIT_24 500 #define Q81_CTL_RD_IPCSUM_ERR BIT_25 501 #define Q81_CTL_RD_MAC_ERR BIT_26 502 #define Q81_CTL_RD_RSS_TCP_IPV6 BIT_27 503 #define Q81_CTL_RD_RSS_TCP_IPV4 BIT_28 504 #define Q81_CTL_RD_RSS_IPV6 BIT_29 505 #define Q81_CTL_RD_RSS_IPV4 BIT_30 506 #define Q81_CTL_RD_RSS_MATCH BIT_31 507 508 509 /********************************************************************* 510 * Host Data Structures * 511 *********************************************************************/ 512 513 /* 514 * Work Queue Initialization Control Block 515 */ 516 517 typedef struct _q81_wq_icb { 518 519 uint16_t length_v; 520 #define Q81_WQ_ICB_VALID BIT_4 521 522 uint8_t pri; 523 #define Q81_WQ_ICB_PRI_SHIFT 1 524 525 uint8_t flags; 526 #define Q81_WQ_ICB_FLAGS_LO BIT_7 527 #define Q81_WQ_ICB_FLAGS_LI BIT_6 528 #define Q81_WQ_ICB_FLAGS_LB BIT_5 529 #define Q81_WQ_ICB_FLAGS_LC BIT_4 530 531 uint16_t wqcqid_rss; 532 #define Q81_WQ_ICB_RSS_V BIT_15 533 534 uint16_t rsrvd; 535 536 uint32_t baddr_lo; 537 uint32_t baddr_hi; 538 539 uint32_t ci_addr_lo; 540 uint32_t ci_addr_hi; 541 } __packed q81_wq_icb_t; 542 543 544 /* 545 * Completion Queue Initialization Control Block 546 */ 547 548 typedef struct _q81_cq_icb { 549 uint8_t msix_vector; 550 uint16_t rsrvd0; 551 uint8_t flags; 552 #define Q81_CQ_ICB_FLAGS_LC BIT_7 553 #define Q81_CQ_ICB_FLAGS_LI BIT_6 554 #define Q81_CQ_ICB_FLAGS_LL BIT_5 555 #define Q81_CQ_ICB_FLAGS_LS BIT_4 556 #define Q81_CQ_ICB_FLAGS_LV BIT_3 557 558 uint16_t length_v; 559 #define Q81_CQ_ICB_VALID BIT_4 560 561 uint16_t rsrvd1; 562 563 uint32_t cq_baddr_lo; 564 uint32_t cq_baddr_hi; 565 566 uint32_t cqi_addr_lo; 567 uint32_t cqi_addr_hi; 568 569 uint16_t pkt_idelay; 570 uint16_t idelay; 571 572 uint32_t lbq_baddr_lo; 573 uint32_t lbq_baddr_hi; 574 uint16_t lbq_bsize; 575 uint16_t lbq_length; 576 577 uint32_t sbq_baddr_lo; 578 uint32_t sbq_baddr_hi; 579 uint16_t sbq_bsize; 580 uint16_t sbq_length; 581 } __packed q81_cq_icb_t; 582 583 /* 584 * RSS Initialization Control Block 585 */ 586 typedef struct _q81_rss_icb { 587 uint16_t flags_base_cq_num; 588 #define Q81_RSS_ICB_FLAGS_L4K BIT_7 589 #define Q81_RSS_ICB_FLAGS_L6K BIT_8 590 #define Q81_RSS_ICB_FLAGS_LI BIT_9 591 #define Q81_RSS_ICB_FLAGS_LB BIT_10 592 #define Q81_RSS_ICB_FLAGS_LM BIT_11 593 #define Q81_RSS_ICB_FLAGS_RI4 BIT_12 594 #define Q81_RSS_ICB_FLAGS_RT4 BIT_13 595 #define Q81_RSS_ICB_FLAGS_RI6 BIT_14 596 #define Q81_RSS_ICB_FLAGS_RT6 BIT_15 597 598 uint16_t mask; /* bits 9-0 are valid */ 599 600 #define Q81_RSS_ICB_NUM_INDTBL_ENTRIES 1024 601 /* Indirection Table */ 602 uint8_t cq_id[Q81_RSS_ICB_NUM_INDTBL_ENTRIES]; 603 604 /* Hash Keys */ 605 uint32_t ipv6_rss_hash_key[10]; 606 uint32_t ipv4_rss_hash_key[4]; 607 } __packed q81_rss_icb_t; 608 609 610 611 /* 612 * Transmit Buffer Descriptor 613 */ 614 615 typedef struct _q81_txb_desc { 616 uint64_t baddr; 617 uint16_t length; 618 619 uint16_t flags; 620 #define Q81_TXB_DESC_FLAGS_E BIT_15 621 #define Q81_TXB_DESC_FLAGS_C BIT_14 622 623 } __packed q81_txb_desc_t; 624 625 626 /* 627 * Receive Buffer Descriptor 628 */ 629 630 typedef struct _q81_rxb_desc { 631 uint32_t baddr_lo; 632 #define Q81_RXB_DESC_BADDR_LO_S BIT_1 633 634 uint64_t baddr; 635 636 uint16_t length; 637 638 uint16_t flags; 639 #define Q81_RXB_DESC_FLAGS_E BIT_15 640 #define Q81_RXB_DESC_FLAGS_C BIT_14 641 642 } __packed q81_rxb_desc_t; 643 644 /* 645 * IOCB Types 646 */ 647 648 #define Q81_IOCB_TX_MAC 0x01 649 #define Q81_IOCB_TX_TSO 0x02 650 #define Q81_IOCB_RX 0x20 651 #define Q81_IOCB_MPI 0x21 652 #define Q81_IOCB_SYS 0x3F 653 654 655 /* 656 * IOCB Definitions 657 */ 658 659 /* 660 * MAC Tx Frame IOCB 661 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 662 */ 663 #define MAX_TX_MAC_DESC 8 664 665 typedef struct _q81_tx_mac { 666 667 uint8_t opcode; 668 669 uint16_t flags; 670 #define Q81_TX_MAC_FLAGS_D BIT_3 671 #define Q81_TX_MAC_FLAGS_I BIT_1 672 #define Q81_TX_MAC_FLAGS_OI BIT_0 673 674 uint8_t vlan_off; 675 #define Q81_TX_MAC_VLAN_OFF_SHIFT 3 676 #define Q81_TX_MAC_VLAN_OFF_V BIT_2 677 #define Q81_TX_MAC_VLAN_OFF_DFP BIT_1 678 679 uint32_t rsrvd1; 680 uint32_t rsrvd2; 681 682 uint16_t frame_length; /* only bits0-13 are valid */ 683 uint16_t rsrvd3; 684 685 uint32_t tid_lo; 686 uint32_t tid_hi; 687 688 uint32_t rsrvd4; 689 690 uint16_t vlan_tci; 691 uint16_t rsrvd5; 692 693 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 694 } __packed q81_tx_mac_t; 695 696 697 /* 698 * MAC Tx Frame with TSO IOCB 699 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 700 */ 701 typedef struct _q81_tx_tso { 702 uint8_t opcode; 703 704 uint16_t flags; 705 #define Q81_TX_TSO_FLAGS_OI BIT_0 706 #define Q81_TX_TSO_FLAGS_I BIT_1 707 #define Q81_TX_TSO_FLAGS_D BIT_3 708 #define Q81_TX_TSO_FLAGS_IPV4 BIT_6 709 #define Q81_TX_TSO_FLAGS_IPV6 BIT_7 710 #define Q81_TX_TSO_FLAGS_LSO BIT_13 711 #define Q81_TX_TSO_FLAGS_UC BIT_14 712 #define Q81_TX_TSO_FLAGS_TC BIT_15 713 714 uint8_t vlan_off; 715 #define Q81_TX_TSO_VLAN_OFF_SHIFT 3 716 #define Q81_TX_TSO_VLAN_OFF_V BIT_2 717 #define Q81_TX_TSO_VLAN_OFF_DFP BIT_1 718 #define Q81_TX_TSO_VLAN_OFF_IC BIT_0 719 720 uint32_t rsrvd1; 721 uint32_t rsrvd2; 722 723 uint32_t length; 724 uint32_t tid_lo; 725 uint32_t tid_hi; 726 727 uint16_t phdr_length; 728 729 uint16_t phdr_offsets; 730 #define Q81_TX_TSO_PHDR_SHIFT 6 731 732 uint16_t vlan_tci; 733 uint16_t mss; 734 735 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 736 } __packed q81_tx_tso_t; 737 738 typedef struct _q81_tx_cmd { 739 uint8_t bytes[128]; 740 } __packed q81_tx_cmd_t; 741 742 /* 743 * MAC TX Frame Completion 744 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 745 */ 746 747 typedef struct _q81_tx_mac_comp { 748 uint8_t opcode; 749 750 uint8_t flags; 751 #define Q81_TX_MAC_COMP_FLAGS_OI BIT_0 752 #define Q81_TX_MAC_COMP_FLAGS_I BIT_1 753 #define Q81_TX_MAC_COMP_FLAGS_E BIT_3 754 #define Q81_TX_MAC_COMP_FLAGS_S BIT_4 755 #define Q81_TX_MAC_COMP_FLAGS_L BIT_5 756 #define Q81_TX_MAC_COMP_FLAGS_P BIT_6 757 758 uint8_t rsrvd0; 759 760 uint8_t err; 761 #define Q81_TX_MAC_COMP_ERR_B BIT_7 762 763 uint32_t tid_lo; 764 uint32_t tid_hi; 765 766 uint32_t rsrvd1[13]; 767 } __packed q81_tx_mac_comp_t; 768 769 770 /* 771 * MAC TX Frame with LSO Completion 772 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 773 */ 774 775 typedef struct _q81_tx_tso_comp { 776 uint8_t opcode; 777 778 uint8_t flags; 779 #define Q81_TX_TSO_COMP_FLAGS_OI BIT_0 780 #define Q81_TX_TSO_COMP_FLAGS_I BIT_1 781 #define Q81_TX_TSO_COMP_FLAGS_E BIT_3 782 #define Q81_TX_TSO_COMP_FLAGS_S BIT_4 783 #define Q81_TX_TSO_COMP_FLAGS_P BIT_6 784 785 uint8_t rsrvd0; 786 787 uint8_t err; 788 #define Q81_TX_TSO_COMP_ERR_B BIT_7 789 790 uint32_t tid_lo; 791 uint32_t tid_hi; 792 793 uint32_t rsrvd1[13]; 794 } __packed q81_tx_tso_comp_t; 795 796 797 /* 798 * SYS - Chip Event Notification Completion 799 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 800 */ 801 802 typedef struct _q81_sys_comp { 803 uint8_t opcode; 804 805 uint8_t flags; 806 #define Q81_SYS_COMP_FLAGS_OI BIT_0 807 #define Q81_SYS_COMP_FLAGS_I BIT_1 808 809 uint8_t etype; 810 #define Q81_SYS_COMPE_LINK_UP 0x00 811 #define Q81_SYS_COMPE_LINK_DOWN 0x01 812 #define Q81_SYS_COMPE_MULTI_CAM_LOOKUP 0x06 813 #define Q81_SYS_COMPE_SOFT_ECC 0x07 814 #define Q81_SYS_COMPE_MPI_FATAL_ERROR 0x08 815 #define Q81_SYS_COMPE_MAC_INTR 0x09 816 #define Q81_SYS_COMPE_GPI0_HTOL 0x10 817 #define Q81_SYS_COMPE_GPI0_LTOH 0x20 818 #define Q81_SYS_COMPE_GPI1_HTOL 0x11 819 #define Q81_SYS_COMPE_GPI1_LTOH 0x21 820 821 uint8_t q_id; /* only bits 0-6 are valid */ 822 823 uint32_t rsrvd1[15]; 824 } __packed q81_sys_comp_t; 825 826 827 828 /* 829 * Mac Rx Packet Completion 830 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 831 */ 832 833 typedef struct _q81_rx { 834 uint8_t opcode; 835 836 uint8_t flags0; 837 #define Q81_RX_FLAGS0_OI BIT_0 838 #define Q81_RX_FLAGS0_I BIT_1 839 #define Q81_RX_FLAGS0_TE BIT_2 840 #define Q81_RX_FLAGS0_NU BIT_3 841 #define Q81_RX_FLAGS0_IE BIT_4 842 843 #define Q81_RX_FLAGS0_MCAST_MASK (0x03 << 5) 844 #define Q81_RX_FLAGS0_MCAST_NONE (0x00 << 5) 845 #define Q81_RX_FLAGS0_MCAST_HASH_MATCH (0x01 << 5) 846 #define Q81_RX_FLAGS0_MCAST_REG_MATCH (0x02 << 5) 847 #define Q81_RX_FLAGS0_MCAST_PROMISC (0x03 << 5) 848 849 #define Q81_RX_FLAGS0_B BIT_7 850 851 uint16_t flags1; 852 #define Q81_RX_FLAGS1_P BIT_0 853 #define Q81_RX_FLAGS1_V BIT_1 854 855 #define Q81_RX_FLAGS1_ERR_NONE (0x00 << 2) 856 #define Q81_RX_FLAGS1_ERR_CODE (0x01 << 2) 857 #define Q81_RX_FLAGS1_ERR_OSIZE (0x02 << 2) 858 #define Q81_RX_FLAGS1_ERR_USIZE (0x04 << 2) 859 #define Q81_RX_FLAGS1_ERR_PREAMBLE (0x05 << 2) 860 #define Q81_RX_FLAGS1_ERR_FRAMELENGTH (0x06 << 2) 861 #define Q81_RX_FLAGS1_ERR_CRC (0x07 << 2) 862 #define Q81_RX_FLAGS1_ERR_MASK (0x07 << 2) 863 864 #define Q81_RX_FLAGS1_U BIT_5 865 #define Q81_RX_FLAGS1_T BIT_6 866 #define Q81_RX_FLAGS1_FO BIT_7 867 #define Q81_RX_FLAGS1_RSS_NO_MATCH (0x00 << 8) 868 #define Q81_RX_FLAGS1_RSS_IPV4_MATCH (0x04 << 8) 869 #define Q81_RX_FLAGS1_RSS_IPV6_MATCH (0x02 << 8) 870 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 871 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 872 #define Q81_RX_FLAGS1_RSS_MATCH_MASK (0x07 << 8) 873 #define Q81_RX_FLAGS1_V4 BIT_11 874 #define Q81_RX_FLAGS1_V6 BIT_12 875 #define Q81_RX_FLAGS1_IH BIT_13 876 #define Q81_RX_FLAGS1_DS BIT_14 877 #define Q81_RX_FLAGS1_DL BIT_15 878 879 uint32_t length; 880 uint64_t b_paddr; 881 882 uint32_t rss; 883 uint16_t vlan_tag; 884 uint16_t rsrvd; 885 uint32_t rsrvd1; 886 uint32_t flags2; 887 #define Q81_RX_FLAGS2_HV BIT_13 888 #define Q81_RX_FLAGS2_HS BIT_14 889 #define Q81_RX_FLAGS2_HL BIT_15 890 891 uint32_t hdr_length; 892 uint32_t hdr_baddr_lo; 893 uint32_t hdr_baddr_hi; 894 895 } __packed q81_rx_t; 896 897 typedef struct _q81_cq_e { 898 uint8_t opcode; 899 uint8_t bytes[63]; 900 } __packed q81_cq_e_t; 901 902 typedef struct _q81_bq_addr_e { 903 uint32_t addr_lo; 904 uint32_t addr_hi; 905 } __packed q81_bq_addr_e_t; 906 907 908 /* 909 * Macros for reading and writing registers 910 */ 911 912 #if defined(__i386__) || defined(__amd64__) 913 #define Q8_MB() __asm volatile("mfence" ::: "memory") 914 #define Q8_WMB() __asm volatile("sfence" ::: "memory") 915 #define Q8_RMB() __asm volatile("lfence" ::: "memory") 916 #else 917 #define Q8_MB() 918 #define Q8_WMB() 919 #define Q8_RMB() 920 #endif 921 922 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 923 #define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg) 924 925 #define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 926 927 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 928 929 #define Q81_CTL_INTRE_MASK_VALUE \ 930 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 931 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_ENABLE) 932 933 #define Q81_ENABLE_INTR(ha, idx) \ 934 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 935 936 #define Q81_CTL_INTRD_MASK_VALUE \ 937 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 938 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_DISABLE) 939 940 #define Q81_DISABLE_INTR(ha, idx) \ 941 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx)) 942 943 #define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\ 944 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG), idx) 945 946 #define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ 947 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) 948 949 950 #define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ 951 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 952 Q81_COMPQ_VALID_V) 953 954 #define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\ 955 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 956 (~Q81_COMPQ_VALID_V)) 957 958 #define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 959 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG), idx) 960 961 #define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 962 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG)) 963 964 #define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\ 965 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 966 Q81_COMPQ_VALID_V) 967 968 #define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\ 969 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 970 ~Q81_COMPQ_VALID_V) 971 972 #define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 973 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG), idx) 974 975 #define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 976 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG)) 977 978 #define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 979 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG), idx) 980 981 #define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 982 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) 983 984 985 /* 986 * Flash Related 987 */ 988 989 #define Q81_F0_FLASH_OFFSET 0x140200 990 #define Q81_F1_FLASH_OFFSET 0x140600 991 #define Q81_FLASH_ID "8000" 992 993 typedef struct _q81_flash { 994 995 uint8_t id[4]; /* equal to "8000" */ 996 997 uint16_t version; 998 uint16_t size; 999 uint16_t csum; 1000 uint16_t rsrvd0; 1001 uint16_t total_size; 1002 uint16_t nentries; 1003 1004 uint8_t dtype0; 1005 uint8_t dsize0; 1006 uint8_t mac_addr0[6]; 1007 1008 uint8_t dtype1; 1009 uint8_t dsize1; 1010 uint8_t mac_addr1[6]; 1011 1012 uint8_t dtype2; 1013 uint8_t dsize2; 1014 uint16_t vlan_id; 1015 1016 uint8_t dtype3; 1017 uint8_t dsize3; 1018 uint16_t last; 1019 1020 uint8_t rsrvd1[464]; 1021 1022 uint16_t subsys_vid; 1023 uint16_t subsys_did; 1024 1025 uint8_t rsrvd2[4]; 1026 } __packed q81_flash_t; 1027 1028 1029 /* 1030 * MPI Related 1031 */ 1032 1033 #define Q81_NUM_MBX_REGISTERS 16 1034 #define Q81_NUM_AEN_REGISTERS 9 1035 1036 #define Q81_FUNC0_MBX_IN_REG0 0x1180 1037 #define Q81_FUNC0_MBX_OUT_REG0 0x1190 1038 1039 #define Q81_FUNC1_MBX_IN_REG0 0x1280 1040 #define Q81_FUNC1_MBX_OUT_REG0 0x1290 1041 1042 #define Q81_MBX_NOP 0x0000 1043 #define Q81_MBX_EXEC_FW 0x0002 1044 #define Q81_MBX_REG_TEST 0x0006 1045 #define Q81_MBX_VERIFY_CHKSUM 0x0007 1046 #define Q81_MBX_ABOUT_FW 0x0008 1047 #define Q81_MBX_RISC_MEMCPY 0x000A 1048 #define Q81_MBX_LOAD_RISC_RAM 0x000B 1049 #define Q81_MBX_DUMP_RISC_RAM 0x000C 1050 #define Q81_MBX_WR_RAM_WORD 0x000D 1051 #define Q81_MBX_INIT_RISC_RAM 0x000E 1052 #define Q81_MBX_RD_RAM_WORD 0x000F 1053 #define Q81_MBX_STOP_FW 0x0014 1054 #define Q81_MBX_GEN_SYS_ERR 0x002A 1055 #define Q81_MBX_WR_SFP_PLUS 0x0030 1056 #define Q81_MBX_RD_SFP_PLUS 0x0031 1057 #define Q81_MBX_INIT_FW 0x0060 1058 #define Q81_MBX_GET_IFCB 0x0061 1059 #define Q81_MBX_GET_FW_STATE 0x0069 1060 #define Q81_MBX_IDC_REQ 0x0100 1061 #define Q81_MBX_IDC_ACK 0x0101 1062 #define Q81_MBX_IDC_TIME_EXTEND 0x0102 1063 #define Q81_MBX_WOL_MODE 0x0110 1064 #define Q81_MBX_SET_WOL_FILTER 0x0111 1065 #define Q81_MBX_CLR_WOL_FILTER 0x0112 1066 #define Q81_MBX_SET_WOL_MAGIC 0x0113 1067 #define Q81_MBX_WOL_MODE_IMM 0x0115 1068 #define Q81_MBX_PORT_RESET 0x0120 1069 #define Q81_MBX_SET_PORT_CFG 0x0122 1070 #define Q81_MBX_GET_PORT_CFG 0x0123 1071 #define Q81_MBX_GET_LNK_STATUS 0x0124 1072 #define Q81_MBX_SET_LED_CFG 0x0125 1073 #define Q81_MBX_GET_LED_CFG 0x0126 1074 #define Q81_MBX_SET_DCBX_CTLB 0x0130 1075 #define Q81_MBX_GET_DCBX_CTLB 0x0131 1076 #define Q81_MBX_GET_DCBX_TLV 0x0132 1077 #define Q81_MBX_DIAG_CMDS 0x0150 1078 #define Q81_MBX_SET_MGMT_CTL 0x0160 1079 #define Q81_MBX_SET_MGMT_CTL_STOP 0x01 1080 #define Q81_MBX_SET_MGMT_CTL_RESUME 0x02 1081 #define Q81_MBX_GET_MGMT_CTL 0x0161 1082 #define Q81_MBX_GET_MGMT_CTL_MASK ~0x3 1083 #define Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY 0x02 1084 #define Q81_MBX_GET_MGMT_CTL_SET_MGMT 0x01 1085 1086 #define Q81_MBX_CMD_COMPLETE 0x4000 1087 #define Q81_MBX_CMD_INVALID 0x4001 1088 #define Q81_MBX_CMD_TEST_FAILED 0x4003 1089 #define Q81_MBX_CMD_ERROR 0x4005 1090 #define Q81_MBX_CMD_PARAM_ERROR 0x4006 1091 1092 #endif /* #ifndef _QLS_HW_H_ */
Cache object: aad6f326acbc28d7b447e1a53ec983a3
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