The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/qlxge/qls_hw.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2014 Qlogic Corporation
    5  * All rights reserved.
    6  *
    7  *  Redistribution and use in source and binary forms, with or without
    8  *  modification, are permitted provided that the following conditions
    9  *  are met:
   10  *
   11  *  1. Redistributions of source code must retain the above copyright
   12  *     notice, this list of conditions and the following disclaimer.
   13  *  2. Redistributions in binary form must reproduce the above copyright
   14  *     notice, this list of conditions and the following disclaimer in the
   15  *     documentation and/or other materials provided with the distribution.
   16  *
   17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   27  *  POSSIBILITY OF SUCH DAMAGE.
   28  *
   29  * $FreeBSD$
   30  */
   31 /*
   32  * File: qls_hw.h
   33  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
   34  */
   35 #ifndef _QLS_HW_H_
   36 #define _QLS_HW_H_
   37 
   38 #define Q8_MAX_NUM_MULTICAST_ADDRS      32
   39 #define Q8_MAC_ADDR_LEN                 6
   40 
   41 #define BIT_0                   (0x1 << 0)
   42 #define BIT_1                   (0x1 << 1)
   43 #define BIT_2                   (0x1 << 2)
   44 #define BIT_3                   (0x1 << 3)
   45 #define BIT_4                   (0x1 << 4)
   46 #define BIT_5                   (0x1 << 5)
   47 #define BIT_6                   (0x1 << 6)
   48 #define BIT_7                   (0x1 << 7)
   49 #define BIT_8                   (0x1 << 8)
   50 #define BIT_9                   (0x1 << 9)
   51 #define BIT_10                  (0x1 << 10)
   52 #define BIT_11                  (0x1 << 11)
   53 #define BIT_12                  (0x1 << 12)
   54 #define BIT_13                  (0x1 << 13)
   55 #define BIT_14                  (0x1 << 14)
   56 #define BIT_15                  (0x1 << 15)
   57 #define BIT_16                  (0x1 << 16)
   58 #define BIT_17                  (0x1 << 17)
   59 #define BIT_18                  (0x1 << 18)
   60 #define BIT_19                  (0x1 << 19)
   61 #define BIT_20                  (0x1 << 20)
   62 #define BIT_21                  (0x1 << 21)
   63 #define BIT_22                  (0x1 << 22)
   64 #define BIT_23                  (0x1 << 23)
   65 #define BIT_24                  (0x1 << 24)
   66 #define BIT_25                  (0x1 << 25)
   67 #define BIT_11                  (0x1 << 11)
   68 #define BIT_12                  (0x1 << 12)
   69 #define BIT_13                  (0x1 << 13)
   70 #define BIT_14                  (0x1 << 14)
   71 #define BIT_15                  (0x1 << 15)
   72 #define BIT_16                  (0x1 << 16)
   73 #define BIT_17                  (0x1 << 17)
   74 #define BIT_18                  (0x1 << 18)
   75 #define BIT_19                  (0x1 << 19)
   76 #define BIT_20                  (0x1 << 20)
   77 #define BIT_21                  (0x1 << 21)
   78 #define BIT_22                  (0x1 << 22)
   79 #define BIT_23                  (0x1 << 23)
   80 #define BIT_24                  (0x1 << 24)
   81 #define BIT_25                  (0x1 << 25)
   82 #define BIT_26                  (0x1 << 26)
   83 #define BIT_27                  (0x1 << 27)
   84 #define BIT_28                  (0x1 << 28)
   85 #define BIT_29                  (0x1 << 29)
   86 #define BIT_30                  (0x1 << 30)
   87 #define BIT_31                  (0x1 << 31)
   88 
   89 /*
   90  * Firmware Interface
   91  */
   92 
   93 /*********************************************************************
   94  * Work Queue Register Map
   95  *********************************************************************/
   96 #define Q81_WRKQ_INDEX_REG                      0x00
   97 #define         Q81_WRKQ_CONS_INDEX_MASK        0xFFFF0000
   98 #define         Q81_WRKQ_PROD_INDEX_MASK        0x0000FFFF
   99 #define Q81_WRKQ_VALID_REG                      0x04
  100 #define         Q81_WRKQ_VALID_ONQ              BIT_25
  101 #define         Q81_WRKQ_VALID_V                BIT_4
  102 
  103 /*********************************************************************
  104  * Completion Queue Register Map
  105  *********************************************************************/
  106 #define Q81_COMPQ_INDEX_REG                     0x00
  107 #define         Q81_COMPQ_PROD_INDEX_MASK       0xFFFF0000
  108 #define         Q81_COMPQ_CONS_INDEX_MASK       0x0000FFFF
  109 #define Q81_COMPQ_VALID_REG                     0x04
  110 #define         Q81_COMPQ_VALID_V               BIT_4
  111 #define Q81_LRGBQ_INDEX_REG                     0x18
  112 #define         Q81_LRGBQ_CONS_INDEX_MASK       0xFFFF0000
  113 #define         Q81_LRGBQ_PROD_INDEX_MASK       0x0000FFFF
  114 #define Q81_SMBQ_INDEX_REG                      0x1C
  115 #define         Q81_SMBQ_CONS_INDEX_MASK        0xFFFF0000
  116 #define         Q81_SMBQ_PROD_INDEX_MASK        0x0000FFFF
  117 
  118 /*********************************************************************
  119  * Control Register Definitions
  120  * (Access, Function Specific, Shared via Semaphore, Control by MPI FW)
  121  *********************************************************************/
  122 #define Q81_CTL_PROC_ADDR               0x00 /* R/W  - Y - */
  123 #define Q81_CTL_PROC_DATA               0x04 /* R/W  - Y - */
  124 #define Q81_CTL_SYSTEM                  0x08 /* MWR  - - - */
  125 #define Q81_CTL_RESET                   0x0C /* MWR  Y - - */
  126 #define Q81_CTL_FUNC_SPECIFIC           0x10 /* MWR  Y - - */
  127 #define Q81_CTL_HOST_CMD_STATUS         0x14 /* R/W  Y - - */
  128 #define Q81_CTL_LED                     0x18 /* R/W  Y - Y */
  129 #define Q81_CTL_ICB_ACCESS_ADDR_LO      0x20 /* R/W  - Y - */
  130 #define Q81_CTL_ICB_ACCESS_ADDR_HI      0x24 /* R/W  - Y - */
  131 #define Q81_CTL_CONFIG                  0x28 /* MWR  - - - */
  132 #define Q81_CTL_STATUS                  0x30 /* MWR  Y - - */
  133 #define Q81_CTL_INTR_ENABLE             0x34 /* MWR  Y - - */
  134 #define Q81_CTL_INTR_MASK               0x38 /* MWR  Y - - */
  135 #define Q81_CTL_INTR_STATUS1            0x3C /* RO   Y - - */
  136 #define Q81_CTL_INTR_STATUS2            0x40 /* RO   Y - - */
  137 #define Q81_CTL_INTR_STATUS3            0x44 /* RO   Y - - */
  138 #define Q81_CTL_INTR_STATUS4            0x48 /* RO   Y - - */
  139 #define Q81_CTL_REV_ID                  0x4C /* RO   - - - */
  140 #define Q81_CTL_FATAL_ERR_STATUS        0x54 /* RO   Y - - */
  141 #define Q81_CTL_COR_ECC_ERR_COUNTER     0x60 /* RO   Y - - */
  142 #define Q81_CTL_SEMAPHORE               0x64 /* MWR  Y - - */
  143 #define Q81_CTL_GPIO1                   0x68 /* MWR  Y - - */
  144 #define Q81_CTL_GPIO2                   0x6C /* MWR  Y - - */
  145 #define Q81_CTL_GPIO3                   0x70 /* MWR  Y - - */
  146 #define Q81_CTL_XGMAC_ADDR              0x78 /* R/W  Y Y - */
  147 #define Q81_CTL_XGMAC_DATA              0x7C /* R/W  Y Y Y */
  148 #define Q81_CTL_NIC_ENH_TX_SCHD         0x80 /* R/W  Y - Y */
  149 #define Q81_CTL_CNA_ENH_TX_SCHD         0x84 /* R/W  Y - Y */
  150 #define Q81_CTL_FLASH_ADDR              0x88 /* R/W  - Y - */
  151 #define Q81_CTL_FLASH_DATA              0x8C /* R/W  - Y - */
  152 #define Q81_CTL_STOP_CQ_PROCESSING      0x90 /* MWR  Y - - */
  153 #define Q81_CTL_MAC_PROTO_ADDR_INDEX    0xA8 /* R/W  - Y - */
  154 #define Q81_CTL_MAC_PROTO_ADDR_DATA     0xAC /* R/W  - Y - */
  155 #define Q81_CTL_COS_DEF_CQ1             0xB0 /* R/W  Y - - */
  156 #define Q81_CTL_COS_DEF_CQ2             0xB4 /* R/W  Y - - */
  157 #define Q81_CTL_ETHERTYPE_SKIP_1        0xB8 /* R/W  Y - - */
  158 #define Q81_CTL_ETHERTYPE_SKIP_2        0xBC /* R/W  Y - - */
  159 #define Q81_CTL_SPLIT_HDR               0xC0 /* R/W  Y - - */
  160 #define Q81_CTL_NIC_PAUSE_THRES         0xC8 /* R/W  Y - Y */
  161 #define Q81_CTL_NIC_RCV_CONFIG          0xD4 /* MWR  Y - Y */
  162 #define Q81_CTL_COS_TAGS_IN_NIC_FIFO    0xDC /* R/W  Y - Y */
  163 #define Q81_CTL_MGMT_RCV_CONFIG         0xE0 /* MWR  Y - Y */
  164 #define Q81_CTL_ROUTING_INDEX           0xE4 /* R/W  Y Y - */
  165 #define Q81_CTL_ROUTING_DATA            0xE8 /* R/W  Y Y - */
  166 #define Q81_CTL_XG_SERDES_ADDR          0xF0 /* R/W  Y Y Y */
  167 #define Q81_CTL_XG_SERDES_DATA          0xF4 /* R/W  Y Y Y */
  168 #define Q81_CTL_XG_PROBE_MUX_ADDR       0xF8 /* R/W  - Y - */
  169 #define Q81_CTL_XG_PROBE_MUX_DATA       0xFC /* R/W  - Y - */
  170 
  171 /*
  172  * Process Address Register (0x00)
  173  */
  174 #define Q81_CTL_PROC_ADDR_RDY           BIT_31
  175 #define Q81_CTL_PROC_ADDR_READ          BIT_30
  176 #define Q81_CTL_PROC_ADDR_ERR           BIT_29
  177 #define Q81_CTL_PROC_ADDR_MPI_RISC      (0x00 << 16)
  178 #define Q81_CTL_PROC_ADDR_MDE           (0x01 << 16)
  179 #define Q81_CTL_PROC_ADDR_REG_BLOCK     (0x02 << 16)
  180 #define Q81_CTL_PROC_ADDR_RISC_INT_REG  (0x03 << 16)
  181 
  182 /*
  183  * System Register (0x08)
  184  */
  185 #define Q81_CTL_SYSTEM_MASK_SHIFT               16
  186 #define Q81_CTL_SYSTEM_ENABLE_VQM_WR            BIT_5
  187 #define Q81_CTL_SYSTEM_ENABLE_DWC               BIT_4
  188 #define Q81_CTL_SYSTEM_ENABLE_DA_SINGLE_THRD    BIT_3
  189 #define Q81_CTL_SYSTEM_ENABLE_MDC               BIT_2
  190 #define Q81_CTL_SYSTEM_ENABLE_FAE               BIT_1
  191 #define Q81_CTL_SYSTEM_ENABLE_EFE               BIT_0
  192 
  193 /*
  194  * Reset Register (0x0C)
  195  */
  196 #define Q81_CTL_RESET_MASK_SHIFT                16
  197 #define Q81_CTL_RESET_FUNC                      BIT_15
  198 #define Q81_CTL_RESET_RR_SHIFT                  1
  199 
  200 /*
  201  * Function Specific Control Register (0x10)
  202  */
  203 #define Q81_CTL_FUNC_SPECIFIC_MASK_SHIFT        16
  204 
  205 #define Q81_CTL_FUNC_SPECIFIC_FE                BIT_15                  
  206 #define Q81_CTL_FUNC_SPECIFIC_STE               BIT_13                  
  207 #define Q81_CTL_FUNC_SPECIFIC_DSB               BIT_12                  
  208 #define Q81_CTL_FUNC_SPECIFIC_SH                BIT_11                  
  209 
  210 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK    (0x7 << 8)
  211 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K      (0x1 << 8)
  212 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K      (0x2 << 8)
  213 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K      (0x3 << 8)
  214 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K     (0x6 << 8)
  215 
  216 #define Q81_CTL_FUNC_SPECIFIC_EPC_O             BIT_7                   
  217 #define Q81_CTL_FUNC_SPECIFIC_EPC_I             BIT_6
  218 #define Q81_CTL_FUNC_SPECIFIC_EC                BIT_5
  219 #define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST         (0x00 << 3)
  220 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ   (0x01 << 3)
  221 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ  (0x02 << 3)
  222 #define Q81_CTL_FUNC_SPECIFIC_DBL_128           (0x03 << 3)
  223 #define Q81_CTL_FUNC_SPECIFIC_DBRST_256         0x00                    
  224 #define Q81_CTL_FUNC_SPECIFIC_DBRST_512         0x01                    
  225 #define Q81_CTL_FUNC_SPECIFIC_DBRST_768         0x02                    
  226 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024        0x03                    
  227 
  228 /*
  229  * Host Command/Status Register (0x14)
  230  */
  231 #define Q81_CTL_HCS_CMD_NOP                     (0x00 << 28)
  232 #define Q81_CTL_HCS_CMD_SET_RISC_RESET          (0x01 << 28)
  233 #define Q81_CTL_HCS_CMD_CLR_RISC_RESET          (0x02 << 28)
  234 #define Q81_CTL_HCS_CMD_SET_RISC_PAUSE          (0x03 << 28)
  235 #define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE          (0x04 << 28)
  236 #define Q81_CTL_HCS_CMD_SET_HTR_INTR            (0x05 << 28)
  237 #define Q81_CTL_HCS_CMD_CLR_HTR_INTR            (0x06 << 28)
  238 #define Q81_CTL_HCS_CMD_SET_PARITY_EN           (0x07 << 28)
  239 #define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY        (0x08 << 28)
  240 #define Q81_CTL_HCS_CMD_CLR_BAD_PARITY          (0x09 << 28)
  241 #define Q81_CTL_HCS_CMD_CLR_RTH_INTR            (0x0A << 28)
  242 
  243 #define Q81_CTL_HCS_CMD_PAR_SHIFT               22
  244 #define Q81_CTL_HCS_RISC_PAUSED                 BIT_10
  245 #define Q81_CTL_HCS_HTR_INTR                    BIT_9
  246 #define Q81_CTL_HCS_RISC_RESET                  BIT_8
  247 #define Q81_CTL_HCS_ERR_STATUS_MASK             0x3F
  248 
  249 /*
  250  * Configuration Register (0x28)
  251  */
  252 #define Q81_CTL_CONFIG_MASK_SHIFT               16
  253 #define Q81_CTL_CONFIG_Q_NUM_SHIFT              8
  254 #define Q81_CTL_CONFIG_Q_NUM_MASK       (0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT)
  255 #define Q81_CTL_CONFIG_DCQ                      BIT_7
  256 #define Q81_CTL_CONFIG_LCQ                      BIT_6
  257 #define Q81_CTL_CONFIG_LE                       BIT_5
  258 #define Q81_CTL_CONFIG_DR                       BIT_3
  259 #define Q81_CTL_CONFIG_LR                       BIT_2
  260 #define Q81_CTL_CONFIG_DRQ                      BIT_1
  261 #define Q81_CTL_CONFIG_LRQ                      BIT_0
  262 
  263 /*
  264  * Status Register (0x30)
  265  */
  266 #define Q81_CTL_STATUS_MASK_SHIFT               16
  267 #define Q81_CTL_STATUS_NFE                      BIT_12
  268 #define Q81_CTL_STATUS_F3E                      BIT_11
  269 #define Q81_CTL_STATUS_F2E                      BIT_10
  270 #define Q81_CTL_STATUS_F1E                      BIT_9
  271 #define Q81_CTL_STATUS_F0E                      BIT_8
  272 #define Q81_CTL_STATUS_FUNC_SHIFT               6
  273 #define Q81_CTL_STATUS_PI1                      BIT_5
  274 #define Q81_CTL_STATUS_PI0                      BIT_4
  275 #define Q81_CTL_STATUS_PL1                      BIT_3
  276 #define Q81_CTL_STATUS_PL0                      BIT_2
  277 #define Q81_CTL_STATUS_PI                       BIT_1
  278 #define Q81_CTL_STATUS_FE                       BIT_0
  279 
  280 /*
  281  * Interrupt Enable Register (0x34)
  282  */
  283 #define Q81_CTL_INTRE_MASK_SHIFT                16
  284 #define Q81_CTL_INTRE_EN                        BIT_15
  285 #define Q81_CTL_INTRE_EI                        BIT_14
  286 #define Q81_CTL_INTRE_IHD                       BIT_13
  287 #define Q81_CTL_INTRE_RTYPE_MASK                (0x3 << 8)
  288 #define Q81_CTL_INTRE_RTYPE_ENABLE              (0x1 << 8)
  289 #define Q81_CTL_INTRE_RTYPE_DISABLE             (0x2 << 8)
  290 #define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD         (0x3 << 8)
  291 #define Q81_CTL_INTRE_HOST_INTR_MASK            0x7F
  292 
  293 /*
  294  * Interrupt Mask Register (0x38)
  295  */
  296 #define Q81_CTL_INTRM_MASK_SHIFT                16
  297 #define Q81_CTL_INTRM_MC                        BIT_7
  298 #define Q81_CTL_INTRM_LSC                       BIT_6
  299 #define Q81_CTL_INTRM_LH1                       BIT_4
  300 #define Q81_CTL_INTRM_HL1                       BIT_3
  301 #define Q81_CTL_INTRM_LH0                       BIT_2
  302 #define Q81_CTL_INTRM_HL0                       BIT_1
  303 #define Q81_CTL_INTRM_PI                        BIT_0
  304 
  305 /*
  306  * Interrupt Status 1 Register (0x3C)
  307  */
  308 #define Q81_CTL_INTRS1_COMPQ(i)                 (0x1 << i)
  309 
  310 /*
  311  * Interrupt Status 2 Register (0x40)
  312  */
  313 #define Q81_CTL_INTRS2_COMPQ(i)                 (0x1 << i)
  314 
  315 /*
  316  * Interrupt Status 3 Register (0x44)
  317  */
  318 #define Q81_CTL_INTRS3_COMPQ(i)                 (0x1 << i)
  319 
  320 /*
  321  * Interrupt Status 4 Register (0x48)
  322  */
  323 #define Q81_CTL_INTRS4_COMPQ(i)                 (0x1 << i)
  324 
  325 /*
  326  * Revision ID Register (0x4C)
  327  */
  328 #define Q81_CTL_REV_ID_CHIP_REV_MASK            (0xF << 28)
  329 #define Q81_CTL_REV_ID_XGMAC_RCV_MASK           (0xF << 16)
  330 #define Q81_CTL_REV_ID_XGMAC_ROLL_MASK          (0xF << 8)
  331 #define Q81_CTL_REV_ID_NIC_REV_MASK             (0xF << 4)
  332 #define Q81_CTL_REV_ID_NIC_ROLL_MASK            (0xF << 0)
  333 
  334 /*
  335  * Semaphore Register (0x64)
  336  */
  337 
  338 #define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV      0xC0000000
  339 
  340 #define Q81_CTL_SEM_MASK_RIDX_DATAREG           0x30000000
  341 
  342 #define Q81_CTL_SEM_MASK_FLASH                  0x03000000
  343 
  344 #define Q81_CTL_SEM_MASK_MAC_SERDES             0x00C00000
  345 
  346 #define Q81_CTL_SEM_MASK_ICB                    0x00300000
  347 
  348 #define Q81_CTL_SEM_MASK_XGMAC1                 0x000C0000
  349 
  350 #define Q81_CTL_SEM_MASK_XGMAC0                 0x00030000
  351 
  352 #define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV       0x4000
  353 #define Q81_CTL_SEM_SET_RIDX_DATAREG            0x1000
  354 #define Q81_CTL_SEM_SET_FLASH                   0x0100
  355 #define Q81_CTL_SEM_SET_MAC_SERDES              0x0040
  356 #define Q81_CTL_SEM_SET_ICB                     0x0010
  357 #define Q81_CTL_SEM_SET_XGMAC1                  0x0004
  358 #define Q81_CTL_SEM_SET_XGMAC0                  0x0001
  359 
  360 /*
  361  * Flash Address Register (0x88)
  362  */
  363 #define Q81_CTL_FLASH_ADDR_RDY                  BIT_31
  364 #define Q81_CTL_FLASH_ADDR_R                    BIT_30
  365 #define Q81_CTL_FLASH_ADDR_ERR                  BIT_29
  366 #define Q81_CTL_FLASH_ADDR_MASK                 0x7FFFFF
  367 
  368 /*
  369  * Stop CQ Processing Register (0x90)
  370  */
  371 #define Q81_CTL_STOP_CQ_MASK_SHIFT              16
  372 #define Q81_CTL_STOP_CQ_EN                      BIT_15
  373 #define Q81_CTL_STOP_CQ_RQ_STARTQ               (0x1 << 8)
  374 #define Q81_CTL_STOP_CQ_RQ_STOPQ                (0x2 << 8)
  375 #define Q81_CTL_STOP_CQ_RQ_READ                 (0x3 << 8)
  376 #define Q81_CTL_STOP_CQ_MASK                    0x7F
  377 
  378 /*
  379  * MAC Protocol Address Index Register (0xA8)
  380  */
  381 #define Q81_CTL_MAC_PROTO_AI_MW                 BIT_31
  382 #define Q81_CTL_MAC_PROTO_AI_MR                 BIT_30
  383 #define Q81_CTL_MAC_PROTO_AI_E                  BIT_27
  384 #define Q81_CTL_MAC_PROTO_AI_RS                 BIT_26
  385 #define Q81_CTL_MAC_PROTO_AI_ADR                BIT_25
  386 #define Q81_CTL_MAC_PROTO_AI_TYPE_SHIFT         16
  387 #define Q81_CTL_MAC_PROTO_AI_TYPE_MASK          0xF0000
  388 #define Q81_CTL_MAC_PROTO_AI_IDX_SHIFT          4
  389 #define Q81_CTL_MAC_PROTO_AI_IDX_MASK           0xFFF0
  390 #define Q81_CTL_MAC_PROTO_AI_OFF_MASK           0xF
  391 
  392 #define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC       (0 << 16)
  393 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST         (1 << 16)
  394 #define Q81_CTL_MAC_PROTO_AI_TYPE_VLAN          (2 << 16)
  395 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST_FILTER  (3 << 16)
  396 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_MAC      (5 << 16)
  397 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMMT_VLAN    (6 << 16)
  398 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV4     (7 << 16)
  399 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV6     (8 << 16)
  400 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_PORT     (9 << 16) /* TCP/UDP Port */
  401 
  402 /*
  403  * CAM MAC offset 2 definitions
  404  */
  405 #define Q81_CAM_MAC_OFF2_ROUTE_FC               0x00000000
  406 #define Q81_CAM_MAC_OFF2_ROUTE_NIC              0x00000001
  407 #define Q81_CAM_MAC_OFF2_FUNC_SHIFT             2
  408 #define Q81_CAM_MAC_OFF2_RV                     0x00000010
  409 #define Q81_CAM_MAC_OFF2_CQID_SHIFT             5
  410 #define Q81_CAM_MAC_OFF2_SH                     0x00008000
  411 #define Q81_CAM_MAC_OFF2_MHT                    0x40000000
  412 #define Q81_CAM_MAC_OFF2_VLD                    0x80000000
  413 
  414 /*
  415  * NIC Pause Threshold Register (0xC8)
  416  */
  417 #define Q81_CTL_NIC_PAUSE_THRES_PAUSE_SHIFT     16
  418 #define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT    0
  419 
  420 /*
  421  * NIC Receive Configuration Register (0xD4)
  422  */
  423 #define Q81_CTL_NIC_RCVC_MASK_SHIFT             16
  424 #define Q81_CTL_NIC_RCVC_DCQ_SHIFT              8
  425 #define Q81_CTL_NIC_RCVC_DCQ_MASK               0x7F00
  426 #define Q81_CTL_NIC_RCVC_DTP                    BIT_5
  427 #define Q81_CTL_NIC_RCVC_R4T                    BIT_4
  428 #define Q81_CTL_NIC_RCVC_RV                     BIT_3
  429 #define Q81_CTL_NIC_RCVC_VLAN_ALL               (0x0 << 1)
  430 #define Q81_CTL_NIC_RCVC_VLAN_ONLY              (0x1 << 1)
  431 #define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN          (0x2 << 1)
  432 #define Q81_CTL_NIC_RCVC_VLAN_REJECT            (0x3 << 1)
  433 #define Q81_CTL_NIC_RCVC_PPE                    BIT_0
  434 
  435 /*
  436  * Routing Index Register (0xE4)
  437  */
  438 #define Q81_CTL_RI_MW                           BIT_31
  439 #define Q81_CTL_RI_MR                           BIT_30
  440 #define Q81_CTL_RI_E                            BIT_27
  441 #define Q81_CTL_RI_RS                           BIT_26
  442 
  443 #define Q81_CTL_RI_DST_RSS                      (0x00 << 20)
  444 #define Q81_CTL_RI_DST_CAMQ                     (0x01 << 20)
  445 #define Q81_CTL_RI_DST_COSQ                     (0x02 << 20)
  446 #define Q81_CTL_RI_DST_DFLTQ                    (0x03 << 20)
  447 #define Q81_CTL_RI_DST_DESTQ                    (0x04 << 20)
  448 #define Q81_CTL_RI_DST_DROP                     (0x07 << 20)
  449 
  450 #define Q81_CTL_RI_TYPE_RTMASK                  (0x00 << 16)
  451 #define Q81_CTL_RI_TYPE_RTINVMASK               (0x01 << 16)
  452 #define Q81_CTL_RI_TYPE_NICQMASK                (0x02 << 16)
  453 #define Q81_CTL_RI_TYPE_NICQINVMASK             (0x03 << 16)
  454 
  455 /* these indices for the Routing Index Register are user defined */
  456 #define Q81_CTL_RI_IDX_ALL_ERROR                (0x00 << 8)
  457 #define Q81_CTL_RI_IDX_MAC_ERROR                (0x00 << 8)
  458 #define Q81_CTL_RI_IDX_IPCSUM_ERROR             (0x01 << 8)
  459 #define Q81_CTL_RI_IDX_TCPCSUM_ERROR            (0x02 << 8)
  460 #define Q81_CTL_RI_IDX_BCAST                    (0x03 << 8)
  461 #define Q81_CTL_RI_IDX_MCAST_MATCH              (0x04 << 8)
  462 #define Q81_CTL_RI_IDX_ALLMULTI                 (0x05 << 8)
  463 #define Q81_CTL_RI_IDX_RSS_MATCH                (0x08 << 8)
  464 #define Q81_CTL_RI_IDX_RSS_IPV4                 (0x08 << 8)
  465 #define Q81_CTL_RI_IDX_RSS_IPV6                 (0x09 << 8)
  466 #define Q81_CTL_RI_IDX_RSS_TCPV4                (0x0A << 8)
  467 #define Q81_CTL_RI_IDX_RSS_TCPV6                (0x0B << 8)
  468 #define Q81_CTL_RI_IDX_CAM_HIT                  (0x0C << 8)
  469 #define Q81_CTL_RI_IDX_PROMISCUOUS              (0x0F << 8)
  470 
  471 /* Routing Masks to be loaded into Routing Data Register */
  472 #define Q81_CTL_RD_BCAST                        BIT_0
  473 #define Q81_CTL_RD_MCAST                        BIT_1
  474 #define Q81_CTL_RD_MCAST_MATCH                  BIT_2
  475 #define Q81_CTL_RD_MCAST_REG_MATCH              BIT_3
  476 #define Q81_CTL_RD_MCAST_HASH_MATCH             BIT_4
  477 #define Q81_CTL_RD_CAM_HIT                      BIT_7
  478 #define Q81_CTL_RD_CAM_BIT0                     BIT_8
  479 #define Q81_CTL_RD_CAM_BIT1                     BIT_9
  480 #define Q81_CTL_RD_VLAN_TAG_PRESENT             BIT_10
  481 #define Q81_CTL_RD_VLAN_MATCH                   BIT_11
  482 #define Q81_CTL_RD_VLAN_FILTER_PASS             BIT_12
  483 #define Q81_CTL_RD_SKIP_ETHERTYPE_1             BIT_13
  484 #define Q81_CTL_RD_SKIP_ETHERTYPE_2             BIT_14
  485 #define Q81_CTL_RD_BCAST_OR_MCAST_MATCH         BIT_15
  486 #define Q81_CTL_RD_802_3_PKT                    BIT_16
  487 #define Q81_CTL_RD_LLDP_PKT                     BIT_17
  488 #define Q81_CTL_RD_TUNNELED_PKT                 BIT_18
  489 #define Q81_CTL_RD_ERROR_PKT                    BIT_22
  490 #define Q81_CTL_RD_VALID_PKT                    BIT_23
  491 #define Q81_CTL_RD_TCP_UDP_CSUM_ERR             BIT_24
  492 #define Q81_CTL_RD_IPCSUM_ERR                   BIT_25
  493 #define Q81_CTL_RD_MAC_ERR                      BIT_26
  494 #define Q81_CTL_RD_RSS_TCP_IPV6                 BIT_27
  495 #define Q81_CTL_RD_RSS_TCP_IPV4                 BIT_28
  496 #define Q81_CTL_RD_RSS_IPV6                     BIT_29
  497 #define Q81_CTL_RD_RSS_IPV4                     BIT_30
  498 #define Q81_CTL_RD_RSS_MATCH                    BIT_31
  499 
  500 /*********************************************************************
  501  * Host Data Structures *
  502  *********************************************************************/
  503 
  504 /*
  505  * Work Queue Initialization Control Block
  506  */
  507 
  508 typedef struct _q81_wq_icb {
  509         uint16_t        length_v;
  510 #define Q81_WQ_ICB_VALID                        BIT_4
  511 
  512         uint8_t         pri;
  513 #define Q81_WQ_ICB_PRI_SHIFT                    1
  514 
  515         uint8_t         flags;
  516 #define Q81_WQ_ICB_FLAGS_LO                     BIT_7
  517 #define Q81_WQ_ICB_FLAGS_LI                     BIT_6
  518 #define Q81_WQ_ICB_FLAGS_LB                     BIT_5
  519 #define Q81_WQ_ICB_FLAGS_LC                     BIT_4
  520 
  521         uint16_t        wqcqid_rss;
  522 #define Q81_WQ_ICB_RSS_V                        BIT_15
  523 
  524         uint16_t        rsrvd;
  525 
  526         uint32_t        baddr_lo;
  527         uint32_t        baddr_hi;
  528 
  529         uint32_t        ci_addr_lo;
  530         uint32_t        ci_addr_hi;
  531 } __packed q81_wq_icb_t;
  532 
  533 /*
  534  * Completion Queue Initialization Control Block
  535  */
  536 
  537 typedef struct _q81_cq_icb {
  538         uint8_t         msix_vector;
  539         uint16_t        rsrvd0;
  540         uint8_t         flags;
  541 #define Q81_CQ_ICB_FLAGS_LC                     BIT_7
  542 #define Q81_CQ_ICB_FLAGS_LI                     BIT_6
  543 #define Q81_CQ_ICB_FLAGS_LL                     BIT_5
  544 #define Q81_CQ_ICB_FLAGS_LS                     BIT_4
  545 #define Q81_CQ_ICB_FLAGS_LV                     BIT_3
  546 
  547         uint16_t        length_v;
  548 #define Q81_CQ_ICB_VALID                        BIT_4
  549 
  550         uint16_t        rsrvd1;
  551 
  552         uint32_t        cq_baddr_lo;
  553         uint32_t        cq_baddr_hi;
  554 
  555         uint32_t        cqi_addr_lo;
  556         uint32_t        cqi_addr_hi;
  557 
  558         uint16_t        pkt_idelay;
  559         uint16_t        idelay;
  560 
  561         uint32_t        lbq_baddr_lo;
  562         uint32_t        lbq_baddr_hi;
  563         uint16_t        lbq_bsize;
  564         uint16_t        lbq_length;
  565 
  566         uint32_t        sbq_baddr_lo;
  567         uint32_t        sbq_baddr_hi;
  568         uint16_t        sbq_bsize;
  569         uint16_t        sbq_length;
  570 } __packed q81_cq_icb_t;
  571 
  572 /*
  573  * RSS Initialization Control Block
  574  */
  575 typedef struct _q81_rss_icb {
  576         uint16_t        flags_base_cq_num;
  577 #define Q81_RSS_ICB_FLAGS_L4K           BIT_7
  578 #define Q81_RSS_ICB_FLAGS_L6K           BIT_8
  579 #define Q81_RSS_ICB_FLAGS_LI            BIT_9
  580 #define Q81_RSS_ICB_FLAGS_LB            BIT_10
  581 #define Q81_RSS_ICB_FLAGS_LM            BIT_11
  582 #define Q81_RSS_ICB_FLAGS_RI4           BIT_12
  583 #define Q81_RSS_ICB_FLAGS_RT4           BIT_13
  584 #define Q81_RSS_ICB_FLAGS_RI6           BIT_14
  585 #define Q81_RSS_ICB_FLAGS_RT6           BIT_15
  586 
  587         uint16_t        mask; /* bits 9-0 are valid */
  588 
  589 #define Q81_RSS_ICB_NUM_INDTBL_ENTRIES  1024
  590         /* Indirection Table */
  591         uint8_t         cq_id[Q81_RSS_ICB_NUM_INDTBL_ENTRIES];
  592 
  593         /* Hash Keys */
  594         uint32_t        ipv6_rss_hash_key[10];
  595         uint32_t        ipv4_rss_hash_key[4];
  596 } __packed q81_rss_icb_t;
  597 
  598 /*
  599  * Transmit Buffer Descriptor
  600  */
  601 
  602 typedef struct _q81_txb_desc {
  603         uint64_t        baddr;
  604         uint16_t        length;
  605 
  606         uint16_t        flags;
  607 #define Q81_TXB_DESC_FLAGS_E    BIT_15
  608 #define Q81_TXB_DESC_FLAGS_C    BIT_14
  609 
  610 } __packed q81_txb_desc_t;
  611 
  612 /*
  613  * Receive Buffer Descriptor
  614  */
  615 
  616 typedef struct _q81_rxb_desc {
  617         uint32_t        baddr_lo;
  618 #define Q81_RXB_DESC_BADDR_LO_S BIT_1
  619 
  620         uint64_t        baddr;
  621 
  622         uint16_t        length;
  623 
  624         uint16_t        flags;
  625 #define Q81_RXB_DESC_FLAGS_E    BIT_15
  626 #define Q81_RXB_DESC_FLAGS_C    BIT_14
  627 
  628 } __packed q81_rxb_desc_t;
  629 
  630 /*
  631  * IOCB Types
  632  */
  633 
  634 #define Q81_IOCB_TX_MAC         0x01
  635 #define Q81_IOCB_TX_TSO         0x02
  636 #define Q81_IOCB_RX             0x20
  637 #define Q81_IOCB_MPI            0x21
  638 #define Q81_IOCB_SYS            0x3F
  639 
  640 /*
  641  * IOCB Definitions
  642  */
  643 
  644 /*
  645  * MAC Tx Frame IOCB
  646  * Total Size of each IOCB Entry = 4 * 32 = 128 bytes
  647  */
  648 #define MAX_TX_MAC_DESC         8
  649 
  650 typedef struct _q81_tx_mac {
  651         uint8_t         opcode;
  652 
  653         uint16_t        flags;
  654 #define Q81_TX_MAC_FLAGS_D              BIT_3
  655 #define Q81_TX_MAC_FLAGS_I              BIT_1
  656 #define Q81_TX_MAC_FLAGS_OI             BIT_0
  657 
  658         uint8_t         vlan_off;
  659 #define Q81_TX_MAC_VLAN_OFF_SHIFT       3
  660 #define Q81_TX_MAC_VLAN_OFF_V           BIT_2
  661 #define Q81_TX_MAC_VLAN_OFF_DFP         BIT_1
  662 
  663         uint32_t        rsrvd1;
  664         uint32_t        rsrvd2;
  665 
  666         uint16_t        frame_length; /* only bits0-13 are valid */
  667         uint16_t        rsrvd3;
  668 
  669         uint32_t        tid_lo;
  670         uint32_t        tid_hi;
  671 
  672         uint32_t        rsrvd4;
  673 
  674         uint16_t        vlan_tci;
  675         uint16_t        rsrvd5;
  676 
  677         q81_txb_desc_t  txd[MAX_TX_MAC_DESC];
  678 } __packed q81_tx_mac_t;
  679 
  680 /*
  681  * MAC Tx Frame with TSO IOCB
  682  * Total Size of each IOCB Entry = 4 * 32 = 128 bytes
  683  */
  684 typedef struct _q81_tx_tso {
  685         uint8_t         opcode;
  686 
  687         uint16_t        flags;
  688 #define Q81_TX_TSO_FLAGS_OI             BIT_0
  689 #define Q81_TX_TSO_FLAGS_I              BIT_1
  690 #define Q81_TX_TSO_FLAGS_D              BIT_3
  691 #define Q81_TX_TSO_FLAGS_IPV4           BIT_6
  692 #define Q81_TX_TSO_FLAGS_IPV6           BIT_7
  693 #define Q81_TX_TSO_FLAGS_LSO            BIT_13
  694 #define Q81_TX_TSO_FLAGS_UC             BIT_14
  695 #define Q81_TX_TSO_FLAGS_TC             BIT_15
  696 
  697         uint8_t         vlan_off;
  698 #define Q81_TX_TSO_VLAN_OFF_SHIFT       3
  699 #define Q81_TX_TSO_VLAN_OFF_V           BIT_2
  700 #define Q81_TX_TSO_VLAN_OFF_DFP         BIT_1
  701 #define Q81_TX_TSO_VLAN_OFF_IC          BIT_0
  702 
  703         uint32_t        rsrvd1;
  704         uint32_t        rsrvd2;
  705 
  706         uint32_t        length;
  707         uint32_t        tid_lo;
  708         uint32_t        tid_hi;
  709 
  710         uint16_t        phdr_length;
  711 
  712         uint16_t        phdr_offsets;
  713 #define Q81_TX_TSO_PHDR_SHIFT           6
  714 
  715         uint16_t        vlan_tci;
  716         uint16_t        mss;
  717 
  718         q81_txb_desc_t  txd[MAX_TX_MAC_DESC];
  719 } __packed q81_tx_tso_t;
  720 
  721 typedef struct _q81_tx_cmd {
  722         uint8_t         bytes[128];
  723 } __packed q81_tx_cmd_t;
  724 
  725 /*
  726  * MAC TX Frame Completion
  727  * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
  728  */
  729 
  730 typedef struct _q81_tx_mac_comp {
  731         uint8_t         opcode;
  732 
  733         uint8_t         flags;
  734 #define Q81_TX_MAC_COMP_FLAGS_OI        BIT_0
  735 #define Q81_TX_MAC_COMP_FLAGS_I         BIT_1
  736 #define Q81_TX_MAC_COMP_FLAGS_E         BIT_3
  737 #define Q81_TX_MAC_COMP_FLAGS_S         BIT_4
  738 #define Q81_TX_MAC_COMP_FLAGS_L         BIT_5
  739 #define Q81_TX_MAC_COMP_FLAGS_P         BIT_6
  740 
  741         uint8_t         rsrvd0;
  742 
  743         uint8_t         err;
  744 #define Q81_TX_MAC_COMP_ERR_B           BIT_7
  745 
  746         uint32_t        tid_lo;
  747         uint32_t        tid_hi;
  748 
  749         uint32_t        rsrvd1[13];
  750 } __packed q81_tx_mac_comp_t;
  751 
  752 /*
  753  * MAC TX Frame with LSO Completion
  754  * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
  755  */
  756 
  757 typedef struct _q81_tx_tso_comp {
  758         uint8_t         opcode;
  759 
  760         uint8_t         flags;
  761 #define Q81_TX_TSO_COMP_FLAGS_OI        BIT_0
  762 #define Q81_TX_TSO_COMP_FLAGS_I         BIT_1
  763 #define Q81_TX_TSO_COMP_FLAGS_E         BIT_3
  764 #define Q81_TX_TSO_COMP_FLAGS_S         BIT_4
  765 #define Q81_TX_TSO_COMP_FLAGS_P         BIT_6
  766 
  767         uint8_t         rsrvd0;
  768 
  769         uint8_t         err;
  770 #define Q81_TX_TSO_COMP_ERR_B           BIT_7
  771 
  772         uint32_t        tid_lo;
  773         uint32_t        tid_hi;
  774 
  775         uint32_t        rsrvd1[13];
  776 } __packed q81_tx_tso_comp_t;
  777 
  778 /*
  779  * SYS - Chip Event Notification Completion
  780  * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
  781  */
  782 
  783 typedef struct _q81_sys_comp {
  784         uint8_t         opcode;
  785 
  786         uint8_t         flags;
  787 #define Q81_SYS_COMP_FLAGS_OI           BIT_0
  788 #define Q81_SYS_COMP_FLAGS_I            BIT_1
  789 
  790         uint8_t         etype;
  791 #define Q81_SYS_COMPE_LINK_UP           0x00
  792 #define Q81_SYS_COMPE_LINK_DOWN         0x01
  793 #define Q81_SYS_COMPE_MULTI_CAM_LOOKUP  0x06
  794 #define Q81_SYS_COMPE_SOFT_ECC          0x07
  795 #define Q81_SYS_COMPE_MPI_FATAL_ERROR   0x08
  796 #define Q81_SYS_COMPE_MAC_INTR          0x09
  797 #define Q81_SYS_COMPE_GPI0_HTOL         0x10
  798 #define Q81_SYS_COMPE_GPI0_LTOH         0x20
  799 #define Q81_SYS_COMPE_GPI1_HTOL         0x11
  800 #define Q81_SYS_COMPE_GPI1_LTOH         0x21
  801 
  802         uint8_t         q_id; /* only bits 0-6 are valid */
  803 
  804         uint32_t        rsrvd1[15];
  805 } __packed q81_sys_comp_t;
  806 
  807 /*
  808  * Mac Rx Packet Completion
  809  * Total Size of each IOCB Entry = 4 * 16 = 64 bytes
  810  */
  811 
  812 typedef struct _q81_rx {
  813         uint8_t         opcode;
  814 
  815         uint8_t         flags0;
  816 #define Q81_RX_FLAGS0_OI                BIT_0
  817 #define Q81_RX_FLAGS0_I                 BIT_1
  818 #define Q81_RX_FLAGS0_TE                BIT_2
  819 #define Q81_RX_FLAGS0_NU                BIT_3
  820 #define Q81_RX_FLAGS0_IE                BIT_4
  821 
  822 #define Q81_RX_FLAGS0_MCAST_MASK        (0x03 << 5)
  823 #define Q81_RX_FLAGS0_MCAST_NONE        (0x00 << 5)
  824 #define Q81_RX_FLAGS0_MCAST_HASH_MATCH  (0x01 << 5)
  825 #define Q81_RX_FLAGS0_MCAST_REG_MATCH   (0x02 << 5)
  826 #define Q81_RX_FLAGS0_MCAST_PROMISC     (0x03 << 5)
  827 
  828 #define Q81_RX_FLAGS0_B                 BIT_7
  829 
  830         uint16_t        flags1;
  831 #define Q81_RX_FLAGS1_P                 BIT_0
  832 #define Q81_RX_FLAGS1_V                 BIT_1
  833 
  834 #define Q81_RX_FLAGS1_ERR_NONE          (0x00 << 2)
  835 #define Q81_RX_FLAGS1_ERR_CODE          (0x01 << 2)
  836 #define Q81_RX_FLAGS1_ERR_OSIZE         (0x02 << 2)
  837 #define Q81_RX_FLAGS1_ERR_USIZE         (0x04 << 2)
  838 #define Q81_RX_FLAGS1_ERR_PREAMBLE      (0x05 << 2)
  839 #define Q81_RX_FLAGS1_ERR_FRAMELENGTH   (0x06 << 2)
  840 #define Q81_RX_FLAGS1_ERR_CRC           (0x07 << 2)
  841 #define Q81_RX_FLAGS1_ERR_MASK          (0x07 << 2)
  842 
  843 #define Q81_RX_FLAGS1_U                 BIT_5
  844 #define Q81_RX_FLAGS1_T                 BIT_6
  845 #define Q81_RX_FLAGS1_FO                BIT_7
  846 #define Q81_RX_FLAGS1_RSS_NO_MATCH      (0x00 << 8)
  847 #define Q81_RX_FLAGS1_RSS_IPV4_MATCH    (0x04 << 8)
  848 #define Q81_RX_FLAGS1_RSS_IPV6_MATCH    (0x02 << 8)
  849 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8)
  850 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8)
  851 #define Q81_RX_FLAGS1_RSS_MATCH_MASK    (0x07 << 8)
  852 #define Q81_RX_FLAGS1_V4                BIT_11
  853 #define Q81_RX_FLAGS1_V6                BIT_12
  854 #define Q81_RX_FLAGS1_IH                BIT_13
  855 #define Q81_RX_FLAGS1_DS                BIT_14
  856 #define Q81_RX_FLAGS1_DL                BIT_15
  857 
  858         uint32_t        length;
  859         uint64_t        b_paddr;
  860 
  861         uint32_t        rss;
  862         uint16_t        vlan_tag;
  863         uint16_t        rsrvd;
  864         uint32_t        rsrvd1;
  865         uint32_t        flags2;
  866 #define Q81_RX_FLAGS2_HV                BIT_13
  867 #define Q81_RX_FLAGS2_HS                BIT_14
  868 #define Q81_RX_FLAGS2_HL                BIT_15
  869 
  870         uint32_t        hdr_length;
  871         uint32_t        hdr_baddr_lo;
  872         uint32_t        hdr_baddr_hi;
  873 
  874 } __packed q81_rx_t;
  875 
  876 typedef struct _q81_cq_e {
  877         uint8_t         opcode;
  878         uint8_t         bytes[63];
  879 } __packed q81_cq_e_t;
  880 
  881 typedef struct _q81_bq_addr_e {
  882         uint32_t        addr_lo;
  883         uint32_t        addr_hi;
  884 } __packed q81_bq_addr_e_t;
  885 
  886 /*
  887  * Macros for reading and writing registers
  888  */
  889 
  890 #if defined(__i386__) || defined(__amd64__)
  891 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
  892 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
  893 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
  894 #else
  895 #define Q8_MB()
  896 #define Q8_WMB()
  897 #define Q8_RMB()
  898 #endif
  899 
  900 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
  901 #define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg)
  902 
  903 #define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)
  904 
  905 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)
  906 
  907 #define Q81_CTL_INTRE_MASK_VALUE \
  908         (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \
  909                 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_ENABLE)
  910 
  911 #define Q81_ENABLE_INTR(ha, idx) \
  912         WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx))
  913 
  914 #define Q81_CTL_INTRD_MASK_VALUE \
  915         (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \
  916                 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_DISABLE)
  917 
  918 #define Q81_DISABLE_INTR(ha, idx) \
  919         WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
  920 
  921 #define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\
  922                 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG), idx)
  923 
  924 #define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\
  925                 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG))
  926 
  927 #define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\
  928                 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\
  929                         Q81_COMPQ_VALID_V)
  930 
  931 #define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\
  932                 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\
  933                         (~Q81_COMPQ_VALID_V))
  934 
  935 #define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\
  936                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG), idx)
  937 
  938 #define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\
  939                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG))
  940 
  941 #define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\
  942                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\
  943                         Q81_COMPQ_VALID_V)
  944 
  945 #define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\
  946                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\
  947                         ~Q81_COMPQ_VALID_V)
  948 
  949 #define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\
  950                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG), idx)
  951 
  952 #define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\
  953                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG))
  954 
  955 #define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\
  956                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG), idx)
  957 
  958 #define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\
  959                 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG))
  960 
  961 /*
  962  * Flash Related
  963  */
  964 
  965 #define Q81_F0_FLASH_OFFSET     0x140200
  966 #define Q81_F1_FLASH_OFFSET     0x140600
  967 #define Q81_FLASH_ID            "8000"
  968 
  969 typedef struct _q81_flash {
  970         uint8_t         id[4]; /* equal to "8000" */
  971 
  972         uint16_t        version;
  973         uint16_t        size;
  974         uint16_t        csum;
  975         uint16_t        rsrvd0;
  976         uint16_t        total_size;
  977         uint16_t        nentries;
  978 
  979         uint8_t         dtype0;
  980         uint8_t         dsize0;
  981         uint8_t         mac_addr0[6];
  982 
  983         uint8_t         dtype1;
  984         uint8_t         dsize1;
  985         uint8_t         mac_addr1[6];
  986 
  987         uint8_t         dtype2;
  988         uint8_t         dsize2;
  989         uint16_t        vlan_id;
  990 
  991         uint8_t         dtype3;
  992         uint8_t         dsize3;
  993         uint16_t        last;
  994 
  995         uint8_t         rsrvd1[464];
  996 
  997         uint16_t        subsys_vid;
  998         uint16_t        subsys_did;
  999 
 1000         uint8_t         rsrvd2[4];
 1001 } __packed q81_flash_t;
 1002 
 1003 /*
 1004  * MPI Related 
 1005  */
 1006 
 1007 #define Q81_NUM_MBX_REGISTERS   16
 1008 #define Q81_NUM_AEN_REGISTERS   9
 1009 
 1010 #define Q81_FUNC0_MBX_IN_REG0   0x1180
 1011 #define Q81_FUNC0_MBX_OUT_REG0  0x1190
 1012 
 1013 #define Q81_FUNC1_MBX_IN_REG0   0x1280
 1014 #define Q81_FUNC1_MBX_OUT_REG0  0x1290
 1015 
 1016 #define Q81_MBX_NOP             0x0000
 1017 #define Q81_MBX_EXEC_FW         0x0002
 1018 #define Q81_MBX_REG_TEST        0x0006
 1019 #define Q81_MBX_VERIFY_CHKSUM   0x0007
 1020 #define Q81_MBX_ABOUT_FW        0x0008
 1021 #define Q81_MBX_RISC_MEMCPY     0x000A
 1022 #define Q81_MBX_LOAD_RISC_RAM   0x000B
 1023 #define Q81_MBX_DUMP_RISC_RAM   0x000C
 1024 #define Q81_MBX_WR_RAM_WORD     0x000D
 1025 #define Q81_MBX_INIT_RISC_RAM   0x000E
 1026 #define Q81_MBX_RD_RAM_WORD     0x000F
 1027 #define Q81_MBX_STOP_FW         0x0014
 1028 #define Q81_MBX_GEN_SYS_ERR     0x002A
 1029 #define Q81_MBX_WR_SFP_PLUS     0x0030
 1030 #define Q81_MBX_RD_SFP_PLUS     0x0031
 1031 #define Q81_MBX_INIT_FW         0x0060
 1032 #define Q81_MBX_GET_IFCB        0x0061
 1033 #define Q81_MBX_GET_FW_STATE    0x0069
 1034 #define Q81_MBX_IDC_REQ         0x0100
 1035 #define Q81_MBX_IDC_ACK         0x0101
 1036 #define Q81_MBX_IDC_TIME_EXTEND 0x0102
 1037 #define Q81_MBX_WOL_MODE        0x0110
 1038 #define Q81_MBX_SET_WOL_FILTER  0x0111
 1039 #define Q81_MBX_CLR_WOL_FILTER  0x0112
 1040 #define Q81_MBX_SET_WOL_MAGIC   0x0113
 1041 #define Q81_MBX_WOL_MODE_IMM    0x0115
 1042 #define Q81_MBX_PORT_RESET      0x0120
 1043 #define Q81_MBX_SET_PORT_CFG    0x0122
 1044 #define Q81_MBX_GET_PORT_CFG    0x0123
 1045 #define Q81_MBX_GET_LNK_STATUS  0x0124
 1046 #define Q81_MBX_SET_LED_CFG     0x0125
 1047 #define Q81_MBX_GET_LED_CFG     0x0126
 1048 #define Q81_MBX_SET_DCBX_CTLB   0x0130
 1049 #define Q81_MBX_GET_DCBX_CTLB   0x0131
 1050 #define Q81_MBX_GET_DCBX_TLV    0x0132
 1051 #define Q81_MBX_DIAG_CMDS       0x0150
 1052 #define Q81_MBX_SET_MGMT_CTL    0x0160
 1053 #define         Q81_MBX_SET_MGMT_CTL_STOP       0x01
 1054 #define         Q81_MBX_SET_MGMT_CTL_RESUME     0x02
 1055 #define Q81_MBX_GET_MGMT_CTL    0x0161
 1056 #define         Q81_MBX_GET_MGMT_CTL_MASK       ~0x3
 1057 #define         Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY 0x02
 1058 #define         Q81_MBX_GET_MGMT_CTL_SET_MGMT   0x01
 1059 
 1060 #define Q81_MBX_CMD_COMPLETE    0x4000
 1061 #define Q81_MBX_CMD_INVALID     0x4001
 1062 #define Q81_MBX_CMD_TEST_FAILED 0x4003
 1063 #define Q81_MBX_CMD_ERROR       0x4005
 1064 #define Q81_MBX_CMD_PARAM_ERROR 0x4006
 1065 
 1066 #endif /* #ifndef _QLS_HW_H_ */

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