Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ral/rt2661.c
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1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 61 #include <dev/ral/if_ralrate.h> 62 #include <dev/ral/rt2661reg.h> 63 #include <dev/ral/rt2661var.h> 64 #include <dev/ral/rt2661_ucode.h> 65 66 #ifdef RAL_DEBUG 67 #define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) 69 int ral_debug = 0; 70 SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); 71 #else 72 #define DPRINTF(x) 73 #define DPRINTFN(n, x) 74 #endif 75 76 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 77 int); 78 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *, int); 80 static void rt2661_reset_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *); 82 static void rt2661_free_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *, int); 86 static void rt2661_reset_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *); 88 static void rt2661_free_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90 static struct ieee80211_node *rt2661_node_alloc( 91 struct ieee80211_node_table *); 92 static int rt2661_media_change(struct ifnet *); 93 static void rt2661_next_scan(void *); 94 static int rt2661_newstate(struct ieee80211com *, 95 enum ieee80211_state, int); 96 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 97 static void rt2661_rx_intr(struct rt2661_softc *); 98 static void rt2661_tx_intr(struct rt2661_softc *); 99 static void rt2661_tx_dma_intr(struct rt2661_softc *, 100 struct rt2661_tx_ring *); 101 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 102 static void rt2661_mcu_wakeup(struct rt2661_softc *); 103 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 104 static int rt2661_ack_rate(struct ieee80211com *, int); 105 static uint16_t rt2661_txtime(int, int, uint32_t); 106 static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 107 static uint8_t rt2661_plcp_signal(int); 108 static void rt2661_setup_tx_desc(struct rt2661_softc *, 109 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 110 int, const bus_dma_segment_t *, int, int); 111 static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 112 struct ieee80211_frame *, uint16_t); 113 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 114 struct ieee80211_node *, int); 115 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 116 struct ieee80211_node *); 117 static void rt2661_start(struct ifnet *); 118 static void rt2661_watchdog(struct ifnet *); 119 static int rt2661_reset(struct ifnet *); 120 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 121 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 122 uint8_t); 123 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 124 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 125 uint32_t); 126 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 127 uint16_t); 128 static void rt2661_select_antenna(struct rt2661_softc *); 129 static void rt2661_enable_mrr(struct rt2661_softc *); 130 static void rt2661_set_txpreamble(struct rt2661_softc *); 131 static void rt2661_set_basicrates(struct rt2661_softc *, 132 const struct ieee80211_rateset *); 133 static void rt2661_select_band(struct rt2661_softc *, 134 struct ieee80211_channel *); 135 static void rt2661_set_chan(struct rt2661_softc *, 136 struct ieee80211_channel *); 137 static void rt2661_set_bssid(struct rt2661_softc *, 138 const uint8_t *); 139 static void rt2661_set_macaddr(struct rt2661_softc *, 140 const uint8_t *); 141 static void rt2661_update_promisc(struct rt2661_softc *); 142 static int rt2661_wme_update(struct ieee80211com *) __unused; 143 static void rt2661_update_slot(struct ifnet *); 144 static const char *rt2661_get_rf(int); 145 static void rt2661_read_eeprom(struct rt2661_softc *); 146 static int rt2661_bbp_init(struct rt2661_softc *); 147 static void rt2661_init(void *); 148 static void rt2661_stop(void *); 149 static int rt2661_load_microcode(struct rt2661_softc *, 150 const uint8_t *, int); 151 #ifdef notyet 152 static void rt2661_rx_tune(struct rt2661_softc *); 153 static void rt2661_radar_start(struct rt2661_softc *); 154 static int rt2661_radar_stop(struct rt2661_softc *); 155 #endif 156 static int rt2661_prepare_beacon(struct rt2661_softc *); 157 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 158 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 159 160 static const struct { 161 uint32_t reg; 162 uint32_t val; 163 } rt2661_def_mac[] = { 164 RT2661_DEF_MAC 165 }; 166 167 static const struct { 168 uint8_t reg; 169 uint8_t val; 170 } rt2661_def_bbp[] = { 171 RT2661_DEF_BBP 172 }; 173 174 static const struct rfprog { 175 uint8_t chan; 176 uint32_t r1, r2, r3, r4; 177 } rt2661_rf5225_1[] = { 178 RT2661_RF5225_1 179 }, rt2661_rf5225_2[] = { 180 RT2661_RF5225_2 181 }; 182 183 int 184 rt2661_attach(device_t dev, int id) 185 { 186 struct rt2661_softc *sc = device_get_softc(dev); 187 struct ieee80211com *ic = &sc->sc_ic; 188 struct ifnet *ifp; 189 uint32_t val; 190 const uint8_t *ucode = NULL; 191 int error, i, ac, ntries, size = 0; 192 193 sc->sc_dev = dev; 194 195 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 196 MTX_DEF | MTX_RECURSE); 197 198 callout_init(&sc->scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 199 callout_init(&sc->rssadapt_ch, CALLOUT_MPSAFE); 200 201 /* wait for NIC to initialize */ 202 for (ntries = 0; ntries < 1000; ntries++) { 203 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 204 break; 205 DELAY(1000); 206 } 207 if (ntries == 1000) { 208 device_printf(sc->sc_dev, 209 "timeout waiting for NIC to initialize\n"); 210 error = EIO; 211 goto fail1; 212 } 213 214 /* retrieve RF rev. no and various other things from EEPROM */ 215 rt2661_read_eeprom(sc); 216 217 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 218 rt2661_get_rf(sc->rf_rev)); 219 220 /* 221 * Load 8051 microcode into NIC. 222 */ 223 switch (id) { 224 case 0x0301: 225 ucode = rt2561s_ucode; 226 size = sizeof rt2561s_ucode; 227 break; 228 case 0x0302: 229 ucode = rt2561_ucode; 230 size = sizeof rt2561_ucode; 231 break; 232 case 0x0401: 233 ucode = rt2661_ucode; 234 size = sizeof rt2661_ucode; 235 break; 236 } 237 238 error = rt2661_load_microcode(sc, ucode, size); 239 if (error != 0) { 240 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 241 goto fail1; 242 } 243 244 /* 245 * Allocate Tx and Rx rings. 246 */ 247 for (ac = 0; ac < 4; ac++) { 248 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 249 RT2661_TX_RING_COUNT); 250 if (error != 0) { 251 device_printf(sc->sc_dev, 252 "could not allocate Tx ring %d\n", ac); 253 goto fail2; 254 } 255 } 256 257 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 258 if (error != 0) { 259 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 260 goto fail2; 261 } 262 263 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 264 if (error != 0) { 265 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 266 goto fail3; 267 } 268 269 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 270 if (ifp == NULL) { 271 device_printf(sc->sc_dev, "can not if_alloc()\n"); 272 error = ENOMEM; 273 goto fail4; 274 } 275 276 ifp->if_softc = sc; 277 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 279 ifp->if_init = rt2661_init; 280 ifp->if_ioctl = rt2661_ioctl; 281 ifp->if_start = rt2661_start; 282 ifp->if_watchdog = rt2661_watchdog; 283 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 284 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 ic->ic_ifp = ifp; 288 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 289 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 290 ic->ic_state = IEEE80211_S_INIT; 291 292 /* set device capabilities */ 293 ic->ic_caps = 294 IEEE80211_C_IBSS | /* IBSS mode supported */ 295 IEEE80211_C_MONITOR | /* monitor mode supported */ 296 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 297 IEEE80211_C_TXPMGT | /* tx power management */ 298 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 299 IEEE80211_C_SHSLOT | /* short slot time supported */ 300 #ifdef notyet 301 IEEE80211_C_WME | /* 802.11e */ 302 #endif 303 IEEE80211_C_WPA; /* 802.11i */ 304 305 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 306 /* set supported .11a channels */ 307 for (i = 36; i <= 64; i += 4) { 308 ic->ic_channels[i].ic_freq = 309 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 310 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 311 } 312 for (i = 100; i <= 140; i += 4) { 313 ic->ic_channels[i].ic_freq = 314 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 315 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 316 } 317 for (i = 149; i <= 165; i += 4) { 318 ic->ic_channels[i].ic_freq = 319 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 320 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 321 } 322 } 323 324 /* set supported .11b and .11g channels (1 through 14) */ 325 for (i = 1; i <= 14; i++) { 326 ic->ic_channels[i].ic_freq = 327 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 328 ic->ic_channels[i].ic_flags = 329 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 330 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 331 } 332 333 ieee80211_ifattach(ic); 334 ic->ic_node_alloc = rt2661_node_alloc; 335 /* ic->ic_wme.wme_update = rt2661_wme_update;*/ 336 ic->ic_updateslot = rt2661_update_slot; 337 ic->ic_reset = rt2661_reset; 338 /* enable s/w bmiss handling in sta mode */ 339 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 340 341 /* override state transition machine */ 342 sc->sc_newstate = ic->ic_newstate; 343 ic->ic_newstate = rt2661_newstate; 344 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 345 346 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 347 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 348 349 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 350 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 351 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 352 353 sc->sc_txtap_len = sizeof sc->sc_txtapu; 354 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 355 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 356 357 /* 358 * Add a few sysctl knobs. 359 */ 360 sc->dwelltime = 200; 361 362 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 363 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 364 CTLFLAG_RW, &sc->dwelltime, 0, 365 "channel dwell time (ms) for AP/station scanning"); 366 367 if (bootverbose) 368 ieee80211_announce(ic); 369 370 return 0; 371 372 fail4: rt2661_free_rx_ring(sc, &sc->rxq); 373 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 374 fail2: while (--ac >= 0) 375 rt2661_free_tx_ring(sc, &sc->txq[ac]); 376 fail1: mtx_destroy(&sc->sc_mtx); 377 378 return error; 379 } 380 381 int 382 rt2661_detach(void *xsc) 383 { 384 struct rt2661_softc *sc = xsc; 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct ifnet *ifp = ic->ic_ifp; 387 388 rt2661_stop(sc); 389 callout_stop(&sc->scan_ch); 390 callout_stop(&sc->rssadapt_ch); 391 392 bpfdetach(ifp); 393 ieee80211_ifdetach(ic); 394 395 rt2661_free_tx_ring(sc, &sc->txq[0]); 396 rt2661_free_tx_ring(sc, &sc->txq[1]); 397 rt2661_free_tx_ring(sc, &sc->txq[2]); 398 rt2661_free_tx_ring(sc, &sc->txq[3]); 399 rt2661_free_tx_ring(sc, &sc->mgtq); 400 rt2661_free_rx_ring(sc, &sc->rxq); 401 402 if_free(ifp); 403 404 mtx_destroy(&sc->sc_mtx); 405 406 return 0; 407 } 408 409 void 410 rt2661_shutdown(void *xsc) 411 { 412 struct rt2661_softc *sc = xsc; 413 414 rt2661_stop(sc); 415 } 416 417 void 418 rt2661_suspend(void *xsc) 419 { 420 struct rt2661_softc *sc = xsc; 421 422 rt2661_stop(sc); 423 } 424 425 void 426 rt2661_resume(void *xsc) 427 { 428 struct rt2661_softc *sc = xsc; 429 struct ifnet *ifp = sc->sc_ic.ic_ifp; 430 431 if (ifp->if_flags & IFF_UP) { 432 ifp->if_init(ifp->if_softc); 433 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 434 ifp->if_start(ifp); 435 } 436 } 437 438 static void 439 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 440 { 441 if (error != 0) 442 return; 443 444 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 445 446 *(bus_addr_t *)arg = segs[0].ds_addr; 447 } 448 449 static int 450 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 451 int count) 452 { 453 int i, error; 454 455 ring->count = count; 456 ring->queued = 0; 457 ring->cur = ring->next = ring->stat = 0; 458 459 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 460 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 461 count * RT2661_TX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 462 if (error != 0) { 463 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 464 goto fail; 465 } 466 467 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 468 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 469 if (error != 0) { 470 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 471 goto fail; 472 } 473 474 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 475 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 476 0); 477 if (error != 0) { 478 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 479 goto fail; 480 } 481 482 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 483 M_NOWAIT | M_ZERO); 484 if (ring->data == NULL) { 485 device_printf(sc->sc_dev, "could not allocate soft data\n"); 486 error = ENOMEM; 487 goto fail; 488 } 489 490 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 491 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, RT2661_MAX_SCATTER, 492 MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 493 if (error != 0) { 494 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 495 goto fail; 496 } 497 498 for (i = 0; i < count; i++) { 499 error = bus_dmamap_create(ring->data_dmat, 0, 500 &ring->data[i].map); 501 if (error != 0) { 502 device_printf(sc->sc_dev, "could not create DMA map\n"); 503 goto fail; 504 } 505 } 506 507 return 0; 508 509 fail: rt2661_free_tx_ring(sc, ring); 510 return error; 511 } 512 513 static void 514 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 515 { 516 struct rt2661_tx_desc *desc; 517 struct rt2661_tx_data *data; 518 int i; 519 520 for (i = 0; i < ring->count; i++) { 521 desc = &ring->desc[i]; 522 data = &ring->data[i]; 523 524 if (data->m != NULL) { 525 bus_dmamap_sync(ring->data_dmat, data->map, 526 BUS_DMASYNC_POSTWRITE); 527 bus_dmamap_unload(ring->data_dmat, data->map); 528 m_freem(data->m); 529 data->m = NULL; 530 } 531 532 if (data->ni != NULL) { 533 ieee80211_free_node(data->ni); 534 data->ni = NULL; 535 } 536 537 desc->flags = 0; 538 } 539 540 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 541 542 ring->queued = 0; 543 ring->cur = ring->next = ring->stat = 0; 544 } 545 546 static void 547 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 548 { 549 struct rt2661_tx_data *data; 550 int i; 551 552 if (ring->desc != NULL) { 553 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 556 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 557 } 558 559 if (ring->desc_dmat != NULL) 560 bus_dma_tag_destroy(ring->desc_dmat); 561 562 if (ring->data != NULL) { 563 for (i = 0; i < ring->count; i++) { 564 data = &ring->data[i]; 565 566 if (data->m != NULL) { 567 bus_dmamap_sync(ring->data_dmat, data->map, 568 BUS_DMASYNC_POSTWRITE); 569 bus_dmamap_unload(ring->data_dmat, data->map); 570 m_freem(data->m); 571 } 572 573 if (data->ni != NULL) 574 ieee80211_free_node(data->ni); 575 576 if (data->map != NULL) 577 bus_dmamap_destroy(ring->data_dmat, data->map); 578 } 579 580 free(ring->data, M_DEVBUF); 581 } 582 583 if (ring->data_dmat != NULL) 584 bus_dma_tag_destroy(ring->data_dmat); 585 } 586 587 static int 588 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 589 int count) 590 { 591 struct rt2661_rx_desc *desc; 592 struct rt2661_rx_data *data; 593 bus_addr_t physaddr; 594 int i, error; 595 596 ring->count = count; 597 ring->cur = ring->next = 0; 598 599 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 600 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 601 count * RT2661_RX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 602 if (error != 0) { 603 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 604 goto fail; 605 } 606 607 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 608 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 609 if (error != 0) { 610 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 611 goto fail; 612 } 613 614 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 615 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 616 0); 617 if (error != 0) { 618 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 619 goto fail; 620 } 621 622 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 623 M_NOWAIT | M_ZERO); 624 if (ring->data == NULL) { 625 device_printf(sc->sc_dev, "could not allocate soft data\n"); 626 error = ENOMEM; 627 goto fail; 628 } 629 630 /* 631 * Pre-allocate Rx buffers and populate Rx ring. 632 */ 633 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 634 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 635 NULL, &ring->data_dmat); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 638 goto fail; 639 } 640 641 for (i = 0; i < count; i++) { 642 desc = &sc->rxq.desc[i]; 643 data = &sc->rxq.data[i]; 644 645 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 646 if (error != 0) { 647 device_printf(sc->sc_dev, "could not create DMA map\n"); 648 goto fail; 649 } 650 651 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 652 if (data->m == NULL) { 653 device_printf(sc->sc_dev, 654 "could not allocate rx mbuf\n"); 655 error = ENOMEM; 656 goto fail; 657 } 658 659 error = bus_dmamap_load(ring->data_dmat, data->map, 660 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 661 &physaddr, 0); 662 if (error != 0) { 663 device_printf(sc->sc_dev, 664 "could not load rx buf DMA map"); 665 goto fail; 666 } 667 668 desc->flags = htole32(RT2661_RX_BUSY); 669 desc->physaddr = htole32(physaddr); 670 } 671 672 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 673 674 return 0; 675 676 fail: rt2661_free_rx_ring(sc, ring); 677 return error; 678 } 679 680 static void 681 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 682 { 683 int i; 684 685 for (i = 0; i < ring->count; i++) 686 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 687 688 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 689 690 ring->cur = ring->next = 0; 691 } 692 693 static void 694 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 695 { 696 struct rt2661_rx_data *data; 697 int i; 698 699 if (ring->desc != NULL) { 700 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 701 BUS_DMASYNC_POSTWRITE); 702 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 703 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 704 } 705 706 if (ring->desc_dmat != NULL) 707 bus_dma_tag_destroy(ring->desc_dmat); 708 709 if (ring->data != NULL) { 710 for (i = 0; i < ring->count; i++) { 711 data = &ring->data[i]; 712 713 if (data->m != NULL) { 714 bus_dmamap_sync(ring->data_dmat, data->map, 715 BUS_DMASYNC_POSTREAD); 716 bus_dmamap_unload(ring->data_dmat, data->map); 717 m_freem(data->m); 718 } 719 720 if (data->map != NULL) 721 bus_dmamap_destroy(ring->data_dmat, data->map); 722 } 723 724 free(ring->data, M_DEVBUF); 725 } 726 727 if (ring->data_dmat != NULL) 728 bus_dma_tag_destroy(ring->data_dmat); 729 } 730 731 static struct ieee80211_node * 732 rt2661_node_alloc(struct ieee80211_node_table *nt) 733 { 734 struct rt2661_node *rn; 735 736 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 737 M_NOWAIT | M_ZERO); 738 739 return (rn != NULL) ? &rn->ni : NULL; 740 } 741 742 static int 743 rt2661_media_change(struct ifnet *ifp) 744 { 745 struct rt2661_softc *sc = ifp->if_softc; 746 int error; 747 748 error = ieee80211_media_change(ifp); 749 if (error != ENETRESET) 750 return error; 751 752 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 753 rt2661_init(sc); 754 755 return 0; 756 } 757 758 /* 759 * This function is called periodically (every 200ms) during scanning to 760 * switch from one channel to another. 761 */ 762 static void 763 rt2661_next_scan(void *arg) 764 { 765 struct rt2661_softc *sc = arg; 766 struct ieee80211com *ic = &sc->sc_ic; 767 768 if (ic->ic_state == IEEE80211_S_SCAN) 769 ieee80211_next_scan(ic); 770 } 771 772 /* 773 * This function is called for each node present in the node station table. 774 */ 775 static void 776 rt2661_iter_func(void *arg, struct ieee80211_node *ni) 777 { 778 struct rt2661_node *rn = (struct rt2661_node *)ni; 779 780 ral_rssadapt_updatestats(&rn->rssadapt); 781 } 782 783 /* 784 * This function is called periodically (every 100ms) in RUN state to update 785 * the rate adaptation statistics. 786 */ 787 static void 788 rt2661_update_rssadapt(void *arg) 789 { 790 struct rt2661_softc *sc = arg; 791 struct ieee80211com *ic = &sc->sc_ic; 792 793 RAL_LOCK(sc); 794 795 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 796 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_update_rssadapt, sc); 797 798 RAL_UNLOCK(sc); 799 } 800 801 static int 802 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 803 { 804 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 805 enum ieee80211_state ostate; 806 struct ieee80211_node *ni; 807 uint32_t tmp; 808 int error = 0; 809 810 ostate = ic->ic_state; 811 callout_stop(&sc->scan_ch); 812 813 switch (nstate) { 814 case IEEE80211_S_INIT: 815 callout_stop(&sc->rssadapt_ch); 816 817 if (ostate == IEEE80211_S_RUN) { 818 /* abort TSF synchronization */ 819 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 820 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 821 } 822 break; 823 824 case IEEE80211_S_SCAN: 825 rt2661_set_chan(sc, ic->ic_curchan); 826 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000, 827 rt2661_next_scan, sc); 828 break; 829 830 case IEEE80211_S_AUTH: 831 case IEEE80211_S_ASSOC: 832 rt2661_set_chan(sc, ic->ic_curchan); 833 break; 834 835 case IEEE80211_S_RUN: 836 rt2661_set_chan(sc, ic->ic_curchan); 837 838 ni = ic->ic_bss; 839 840 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 841 rt2661_enable_mrr(sc); 842 rt2661_set_txpreamble(sc); 843 rt2661_set_basicrates(sc, &ni->ni_rates); 844 rt2661_set_bssid(sc, ni->ni_bssid); 845 } 846 847 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 848 ic->ic_opmode == IEEE80211_M_IBSS) { 849 if ((error = rt2661_prepare_beacon(sc)) != 0) 850 break; 851 } 852 853 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 854 callout_reset(&sc->rssadapt_ch, hz / 10, 855 rt2661_update_rssadapt, sc); 856 rt2661_enable_tsf_sync(sc); 857 } 858 break; 859 } 860 861 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 862 } 863 864 /* 865 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 866 * 93C66). 867 */ 868 static uint16_t 869 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 870 { 871 uint32_t tmp; 872 uint16_t val; 873 int n; 874 875 /* clock C once before the first command */ 876 RT2661_EEPROM_CTL(sc, 0); 877 878 RT2661_EEPROM_CTL(sc, RT2661_S); 879 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 880 RT2661_EEPROM_CTL(sc, RT2661_S); 881 882 /* write start bit (1) */ 883 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 884 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 885 886 /* write READ opcode (10) */ 887 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 888 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 889 RT2661_EEPROM_CTL(sc, RT2661_S); 890 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 891 892 /* write address (A5-A0 or A7-A0) */ 893 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 894 for (; n >= 0; n--) { 895 RT2661_EEPROM_CTL(sc, RT2661_S | 896 (((addr >> n) & 1) << RT2661_SHIFT_D)); 897 RT2661_EEPROM_CTL(sc, RT2661_S | 898 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 899 } 900 901 RT2661_EEPROM_CTL(sc, RT2661_S); 902 903 /* read data Q15-Q0 */ 904 val = 0; 905 for (n = 15; n >= 0; n--) { 906 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 907 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 908 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 909 RT2661_EEPROM_CTL(sc, RT2661_S); 910 } 911 912 RT2661_EEPROM_CTL(sc, 0); 913 914 /* clear Chip Select and clock C */ 915 RT2661_EEPROM_CTL(sc, RT2661_S); 916 RT2661_EEPROM_CTL(sc, 0); 917 RT2661_EEPROM_CTL(sc, RT2661_C); 918 919 return val; 920 } 921 922 static void 923 rt2661_tx_intr(struct rt2661_softc *sc) 924 { 925 struct ieee80211com *ic = &sc->sc_ic; 926 struct ifnet *ifp = ic->ic_ifp; 927 struct rt2661_tx_ring *txq; 928 struct rt2661_tx_data *data; 929 struct rt2661_node *rn; 930 uint32_t val; 931 int qid, retrycnt; 932 933 for (;;) { 934 val = RAL_READ(sc, RT2661_STA_CSR4); 935 if (!(val & RT2661_TX_STAT_VALID)) 936 break; 937 938 /* retrieve the queue in which this frame was sent */ 939 qid = RT2661_TX_QID(val); 940 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 941 942 /* retrieve rate control algorithm context */ 943 data = &txq->data[txq->stat]; 944 rn = (struct rt2661_node *)data->ni; 945 946 /* if no frame has been sent, ignore */ 947 if (rn == NULL) 948 continue; 949 950 switch (RT2661_TX_RESULT(val)) { 951 case RT2661_TX_SUCCESS: 952 retrycnt = RT2661_TX_RETRYCNT(val); 953 954 DPRINTFN(10, ("data frame sent successfully after " 955 "%d retries\n", retrycnt)); 956 if (retrycnt == 0 && data->id.id_node != NULL) { 957 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 958 &data->id); 959 } 960 ifp->if_opackets++; 961 break; 962 963 case RT2661_TX_RETRY_FAIL: 964 DPRINTFN(9, ("sending data frame failed (too much " 965 "retries)\n")); 966 if (data->id.id_node != NULL) { 967 ral_rssadapt_lower_rate(ic, data->ni, 968 &rn->rssadapt, &data->id); 969 } 970 ifp->if_oerrors++; 971 break; 972 973 default: 974 /* other failure */ 975 device_printf(sc->sc_dev, 976 "sending data frame failed 0x%08x\n", val); 977 ifp->if_oerrors++; 978 } 979 980 ieee80211_free_node(data->ni); 981 data->ni = NULL; 982 983 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 984 985 txq->queued--; 986 if (++txq->stat >= txq->count) /* faster than % count */ 987 txq->stat = 0; 988 } 989 990 sc->sc_tx_timer = 0; 991 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 992 rt2661_start(ifp); 993 } 994 995 static void 996 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 997 { 998 struct rt2661_tx_desc *desc; 999 struct rt2661_tx_data *data; 1000 1001 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1002 1003 for (;;) { 1004 desc = &txq->desc[txq->next]; 1005 data = &txq->data[txq->next]; 1006 1007 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1008 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1009 break; 1010 1011 bus_dmamap_sync(txq->data_dmat, data->map, 1012 BUS_DMASYNC_POSTWRITE); 1013 bus_dmamap_unload(txq->data_dmat, data->map); 1014 m_freem(data->m); 1015 data->m = NULL; 1016 /* node reference is released in rt2661_tx_intr() */ 1017 1018 /* descriptor is no longer valid */ 1019 desc->flags &= ~htole32(RT2661_TX_VALID); 1020 1021 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1022 1023 if (++txq->next >= txq->count) /* faster than % count */ 1024 txq->next = 0; 1025 } 1026 1027 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1028 } 1029 1030 static void 1031 rt2661_rx_intr(struct rt2661_softc *sc) 1032 { 1033 struct ieee80211com *ic = &sc->sc_ic; 1034 struct ifnet *ifp = ic->ic_ifp; 1035 struct rt2661_rx_desc *desc; 1036 struct rt2661_rx_data *data; 1037 bus_addr_t physaddr; 1038 struct ieee80211_frame *wh; 1039 struct ieee80211_node *ni; 1040 struct rt2661_node *rn; 1041 struct mbuf *mnew, *m; 1042 int error; 1043 1044 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1045 BUS_DMASYNC_POSTREAD); 1046 1047 for (;;) { 1048 desc = &sc->rxq.desc[sc->rxq.cur]; 1049 data = &sc->rxq.data[sc->rxq.cur]; 1050 1051 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1052 break; 1053 1054 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1055 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1056 /* 1057 * This should not happen since we did not request 1058 * to receive those frames when we filled TXRX_CSR0. 1059 */ 1060 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1061 le32toh(desc->flags))); 1062 ifp->if_ierrors++; 1063 goto skip; 1064 } 1065 1066 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1067 ifp->if_ierrors++; 1068 goto skip; 1069 } 1070 1071 /* 1072 * Try to allocate a new mbuf for this ring element and load it 1073 * before processing the current mbuf. If the ring element 1074 * cannot be loaded, drop the received packet and reuse the old 1075 * mbuf. In the unlikely case that the old mbuf can't be 1076 * reloaded either, explicitly panic. 1077 */ 1078 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1079 if (mnew == NULL) { 1080 ifp->if_ierrors++; 1081 goto skip; 1082 } 1083 1084 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1085 BUS_DMASYNC_POSTREAD); 1086 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1087 1088 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1089 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1090 &physaddr, 0); 1091 if (error != 0) { 1092 m_freem(mnew); 1093 1094 /* try to reload the old mbuf */ 1095 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1096 mtod(data->m, void *), MCLBYTES, 1097 rt2661_dma_map_addr, &physaddr, 0); 1098 if (error != 0) { 1099 /* very unlikely that it will fail... */ 1100 panic("%s: could not load old rx mbuf", 1101 device_get_name(sc->sc_dev)); 1102 } 1103 ifp->if_ierrors++; 1104 goto skip; 1105 } 1106 1107 /* 1108 * New mbuf successfully loaded, update Rx ring and continue 1109 * processing. 1110 */ 1111 m = data->m; 1112 data->m = mnew; 1113 desc->physaddr = htole32(physaddr); 1114 1115 /* finalize mbuf */ 1116 m->m_pkthdr.rcvif = ifp; 1117 m->m_pkthdr.len = m->m_len = 1118 (le32toh(desc->flags) >> 16) & 0xfff; 1119 1120 if (bpf_peers_present(sc->sc_drvbpf)) { 1121 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1122 uint32_t tsf_lo, tsf_hi; 1123 1124 /* get timestamp (low and high 32 bits) */ 1125 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1126 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1127 1128 tap->wr_tsf = 1129 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1130 tap->wr_flags = 0; 1131 tap->wr_rate = rt2661_rxrate(desc); 1132 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1133 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1134 tap->wr_antsignal = desc->rssi; 1135 1136 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1137 } 1138 1139 wh = mtod(m, struct ieee80211_frame *); 1140 ni = ieee80211_find_rxnode(ic, 1141 (struct ieee80211_frame_min *)wh); 1142 1143 /* send the frame to the 802.11 layer */ 1144 ieee80211_input(ic, m, ni, desc->rssi, 0); 1145 1146 /* give rssi to the rate adatation algorithm */ 1147 rn = (struct rt2661_node *)ni; 1148 ral_rssadapt_input(ic, ni, &rn->rssadapt, 1149 rt2661_get_rssi(sc, desc->rssi)); 1150 1151 /* node is no longer needed */ 1152 ieee80211_free_node(ni); 1153 1154 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1155 1156 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1157 1158 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1159 } 1160 1161 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1162 BUS_DMASYNC_PREWRITE); 1163 } 1164 1165 /* ARGSUSED */ 1166 static void 1167 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1168 { 1169 /* do nothing */ 1170 } 1171 1172 static void 1173 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1174 { 1175 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1176 1177 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1178 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1179 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1180 1181 /* send wakeup command to MCU */ 1182 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1183 } 1184 1185 static void 1186 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1187 { 1188 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1189 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1190 } 1191 1192 void 1193 rt2661_intr(void *arg) 1194 { 1195 struct rt2661_softc *sc = arg; 1196 struct ifnet *ifp = sc->sc_ifp; 1197 uint32_t r1, r2; 1198 1199 RAL_LOCK(sc); 1200 1201 /* disable MAC and MCU interrupts */ 1202 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1203 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1204 1205 /* don't re-enable interrupts if we're shutting down */ 1206 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1207 RAL_UNLOCK(sc); 1208 return; 1209 } 1210 1211 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1212 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1213 1214 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1215 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1216 1217 if (r1 & RT2661_MGT_DONE) 1218 rt2661_tx_dma_intr(sc, &sc->mgtq); 1219 1220 if (r1 & RT2661_RX_DONE) 1221 rt2661_rx_intr(sc); 1222 1223 if (r1 & RT2661_TX0_DMA_DONE) 1224 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1225 1226 if (r1 & RT2661_TX1_DMA_DONE) 1227 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1228 1229 if (r1 & RT2661_TX2_DMA_DONE) 1230 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1231 1232 if (r1 & RT2661_TX3_DMA_DONE) 1233 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1234 1235 if (r1 & RT2661_TX_DONE) 1236 rt2661_tx_intr(sc); 1237 1238 if (r2 & RT2661_MCU_CMD_DONE) 1239 rt2661_mcu_cmd_intr(sc); 1240 1241 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1242 rt2661_mcu_beacon_expire(sc); 1243 1244 if (r2 & RT2661_MCU_WAKEUP) 1245 rt2661_mcu_wakeup(sc); 1246 1247 /* re-enable MAC and MCU interrupts */ 1248 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1249 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1250 1251 RAL_UNLOCK(sc); 1252 } 1253 1254 /* quickly determine if a given rate is CCK or OFDM */ 1255 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1256 1257 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1258 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1259 1260 #define RAL_SIFS 10 /* us */ 1261 1262 /* 1263 * This function is only used by the Rx radiotap code. It returns the rate at 1264 * which a given frame was received. 1265 */ 1266 static uint8_t 1267 rt2661_rxrate(struct rt2661_rx_desc *desc) 1268 { 1269 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1270 /* reverse function of rt2661_plcp_signal */ 1271 switch (desc->rate & 0xf) { 1272 case 0xb: return 12; 1273 case 0xf: return 18; 1274 case 0xa: return 24; 1275 case 0xe: return 36; 1276 case 0x9: return 48; 1277 case 0xd: return 72; 1278 case 0x8: return 96; 1279 case 0xc: return 108; 1280 } 1281 } else { 1282 if (desc->rate == 10) 1283 return 2; 1284 if (desc->rate == 20) 1285 return 4; 1286 if (desc->rate == 55) 1287 return 11; 1288 if (desc->rate == 110) 1289 return 22; 1290 } 1291 return 2; /* should not get there */ 1292 } 1293 1294 /* 1295 * Return the expected ack rate for a frame transmitted at rate `rate'. 1296 * XXX: this should depend on the destination node basic rate set. 1297 */ 1298 static int 1299 rt2661_ack_rate(struct ieee80211com *ic, int rate) 1300 { 1301 switch (rate) { 1302 /* CCK rates */ 1303 case 2: 1304 return 2; 1305 case 4: 1306 case 11: 1307 case 22: 1308 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1309 1310 /* OFDM rates */ 1311 case 12: 1312 case 18: 1313 return 12; 1314 case 24: 1315 case 36: 1316 return 24; 1317 case 48: 1318 case 72: 1319 case 96: 1320 case 108: 1321 return 48; 1322 } 1323 1324 /* default to 1Mbps */ 1325 return 2; 1326 } 1327 1328 /* 1329 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1330 * The function automatically determines the operating mode depending on the 1331 * given rate. `flags' indicates whether short preamble is in use or not. 1332 */ 1333 static uint16_t 1334 rt2661_txtime(int len, int rate, uint32_t flags) 1335 { 1336 uint16_t txtime; 1337 1338 if (RAL_RATE_IS_OFDM(rate)) { 1339 /* IEEE Std 802.11a-1999, pp. 37 */ 1340 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1341 txtime = 16 + 4 + 4 * txtime + 6; 1342 } else { 1343 /* IEEE Std 802.11b-1999, pp. 28 */ 1344 txtime = (16 * len + rate - 1) / rate; 1345 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1346 txtime += 72 + 24; 1347 else 1348 txtime += 144 + 48; 1349 } 1350 1351 return txtime; 1352 } 1353 1354 static uint8_t 1355 rt2661_plcp_signal(int rate) 1356 { 1357 switch (rate) { 1358 /* CCK rates (returned values are device-dependent) */ 1359 case 2: return 0x0; 1360 case 4: return 0x1; 1361 case 11: return 0x2; 1362 case 22: return 0x3; 1363 1364 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1365 case 12: return 0xb; 1366 case 18: return 0xf; 1367 case 24: return 0xa; 1368 case 36: return 0xe; 1369 case 48: return 0x9; 1370 case 72: return 0xd; 1371 case 96: return 0x8; 1372 case 108: return 0xc; 1373 1374 /* unsupported rates (should not get there) */ 1375 default: return 0xff; 1376 } 1377 } 1378 1379 static void 1380 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1381 uint32_t flags, uint16_t xflags, int len, int rate, 1382 const bus_dma_segment_t *segs, int nsegs, int ac) 1383 { 1384 struct ieee80211com *ic = &sc->sc_ic; 1385 uint16_t plcp_length; 1386 int i, remainder; 1387 1388 desc->flags = htole32(flags); 1389 desc->flags |= htole32(len << 16); 1390 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1391 1392 desc->xflags = htole16(xflags); 1393 desc->xflags |= htole16(nsegs << 13); 1394 1395 desc->wme = htole16( 1396 RT2661_QID(ac) | 1397 RT2661_AIFSN(2) | 1398 RT2661_LOGCWMIN(4) | 1399 RT2661_LOGCWMAX(10)); 1400 1401 /* 1402 * Remember in which queue this frame was sent. This field is driver 1403 * private data only. It will be made available by the NIC in STA_CSR4 1404 * on Tx interrupts. 1405 */ 1406 desc->qid = ac; 1407 1408 /* setup PLCP fields */ 1409 desc->plcp_signal = rt2661_plcp_signal(rate); 1410 desc->plcp_service = 4; 1411 1412 len += IEEE80211_CRC_LEN; 1413 if (RAL_RATE_IS_OFDM(rate)) { 1414 desc->flags |= htole32(RT2661_TX_OFDM); 1415 1416 plcp_length = len & 0xfff; 1417 desc->plcp_length_hi = plcp_length >> 6; 1418 desc->plcp_length_lo = plcp_length & 0x3f; 1419 } else { 1420 plcp_length = (16 * len + rate - 1) / rate; 1421 if (rate == 22) { 1422 remainder = (16 * len) % 22; 1423 if (remainder != 0 && remainder < 7) 1424 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1425 } 1426 desc->plcp_length_hi = plcp_length >> 8; 1427 desc->plcp_length_lo = plcp_length & 0xff; 1428 1429 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1430 desc->plcp_signal |= 0x08; 1431 } 1432 1433 /* RT2x61 supports scatter with up to 5 segments */ 1434 for (i = 0; i < nsegs; i++) { 1435 desc->addr[i] = htole32(segs[i].ds_addr); 1436 desc->len [i] = htole16(segs[i].ds_len); 1437 } 1438 } 1439 1440 static int 1441 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1442 struct ieee80211_node *ni) 1443 { 1444 struct ieee80211com *ic = &sc->sc_ic; 1445 struct rt2661_tx_desc *desc; 1446 struct rt2661_tx_data *data; 1447 struct ieee80211_frame *wh; 1448 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1449 uint16_t dur; 1450 uint32_t flags = 0; /* XXX HWSEQ */ 1451 int nsegs, rate, error; 1452 1453 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1454 data = &sc->mgtq.data[sc->mgtq.cur]; 1455 1456 /* send mgt frames at the lowest available rate */ 1457 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1458 1459 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1460 segs, &nsegs, 0); 1461 if (error != 0) { 1462 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1463 error); 1464 m_freem(m0); 1465 return error; 1466 } 1467 1468 if (bpf_peers_present(sc->sc_drvbpf)) { 1469 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1470 1471 tap->wt_flags = 0; 1472 tap->wt_rate = rate; 1473 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1474 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1475 1476 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1477 } 1478 1479 data->m = m0; 1480 data->ni = ni; 1481 1482 wh = mtod(m0, struct ieee80211_frame *); 1483 1484 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1485 flags |= RT2661_TX_NEED_ACK; 1486 1487 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1488 RAL_SIFS; 1489 *(uint16_t *)wh->i_dur = htole16(dur); 1490 1491 /* tell hardware to add timestamp in probe responses */ 1492 if ((wh->i_fc[0] & 1493 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1494 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1495 flags |= RT2661_TX_TIMESTAMP; 1496 } 1497 1498 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1499 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1500 1501 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1502 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1503 BUS_DMASYNC_PREWRITE); 1504 1505 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1506 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1507 1508 /* kick mgt */ 1509 sc->mgtq.queued++; 1510 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1511 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1512 1513 return 0; 1514 } 1515 1516 /* 1517 * Build a RTS control frame. 1518 */ 1519 static struct mbuf * 1520 rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1521 uint16_t dur) 1522 { 1523 struct ieee80211_frame_rts *rts; 1524 struct mbuf *m; 1525 1526 MGETHDR(m, M_DONTWAIT, MT_DATA); 1527 if (m == NULL) { 1528 sc->sc_ic.ic_stats.is_tx_nobuf++; 1529 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1530 return NULL; 1531 } 1532 1533 rts = mtod(m, struct ieee80211_frame_rts *); 1534 1535 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1536 IEEE80211_FC0_SUBTYPE_RTS; 1537 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1538 *(uint16_t *)rts->i_dur = htole16(dur); 1539 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1540 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1541 1542 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1543 1544 return m; 1545 } 1546 1547 static int 1548 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1549 struct ieee80211_node *ni, int ac) 1550 { 1551 struct ieee80211com *ic = &sc->sc_ic; 1552 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1553 struct rt2661_tx_desc *desc; 1554 struct rt2661_tx_data *data; 1555 struct rt2661_node *rn; 1556 struct ieee80211_rateset *rs; 1557 struct ieee80211_frame *wh; 1558 struct ieee80211_key *k; 1559 const struct chanAccParams *cap; 1560 struct mbuf *mnew; 1561 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1562 uint16_t dur; 1563 uint32_t flags = 0; 1564 int error, nsegs, rate, noack = 0; 1565 1566 wh = mtod(m0, struct ieee80211_frame *); 1567 1568 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1569 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1570 rate = rs->rs_rates[ic->ic_fixed_rate]; 1571 } else { 1572 rs = &ni->ni_rates; 1573 rn = (struct rt2661_node *)ni; 1574 ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, 1575 wh, m0->m_pkthdr.len, NULL, 0); 1576 rate = rs->rs_rates[ni->ni_txrate]; 1577 } 1578 rate &= IEEE80211_RATE_VAL; 1579 1580 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1581 cap = &ic->ic_wme.wme_chanParams; 1582 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1583 } 1584 1585 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1586 k = ieee80211_crypto_encap(ic, ni, m0); 1587 if (k == NULL) { 1588 m_freem(m0); 1589 return ENOBUFS; 1590 } 1591 1592 /* packet header may have moved, reset our local pointer */ 1593 wh = mtod(m0, struct ieee80211_frame *); 1594 } 1595 1596 /* 1597 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1598 * for directed frames only when the length of the MPDU is greater 1599 * than the length threshold indicated by [...]" ic_rtsthreshold. 1600 */ 1601 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1602 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1603 struct mbuf *m; 1604 uint16_t dur; 1605 int rtsrate, ackrate; 1606 1607 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1608 ackrate = rt2661_ack_rate(ic, rate); 1609 1610 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1611 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1612 /* XXX: noack (QoS)? */ 1613 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1614 3 * RAL_SIFS; 1615 1616 m = rt2661_get_rts(sc, wh, dur); 1617 1618 desc = &txq->desc[txq->cur]; 1619 data = &txq->data[txq->cur]; 1620 1621 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m, 1622 segs, &nsegs, 0); 1623 if (error != 0) { 1624 device_printf(sc->sc_dev, 1625 "could not map mbuf (error %d)\n", error); 1626 m_freem(m); 1627 m_freem(m0); 1628 return error; 1629 } 1630 1631 /* avoid multiple free() of the same node for each fragment */ 1632 ieee80211_ref_node(ni); 1633 1634 data->m = m; 1635 data->ni = ni; 1636 1637 /* RTS frames are not taken into account for rssadapt */ 1638 data->id.id_node = NULL; 1639 1640 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1641 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, segs, 1642 nsegs, ac); 1643 1644 bus_dmamap_sync(txq->data_dmat, data->map, 1645 BUS_DMASYNC_PREWRITE); 1646 1647 txq->queued++; 1648 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1649 1650 /* 1651 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1652 * asynchronous data frame shall be transmitted after the CTS 1653 * frame and a SIFS period. 1654 */ 1655 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1656 } 1657 1658 data = &txq->data[txq->cur]; 1659 desc = &txq->desc[txq->cur]; 1660 1661 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1662 &nsegs, 0); 1663 if (error != 0 && error != EFBIG) { 1664 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1665 error); 1666 m_freem(m0); 1667 return error; 1668 } 1669 if (error != 0) { 1670 mnew = m_defrag(m0, M_DONTWAIT); 1671 if (mnew == NULL) { 1672 device_printf(sc->sc_dev, 1673 "could not defragment mbuf\n"); 1674 m_freem(m0); 1675 return ENOBUFS; 1676 } 1677 m0 = mnew; 1678 1679 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1680 segs, &nsegs, 0); 1681 if (error != 0) { 1682 device_printf(sc->sc_dev, 1683 "could not map mbuf (error %d)\n", error); 1684 m_freem(m0); 1685 return error; 1686 } 1687 1688 /* packet header have moved, reset our local pointer */ 1689 wh = mtod(m0, struct ieee80211_frame *); 1690 } 1691 1692 if (bpf_peers_present(sc->sc_drvbpf)) { 1693 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1694 1695 tap->wt_flags = 0; 1696 tap->wt_rate = rate; 1697 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1698 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1699 1700 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1701 } 1702 1703 data->m = m0; 1704 data->ni = ni; 1705 1706 /* remember link conditions for rate adaptation algorithm */ 1707 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1708 data->id.id_len = m0->m_pkthdr.len; 1709 data->id.id_rateidx = ni->ni_txrate; 1710 data->id.id_node = ni; 1711 data->id.id_rssi = ni->ni_rssi; 1712 } else 1713 data->id.id_node = NULL; 1714 1715 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1716 flags |= RT2661_TX_NEED_ACK; 1717 1718 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1719 ic->ic_flags) + RAL_SIFS; 1720 *(uint16_t *)wh->i_dur = htole16(dur); 1721 } 1722 1723 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1724 nsegs, ac); 1725 1726 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1727 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1728 1729 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1730 m0->m_pkthdr.len, txq->cur, rate)); 1731 1732 /* kick Tx */ 1733 txq->queued++; 1734 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1735 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1736 1737 return 0; 1738 } 1739 1740 static void 1741 rt2661_start(struct ifnet *ifp) 1742 { 1743 struct rt2661_softc *sc = ifp->if_softc; 1744 struct ieee80211com *ic = &sc->sc_ic; 1745 struct mbuf *m0; 1746 struct ether_header *eh; 1747 struct ieee80211_node *ni; 1748 int ac; 1749 1750 RAL_LOCK(sc); 1751 1752 /* prevent management frames from being sent if we're not ready */ 1753 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1754 RAL_UNLOCK(sc); 1755 return; 1756 } 1757 1758 for (;;) { 1759 IF_POLL(&ic->ic_mgtq, m0); 1760 if (m0 != NULL) { 1761 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1762 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1763 break; 1764 } 1765 IF_DEQUEUE(&ic->ic_mgtq, m0); 1766 1767 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1768 m0->m_pkthdr.rcvif = NULL; 1769 1770 if (bpf_peers_present(ic->ic_rawbpf)) 1771 bpf_mtap(ic->ic_rawbpf, m0); 1772 1773 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1774 break; 1775 1776 } else { 1777 if (ic->ic_state != IEEE80211_S_RUN) 1778 break; 1779 1780 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1781 if (m0 == NULL) 1782 break; 1783 1784 if (m0->m_len < sizeof (struct ether_header) && 1785 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1786 continue; 1787 1788 eh = mtod(m0, struct ether_header *); 1789 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1790 if (ni == NULL) { 1791 m_freem(m0); 1792 ifp->if_oerrors++; 1793 continue; 1794 } 1795 1796 /* classify mbuf so we can find which tx ring to use */ 1797 if (ieee80211_classify(ic, m0, ni) != 0) { 1798 m_freem(m0); 1799 ieee80211_free_node(ni); 1800 ifp->if_oerrors++; 1801 continue; 1802 } 1803 1804 /* no QoS encapsulation for EAPOL frames */ 1805 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1806 M_WME_GETAC(m0) : WME_AC_BE; 1807 1808 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1809 /* there is no place left in this ring */ 1810 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1811 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1812 break; 1813 } 1814 1815 BPF_MTAP(ifp, m0); 1816 1817 m0 = ieee80211_encap(ic, m0, ni); 1818 if (m0 == NULL) { 1819 ieee80211_free_node(ni); 1820 ifp->if_oerrors++; 1821 continue; 1822 } 1823 1824 if (bpf_peers_present(ic->ic_rawbpf)) 1825 bpf_mtap(ic->ic_rawbpf, m0); 1826 1827 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1828 ieee80211_free_node(ni); 1829 ifp->if_oerrors++; 1830 break; 1831 } 1832 } 1833 1834 sc->sc_tx_timer = 5; 1835 ifp->if_timer = 1; 1836 } 1837 1838 RAL_UNLOCK(sc); 1839 } 1840 1841 static void 1842 rt2661_watchdog(struct ifnet *ifp) 1843 { 1844 struct rt2661_softc *sc = ifp->if_softc; 1845 struct ieee80211com *ic = &sc->sc_ic; 1846 1847 RAL_LOCK(sc); 1848 1849 ifp->if_timer = 0; 1850 1851 if (sc->sc_tx_timer > 0) { 1852 if (--sc->sc_tx_timer == 0) { 1853 device_printf(sc->sc_dev, "device timeout\n"); 1854 rt2661_init(sc); 1855 ifp->if_oerrors++; 1856 RAL_UNLOCK(sc); 1857 return; 1858 } 1859 ifp->if_timer = 1; 1860 } 1861 1862 ieee80211_watchdog(ic); 1863 1864 RAL_UNLOCK(sc); 1865 } 1866 1867 /* 1868 * This function allows for fast channel switching in monitor mode (used by 1869 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 1870 * generate a new beacon frame. 1871 */ 1872 static int 1873 rt2661_reset(struct ifnet *ifp) 1874 { 1875 struct rt2661_softc *sc = ifp->if_softc; 1876 struct ieee80211com *ic = &sc->sc_ic; 1877 1878 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1879 return ENETRESET; 1880 1881 rt2661_set_chan(sc, ic->ic_curchan); 1882 1883 return 0; 1884 } 1885 1886 static int 1887 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1888 { 1889 struct rt2661_softc *sc = ifp->if_softc; 1890 struct ieee80211com *ic = &sc->sc_ic; 1891 int error = 0; 1892 1893 RAL_LOCK(sc); 1894 1895 switch (cmd) { 1896 case SIOCSIFFLAGS: 1897 if (ifp->if_flags & IFF_UP) { 1898 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1899 rt2661_update_promisc(sc); 1900 else 1901 rt2661_init(sc); 1902 } else { 1903 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1904 rt2661_stop(sc); 1905 } 1906 break; 1907 1908 default: 1909 error = ieee80211_ioctl(ic, cmd, data); 1910 } 1911 1912 if (error == ENETRESET) { 1913 if ((ifp->if_flags & IFF_UP) && 1914 (ifp->if_drv_flags & IFF_DRV_RUNNING) && 1915 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1916 rt2661_init(sc); 1917 error = 0; 1918 } 1919 1920 RAL_UNLOCK(sc); 1921 1922 return error; 1923 } 1924 1925 static void 1926 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1927 { 1928 uint32_t tmp; 1929 int ntries; 1930 1931 for (ntries = 0; ntries < 100; ntries++) { 1932 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1933 break; 1934 DELAY(1); 1935 } 1936 if (ntries == 100) { 1937 device_printf(sc->sc_dev, "could not write to BBP\n"); 1938 return; 1939 } 1940 1941 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1942 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1943 1944 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1945 } 1946 1947 static uint8_t 1948 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1949 { 1950 uint32_t val; 1951 int ntries; 1952 1953 for (ntries = 0; ntries < 100; ntries++) { 1954 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1955 break; 1956 DELAY(1); 1957 } 1958 if (ntries == 100) { 1959 device_printf(sc->sc_dev, "could not read from BBP\n"); 1960 return 0; 1961 } 1962 1963 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1964 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1965 1966 for (ntries = 0; ntries < 100; ntries++) { 1967 val = RAL_READ(sc, RT2661_PHY_CSR3); 1968 if (!(val & RT2661_BBP_BUSY)) 1969 return val & 0xff; 1970 DELAY(1); 1971 } 1972 1973 device_printf(sc->sc_dev, "could not read from BBP\n"); 1974 return 0; 1975 } 1976 1977 static void 1978 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1979 { 1980 uint32_t tmp; 1981 int ntries; 1982 1983 for (ntries = 0; ntries < 100; ntries++) { 1984 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1985 break; 1986 DELAY(1); 1987 } 1988 if (ntries == 100) { 1989 device_printf(sc->sc_dev, "could not write to RF\n"); 1990 return; 1991 } 1992 1993 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1994 (reg & 3); 1995 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1996 1997 /* remember last written value in sc */ 1998 sc->rf_regs[reg] = val; 1999 2000 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2001 } 2002 2003 static int 2004 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2005 { 2006 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2007 return EIO; /* there is already a command pending */ 2008 2009 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2010 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2011 2012 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2013 2014 return 0; 2015 } 2016 2017 static void 2018 rt2661_select_antenna(struct rt2661_softc *sc) 2019 { 2020 uint8_t bbp4, bbp77; 2021 uint32_t tmp; 2022 2023 bbp4 = rt2661_bbp_read(sc, 4); 2024 bbp77 = rt2661_bbp_read(sc, 77); 2025 2026 /* TBD */ 2027 2028 /* make sure Rx is disabled before switching antenna */ 2029 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2030 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2031 2032 rt2661_bbp_write(sc, 4, bbp4); 2033 rt2661_bbp_write(sc, 77, bbp77); 2034 2035 /* restore Rx filter */ 2036 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2037 } 2038 2039 /* 2040 * Enable multi-rate retries for frames sent at OFDM rates. 2041 * In 802.11b/g mode, allow fallback to CCK rates. 2042 */ 2043 static void 2044 rt2661_enable_mrr(struct rt2661_softc *sc) 2045 { 2046 struct ieee80211com *ic = &sc->sc_ic; 2047 uint32_t tmp; 2048 2049 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2050 2051 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2052 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2053 tmp |= RT2661_MRR_CCK_FALLBACK; 2054 tmp |= RT2661_MRR_ENABLED; 2055 2056 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2057 } 2058 2059 static void 2060 rt2661_set_txpreamble(struct rt2661_softc *sc) 2061 { 2062 uint32_t tmp; 2063 2064 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2065 2066 tmp &= ~RT2661_SHORT_PREAMBLE; 2067 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2068 tmp |= RT2661_SHORT_PREAMBLE; 2069 2070 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2071 } 2072 2073 static void 2074 rt2661_set_basicrates(struct rt2661_softc *sc, 2075 const struct ieee80211_rateset *rs) 2076 { 2077 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2078 struct ieee80211com *ic = &sc->sc_ic; 2079 uint32_t mask = 0; 2080 uint8_t rate; 2081 int i, j; 2082 2083 for (i = 0; i < rs->rs_nrates; i++) { 2084 rate = rs->rs_rates[i]; 2085 2086 if (!(rate & IEEE80211_RATE_BASIC)) 2087 continue; 2088 2089 /* 2090 * Find h/w rate index. We know it exists because the rate 2091 * set has already been negotiated. 2092 */ 2093 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 2094 2095 mask |= 1 << j; 2096 } 2097 2098 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2099 2100 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2101 #undef RV 2102 } 2103 2104 /* 2105 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2106 * driver. 2107 */ 2108 static void 2109 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2110 { 2111 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2112 uint32_t tmp; 2113 2114 /* update all BBP registers that depend on the band */ 2115 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2116 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2117 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2118 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2119 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2120 } 2121 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2122 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2123 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2124 } 2125 2126 rt2661_bbp_write(sc, 17, bbp17); 2127 rt2661_bbp_write(sc, 96, bbp96); 2128 rt2661_bbp_write(sc, 104, bbp104); 2129 2130 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2131 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2132 rt2661_bbp_write(sc, 75, 0x80); 2133 rt2661_bbp_write(sc, 86, 0x80); 2134 rt2661_bbp_write(sc, 88, 0x80); 2135 } 2136 2137 rt2661_bbp_write(sc, 35, bbp35); 2138 rt2661_bbp_write(sc, 97, bbp97); 2139 rt2661_bbp_write(sc, 98, bbp98); 2140 2141 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2142 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2143 if (IEEE80211_IS_CHAN_2GHZ(c)) 2144 tmp |= RT2661_PA_PE_2GHZ; 2145 else 2146 tmp |= RT2661_PA_PE_5GHZ; 2147 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2148 } 2149 2150 static void 2151 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2152 { 2153 struct ieee80211com *ic = &sc->sc_ic; 2154 const struct rfprog *rfprog; 2155 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2156 int8_t power; 2157 u_int i, chan; 2158 2159 chan = ieee80211_chan2ieee(ic, c); 2160 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2161 return; 2162 2163 /* select the appropriate RF settings based on what EEPROM says */ 2164 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2165 2166 /* find the settings for this channel (we know it exists) */ 2167 for (i = 0; rfprog[i].chan != chan; i++); 2168 2169 power = sc->txpow[i]; 2170 if (power < 0) { 2171 bbp94 += power; 2172 power = 0; 2173 } else if (power > 31) { 2174 bbp94 += power - 31; 2175 power = 31; 2176 } 2177 2178 /* 2179 * If we are switching from the 2GHz band to the 5GHz band or 2180 * vice-versa, BBP registers need to be reprogrammed. 2181 */ 2182 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2183 rt2661_select_band(sc, c); 2184 rt2661_select_antenna(sc); 2185 } 2186 sc->sc_curchan = c; 2187 2188 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2189 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2190 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2191 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2192 2193 DELAY(200); 2194 2195 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2196 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2197 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2198 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2199 2200 DELAY(200); 2201 2202 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2203 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2204 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2205 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2206 2207 /* enable smart mode for MIMO-capable RFs */ 2208 bbp3 = rt2661_bbp_read(sc, 3); 2209 2210 bbp3 &= ~RT2661_SMART_MODE; 2211 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2212 bbp3 |= RT2661_SMART_MODE; 2213 2214 rt2661_bbp_write(sc, 3, bbp3); 2215 2216 if (bbp94 != RT2661_BBPR94_DEFAULT) 2217 rt2661_bbp_write(sc, 94, bbp94); 2218 2219 /* 5GHz radio needs a 1ms delay here */ 2220 if (IEEE80211_IS_CHAN_5GHZ(c)) 2221 DELAY(1000); 2222 } 2223 2224 static void 2225 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2226 { 2227 uint32_t tmp; 2228 2229 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2230 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2231 2232 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2233 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2234 } 2235 2236 static void 2237 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2238 { 2239 uint32_t tmp; 2240 2241 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2242 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2243 2244 tmp = addr[4] | addr[5] << 8; 2245 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2246 } 2247 2248 static void 2249 rt2661_update_promisc(struct rt2661_softc *sc) 2250 { 2251 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2252 uint32_t tmp; 2253 2254 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2255 2256 tmp &= ~RT2661_DROP_NOT_TO_ME; 2257 if (!(ifp->if_flags & IFF_PROMISC)) 2258 tmp |= RT2661_DROP_NOT_TO_ME; 2259 2260 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2261 2262 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2263 "entering" : "leaving")); 2264 } 2265 2266 /* 2267 * Update QoS (802.11e) settings for each h/w Tx ring. 2268 */ 2269 static int 2270 rt2661_wme_update(struct ieee80211com *ic) 2271 { 2272 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2273 const struct wmeParams *wmep; 2274 2275 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2276 2277 /* XXX: not sure about shifts. */ 2278 /* XXX: the reference driver plays with AC_VI settings too. */ 2279 2280 /* update TxOp */ 2281 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2282 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2283 wmep[WME_AC_BK].wmep_txopLimit); 2284 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2285 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2286 wmep[WME_AC_VO].wmep_txopLimit); 2287 2288 /* update CWmin */ 2289 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2290 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2291 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2292 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2293 wmep[WME_AC_VO].wmep_logcwmin); 2294 2295 /* update CWmax */ 2296 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2297 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2298 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2299 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2300 wmep[WME_AC_VO].wmep_logcwmax); 2301 2302 /* update Aifsn */ 2303 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2304 wmep[WME_AC_BE].wmep_aifsn << 12 | 2305 wmep[WME_AC_BK].wmep_aifsn << 8 | 2306 wmep[WME_AC_VI].wmep_aifsn << 4 | 2307 wmep[WME_AC_VO].wmep_aifsn); 2308 2309 return 0; 2310 } 2311 2312 static void 2313 rt2661_update_slot(struct ifnet *ifp) 2314 { 2315 struct rt2661_softc *sc = ifp->if_softc; 2316 struct ieee80211com *ic = &sc->sc_ic; 2317 uint8_t slottime; 2318 uint32_t tmp; 2319 2320 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2321 2322 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2323 tmp = (tmp & ~0xff) | slottime; 2324 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2325 } 2326 2327 static const char * 2328 rt2661_get_rf(int rev) 2329 { 2330 switch (rev) { 2331 case RT2661_RF_5225: return "RT5225"; 2332 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2333 case RT2661_RF_2527: return "RT2527"; 2334 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2335 default: return "unknown"; 2336 } 2337 } 2338 2339 static void 2340 rt2661_read_eeprom(struct rt2661_softc *sc) 2341 { 2342 struct ieee80211com *ic = &sc->sc_ic; 2343 uint16_t val; 2344 int i; 2345 2346 /* read MAC address */ 2347 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2348 ic->ic_myaddr[0] = val & 0xff; 2349 ic->ic_myaddr[1] = val >> 8; 2350 2351 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2352 ic->ic_myaddr[2] = val & 0xff; 2353 ic->ic_myaddr[3] = val >> 8; 2354 2355 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2356 ic->ic_myaddr[4] = val & 0xff; 2357 ic->ic_myaddr[5] = val >> 8; 2358 2359 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2360 /* XXX: test if different from 0xffff? */ 2361 sc->rf_rev = (val >> 11) & 0x1f; 2362 sc->hw_radio = (val >> 10) & 0x1; 2363 sc->rx_ant = (val >> 4) & 0x3; 2364 sc->tx_ant = (val >> 2) & 0x3; 2365 sc->nb_ant = val & 0x3; 2366 2367 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2368 2369 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2370 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2371 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2372 2373 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2374 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2375 2376 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2377 if ((val & 0xff) != 0xff) 2378 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2379 2380 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2381 if ((val & 0xff) != 0xff) 2382 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2383 2384 /* adjust RSSI correction for external low-noise amplifier */ 2385 if (sc->ext_2ghz_lna) 2386 sc->rssi_2ghz_corr -= 14; 2387 if (sc->ext_5ghz_lna) 2388 sc->rssi_5ghz_corr -= 14; 2389 2390 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2391 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2392 2393 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2394 if ((val >> 8) != 0xff) 2395 sc->rfprog = (val >> 8) & 0x3; 2396 if ((val & 0xff) != 0xff) 2397 sc->rffreq = val & 0xff; 2398 2399 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2400 2401 /* read Tx power for all a/b/g channels */ 2402 for (i = 0; i < 19; i++) { 2403 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2404 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2405 DPRINTF(("Channel=%d Tx power=%d\n", 2406 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2407 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2408 DPRINTF(("Channel=%d Tx power=%d\n", 2409 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2410 } 2411 2412 /* read vendor-specific BBP values */ 2413 for (i = 0; i < 16; i++) { 2414 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2415 if (val == 0 || val == 0xffff) 2416 continue; /* skip invalid entries */ 2417 sc->bbp_prom[i].reg = val >> 8; 2418 sc->bbp_prom[i].val = val & 0xff; 2419 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2420 sc->bbp_prom[i].val)); 2421 } 2422 } 2423 2424 static int 2425 rt2661_bbp_init(struct rt2661_softc *sc) 2426 { 2427 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2428 int i, ntries; 2429 uint8_t val; 2430 2431 /* wait for BBP to be ready */ 2432 for (ntries = 0; ntries < 100; ntries++) { 2433 val = rt2661_bbp_read(sc, 0); 2434 if (val != 0 && val != 0xff) 2435 break; 2436 DELAY(100); 2437 } 2438 if (ntries == 100) { 2439 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2440 return EIO; 2441 } 2442 2443 /* initialize BBP registers to default values */ 2444 for (i = 0; i < N(rt2661_def_bbp); i++) { 2445 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2446 rt2661_def_bbp[i].val); 2447 } 2448 2449 /* write vendor-specific BBP values (from EEPROM) */ 2450 for (i = 0; i < 16; i++) { 2451 if (sc->bbp_prom[i].reg == 0) 2452 continue; 2453 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2454 } 2455 2456 return 0; 2457 #undef N 2458 } 2459 2460 static void 2461 rt2661_init(void *priv) 2462 { 2463 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2464 struct rt2661_softc *sc = priv; 2465 struct ieee80211com *ic = &sc->sc_ic; 2466 struct ifnet *ifp = ic->ic_ifp; 2467 uint32_t tmp, sta[3]; 2468 int i, ntries; 2469 2470 RAL_LOCK(sc); 2471 2472 rt2661_stop(sc); 2473 2474 /* initialize Tx rings */ 2475 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2476 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2477 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2478 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2479 2480 /* initialize Mgt ring */ 2481 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2482 2483 /* initialize Rx ring */ 2484 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2485 2486 /* initialize Tx rings sizes */ 2487 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2488 RT2661_TX_RING_COUNT << 24 | 2489 RT2661_TX_RING_COUNT << 16 | 2490 RT2661_TX_RING_COUNT << 8 | 2491 RT2661_TX_RING_COUNT); 2492 2493 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2494 RT2661_TX_DESC_WSIZE << 16 | 2495 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2496 RT2661_MGT_RING_COUNT); 2497 2498 /* initialize Rx rings */ 2499 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2500 RT2661_RX_DESC_BACK << 16 | 2501 RT2661_RX_DESC_WSIZE << 8 | 2502 RT2661_RX_RING_COUNT); 2503 2504 /* XXX: some magic here */ 2505 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2506 2507 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2508 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2509 2510 /* load base address of Rx ring */ 2511 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2512 2513 /* initialize MAC registers to default values */ 2514 for (i = 0; i < N(rt2661_def_mac); i++) 2515 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2516 2517 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2518 rt2661_set_macaddr(sc, ic->ic_myaddr); 2519 2520 /* set host ready */ 2521 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2522 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2523 2524 /* wait for BBP/RF to wakeup */ 2525 for (ntries = 0; ntries < 1000; ntries++) { 2526 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2527 break; 2528 DELAY(1000); 2529 } 2530 if (ntries == 1000) { 2531 printf("timeout waiting for BBP/RF to wakeup\n"); 2532 rt2661_stop(sc); 2533 RAL_UNLOCK(sc); 2534 return; 2535 } 2536 2537 if (rt2661_bbp_init(sc) != 0) { 2538 rt2661_stop(sc); 2539 RAL_UNLOCK(sc); 2540 return; 2541 } 2542 2543 /* select default channel */ 2544 sc->sc_curchan = ic->ic_curchan; 2545 rt2661_select_band(sc, sc->sc_curchan); 2546 rt2661_select_antenna(sc); 2547 rt2661_set_chan(sc, sc->sc_curchan); 2548 2549 /* update Rx filter */ 2550 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2551 2552 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2553 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2554 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2555 RT2661_DROP_ACKCTS; 2556 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2557 tmp |= RT2661_DROP_TODS; 2558 if (!(ifp->if_flags & IFF_PROMISC)) 2559 tmp |= RT2661_DROP_NOT_TO_ME; 2560 } 2561 2562 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2563 2564 /* clear STA registers */ 2565 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2566 2567 /* initialize ASIC */ 2568 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2569 2570 /* clear any pending interrupt */ 2571 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2572 2573 /* enable interrupts */ 2574 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2575 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2576 2577 /* kick Rx */ 2578 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2579 2580 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2581 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2582 2583 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2584 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2585 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2586 } else 2587 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2588 2589 RAL_UNLOCK(sc); 2590 #undef N 2591 } 2592 2593 void 2594 rt2661_stop(void *priv) 2595 { 2596 struct rt2661_softc *sc = priv; 2597 struct ieee80211com *ic = &sc->sc_ic; 2598 struct ifnet *ifp = ic->ic_ifp; 2599 uint32_t tmp; 2600 2601 sc->sc_tx_timer = 0; 2602 ifp->if_timer = 0; 2603 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2604 2605 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2606 2607 /* abort Tx (for all 5 Tx rings) */ 2608 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2609 2610 /* disable Rx (value remains after reset!) */ 2611 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2612 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2613 2614 /* reset ASIC */ 2615 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2616 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2617 2618 /* disable interrupts */ 2619 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2620 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2621 2622 /* clear any pending interrupt */ 2623 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2624 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2625 2626 /* reset Tx and Rx rings */ 2627 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2628 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2629 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2630 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2631 rt2661_reset_tx_ring(sc, &sc->mgtq); 2632 rt2661_reset_rx_ring(sc, &sc->rxq); 2633 } 2634 2635 static int 2636 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2637 { 2638 int ntries; 2639 2640 /* reset 8051 */ 2641 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2642 2643 /* cancel any pending Host to MCU command */ 2644 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2645 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2646 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2647 2648 /* write 8051's microcode */ 2649 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2650 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2651 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2652 2653 /* kick 8051's ass */ 2654 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2655 2656 /* wait for 8051 to initialize */ 2657 for (ntries = 0; ntries < 500; ntries++) { 2658 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2659 break; 2660 DELAY(100); 2661 } 2662 if (ntries == 500) { 2663 printf("timeout waiting for MCU to initialize\n"); 2664 return EIO; 2665 } 2666 return 0; 2667 } 2668 2669 #ifdef notyet 2670 /* 2671 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2672 * false CCA count. This function is called periodically (every seconds) when 2673 * in the RUN state. Values taken from the reference driver. 2674 */ 2675 static void 2676 rt2661_rx_tune(struct rt2661_softc *sc) 2677 { 2678 uint8_t bbp17; 2679 uint16_t cca; 2680 int lo, hi, dbm; 2681 2682 /* 2683 * Tuning range depends on operating band and on the presence of an 2684 * external low-noise amplifier. 2685 */ 2686 lo = 0x20; 2687 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2688 lo += 0x08; 2689 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2690 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2691 lo += 0x10; 2692 hi = lo + 0x20; 2693 2694 /* retrieve false CCA count since last call (clear on read) */ 2695 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2696 2697 if (dbm >= -35) { 2698 bbp17 = 0x60; 2699 } else if (dbm >= -58) { 2700 bbp17 = hi; 2701 } else if (dbm >= -66) { 2702 bbp17 = lo + 0x10; 2703 } else if (dbm >= -74) { 2704 bbp17 = lo + 0x08; 2705 } else { 2706 /* RSSI < -74dBm, tune using false CCA count */ 2707 2708 bbp17 = sc->bbp17; /* current value */ 2709 2710 hi -= 2 * (-74 - dbm); 2711 if (hi < lo) 2712 hi = lo; 2713 2714 if (bbp17 > hi) { 2715 bbp17 = hi; 2716 2717 } else if (cca > 512) { 2718 if (++bbp17 > hi) 2719 bbp17 = hi; 2720 } else if (cca < 100) { 2721 if (--bbp17 < lo) 2722 bbp17 = lo; 2723 } 2724 } 2725 2726 if (bbp17 != sc->bbp17) { 2727 rt2661_bbp_write(sc, 17, bbp17); 2728 sc->bbp17 = bbp17; 2729 } 2730 } 2731 2732 /* 2733 * Enter/Leave radar detection mode. 2734 * This is for 802.11h additional regulatory domains. 2735 */ 2736 static void 2737 rt2661_radar_start(struct rt2661_softc *sc) 2738 { 2739 uint32_t tmp; 2740 2741 /* disable Rx */ 2742 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2743 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2744 2745 rt2661_bbp_write(sc, 82, 0x20); 2746 rt2661_bbp_write(sc, 83, 0x00); 2747 rt2661_bbp_write(sc, 84, 0x40); 2748 2749 /* save current BBP registers values */ 2750 sc->bbp18 = rt2661_bbp_read(sc, 18); 2751 sc->bbp21 = rt2661_bbp_read(sc, 21); 2752 sc->bbp22 = rt2661_bbp_read(sc, 22); 2753 sc->bbp16 = rt2661_bbp_read(sc, 16); 2754 sc->bbp17 = rt2661_bbp_read(sc, 17); 2755 sc->bbp64 = rt2661_bbp_read(sc, 64); 2756 2757 rt2661_bbp_write(sc, 18, 0xff); 2758 rt2661_bbp_write(sc, 21, 0x3f); 2759 rt2661_bbp_write(sc, 22, 0x3f); 2760 rt2661_bbp_write(sc, 16, 0xbd); 2761 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2762 rt2661_bbp_write(sc, 64, 0x21); 2763 2764 /* restore Rx filter */ 2765 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2766 } 2767 2768 static int 2769 rt2661_radar_stop(struct rt2661_softc *sc) 2770 { 2771 uint8_t bbp66; 2772 2773 /* read radar detection result */ 2774 bbp66 = rt2661_bbp_read(sc, 66); 2775 2776 /* restore BBP registers values */ 2777 rt2661_bbp_write(sc, 16, sc->bbp16); 2778 rt2661_bbp_write(sc, 17, sc->bbp17); 2779 rt2661_bbp_write(sc, 18, sc->bbp18); 2780 rt2661_bbp_write(sc, 21, sc->bbp21); 2781 rt2661_bbp_write(sc, 22, sc->bbp22); 2782 rt2661_bbp_write(sc, 64, sc->bbp64); 2783 2784 return bbp66 == 1; 2785 } 2786 #endif 2787 2788 static int 2789 rt2661_prepare_beacon(struct rt2661_softc *sc) 2790 { 2791 struct ieee80211com *ic = &sc->sc_ic; 2792 struct ieee80211_beacon_offsets bo; 2793 struct rt2661_tx_desc desc; 2794 struct mbuf *m0; 2795 int rate; 2796 2797 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2798 if (m0 == NULL) { 2799 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2800 return ENOBUFS; 2801 } 2802 2803 /* send beacons at the lowest available rate */ 2804 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2805 2806 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2807 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2808 2809 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2810 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2811 2812 /* copy beacon header and payload into NIC memory */ 2813 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2814 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2815 2816 m_freem(m0); 2817 2818 return 0; 2819 } 2820 2821 /* 2822 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2823 * and HostAP operating modes. 2824 */ 2825 static void 2826 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2827 { 2828 struct ieee80211com *ic = &sc->sc_ic; 2829 uint32_t tmp; 2830 2831 if (ic->ic_opmode != IEEE80211_M_STA) { 2832 /* 2833 * Change default 16ms TBTT adjustment to 8ms. 2834 * Must be done before enabling beacon generation. 2835 */ 2836 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2837 } 2838 2839 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2840 2841 /* set beacon interval (in 1/16ms unit) */ 2842 tmp |= ic->ic_bss->ni_intval * 16; 2843 2844 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2845 if (ic->ic_opmode == IEEE80211_M_STA) 2846 tmp |= RT2661_TSF_MODE(1); 2847 else 2848 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2849 2850 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2851 } 2852 2853 /* 2854 * Retrieve the "Received Signal Strength Indicator" from the raw values 2855 * contained in Rx descriptors. The computation depends on which band the 2856 * frame was received. Correction values taken from the reference driver. 2857 */ 2858 static int 2859 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2860 { 2861 int lna, agc, rssi; 2862 2863 lna = (raw >> 5) & 0x3; 2864 agc = raw & 0x1f; 2865 2866 rssi = 2 * agc; 2867 2868 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2869 rssi += sc->rssi_2ghz_corr; 2870 2871 if (lna == 1) 2872 rssi -= 64; 2873 else if (lna == 2) 2874 rssi -= 74; 2875 else if (lna == 3) 2876 rssi -= 90; 2877 } else { 2878 rssi += sc->rssi_5ghz_corr; 2879 2880 if (lna == 1) 2881 rssi -= 64; 2882 else if (lna == 2) 2883 rssi -= 86; 2884 else if (lna == 3) 2885 rssi -= 100; 2886 } 2887 return rssi; 2888 }
Cache object: 4d4752822eefa83e9e65e24774acee26
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