The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ral/rt2661reg.h

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    1 /*      $FreeBSD$       */
    2 
    3 /*-
    4  * Copyright (c) 2006
    5  *      Damien Bergamini <damien.bergamini@free.fr>
    6  *
    7  * Permission to use, copy, modify, and distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  */
   19 
   20 #define RT2661_NOISE_FLOOR      -95
   21 
   22 #define RT2661_TX_RING_COUNT    32
   23 #define RT2661_MGT_RING_COUNT   32
   24 #define RT2661_RX_RING_COUNT    64
   25 
   26 #define RT2661_TX_DESC_SIZE     (sizeof (struct rt2661_tx_desc))
   27 #define RT2661_TX_DESC_WSIZE    (RT2661_TX_DESC_SIZE / 4)
   28 #define RT2661_RX_DESC_SIZE     (sizeof (struct rt2661_rx_desc))
   29 #define RT2661_RX_DESC_WSIZE    (RT2661_RX_DESC_SIZE / 4)
   30 
   31 #define RT2661_MAX_SCATTER      5
   32 
   33 /*
   34  * Control and status registers.
   35  */
   36 #define RT2661_HOST_CMD_CSR             0x0008
   37 #define RT2661_MCU_CNTL_CSR             0x000c
   38 #define RT2661_SOFT_RESET_CSR           0x0010
   39 #define RT2661_MCU_INT_SOURCE_CSR       0x0014
   40 #define RT2661_MCU_INT_MASK_CSR         0x0018
   41 #define RT2661_PCI_USEC_CSR             0x001c
   42 #define RT2661_H2M_MAILBOX_CSR          0x2100
   43 #define RT2661_M2H_CMD_DONE_CSR         0x2104
   44 #define RT2661_HW_BEACON_BASE0          0x2c00
   45 #define RT2661_MAC_CSR0                 0x3000
   46 #define RT2661_MAC_CSR1                 0x3004
   47 #define RT2661_MAC_CSR2                 0x3008
   48 #define RT2661_MAC_CSR3                 0x300c
   49 #define RT2661_MAC_CSR4                 0x3010
   50 #define RT2661_MAC_CSR5                 0x3014
   51 #define RT2661_MAC_CSR6                 0x3018
   52 #define RT2661_MAC_CSR7                 0x301c
   53 #define RT2661_MAC_CSR8                 0x3020
   54 #define RT2661_MAC_CSR9                 0x3024
   55 #define RT2661_MAC_CSR10                0x3028
   56 #define RT2661_MAC_CSR11                0x302c
   57 #define RT2661_MAC_CSR12                0x3030
   58 #define RT2661_MAC_CSR13                0x3034
   59 #define RT2661_MAC_CSR14                0x3038
   60 #define RT2661_MAC_CSR15                0x303c
   61 #define RT2661_TXRX_CSR0                0x3040
   62 #define RT2661_TXRX_CSR1                0x3044
   63 #define RT2661_TXRX_CSR2                0x3048
   64 #define RT2661_TXRX_CSR3                0x304c
   65 #define RT2661_TXRX_CSR4                0x3050
   66 #define RT2661_TXRX_CSR5                0x3054
   67 #define RT2661_TXRX_CSR6                0x3058
   68 #define RT2661_TXRX_CSR7                0x305c
   69 #define RT2661_TXRX_CSR8                0x3060
   70 #define RT2661_TXRX_CSR9                0x3064
   71 #define RT2661_TXRX_CSR10               0x3068
   72 #define RT2661_TXRX_CSR11               0x306c
   73 #define RT2661_TXRX_CSR12               0x3070
   74 #define RT2661_TXRX_CSR13               0x3074
   75 #define RT2661_TXRX_CSR14               0x3078
   76 #define RT2661_TXRX_CSR15               0x307c
   77 #define RT2661_PHY_CSR0                 0x3080
   78 #define RT2661_PHY_CSR1                 0x3084
   79 #define RT2661_PHY_CSR2                 0x3088
   80 #define RT2661_PHY_CSR3                 0x308c
   81 #define RT2661_PHY_CSR4                 0x3090
   82 #define RT2661_PHY_CSR5                 0x3094
   83 #define RT2661_PHY_CSR6                 0x3098
   84 #define RT2661_PHY_CSR7                 0x309c
   85 #define RT2661_SEC_CSR0                 0x30a0
   86 #define RT2661_SEC_CSR1                 0x30a4
   87 #define RT2661_SEC_CSR2                 0x30a8
   88 #define RT2661_SEC_CSR3                 0x30ac
   89 #define RT2661_SEC_CSR4                 0x30b0
   90 #define RT2661_SEC_CSR5                 0x30b4
   91 #define RT2661_STA_CSR0                 0x30c0
   92 #define RT2661_STA_CSR1                 0x30c4
   93 #define RT2661_STA_CSR2                 0x30c8
   94 #define RT2661_STA_CSR3                 0x30cc
   95 #define RT2661_STA_CSR4                 0x30d0
   96 #define RT2661_AC0_BASE_CSR             0x3400
   97 #define RT2661_AC1_BASE_CSR             0x3404
   98 #define RT2661_AC2_BASE_CSR             0x3408
   99 #define RT2661_AC3_BASE_CSR             0x340c
  100 #define RT2661_MGT_BASE_CSR             0x3410
  101 #define RT2661_TX_RING_CSR0             0x3418
  102 #define RT2661_TX_RING_CSR1             0x341c
  103 #define RT2661_AIFSN_CSR                0x3420
  104 #define RT2661_CWMIN_CSR                0x3424
  105 #define RT2661_CWMAX_CSR                0x3428
  106 #define RT2661_TX_DMA_DST_CSR           0x342c
  107 #define RT2661_TX_CNTL_CSR              0x3430
  108 #define RT2661_LOAD_TX_RING_CSR         0x3434
  109 #define RT2661_RX_BASE_CSR              0x3450
  110 #define RT2661_RX_RING_CSR              0x3454
  111 #define RT2661_RX_CNTL_CSR              0x3458
  112 #define RT2661_PCI_CFG_CSR              0x3460
  113 #define RT2661_INT_SOURCE_CSR           0x3468
  114 #define RT2661_INT_MASK_CSR             0x346c
  115 #define RT2661_E2PROM_CSR               0x3470
  116 #define RT2661_AC_TXOP_CSR0             0x3474
  117 #define RT2661_AC_TXOP_CSR1             0x3478
  118 #define RT2661_TEST_MODE_CSR            0x3484
  119 #define RT2661_IO_CNTL_CSR              0x3498
  120 #define RT2661_MCU_CODE_BASE            0x4000
  121 
  122 
  123 /* possible flags for register HOST_CMD_CSR */
  124 #define RT2661_KICK_CMD         (1 << 7)
  125 /* Host to MCU (8051) command identifiers */
  126 #define RT2661_MCU_CMD_SLEEP    0x30
  127 #define RT2661_MCU_CMD_WAKEUP   0x31
  128 #define RT2661_MCU_SET_LED      0x50
  129 #define RT2661_MCU_SET_RSSI_LED 0x52
  130 
  131 /* possible flags for register MCU_CNTL_CSR */
  132 #define RT2661_MCU_SEL          (1 << 0)
  133 #define RT2661_MCU_RESET        (1 << 1)
  134 #define RT2661_MCU_READY        (1 << 2)
  135 
  136 /* possible flags for register MCU_INT_SOURCE_CSR */
  137 #define RT2661_MCU_CMD_DONE             0xff
  138 #define RT2661_MCU_WAKEUP               (1 << 8)
  139 #define RT2661_MCU_BEACON_EXPIRE        (1 << 9)
  140 
  141 /* possible flags for register H2M_MAILBOX_CSR */
  142 #define RT2661_H2M_BUSY         (1 << 24)
  143 #define RT2661_TOKEN_NO_INTR    0xff
  144 
  145 /* possible flags for register MAC_CSR5 */
  146 #define RT2661_ONE_BSSID        3
  147 
  148 /* possible flags for register TXRX_CSR0 */
  149 /* Tx filter flags are in the low 16 bits */
  150 #define RT2661_AUTO_TX_SEQ      (1 << 15)
  151 /* Rx filter flags are in the high 16 bits */
  152 #define RT2661_DISABLE_RX       (1 << 16)
  153 #define RT2661_DROP_CRC_ERROR   (1 << 17)
  154 #define RT2661_DROP_PHY_ERROR   (1 << 18)
  155 #define RT2661_DROP_CTL         (1 << 19)
  156 #define RT2661_DROP_NOT_TO_ME   (1 << 20)
  157 #define RT2661_DROP_TODS        (1 << 21)
  158 #define RT2661_DROP_VER_ERROR   (1 << 22)
  159 #define RT2661_DROP_MULTICAST   (1 << 23)
  160 #define RT2661_DROP_BROADCAST   (1 << 24)
  161 #define RT2661_DROP_ACKCTS      (1 << 25)
  162 
  163 /* possible flags for register TXRX_CSR4 */
  164 #define RT2661_SHORT_PREAMBLE   (1 << 19)
  165 #define RT2661_MRR_ENABLED      (1 << 20)
  166 #define RT2661_MRR_CCK_FALLBACK (1 << 23)
  167 
  168 /* possible flags for register TXRX_CSR9 */
  169 #define RT2661_TSF_TICKING      (1 << 16)
  170 #define RT2661_TSF_MODE(x)      (((x) & 0x3) << 17)
  171 /* TBTT stands for Target Beacon Transmission Time */
  172 #define RT2661_ENABLE_TBTT      (1 << 19)
  173 #define RT2661_GENERATE_BEACON  (1 << 20)
  174 
  175 /* possible flags for register PHY_CSR0 */
  176 #define RT2661_PA_PE_2GHZ       (1 << 16)
  177 #define RT2661_PA_PE_5GHZ       (1 << 17)
  178 
  179 /* possible flags for register PHY_CSR3 */
  180 #define RT2661_BBP_READ (1 << 15)
  181 #define RT2661_BBP_BUSY (1 << 16)
  182 
  183 /* possible flags for register PHY_CSR4 */
  184 #define RT2661_RF_21BIT (21 << 24)
  185 #define RT2661_RF_BUSY  (1 << 31)
  186 
  187 /* possible values for register STA_CSR4 */
  188 #define RT2661_TX_STAT_VALID    (1 << 0)
  189 #define RT2661_TX_RESULT(v)     (((v) >> 1) & 0x7)
  190 #define RT2661_TX_RETRYCNT(v)   (((v) >> 4) & 0xf)
  191 #define RT2661_TX_QID(v)        (((v) >> 8) & 0xf)
  192 #define RT2661_TX_SUCCESS       0
  193 #define RT2661_TX_RETRY_FAIL    6
  194 
  195 /* possible flags for register TX_CNTL_CSR */
  196 #define RT2661_KICK_MGT (1 << 4)
  197 
  198 /* possible flags for register INT_SOURCE_CSR */
  199 #define RT2661_TX_DONE          (1 << 0)
  200 #define RT2661_RX_DONE          (1 << 1)
  201 #define RT2661_TX0_DMA_DONE     (1 << 16)
  202 #define RT2661_TX1_DMA_DONE     (1 << 17)
  203 #define RT2661_TX2_DMA_DONE     (1 << 18)
  204 #define RT2661_TX3_DMA_DONE     (1 << 19)
  205 #define RT2661_MGT_DONE         (1 << 20)
  206 
  207 /* possible flags for register E2PROM_CSR */
  208 #define RT2661_C        (1 << 1)
  209 #define RT2661_S        (1 << 2)
  210 #define RT2661_D        (1 << 3)
  211 #define RT2661_Q        (1 << 4)
  212 #define RT2661_93C46    (1 << 5)
  213 
  214 /* Tx descriptor */
  215 struct rt2661_tx_desc {
  216         uint32_t        flags;
  217 #define RT2661_TX_BUSY          (1 << 0)
  218 #define RT2661_TX_VALID         (1 << 1)
  219 #define RT2661_TX_MORE_FRAG     (1 << 2)
  220 #define RT2661_TX_NEED_ACK      (1 << 3)
  221 #define RT2661_TX_TIMESTAMP     (1 << 4)
  222 #define RT2661_TX_OFDM          (1 << 5)
  223 #define RT2661_TX_IFS           (1 << 6)
  224 #define RT2661_TX_LONG_RETRY    (1 << 7)
  225 #define RT2661_TX_BURST         (1 << 28)
  226 
  227         uint16_t        wme;
  228 #define RT2661_QID(v)           (v)
  229 #define RT2661_AIFSN(v)         ((v) << 4)
  230 #define RT2661_LOGCWMIN(v)      ((v) << 8)
  231 #define RT2661_LOGCWMAX(v)      ((v) << 12)
  232 
  233         uint16_t        xflags;
  234 #define RT2661_TX_HWSEQ         (1 << 12)
  235 
  236         uint8_t         plcp_signal;
  237         uint8_t         plcp_service;
  238 #define RT2661_PLCP_LENGEXT     0x80
  239 
  240         uint8_t         plcp_length_lo;
  241         uint8_t         plcp_length_hi;
  242 
  243         uint32_t        iv;
  244         uint32_t        eiv;
  245 
  246         uint8_t         offset;
  247         uint8_t         qid;
  248 #define RT2661_QID_MGT  13
  249 
  250         uint8_t         txpower;
  251 #define RT2661_DEFAULT_TXPOWER  0
  252 
  253         uint8_t         reserved1;
  254 
  255         uint32_t        addr[RT2661_MAX_SCATTER];
  256         uint16_t        len[RT2661_MAX_SCATTER];
  257 
  258         uint16_t        reserved2;
  259 } __packed;
  260 
  261 /* Rx descriptor */
  262 struct rt2661_rx_desc {
  263         uint32_t        flags;
  264 #define RT2661_RX_BUSY          (1 << 0)
  265 #define RT2661_RX_DROP          (1 << 1)
  266 #define RT2661_RX_CRC_ERROR     (1 << 6)
  267 #define RT2661_RX_OFDM          (1 << 7)
  268 #define RT2661_RX_PHY_ERROR     (1 << 8)
  269 #define RT2661_RX_CIPHER_MASK   0x00000600
  270 
  271         uint8_t         rate;
  272         uint8_t         rssi;
  273         uint8_t         reserved1;
  274         uint8_t         offset;
  275         uint32_t        iv;
  276         uint32_t        eiv;
  277         uint32_t        reserved2;
  278         uint32_t        physaddr;
  279         uint32_t        reserved3[10];
  280 } __packed;
  281 
  282 #define RAL_RF1 0
  283 #define RAL_RF2 2
  284 #define RAL_RF3 1
  285 #define RAL_RF4 3
  286 
  287 /* dual-band RF */
  288 #define RT2661_RF_5225  1
  289 #define RT2661_RF_5325  2
  290 /* single-band RF */
  291 #define RT2661_RF_2527  3
  292 #define RT2661_RF_2529  4
  293 
  294 #define RT2661_RX_DESC_BACK     4
  295 
  296 #define RT2661_SMART_MODE       (1 << 0)
  297 
  298 #define RT2661_BBPR94_DEFAULT   6
  299 
  300 #define RT2661_SHIFT_D  3
  301 #define RT2661_SHIFT_Q  4
  302 
  303 #define RT2661_EEPROM_MAC01             0x02
  304 #define RT2661_EEPROM_MAC23             0x03
  305 #define RT2661_EEPROM_MAC45             0x04
  306 #define RT2661_EEPROM_ANTENNA           0x10
  307 #define RT2661_EEPROM_CONFIG2           0x11
  308 #define RT2661_EEPROM_BBP_BASE          0x13
  309 #define RT2661_EEPROM_TXPOWER           0x23
  310 #define RT2661_EEPROM_FREQ_OFFSET       0x2f
  311 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET  0x4d
  312 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET  0x4e
  313 
  314 #define RT2661_EEPROM_DELAY     1       /* minimum hold time (microsecond) */
  315 
  316 /*
  317  * control and status registers access macros
  318  */
  319 #define RAL_READ(sc, reg)                                               \
  320         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
  321 
  322 #define RAL_READ_REGION_4(sc, offset, datap, count)                     \
  323         bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset),     \
  324             (datap), (count))
  325 
  326 #define RAL_WRITE(sc, reg, val)                                         \
  327         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  328 
  329 #define RAL_WRITE_REGION_1(sc, offset, datap, count)                    \
  330         bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset),    \
  331             (datap), (count))
  332 
  333 /*
  334  * EEPROM access macro
  335  */
  336 #define RT2661_EEPROM_CTL(sc, val) do {                                 \
  337         RAL_WRITE((sc), RT2661_E2PROM_CSR, (val));                      \
  338         DELAY(RT2661_EEPROM_DELAY);                                     \
  339 } while (/* CONSTCOND */0)
  340 
  341 /*
  342  * Default values for MAC registers; values taken from the reference driver.
  343  */
  344 #define RT2661_DEF_MAC                                  \
  345         { RT2661_TXRX_CSR0,        0x0000b032 },        \
  346         { RT2661_TXRX_CSR1,        0x9eb39eb3 },        \
  347         { RT2661_TXRX_CSR2,        0x8a8b8c8d },        \
  348         { RT2661_TXRX_CSR3,        0x00858687 },        \
  349         { RT2661_TXRX_CSR7,        0x2e31353b },        \
  350         { RT2661_TXRX_CSR8,        0x2a2a2a2c },        \
  351         { RT2661_TXRX_CSR15,       0x0000000f },        \
  352         { RT2661_MAC_CSR6,         0x00000fff },        \
  353         { RT2661_MAC_CSR8,         0x016c030a },        \
  354         { RT2661_MAC_CSR10,        0x00000718 },        \
  355         { RT2661_MAC_CSR12,        0x00000004 },        \
  356         { RT2661_MAC_CSR13,        0x0000e000 },        \
  357         { RT2661_SEC_CSR0,         0x00000000 },        \
  358         { RT2661_SEC_CSR1,         0x00000000 },        \
  359         { RT2661_SEC_CSR5,         0x00000000 },        \
  360         { RT2661_PHY_CSR1,         0x000023b0 },        \
  361         { RT2661_PHY_CSR5,         0x060a100c },        \
  362         { RT2661_PHY_CSR6,         0x00080606 },        \
  363         { RT2661_PHY_CSR7,         0x00000a08 },        \
  364         { RT2661_PCI_CFG_CSR,      0x3cca4808 },        \
  365         { RT2661_AIFSN_CSR,        0x00002273 },        \
  366         { RT2661_CWMIN_CSR,        0x00002344 },        \
  367         { RT2661_CWMAX_CSR,        0x000034aa },        \
  368         { RT2661_TEST_MODE_CSR,    0x00000200 },        \
  369         { RT2661_M2H_CMD_DONE_CSR, 0xffffffff }
  370 
  371 /*
  372  * Default values for BBP registers; values taken from the reference driver.
  373  */
  374 #define RT2661_DEF_BBP  \
  375         {   3, 0x00 },  \
  376         {  15, 0x30 },  \
  377         {  17, 0x20 },  \
  378         {  21, 0xc8 },  \
  379         {  22, 0x38 },  \
  380         {  23, 0x06 },  \
  381         {  24, 0xfe },  \
  382         {  25, 0x0a },  \
  383         {  26, 0x0d },  \
  384         {  34, 0x12 },  \
  385         {  37, 0x07 },  \
  386         {  39, 0xf8 },  \
  387         {  41, 0x60 },  \
  388         {  53, 0x10 },  \
  389         {  54, 0x18 },  \
  390         {  60, 0x10 },  \
  391         {  61, 0x04 },  \
  392         {  62, 0x04 },  \
  393         {  75, 0xfe },  \
  394         {  86, 0xfe },  \
  395         {  88, 0xfe },  \
  396         {  90, 0x0f },  \
  397         {  99, 0x00 },  \
  398         { 102, 0x16 },  \
  399         { 107, 0x04 }
  400 
  401 /*
  402  * Default settings for RF registers; values taken from the reference driver.
  403  */
  404 #define RT2661_RF5225_1                                 \
  405         {   1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },    \
  406         {   2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },    \
  407         {   3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },    \
  408         {   4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },    \
  409         {   5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },    \
  410         {   6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },    \
  411         {   7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },    \
  412         {   8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },    \
  413         {   9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },    \
  414         {  10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },    \
  415         {  11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },    \
  416         {  12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },    \
  417         {  13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },    \
  418         {  14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },    \
  419                                                         \
  420         {  36, 0x00b33, 0x01266, 0x26014, 0x30288 },    \
  421         {  40, 0x00b33, 0x01268, 0x26014, 0x30280 },    \
  422         {  44, 0x00b33, 0x01269, 0x26014, 0x30282 },    \
  423         {  48, 0x00b33, 0x0126a, 0x26014, 0x30284 },    \
  424         {  52, 0x00b33, 0x0126b, 0x26014, 0x30286 },    \
  425         {  56, 0x00b33, 0x0126c, 0x26014, 0x30288 },    \
  426         {  60, 0x00b33, 0x0126e, 0x26014, 0x30280 },    \
  427         {  64, 0x00b33, 0x0126f, 0x26014, 0x30282 },    \
  428                                                         \
  429         { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 },    \
  430         { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 },    \
  431         { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 },    \
  432         { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 },    \
  433         { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 },    \
  434         { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 },    \
  435         { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 },    \
  436         { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 },    \
  437         { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 },    \
  438         { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 },    \
  439         { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 },    \
  440                                                         \
  441         { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 },    \
  442         { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 },    \
  443         { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 },    \
  444         { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 },    \
  445         { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
  446 
  447 #define RT2661_RF5225_2                                 \
  448         {   1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },    \
  449         {   2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },    \
  450         {   3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },    \
  451         {   4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },    \
  452         {   5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },    \
  453         {   6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },    \
  454         {   7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },    \
  455         {   8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },    \
  456         {   9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },    \
  457         {  10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },    \
  458         {  11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },    \
  459         {  12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },    \
  460         {  13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },    \
  461         {  14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },    \
  462                                                         \
  463         {  36, 0x00b35, 0x11206, 0x26014, 0x30280 },    \
  464         {  40, 0x00b34, 0x111a0, 0x26014, 0x30280 },    \
  465         {  44, 0x00b34, 0x111a1, 0x26014, 0x30286 },    \
  466         {  48, 0x00b34, 0x111a3, 0x26014, 0x30282 },    \
  467         {  52, 0x00b34, 0x111a4, 0x26014, 0x30288 },    \
  468         {  56, 0x00b34, 0x111a6, 0x26014, 0x30284 },    \
  469         {  60, 0x00b34, 0x111a8, 0x26014, 0x30280 },    \
  470         {  64, 0x00b34, 0x111a9, 0x26014, 0x30286 },    \
  471                                                         \
  472         { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 },    \
  473         { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 },    \
  474         { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 },    \
  475         { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 },    \
  476         { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 },    \
  477         { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 },    \
  478         { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 },    \
  479         { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 },    \
  480         { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 },    \
  481         { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 },    \
  482         { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 },    \
  483                                                         \
  484         { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 },    \
  485         { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 },    \
  486         { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 },    \
  487         { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 },    \
  488         { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }

Cache object: 3fabd49ab561e45596792da384a70311


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