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sys/dev/ral/rt2860.c
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1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_ratectl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2860reg.h> 68 #include <dev/ral/rt2860var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83 static void rt2860_vap_delete(struct ieee80211vap *); 84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92 static void rt2860_free_tx_pool(struct rt2860_softc *); 93 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_updatestats(struct rt2860_softc *); 100 static void rt2860_newassoc(struct ieee80211_node *, int); 101 static void rt2860_node_free(struct ieee80211_node *); 102 #ifdef IEEE80211_HT 103 static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107 #endif 108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112 static void rt2860_intr_coherent(struct rt2860_softc *); 113 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114 static void rt2860_tx_intr(struct rt2860_softc *, int); 115 static void rt2860_rx_intr(struct rt2860_softc *); 116 static void rt2860_tbtt_intr(struct rt2860_softc *); 117 static void rt2860_gp_intr(struct rt2860_softc *); 118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126 static void rt2860_start(struct rt2860_softc *); 127 static void rt2860_watchdog(void *); 128 static void rt2860_parent(struct ieee80211com *); 129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135 static void rt2860_enable_mrr(struct rt2860_softc *); 136 static void rt2860_set_txpreamble(struct rt2860_softc *); 137 static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2860_scan_start(struct ieee80211com *); 140 static void rt2860_scan_end(struct ieee80211com *); 141 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 142 struct ieee80211_channel[]); 143 static void rt2860_set_channel(struct ieee80211com *); 144 static void rt2860_select_chan_group(struct rt2860_softc *, int); 145 static void rt2860_set_chan(struct rt2860_softc *, u_int); 146 static void rt3090_set_chan(struct rt2860_softc *, u_int); 147 static void rt5390_set_chan(struct rt2860_softc *, u_int); 148 static int rt3090_rf_init(struct rt2860_softc *); 149 static void rt5390_rf_init(struct rt2860_softc *); 150 static void rt3090_rf_wakeup(struct rt2860_softc *); 151 static void rt5390_rf_wakeup(struct rt2860_softc *); 152 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 153 uint8_t *); 154 static void rt3090_rf_setup(struct rt2860_softc *); 155 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 156 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 157 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 158 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 159 static void rt2860_update_promisc(struct ieee80211com *); 160 static void rt2860_updateslot(struct ieee80211com *); 161 static void rt2860_updateprot(struct rt2860_softc *); 162 static int rt2860_updateedca(struct ieee80211com *); 163 #ifdef HW_CRYPTO 164 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 165 struct ieee80211_key *); 166 static void rt2860_delete_key(struct ieee80211com *, 167 struct ieee80211_node *, struct ieee80211_key *); 168 #endif 169 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 170 static const char *rt2860_get_rf(uint16_t); 171 static int rt2860_read_eeprom(struct rt2860_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173 static int rt2860_bbp_init(struct rt2860_softc *); 174 static void rt5390_bbp_init(struct rt2860_softc *); 175 static int rt2860_txrx_enable(struct rt2860_softc *); 176 static void rt2860_init(void *); 177 static void rt2860_init_locked(struct rt2860_softc *); 178 static void rt2860_stop(void *); 179 static void rt2860_stop_locked(struct rt2860_softc *); 180 static int rt2860_load_microcode(struct rt2860_softc *); 181 #ifdef NOT_YET 182 static void rt2860_calib(struct rt2860_softc *); 183 #endif 184 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 185 static void rt2860_switch_chan(struct rt2860_softc *, 186 struct ieee80211_channel *); 187 static int rt2860_setup_beacon(struct rt2860_softc *, 188 struct ieee80211vap *); 189 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 190 191 static const struct { 192 uint32_t reg; 193 uint32_t val; 194 } rt2860_def_mac[] = { 195 RT2860_DEF_MAC 196 }; 197 198 static const struct { 199 uint8_t reg; 200 uint8_t val; 201 } rt2860_def_bbp[] = { 202 RT2860_DEF_BBP 203 }, rt5390_def_bbp[] = { 204 RT5390_DEF_BBP 205 }; 206 207 static const struct rfprog { 208 uint8_t chan; 209 uint32_t r1, r2, r3, r4; 210 } rt2860_rf2850[] = { 211 RT2860_RF2850 212 }; 213 214 struct { 215 uint8_t n, r, k; 216 } rt3090_freqs[] = { 217 RT3070_RF3052 218 }; 219 220 static const struct { 221 uint8_t reg; 222 uint8_t val; 223 } rt3090_def_rf[] = { 224 RT3070_DEF_RF 225 }, rt5390_def_rf[] = { 226 RT5390_DEF_RF 227 }, rt5392_def_rf[] = { 228 RT5392_DEF_RF 229 }; 230 231 static const uint8_t rt2860_chan_5ghz[] = 232 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 233 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 234 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 235 236 int 237 rt2860_attach(device_t dev, int id) 238 { 239 struct rt2860_softc *sc = device_get_softc(dev); 240 struct ieee80211com *ic = &sc->sc_ic; 241 uint32_t tmp; 242 int error, ntries, qid; 243 244 sc->sc_dev = dev; 245 sc->sc_debug = 0; 246 247 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 248 MTX_DEF | MTX_RECURSE); 249 250 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 251 mbufq_init(&sc->sc_snd, ifqmaxlen); 252 253 /* wait for NIC to initialize */ 254 for (ntries = 0; ntries < 100; ntries++) { 255 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 256 if (tmp != 0 && tmp != 0xffffffff) 257 break; 258 DELAY(10); 259 } 260 if (ntries == 100) { 261 device_printf(sc->sc_dev, 262 "timeout waiting for NIC to initialize\n"); 263 error = EIO; 264 goto fail1; 265 } 266 sc->mac_ver = tmp >> 16; 267 sc->mac_rev = tmp & 0xffff; 268 269 if (sc->mac_ver != 0x2860 && 270 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 271 sc->sc_flags |= RT2860_ADVANCED_PS; 272 273 /* retrieve RF rev. no and various other things from EEPROM */ 274 rt2860_read_eeprom(sc, ic->ic_macaddr); 275 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 276 "RF %s (MIMO %dT%dR), address %6D\n", 277 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 278 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 279 280 /* 281 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 282 */ 283 for (qid = 0; qid < 6; qid++) { 284 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 285 device_printf(sc->sc_dev, 286 "could not allocate Tx ring %d\n", qid); 287 goto fail2; 288 } 289 } 290 291 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 292 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 293 goto fail2; 294 } 295 296 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 297 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 298 goto fail3; 299 } 300 301 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 302 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 303 WME_AC_VO : 5; 304 305 ic->ic_softc = sc; 306 ic->ic_name = device_get_nameunit(dev); 307 ic->ic_opmode = IEEE80211_M_STA; 308 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 309 310 /* set device capabilities */ 311 ic->ic_caps = 312 IEEE80211_C_STA /* station mode */ 313 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 314 | IEEE80211_C_HOSTAP /* hostap mode */ 315 | IEEE80211_C_MONITOR /* monitor mode */ 316 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 317 | IEEE80211_C_WDS /* 4-address traffic works */ 318 | IEEE80211_C_MBSS /* mesh point link mode */ 319 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 320 | IEEE80211_C_SHSLOT /* short slot time supported */ 321 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 322 #if 0 323 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 324 #endif 325 | IEEE80211_C_WME /* 802.11e */ 326 ; 327 328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 329 ic->ic_channels); 330 331 ieee80211_ifattach(ic); 332 333 ic->ic_wme.wme_update = rt2860_updateedca; 334 ic->ic_scan_start = rt2860_scan_start; 335 ic->ic_scan_end = rt2860_scan_end; 336 ic->ic_getradiocaps = rt2860_getradiocaps; 337 ic->ic_set_channel = rt2860_set_channel; 338 ic->ic_updateslot = rt2860_updateslot; 339 ic->ic_update_promisc = rt2860_update_promisc; 340 ic->ic_raw_xmit = rt2860_raw_xmit; 341 sc->sc_node_free = ic->ic_node_free; 342 ic->ic_node_free = rt2860_node_free; 343 ic->ic_newassoc = rt2860_newassoc; 344 ic->ic_transmit = rt2860_transmit; 345 ic->ic_parent = rt2860_parent; 346 ic->ic_vap_create = rt2860_vap_create; 347 ic->ic_vap_delete = rt2860_vap_delete; 348 349 ieee80211_radiotap_attach(ic, 350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 351 RT2860_TX_RADIOTAP_PRESENT, 352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 353 RT2860_RX_RADIOTAP_PRESENT); 354 355 #ifdef RAL_DEBUG 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 359 #endif 360 if (bootverbose) 361 ieee80211_announce(ic); 362 363 return 0; 364 365 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 366 fail2: while (--qid >= 0) 367 rt2860_free_tx_ring(sc, &sc->txq[qid]); 368 fail1: mtx_destroy(&sc->sc_mtx); 369 return error; 370 } 371 372 int 373 rt2860_detach(void *xsc) 374 { 375 struct rt2860_softc *sc = xsc; 376 struct ieee80211com *ic = &sc->sc_ic; 377 int qid; 378 379 RAL_LOCK(sc); 380 rt2860_stop_locked(sc); 381 RAL_UNLOCK(sc); 382 383 ieee80211_ifdetach(ic); 384 mbufq_drain(&sc->sc_snd); 385 for (qid = 0; qid < 6; qid++) 386 rt2860_free_tx_ring(sc, &sc->txq[qid]); 387 rt2860_free_rx_ring(sc, &sc->rxq); 388 rt2860_free_tx_pool(sc); 389 390 mtx_destroy(&sc->sc_mtx); 391 392 return 0; 393 } 394 395 void 396 rt2860_shutdown(void *xsc) 397 { 398 struct rt2860_softc *sc = xsc; 399 400 rt2860_stop(sc); 401 } 402 403 void 404 rt2860_suspend(void *xsc) 405 { 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409 } 410 411 void 412 rt2860_resume(void *xsc) 413 { 414 struct rt2860_softc *sc = xsc; 415 416 if (sc->sc_ic.ic_nrunning > 0) 417 rt2860_init(sc); 418 } 419 420 static struct ieee80211vap * 421 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 422 enum ieee80211_opmode opmode, int flags, 423 const uint8_t bssid[IEEE80211_ADDR_LEN], 424 const uint8_t mac[IEEE80211_ADDR_LEN]) 425 { 426 struct rt2860_softc *sc = ic->ic_softc; 427 struct rt2860_vap *rvp; 428 struct ieee80211vap *vap; 429 430 switch (opmode) { 431 case IEEE80211_M_STA: 432 case IEEE80211_M_IBSS: 433 case IEEE80211_M_AHDEMO: 434 case IEEE80211_M_MONITOR: 435 case IEEE80211_M_HOSTAP: 436 case IEEE80211_M_MBSS: 437 /* XXXRP: TBD */ 438 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 439 device_printf(sc->sc_dev, "only 1 vap supported\n"); 440 return NULL; 441 } 442 if (opmode == IEEE80211_M_STA) 443 flags |= IEEE80211_CLONE_NOBEACONS; 444 break; 445 case IEEE80211_M_WDS: 446 if (TAILQ_EMPTY(&ic->ic_vaps) || 447 ic->ic_opmode != IEEE80211_M_HOSTAP) { 448 device_printf(sc->sc_dev, 449 "wds only supported in ap mode\n"); 450 return NULL; 451 } 452 /* 453 * Silently remove any request for a unique 454 * bssid; WDS vap's always share the local 455 * mac address. 456 */ 457 flags &= ~IEEE80211_CLONE_BSSID; 458 break; 459 default: 460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 461 return NULL; 462 } 463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 464 vap = &rvp->ral_vap; 465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 466 467 /* override state transition machine */ 468 rvp->ral_newstate = vap->iv_newstate; 469 vap->iv_newstate = rt2860_newstate; 470 #if 0 471 vap->iv_update_beacon = rt2860_beacon_update; 472 #endif 473 474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 476 477 ieee80211_ratectl_init(vap); 478 /* complete setup */ 479 ieee80211_vap_attach(vap, ieee80211_media_change, 480 ieee80211_media_status, mac); 481 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 482 ic->ic_opmode = opmode; 483 return vap; 484 } 485 486 static void 487 rt2860_vap_delete(struct ieee80211vap *vap) 488 { 489 struct rt2860_vap *rvp = RT2860_VAP(vap); 490 491 ieee80211_ratectl_deinit(vap); 492 ieee80211_vap_detach(vap); 493 free(rvp, M_80211_VAP); 494 } 495 496 static void 497 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 498 { 499 if (error != 0) 500 return; 501 502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 503 504 *(bus_addr_t *)arg = segs[0].ds_addr; 505 } 506 507 508 static int 509 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 510 { 511 int size, error; 512 513 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 514 515 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 516 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 517 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 518 if (error != 0) { 519 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 520 goto fail; 521 } 522 523 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 524 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 525 if (error != 0) { 526 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 527 goto fail; 528 } 529 530 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 531 size, rt2860_dma_map_addr, &ring->paddr, 0); 532 if (error != 0) { 533 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 534 goto fail; 535 } 536 537 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 538 539 return 0; 540 541 fail: rt2860_free_tx_ring(sc, ring); 542 return error; 543 } 544 545 void 546 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 547 { 548 struct rt2860_tx_data *data; 549 int i; 550 551 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 552 if ((data = ring->data[i]) == NULL) 553 continue; /* nothing mapped in this slot */ 554 555 if (data->m != NULL) { 556 bus_dmamap_sync(sc->txwi_dmat, data->map, 557 BUS_DMASYNC_POSTWRITE); 558 bus_dmamap_unload(sc->txwi_dmat, data->map); 559 m_freem(data->m); 560 data->m = NULL; 561 } 562 if (data->ni != NULL) { 563 ieee80211_free_node(data->ni); 564 data->ni = NULL; 565 } 566 567 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 568 ring->data[i] = NULL; 569 } 570 571 ring->queued = 0; 572 ring->cur = ring->next = 0; 573 } 574 575 void 576 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 577 { 578 struct rt2860_tx_data *data; 579 int i; 580 581 if (ring->txd != NULL) { 582 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 583 BUS_DMASYNC_POSTWRITE); 584 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 585 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 586 } 587 if (ring->desc_dmat != NULL) 588 bus_dma_tag_destroy(ring->desc_dmat); 589 590 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 591 if ((data = ring->data[i]) == NULL) 592 continue; /* nothing mapped in this slot */ 593 594 if (data->m != NULL) { 595 bus_dmamap_sync(sc->txwi_dmat, data->map, 596 BUS_DMASYNC_POSTWRITE); 597 bus_dmamap_unload(sc->txwi_dmat, data->map); 598 m_freem(data->m); 599 } 600 if (data->ni != NULL) 601 ieee80211_free_node(data->ni); 602 603 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 604 } 605 } 606 607 /* 608 * Allocate a pool of TX Wireless Information blocks. 609 */ 610 int 611 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 612 { 613 caddr_t vaddr; 614 bus_addr_t paddr; 615 int i, size, error; 616 617 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 618 619 /* init data_pool early in case of failure.. */ 620 SLIST_INIT(&sc->data_pool); 621 622 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 623 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 624 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 625 if (error != 0) { 626 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 627 goto fail; 628 } 629 630 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 631 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 632 if (error != 0) { 633 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 634 goto fail; 635 } 636 637 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 638 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 641 goto fail; 642 } 643 644 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 645 646 vaddr = sc->txwi_vaddr; 647 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 648 struct rt2860_tx_data *data = &sc->data[i]; 649 650 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 651 if (error != 0) { 652 device_printf(sc->sc_dev, "could not create DMA map\n"); 653 goto fail; 654 } 655 data->txwi = (struct rt2860_txwi *)vaddr; 656 data->paddr = paddr; 657 vaddr += RT2860_TXWI_DMASZ; 658 paddr += RT2860_TXWI_DMASZ; 659 660 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 661 } 662 663 return 0; 664 665 fail: rt2860_free_tx_pool(sc); 666 return error; 667 } 668 669 void 670 rt2860_free_tx_pool(struct rt2860_softc *sc) 671 { 672 if (sc->txwi_vaddr != NULL) { 673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 674 BUS_DMASYNC_POSTWRITE); 675 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 676 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 677 } 678 if (sc->txwi_dmat != NULL) 679 bus_dma_tag_destroy(sc->txwi_dmat); 680 681 while (!SLIST_EMPTY(&sc->data_pool)) { 682 struct rt2860_tx_data *data; 683 data = SLIST_FIRST(&sc->data_pool); 684 bus_dmamap_destroy(sc->txwi_dmat, data->map); 685 SLIST_REMOVE_HEAD(&sc->data_pool, next); 686 } 687 } 688 689 int 690 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 691 { 692 bus_addr_t physaddr; 693 int i, size, error; 694 695 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 696 697 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 698 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 699 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 700 if (error != 0) { 701 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 702 goto fail; 703 } 704 705 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 706 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 707 if (error != 0) { 708 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 709 goto fail; 710 } 711 712 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 713 size, rt2860_dma_map_addr, &ring->paddr, 0); 714 if (error != 0) { 715 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 716 goto fail; 717 } 718 719 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 720 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 721 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 722 if (error != 0) { 723 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 724 goto fail; 725 } 726 727 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 728 struct rt2860_rx_data *data = &ring->data[i]; 729 struct rt2860_rxd *rxd = &ring->rxd[i]; 730 731 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 732 if (error != 0) { 733 device_printf(sc->sc_dev, "could not create DMA map\n"); 734 goto fail; 735 } 736 737 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 738 if (data->m == NULL) { 739 device_printf(sc->sc_dev, 740 "could not allocate rx mbuf\n"); 741 error = ENOMEM; 742 goto fail; 743 } 744 745 error = bus_dmamap_load(ring->data_dmat, data->map, 746 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 747 &physaddr, 0); 748 if (error != 0) { 749 device_printf(sc->sc_dev, 750 "could not load rx buf DMA map"); 751 goto fail; 752 } 753 754 rxd->sdp0 = htole32(physaddr); 755 rxd->sdl0 = htole16(MCLBYTES); 756 } 757 758 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 762 fail: rt2860_free_rx_ring(sc, ring); 763 return error; 764 } 765 766 void 767 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 768 { 769 int i; 770 771 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 772 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 773 774 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 775 776 ring->cur = 0; 777 } 778 779 void 780 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 781 { 782 int i; 783 784 if (ring->rxd != NULL) { 785 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 786 BUS_DMASYNC_POSTWRITE); 787 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 788 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 789 } 790 if (ring->desc_dmat != NULL) 791 bus_dma_tag_destroy(ring->desc_dmat); 792 793 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 794 struct rt2860_rx_data *data = &ring->data[i]; 795 796 if (data->m != NULL) { 797 bus_dmamap_sync(ring->data_dmat, data->map, 798 BUS_DMASYNC_POSTREAD); 799 bus_dmamap_unload(ring->data_dmat, data->map); 800 m_freem(data->m); 801 } 802 if (data->map != NULL) 803 bus_dmamap_destroy(ring->data_dmat, data->map); 804 } 805 if (ring->data_dmat != NULL) 806 bus_dma_tag_destroy(ring->data_dmat); 807 } 808 809 static void 810 rt2860_updatestats(struct rt2860_softc *sc) 811 { 812 struct ieee80211com *ic = &sc->sc_ic; 813 814 /* 815 * In IBSS or HostAP modes (when the hardware sends beacons), the 816 * MAC can run into a livelock and start sending CTS-to-self frames 817 * like crazy if protection is enabled. Fortunately, we can detect 818 * when such a situation occurs and reset the MAC. 819 */ 820 if (ic->ic_curmode != IEEE80211_M_STA) { 821 /* check if we're in a livelock situation.. */ 822 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 823 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 824 /* ..and reset MAC/BBP for a while.. */ 825 DPRINTF(("CTS-to-self livelock detected\n")); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 827 RAL_BARRIER_WRITE(sc); 828 DELAY(1); 829 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 830 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 831 } 832 } 833 } 834 835 static void 836 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 837 { 838 struct ieee80211com *ic = ni->ni_ic; 839 struct rt2860_softc *sc = ic->ic_softc; 840 uint8_t wcid; 841 842 wcid = IEEE80211_AID(ni->ni_associd); 843 if (isnew && ni->ni_associd != 0) { 844 sc->wcid2ni[wcid] = ni; 845 846 /* init WCID table entry */ 847 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 848 ni->ni_macaddr, IEEE80211_ADDR_LEN); 849 } 850 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 851 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 852 } 853 854 static void 855 rt2860_node_free(struct ieee80211_node *ni) 856 { 857 struct ieee80211com *ic = ni->ni_ic; 858 struct rt2860_softc *sc = ic->ic_softc; 859 uint8_t wcid; 860 861 if (ni->ni_associd != 0) { 862 wcid = IEEE80211_AID(ni->ni_associd); 863 864 /* clear Rx WCID search table entry */ 865 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 866 } 867 sc->sc_node_free(ni); 868 } 869 870 #ifdef IEEE80211_HT 871 static int 872 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 873 uint8_t tid) 874 { 875 struct rt2860_softc *sc = ic->ic_softc; 876 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 877 uint32_t tmp; 878 879 /* update BA session mask */ 880 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 881 tmp |= (1 << tid) << 16; 882 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 883 return 0; 884 } 885 886 static void 887 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 888 uint8_t tid) 889 { 890 struct rt2860_softc *sc = ic->ic_softc; 891 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 892 uint32_t tmp; 893 894 /* update BA session mask */ 895 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 896 tmp &= ~((1 << tid) << 16); 897 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 898 } 899 #endif 900 901 static int 902 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 903 { 904 struct rt2860_vap *rvp = RT2860_VAP(vap); 905 struct ieee80211com *ic = vap->iv_ic; 906 struct rt2860_softc *sc = ic->ic_softc; 907 uint32_t tmp; 908 int error; 909 910 if (vap->iv_state == IEEE80211_S_RUN) { 911 /* turn link LED off */ 912 rt2860_set_leds(sc, RT2860_LED_RADIO); 913 } 914 915 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 916 /* abort TSF synchronization */ 917 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 918 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 919 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 920 RT2860_TBTT_TIMER_EN)); 921 } 922 923 rt2860_set_gp_timer(sc, 0); 924 925 error = rvp->ral_newstate(vap, nstate, arg); 926 if (error != 0) 927 return (error); 928 929 if (nstate == IEEE80211_S_RUN) { 930 struct ieee80211_node *ni = vap->iv_bss; 931 932 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 933 rt2860_enable_mrr(sc); 934 rt2860_set_txpreamble(sc); 935 rt2860_set_basicrates(sc, &ni->ni_rates); 936 rt2860_set_bssid(sc, ni->ni_bssid); 937 } 938 939 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 940 vap->iv_opmode == IEEE80211_M_IBSS || 941 vap->iv_opmode == IEEE80211_M_MBSS) { 942 error = rt2860_setup_beacon(sc, vap); 943 if (error != 0) 944 return error; 945 } 946 947 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 948 rt2860_enable_tsf_sync(sc); 949 rt2860_set_gp_timer(sc, 500); 950 } 951 952 /* turn link LED on */ 953 rt2860_set_leds(sc, RT2860_LED_RADIO | 954 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 955 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 956 } 957 return error; 958 } 959 960 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 961 static uint16_t 962 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 963 { 964 uint32_t tmp; 965 uint16_t reg; 966 int ntries; 967 968 addr *= 2; 969 /*- 970 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 971 * DATA0: F E D C 972 * DATA1: B A 9 8 973 * DATA2: 7 6 5 4 974 * DATA3: 3 2 1 0 975 */ 976 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 977 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 978 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 979 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 980 for (ntries = 0; ntries < 500; ntries++) { 981 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 982 if (!(tmp & RT3070_EFSROM_KICK)) 983 break; 984 DELAY(2); 985 } 986 if (ntries == 500) 987 return 0xffff; 988 989 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 990 return 0xffff; /* address not found */ 991 992 /* determine to which 32-bit register our 16-bit word belongs */ 993 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 994 tmp = RAL_READ(sc, reg); 995 996 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 997 } 998 999 /* 1000 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1001 * 93C66 or 93C86). 1002 */ 1003 static uint16_t 1004 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1005 { 1006 uint32_t tmp; 1007 uint16_t val; 1008 int n; 1009 1010 /* clock C once before the first command */ 1011 RT2860_EEPROM_CTL(sc, 0); 1012 1013 RT2860_EEPROM_CTL(sc, RT2860_S); 1014 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1015 RT2860_EEPROM_CTL(sc, RT2860_S); 1016 1017 /* write start bit (1) */ 1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1020 1021 /* write READ opcode (10) */ 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1023 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1024 RT2860_EEPROM_CTL(sc, RT2860_S); 1025 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1026 1027 /* write address (A5-A0 or A7-A0) */ 1028 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1029 for (; n >= 0; n--) { 1030 RT2860_EEPROM_CTL(sc, RT2860_S | 1031 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1032 RT2860_EEPROM_CTL(sc, RT2860_S | 1033 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1034 } 1035 1036 RT2860_EEPROM_CTL(sc, RT2860_S); 1037 1038 /* read data Q15-Q0 */ 1039 val = 0; 1040 for (n = 15; n >= 0; n--) { 1041 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1042 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1043 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1044 RT2860_EEPROM_CTL(sc, RT2860_S); 1045 } 1046 1047 RT2860_EEPROM_CTL(sc, 0); 1048 1049 /* clear Chip Select and clock C */ 1050 RT2860_EEPROM_CTL(sc, RT2860_S); 1051 RT2860_EEPROM_CTL(sc, 0); 1052 RT2860_EEPROM_CTL(sc, RT2860_C); 1053 1054 return val; 1055 } 1056 1057 static __inline uint16_t 1058 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1059 { 1060 /* either eFUSE ROM or EEPROM */ 1061 return sc->sc_srom_read(sc, addr); 1062 } 1063 1064 static void 1065 rt2860_intr_coherent(struct rt2860_softc *sc) 1066 { 1067 uint32_t tmp; 1068 1069 /* DMA finds data coherent event when checking the DDONE bit */ 1070 1071 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1072 1073 /* restart DMA engine */ 1074 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1075 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1076 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1077 1078 (void)rt2860_txrx_enable(sc); 1079 } 1080 1081 static void 1082 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1083 { 1084 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1085 struct ieee80211_node *ni; 1086 uint32_t stat; 1087 uint8_t wcid, mcs, pid; 1088 1089 /* drain Tx status FIFO (maxsize = 16) */ 1090 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1091 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1092 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1093 1094 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1095 if (wcid > RT2860_WCID_MAX) 1096 continue; 1097 ni = sc->wcid2ni[wcid]; 1098 1099 /* if no ACK was requested, no feedback is available */ 1100 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1101 continue; 1102 1103 /* update per-STA AMRR stats */ 1104 if (stat & RT2860_TXQ_OK) { 1105 /* 1106 * Check if there were retries, ie if the Tx success 1107 * rate is different from the requested rate. Note 1108 * that it works only because we do not allow rate 1109 * fallback from OFDM to CCK. 1110 */ 1111 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1112 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1113 if (mcs + 1 != pid) 1114 txs->long_retries = 1; 1115 else 1116 txs->long_retries = 0; 1117 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1118 ieee80211_ratectl_tx_complete(ni, txs); 1119 } else { 1120 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1121 txs->long_retries = 1; /* XXX */ 1122 ieee80211_ratectl_tx_complete(ni, txs); 1123 if_inc_counter(ni->ni_vap->iv_ifp, 1124 IFCOUNTER_OERRORS, 1); 1125 } 1126 } 1127 } 1128 1129 static void 1130 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1131 { 1132 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1133 uint32_t hw; 1134 1135 rt2860_drain_stats_fifo(sc); 1136 1137 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1138 while (ring->next != hw) { 1139 struct rt2860_tx_data *data = ring->data[ring->next]; 1140 1141 if (data != NULL) { 1142 bus_dmamap_sync(sc->txwi_dmat, data->map, 1143 BUS_DMASYNC_POSTWRITE); 1144 bus_dmamap_unload(sc->txwi_dmat, data->map); 1145 ieee80211_tx_complete(data->ni, data->m, 0); 1146 data->ni = NULL; 1147 data->m = NULL; 1148 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1149 ring->data[ring->next] = NULL; 1150 } 1151 ring->queued--; 1152 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1153 } 1154 1155 sc->sc_tx_timer = 0; 1156 if (ring->queued < RT2860_TX_RING_COUNT) 1157 sc->qfullmsk &= ~(1 << qid); 1158 rt2860_start(sc); 1159 } 1160 1161 /* 1162 * Return the Rx chain with the highest RSSI for a given frame. 1163 */ 1164 static __inline uint8_t 1165 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1166 { 1167 uint8_t rxchain = 0; 1168 1169 if (sc->nrxchains > 1) { 1170 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1171 rxchain = 1; 1172 if (sc->nrxchains > 2) 1173 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1174 rxchain = 2; 1175 } 1176 return rxchain; 1177 } 1178 1179 static void 1180 rt2860_rx_intr(struct rt2860_softc *sc) 1181 { 1182 struct rt2860_rx_radiotap_header *tap; 1183 struct ieee80211com *ic = &sc->sc_ic; 1184 struct ieee80211_frame *wh; 1185 struct ieee80211_node *ni; 1186 struct mbuf *m, *m1; 1187 bus_addr_t physaddr; 1188 uint32_t hw; 1189 uint16_t phy; 1190 uint8_t ant; 1191 int8_t rssi, nf; 1192 int error; 1193 1194 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1195 while (sc->rxq.cur != hw) { 1196 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1197 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1198 struct rt2860_rxwi *rxwi; 1199 1200 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1201 BUS_DMASYNC_POSTREAD); 1202 1203 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1204 DPRINTF(("RXD DDONE bit not set!\n")); 1205 break; /* should not happen */ 1206 } 1207 1208 if (__predict_false(rxd->flags & 1209 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1210 counter_u64_add(ic->ic_ierrors, 1); 1211 goto skip; 1212 } 1213 1214 #ifdef HW_CRYPTO 1215 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1216 /* report MIC failures to net80211 for TKIP */ 1217 ic->ic_stats.is_rx_locmicfail++; 1218 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1219 counter_u64_add(ic->ic_ierrors, 1); 1220 goto skip; 1221 } 1222 #endif 1223 1224 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1225 if (__predict_false(m1 == NULL)) { 1226 counter_u64_add(ic->ic_ierrors, 1); 1227 goto skip; 1228 } 1229 1230 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1231 BUS_DMASYNC_POSTREAD); 1232 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1233 1234 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1235 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1236 &physaddr, 0); 1237 if (__predict_false(error != 0)) { 1238 m_freem(m1); 1239 1240 /* try to reload the old mbuf */ 1241 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1242 mtod(data->m, void *), MCLBYTES, 1243 rt2860_dma_map_addr, &physaddr, 0); 1244 if (__predict_false(error != 0)) { 1245 panic("%s: could not load old rx mbuf", 1246 device_get_name(sc->sc_dev)); 1247 } 1248 /* physical address may have changed */ 1249 rxd->sdp0 = htole32(physaddr); 1250 counter_u64_add(ic->ic_ierrors, 1); 1251 goto skip; 1252 } 1253 1254 /* 1255 * New mbuf successfully loaded, update Rx ring and continue 1256 * processing. 1257 */ 1258 m = data->m; 1259 data->m = m1; 1260 rxd->sdp0 = htole32(physaddr); 1261 1262 rxwi = mtod(m, struct rt2860_rxwi *); 1263 1264 /* finalize mbuf */ 1265 m->m_data = (caddr_t)(rxwi + 1); 1266 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1267 1268 wh = mtod(m, struct ieee80211_frame *); 1269 #ifdef HW_CRYPTO 1270 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1271 /* frame is decrypted by hardware */ 1272 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1273 } 1274 #endif 1275 1276 /* HW may insert 2 padding bytes after 802.11 header */ 1277 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1278 u_int hdrlen = ieee80211_hdrsize(wh); 1279 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1280 m->m_data += 2; 1281 wh = mtod(m, struct ieee80211_frame *); 1282 } 1283 1284 ant = rt2860_maxrssi_chain(sc, rxwi); 1285 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1286 nf = RT2860_NOISE_FLOOR; 1287 1288 if (ieee80211_radiotap_active(ic)) { 1289 tap = &sc->sc_rxtap; 1290 tap->wr_flags = 0; 1291 tap->wr_antenna = ant; 1292 tap->wr_antsignal = nf + rssi; 1293 tap->wr_antnoise = nf; 1294 /* in case it can't be found below */ 1295 tap->wr_rate = 2; 1296 phy = le16toh(rxwi->phy); 1297 switch (phy & RT2860_PHY_MODE) { 1298 case RT2860_PHY_CCK: 1299 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1300 case 0: tap->wr_rate = 2; break; 1301 case 1: tap->wr_rate = 4; break; 1302 case 2: tap->wr_rate = 11; break; 1303 case 3: tap->wr_rate = 22; break; 1304 } 1305 if (phy & RT2860_PHY_SHPRE) 1306 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1307 break; 1308 case RT2860_PHY_OFDM: 1309 switch (phy & RT2860_PHY_MCS) { 1310 case 0: tap->wr_rate = 12; break; 1311 case 1: tap->wr_rate = 18; break; 1312 case 2: tap->wr_rate = 24; break; 1313 case 3: tap->wr_rate = 36; break; 1314 case 4: tap->wr_rate = 48; break; 1315 case 5: tap->wr_rate = 72; break; 1316 case 6: tap->wr_rate = 96; break; 1317 case 7: tap->wr_rate = 108; break; 1318 } 1319 break; 1320 } 1321 } 1322 1323 RAL_UNLOCK(sc); 1324 wh = mtod(m, struct ieee80211_frame *); 1325 1326 /* send the frame to the 802.11 layer */ 1327 ni = ieee80211_find_rxnode(ic, 1328 (struct ieee80211_frame_min *)wh); 1329 if (ni != NULL) { 1330 (void)ieee80211_input(ni, m, rssi - nf, nf); 1331 ieee80211_free_node(ni); 1332 } else 1333 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1334 1335 RAL_LOCK(sc); 1336 1337 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1338 1339 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1340 BUS_DMASYNC_PREWRITE); 1341 1342 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1343 } 1344 1345 /* tell HW what we have processed */ 1346 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1347 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1348 } 1349 1350 static void 1351 rt2860_tbtt_intr(struct rt2860_softc *sc) 1352 { 1353 #if 0 1354 struct ieee80211com *ic = &sc->sc_ic; 1355 1356 #ifndef IEEE80211_STA_ONLY 1357 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1358 /* one less beacon until next DTIM */ 1359 if (ic->ic_dtim_count == 0) 1360 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1361 else 1362 ic->ic_dtim_count--; 1363 1364 /* update dynamic parts of beacon */ 1365 rt2860_setup_beacon(sc); 1366 1367 /* flush buffered multicast frames */ 1368 if (ic->ic_dtim_count == 0) 1369 ieee80211_notify_dtim(ic); 1370 } 1371 #endif 1372 /* check if protection mode has changed */ 1373 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1374 rt2860_updateprot(sc); 1375 sc->sc_ic_flags = ic->ic_flags; 1376 } 1377 #endif 1378 } 1379 1380 static void 1381 rt2860_gp_intr(struct rt2860_softc *sc) 1382 { 1383 struct ieee80211com *ic = &sc->sc_ic; 1384 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1385 1386 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1387 1388 if (vap->iv_state == IEEE80211_S_RUN) 1389 rt2860_updatestats(sc); 1390 } 1391 1392 void 1393 rt2860_intr(void *arg) 1394 { 1395 struct rt2860_softc *sc = arg; 1396 uint32_t r; 1397 1398 RAL_LOCK(sc); 1399 1400 r = RAL_READ(sc, RT2860_INT_STATUS); 1401 if (__predict_false(r == 0xffffffff)) { 1402 RAL_UNLOCK(sc); 1403 return; /* device likely went away */ 1404 } 1405 if (r == 0) { 1406 RAL_UNLOCK(sc); 1407 return; /* not for us */ 1408 } 1409 1410 /* acknowledge interrupts */ 1411 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1412 1413 if (r & RT2860_TX_RX_COHERENT) 1414 rt2860_intr_coherent(sc); 1415 1416 if (r & RT2860_MAC_INT_2) /* TX status */ 1417 rt2860_drain_stats_fifo(sc); 1418 1419 if (r & RT2860_TX_DONE_INT5) 1420 rt2860_tx_intr(sc, 5); 1421 1422 if (r & RT2860_RX_DONE_INT) 1423 rt2860_rx_intr(sc); 1424 1425 if (r & RT2860_TX_DONE_INT4) 1426 rt2860_tx_intr(sc, 4); 1427 1428 if (r & RT2860_TX_DONE_INT3) 1429 rt2860_tx_intr(sc, 3); 1430 1431 if (r & RT2860_TX_DONE_INT2) 1432 rt2860_tx_intr(sc, 2); 1433 1434 if (r & RT2860_TX_DONE_INT1) 1435 rt2860_tx_intr(sc, 1); 1436 1437 if (r & RT2860_TX_DONE_INT0) 1438 rt2860_tx_intr(sc, 0); 1439 1440 if (r & RT2860_MAC_INT_0) /* TBTT */ 1441 rt2860_tbtt_intr(sc); 1442 1443 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1444 /* TBD wakeup */; 1445 1446 if (r & RT2860_MAC_INT_4) /* GP timer */ 1447 rt2860_gp_intr(sc); 1448 1449 RAL_UNLOCK(sc); 1450 } 1451 1452 static int 1453 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1454 { 1455 struct ieee80211com *ic = &sc->sc_ic; 1456 struct ieee80211vap *vap = ni->ni_vap; 1457 struct rt2860_tx_ring *ring; 1458 struct rt2860_tx_data *data; 1459 struct rt2860_txd *txd; 1460 struct rt2860_txwi *txwi; 1461 struct ieee80211_frame *wh; 1462 const struct ieee80211_txparam *tp = ni->ni_txparms; 1463 struct ieee80211_key *k; 1464 struct mbuf *m1; 1465 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1466 bus_dma_segment_t *seg; 1467 u_int hdrlen; 1468 uint16_t qos, dur; 1469 uint8_t type, qsel, mcs, pid, tid, qid; 1470 int i, nsegs, ntxds, pad, rate, ridx, error; 1471 1472 /* the data pool contains at least one element, pick the first */ 1473 data = SLIST_FIRST(&sc->data_pool); 1474 1475 wh = mtod(m, struct ieee80211_frame *); 1476 1477 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1478 k = ieee80211_crypto_encap(ni, m); 1479 if (k == NULL) { 1480 m_freem(m); 1481 return ENOBUFS; 1482 } 1483 1484 /* packet header may have moved, reset our local pointer */ 1485 wh = mtod(m, struct ieee80211_frame *); 1486 } 1487 1488 hdrlen = ieee80211_anyhdrsize(wh); 1489 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1490 1491 if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1494 rate = tp->mcastrate; 1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1496 rate = tp->ucastrate; 1497 } else { 1498 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1499 rate = ni->ni_txrate; 1500 } 1501 rate &= IEEE80211_RATE_VAL; 1502 1503 qid = M_WME_GETAC(m); 1504 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1505 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1506 tid = qos & IEEE80211_QOS_TID; 1507 } else { 1508 qos = 0; 1509 tid = 0; 1510 } 1511 ring = &sc->txq[qid]; 1512 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1513 1514 /* get MCS code from rate index */ 1515 mcs = rt2860_rates[ridx].mcs; 1516 1517 /* setup TX Wireless Information */ 1518 txwi = data->txwi; 1519 txwi->flags = 0; 1520 /* let HW generate seq numbers for non-QoS frames */ 1521 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1522 if (type == IEEE80211_FC0_TYPE_DATA) 1523 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1524 else 1525 txwi->wcid = 0xff; 1526 txwi->len = htole16(m->m_pkthdr.len); 1527 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1528 txwi->phy = htole16(RT2860_PHY_CCK); 1529 if (ridx != RT2860_RIDX_CCK1 && 1530 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1531 mcs |= RT2860_PHY_SHPRE; 1532 } else 1533 txwi->phy = htole16(RT2860_PHY_OFDM); 1534 txwi->phy |= htole16(mcs); 1535 1536 /* 1537 * We store the MCS code into the driver-private PacketID field. 1538 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1539 * that we know at which initial rate the frame was transmitted. 1540 * We add 1 to the MCS code because setting the PacketID field to 1541 * 0 means that we don't want feedback in TX_STAT_FIFO. 1542 */ 1543 pid = (mcs + 1) & 0xf; 1544 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1545 1546 /* check if RTS/CTS or CTS-to-self protection is required */ 1547 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1548 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1549 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1550 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1551 txwi->txop = RT2860_TX_TXOP_HT; 1552 else 1553 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1554 1555 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1556 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1557 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1558 txwi->xflags |= RT2860_TX_ACK; 1559 1560 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1561 dur = rt2860_rates[ridx].sp_ack_dur; 1562 else 1563 dur = rt2860_rates[ridx].lp_ack_dur; 1564 *(uint16_t *)wh->i_dur = htole16(dur); 1565 } 1566 /* ask MAC to insert timestamp into probe responses */ 1567 if ((wh->i_fc[0] & 1568 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1569 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1570 /* NOTE: beacons do not pass through tx_data() */ 1571 txwi->flags |= RT2860_TX_TS; 1572 1573 if (ieee80211_radiotap_active_vap(vap)) { 1574 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1575 1576 tap->wt_flags = 0; 1577 tap->wt_rate = rate; 1578 if (mcs & RT2860_PHY_SHPRE) 1579 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1580 1581 ieee80211_radiotap_tx(vap, m); 1582 } 1583 1584 pad = (hdrlen + 3) & ~3; 1585 1586 /* copy and trim 802.11 header */ 1587 memcpy(txwi + 1, wh, hdrlen); 1588 m_adj(m, hdrlen); 1589 1590 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1591 &nsegs, 0); 1592 if (__predict_false(error != 0 && error != EFBIG)) { 1593 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1594 error); 1595 m_freem(m); 1596 return error; 1597 } 1598 if (__predict_true(error == 0)) { 1599 /* determine how many TXDs are required */ 1600 ntxds = 1 + (nsegs / 2); 1601 1602 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1603 /* not enough free TXDs, force mbuf defrag */ 1604 bus_dmamap_unload(sc->txwi_dmat, data->map); 1605 error = EFBIG; 1606 } 1607 } 1608 if (__predict_false(error != 0)) { 1609 m1 = m_defrag(m, M_NOWAIT); 1610 if (m1 == NULL) { 1611 device_printf(sc->sc_dev, 1612 "could not defragment mbuf\n"); 1613 m_freem(m); 1614 return ENOBUFS; 1615 } 1616 m = m1; 1617 1618 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1619 segs, &nsegs, 0); 1620 if (__predict_false(error != 0)) { 1621 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1622 error); 1623 m_freem(m); 1624 return error; 1625 } 1626 1627 /* determine how many TXDs are now required */ 1628 ntxds = 1 + (nsegs / 2); 1629 1630 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1631 /* this is a hopeless case, drop the mbuf! */ 1632 bus_dmamap_unload(sc->txwi_dmat, data->map); 1633 m_freem(m); 1634 return ENOBUFS; 1635 } 1636 } 1637 1638 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1639 1640 /* first segment is TXWI + 802.11 header */ 1641 txd = &ring->txd[ring->cur]; 1642 txd->sdp0 = htole32(data->paddr); 1643 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1644 txd->flags = qsel; 1645 1646 /* setup payload segments */ 1647 seg = &segs[0]; 1648 for (i = nsegs; i >= 2; i -= 2) { 1649 txd->sdp1 = htole32(seg->ds_addr); 1650 txd->sdl1 = htole16(seg->ds_len); 1651 seg++; 1652 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1653 /* grab a new Tx descriptor */ 1654 txd = &ring->txd[ring->cur]; 1655 txd->sdp0 = htole32(seg->ds_addr); 1656 txd->sdl0 = htole16(seg->ds_len); 1657 txd->flags = qsel; 1658 seg++; 1659 } 1660 /* finalize last segment */ 1661 if (i > 0) { 1662 txd->sdp1 = htole32(seg->ds_addr); 1663 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1664 } else { 1665 txd->sdl0 |= htole16(RT2860_TX_LS0); 1666 txd->sdl1 = 0; 1667 } 1668 1669 /* remove from the free pool and link it into the SW Tx slot */ 1670 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1671 data->m = m; 1672 data->ni = ni; 1673 ring->data[ring->cur] = data; 1674 1675 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1676 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1677 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1678 1679 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1680 qid, txwi->wcid, nsegs, ridx)); 1681 1682 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1683 ring->queued += ntxds; 1684 if (ring->queued >= RT2860_TX_RING_COUNT) 1685 sc->qfullmsk |= 1 << qid; 1686 1687 /* kick Tx */ 1688 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1689 1690 return 0; 1691 } 1692 1693 static int 1694 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1695 const struct ieee80211_bpf_params *params) 1696 { 1697 struct ieee80211com *ic = ni->ni_ic; 1698 struct rt2860_softc *sc = ic->ic_softc; 1699 int error; 1700 1701 RAL_LOCK(sc); 1702 1703 /* prevent management frames from being sent if we're not ready */ 1704 if (!(sc->sc_flags & RT2860_RUNNING)) { 1705 RAL_UNLOCK(sc); 1706 m_freem(m); 1707 return ENETDOWN; 1708 } 1709 if (params == NULL) { 1710 /* 1711 * Legacy path; interpret frame contents to decide 1712 * precisely how to send the frame. 1713 */ 1714 error = rt2860_tx(sc, m, ni); 1715 } else { 1716 /* 1717 * Caller supplied explicit parameters to use in 1718 * sending the frame. 1719 */ 1720 error = rt2860_tx_raw(sc, m, ni, params); 1721 } 1722 sc->sc_tx_timer = 5; 1723 RAL_UNLOCK(sc); 1724 return error; 1725 } 1726 1727 static int 1728 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1729 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1730 { 1731 struct ieee80211com *ic = &sc->sc_ic; 1732 struct ieee80211vap *vap = ni->ni_vap; 1733 struct rt2860_tx_ring *ring; 1734 struct rt2860_tx_data *data; 1735 struct rt2860_txd *txd; 1736 struct rt2860_txwi *txwi; 1737 struct ieee80211_frame *wh; 1738 struct mbuf *m1; 1739 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1740 bus_dma_segment_t *seg; 1741 u_int hdrlen; 1742 uint16_t dur; 1743 uint8_t type, qsel, mcs, pid, tid, qid; 1744 int i, nsegs, ntxds, pad, rate, ridx, error; 1745 1746 /* the data pool contains at least one element, pick the first */ 1747 data = SLIST_FIRST(&sc->data_pool); 1748 1749 wh = mtod(m, struct ieee80211_frame *); 1750 hdrlen = ieee80211_hdrsize(wh); 1751 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1752 1753 /* Choose a TX rate index. */ 1754 rate = params->ibp_rate0; 1755 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1756 rate & IEEE80211_RATE_VAL); 1757 if (ridx == (uint8_t)-1) { 1758 /* XXX fall back to mcast/mgmt rate? */ 1759 m_freem(m); 1760 return EINVAL; 1761 } 1762 1763 qid = params->ibp_pri & 3; 1764 tid = 0; 1765 ring = &sc->txq[qid]; 1766 1767 /* get MCS code from rate index */ 1768 mcs = rt2860_rates[ridx].mcs; 1769 1770 /* setup TX Wireless Information */ 1771 txwi = data->txwi; 1772 txwi->flags = 0; 1773 /* let HW generate seq numbers for non-QoS frames */ 1774 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1775 txwi->wcid = 0xff; 1776 txwi->len = htole16(m->m_pkthdr.len); 1777 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1778 txwi->phy = htole16(RT2860_PHY_CCK); 1779 if (ridx != RT2860_RIDX_CCK1 && 1780 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1781 mcs |= RT2860_PHY_SHPRE; 1782 } else 1783 txwi->phy = htole16(RT2860_PHY_OFDM); 1784 txwi->phy |= htole16(mcs); 1785 1786 /* 1787 * We store the MCS code into the driver-private PacketID field. 1788 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1789 * that we know at which initial rate the frame was transmitted. 1790 * We add 1 to the MCS code because setting the PacketID field to 1791 * 0 means that we don't want feedback in TX_STAT_FIFO. 1792 */ 1793 pid = (mcs + 1) & 0xf; 1794 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1795 1796 /* check if RTS/CTS or CTS-to-self protection is required */ 1797 if (params->ibp_flags & IEEE80211_BPF_RTS || 1798 params->ibp_flags & IEEE80211_BPF_CTS) 1799 txwi->txop = RT2860_TX_TXOP_HT; 1800 else 1801 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1802 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1803 txwi->xflags |= RT2860_TX_ACK; 1804 1805 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1806 dur = rt2860_rates[ridx].sp_ack_dur; 1807 else 1808 dur = rt2860_rates[ridx].lp_ack_dur; 1809 *(uint16_t *)wh->i_dur = htole16(dur); 1810 } 1811 /* ask MAC to insert timestamp into probe responses */ 1812 if ((wh->i_fc[0] & 1813 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1814 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1815 /* NOTE: beacons do not pass through tx_data() */ 1816 txwi->flags |= RT2860_TX_TS; 1817 1818 if (ieee80211_radiotap_active_vap(vap)) { 1819 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1820 1821 tap->wt_flags = 0; 1822 tap->wt_rate = rate; 1823 if (mcs & RT2860_PHY_SHPRE) 1824 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1825 1826 ieee80211_radiotap_tx(vap, m); 1827 } 1828 1829 pad = (hdrlen + 3) & ~3; 1830 1831 /* copy and trim 802.11 header */ 1832 memcpy(txwi + 1, wh, hdrlen); 1833 m_adj(m, hdrlen); 1834 1835 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1836 &nsegs, 0); 1837 if (__predict_false(error != 0 && error != EFBIG)) { 1838 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1839 error); 1840 m_freem(m); 1841 return error; 1842 } 1843 if (__predict_true(error == 0)) { 1844 /* determine how many TXDs are required */ 1845 ntxds = 1 + (nsegs / 2); 1846 1847 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1848 /* not enough free TXDs, force mbuf defrag */ 1849 bus_dmamap_unload(sc->txwi_dmat, data->map); 1850 error = EFBIG; 1851 } 1852 } 1853 if (__predict_false(error != 0)) { 1854 m1 = m_defrag(m, M_NOWAIT); 1855 if (m1 == NULL) { 1856 device_printf(sc->sc_dev, 1857 "could not defragment mbuf\n"); 1858 m_freem(m); 1859 return ENOBUFS; 1860 } 1861 m = m1; 1862 1863 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1864 segs, &nsegs, 0); 1865 if (__predict_false(error != 0)) { 1866 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1867 error); 1868 m_freem(m); 1869 return error; 1870 } 1871 1872 /* determine how many TXDs are now required */ 1873 ntxds = 1 + (nsegs / 2); 1874 1875 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1876 /* this is a hopeless case, drop the mbuf! */ 1877 bus_dmamap_unload(sc->txwi_dmat, data->map); 1878 m_freem(m); 1879 return ENOBUFS; 1880 } 1881 } 1882 1883 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1884 1885 /* first segment is TXWI + 802.11 header */ 1886 txd = &ring->txd[ring->cur]; 1887 txd->sdp0 = htole32(data->paddr); 1888 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1889 txd->flags = qsel; 1890 1891 /* setup payload segments */ 1892 seg = &segs[0]; 1893 for (i = nsegs; i >= 2; i -= 2) { 1894 txd->sdp1 = htole32(seg->ds_addr); 1895 txd->sdl1 = htole16(seg->ds_len); 1896 seg++; 1897 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1898 /* grab a new Tx descriptor */ 1899 txd = &ring->txd[ring->cur]; 1900 txd->sdp0 = htole32(seg->ds_addr); 1901 txd->sdl0 = htole16(seg->ds_len); 1902 txd->flags = qsel; 1903 seg++; 1904 } 1905 /* finalize last segment */ 1906 if (i > 0) { 1907 txd->sdp1 = htole32(seg->ds_addr); 1908 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1909 } else { 1910 txd->sdl0 |= htole16(RT2860_TX_LS0); 1911 txd->sdl1 = 0; 1912 } 1913 1914 /* remove from the free pool and link it into the SW Tx slot */ 1915 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1916 data->m = m; 1917 data->ni = ni; 1918 ring->data[ring->cur] = data; 1919 1920 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1921 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1922 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1923 1924 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1925 qid, txwi->wcid, nsegs, ridx)); 1926 1927 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1928 ring->queued += ntxds; 1929 if (ring->queued >= RT2860_TX_RING_COUNT) 1930 sc->qfullmsk |= 1 << qid; 1931 1932 /* kick Tx */ 1933 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1934 1935 return 0; 1936 } 1937 1938 static int 1939 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1940 { 1941 struct rt2860_softc *sc = ic->ic_softc; 1942 int error; 1943 1944 RAL_LOCK(sc); 1945 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1946 RAL_UNLOCK(sc); 1947 return (ENXIO); 1948 } 1949 error = mbufq_enqueue(&sc->sc_snd, m); 1950 if (error) { 1951 RAL_UNLOCK(sc); 1952 return (error); 1953 } 1954 rt2860_start(sc); 1955 RAL_UNLOCK(sc); 1956 1957 return (0); 1958 } 1959 1960 static void 1961 rt2860_start(struct rt2860_softc *sc) 1962 { 1963 struct ieee80211_node *ni; 1964 struct mbuf *m; 1965 1966 RAL_LOCK_ASSERT(sc); 1967 1968 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1969 return; 1970 1971 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1972 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1973 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1974 if (rt2860_tx(sc, m, ni) != 0) { 1975 if_inc_counter(ni->ni_vap->iv_ifp, 1976 IFCOUNTER_OERRORS, 1); 1977 ieee80211_free_node(ni); 1978 continue; 1979 } 1980 sc->sc_tx_timer = 5; 1981 } 1982 } 1983 1984 static void 1985 rt2860_watchdog(void *arg) 1986 { 1987 struct rt2860_softc *sc = arg; 1988 1989 RAL_LOCK_ASSERT(sc); 1990 1991 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1992 1993 if (sc->sc_invalid) /* card ejected */ 1994 return; 1995 1996 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1997 device_printf(sc->sc_dev, "device timeout\n"); 1998 rt2860_stop_locked(sc); 1999 rt2860_init_locked(sc); 2000 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2001 return; 2002 } 2003 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2004 } 2005 2006 static void 2007 rt2860_parent(struct ieee80211com *ic) 2008 { 2009 struct rt2860_softc *sc = ic->ic_softc; 2010 int startall = 0; 2011 2012 RAL_LOCK(sc); 2013 if (ic->ic_nrunning> 0) { 2014 if (!(sc->sc_flags & RT2860_RUNNING)) { 2015 rt2860_init_locked(sc); 2016 startall = 1; 2017 } else 2018 rt2860_update_promisc(ic); 2019 } else if (sc->sc_flags & RT2860_RUNNING) 2020 rt2860_stop_locked(sc); 2021 RAL_UNLOCK(sc); 2022 if (startall) 2023 ieee80211_start_all(ic); 2024 } 2025 2026 /* 2027 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2028 * We access the BBP through the 8051 microcontroller unit which means that 2029 * the microcode must be loaded first. 2030 */ 2031 void 2032 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2033 { 2034 int ntries; 2035 2036 for (ntries = 0; ntries < 100; ntries++) { 2037 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2038 break; 2039 DELAY(1); 2040 } 2041 if (ntries == 100) { 2042 device_printf(sc->sc_dev, 2043 "could not write to BBP through MCU\n"); 2044 return; 2045 } 2046 2047 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2048 RT2860_BBP_CSR_KICK | reg << 8 | val); 2049 RAL_BARRIER_WRITE(sc); 2050 2051 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2052 DELAY(1000); 2053 } 2054 2055 uint8_t 2056 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2057 { 2058 uint32_t val; 2059 int ntries; 2060 2061 for (ntries = 0; ntries < 100; ntries++) { 2062 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2063 break; 2064 DELAY(1); 2065 } 2066 if (ntries == 100) { 2067 device_printf(sc->sc_dev, 2068 "could not read from BBP through MCU\n"); 2069 return 0; 2070 } 2071 2072 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2073 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2074 RAL_BARRIER_WRITE(sc); 2075 2076 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2077 DELAY(1000); 2078 2079 for (ntries = 0; ntries < 100; ntries++) { 2080 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2081 if (!(val & RT2860_BBP_CSR_KICK)) 2082 return val & 0xff; 2083 DELAY(1); 2084 } 2085 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2086 2087 return 0; 2088 } 2089 2090 /* 2091 * Write to one of the 4 programmable 24-bit RF registers. 2092 */ 2093 static void 2094 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2095 { 2096 uint32_t tmp; 2097 int ntries; 2098 2099 for (ntries = 0; ntries < 100; ntries++) { 2100 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2101 break; 2102 DELAY(1); 2103 } 2104 if (ntries == 100) { 2105 device_printf(sc->sc_dev, "could not write to RF\n"); 2106 return; 2107 } 2108 2109 /* RF registers are 24-bit on the RT2860 */ 2110 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2111 (val & 0x3fffff) << 2 | (reg & 3); 2112 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2113 } 2114 2115 static uint8_t 2116 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2117 { 2118 uint32_t tmp; 2119 int ntries; 2120 2121 for (ntries = 0; ntries < 100; ntries++) { 2122 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2123 break; 2124 DELAY(1); 2125 } 2126 if (ntries == 100) { 2127 device_printf(sc->sc_dev, "could not read RF register\n"); 2128 return 0xff; 2129 } 2130 tmp = RT3070_RF_KICK | reg << 8; 2131 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2132 2133 for (ntries = 0; ntries < 100; ntries++) { 2134 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2135 if (!(tmp & RT3070_RF_KICK)) 2136 break; 2137 DELAY(1); 2138 } 2139 if (ntries == 100) { 2140 device_printf(sc->sc_dev, "could not read RF register\n"); 2141 return 0xff; 2142 } 2143 return tmp & 0xff; 2144 } 2145 2146 void 2147 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2148 { 2149 uint32_t tmp; 2150 int ntries; 2151 2152 for (ntries = 0; ntries < 10; ntries++) { 2153 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2154 break; 2155 DELAY(10); 2156 } 2157 if (ntries == 10) { 2158 device_printf(sc->sc_dev, "could not write to RF\n"); 2159 return; 2160 } 2161 2162 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2163 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2164 } 2165 2166 /* 2167 * Send a command to the 8051 microcontroller unit. 2168 */ 2169 int 2170 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2171 { 2172 int slot, ntries; 2173 uint32_t tmp; 2174 uint8_t cid; 2175 2176 for (ntries = 0; ntries < 100; ntries++) { 2177 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2178 break; 2179 DELAY(2); 2180 } 2181 if (ntries == 100) 2182 return EIO; 2183 2184 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2185 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2186 RAL_BARRIER_WRITE(sc); 2187 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2188 2189 if (!wait) 2190 return 0; 2191 /* wait for the command to complete */ 2192 for (ntries = 0; ntries < 200; ntries++) { 2193 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2194 /* find the command slot */ 2195 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2196 if ((tmp & 0xff) == cid) 2197 break; 2198 if (slot < 4) 2199 break; 2200 DELAY(100); 2201 } 2202 if (ntries == 200) { 2203 /* clear command and status */ 2204 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2205 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2206 return ETIMEDOUT; 2207 } 2208 /* get command status (1 means success) */ 2209 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2210 tmp = (tmp >> (slot * 8)) & 0xff; 2211 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2212 cmd, slot, tmp)); 2213 /* clear command and status */ 2214 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2215 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2216 return (tmp == 1) ? 0 : EIO; 2217 } 2218 2219 static void 2220 rt2860_enable_mrr(struct rt2860_softc *sc) 2221 { 2222 #define CCK(mcs) (mcs) 2223 #define OFDM(mcs) (1 << 3 | (mcs)) 2224 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2225 OFDM(6) << 28 | /* 54->48 */ 2226 OFDM(5) << 24 | /* 48->36 */ 2227 OFDM(4) << 20 | /* 36->24 */ 2228 OFDM(3) << 16 | /* 24->18 */ 2229 OFDM(2) << 12 | /* 18->12 */ 2230 OFDM(1) << 8 | /* 12-> 9 */ 2231 OFDM(0) << 4 | /* 9-> 6 */ 2232 OFDM(0)); /* 6-> 6 */ 2233 2234 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2235 CCK(2) << 12 | /* 11->5.5 */ 2236 CCK(1) << 8 | /* 5.5-> 2 */ 2237 CCK(0) << 4 | /* 2-> 1 */ 2238 CCK(0)); /* 1-> 1 */ 2239 #undef OFDM 2240 #undef CCK 2241 } 2242 2243 static void 2244 rt2860_set_txpreamble(struct rt2860_softc *sc) 2245 { 2246 struct ieee80211com *ic = &sc->sc_ic; 2247 uint32_t tmp; 2248 2249 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2250 tmp &= ~RT2860_CCK_SHORT_EN; 2251 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2252 tmp |= RT2860_CCK_SHORT_EN; 2253 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2254 } 2255 2256 void 2257 rt2860_set_basicrates(struct rt2860_softc *sc, 2258 const struct ieee80211_rateset *rs) 2259 { 2260 struct ieee80211com *ic = &sc->sc_ic; 2261 uint32_t mask = 0; 2262 uint8_t rate; 2263 int i; 2264 2265 for (i = 0; i < rs->rs_nrates; i++) { 2266 rate = rs->rs_rates[i]; 2267 2268 if (!(rate & IEEE80211_RATE_BASIC)) 2269 continue; 2270 2271 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2272 IEEE80211_RV(rate)); 2273 } 2274 2275 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2276 } 2277 2278 static void 2279 rt2860_scan_start(struct ieee80211com *ic) 2280 { 2281 struct rt2860_softc *sc = ic->ic_softc; 2282 uint32_t tmp; 2283 2284 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2285 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2286 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2287 RT2860_TBTT_TIMER_EN)); 2288 rt2860_set_gp_timer(sc, 0); 2289 } 2290 2291 static void 2292 rt2860_scan_end(struct ieee80211com *ic) 2293 { 2294 struct rt2860_softc *sc = ic->ic_softc; 2295 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2296 2297 if (vap->iv_state == IEEE80211_S_RUN) { 2298 rt2860_enable_tsf_sync(sc); 2299 rt2860_set_gp_timer(sc, 500); 2300 } 2301 } 2302 2303 static void 2304 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2305 struct ieee80211_channel chans[]) 2306 { 2307 struct rt2860_softc *sc = ic->ic_softc; 2308 uint8_t bands[IEEE80211_MODE_BYTES]; 2309 2310 memset(bands, 0, sizeof(bands)); 2311 setbit(bands, IEEE80211_MODE_11B); 2312 setbit(bands, IEEE80211_MODE_11G); 2313 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2314 2315 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2316 setbit(bands, IEEE80211_MODE_11A); 2317 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2318 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2319 } 2320 } 2321 2322 static void 2323 rt2860_set_channel(struct ieee80211com *ic) 2324 { 2325 struct rt2860_softc *sc = ic->ic_softc; 2326 2327 RAL_LOCK(sc); 2328 rt2860_switch_chan(sc, ic->ic_curchan); 2329 RAL_UNLOCK(sc); 2330 } 2331 2332 static void 2333 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2334 { 2335 uint32_t tmp; 2336 uint8_t agc; 2337 2338 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2339 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2340 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2341 rt2860_mcu_bbp_write(sc, 86, 0x00); 2342 2343 if (group == 0) { 2344 if (sc->ext_2ghz_lna) { 2345 rt2860_mcu_bbp_write(sc, 82, 0x62); 2346 rt2860_mcu_bbp_write(sc, 75, 0x46); 2347 } else { 2348 rt2860_mcu_bbp_write(sc, 82, 0x84); 2349 rt2860_mcu_bbp_write(sc, 75, 0x50); 2350 } 2351 } else { 2352 if (sc->ext_5ghz_lna) { 2353 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2354 rt2860_mcu_bbp_write(sc, 75, 0x46); 2355 } else { 2356 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2357 rt2860_mcu_bbp_write(sc, 75, 0x50); 2358 } 2359 } 2360 2361 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2362 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2363 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2364 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2365 2366 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2367 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2368 if (sc->nrxchains > 1) 2369 tmp |= RT2860_LNA_PE1_EN; 2370 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2371 tmp |= RT3593_LNA_PE2_EN; 2372 if (group == 0) { /* 2GHz */ 2373 tmp |= RT2860_PA_PE_G0_EN; 2374 if (sc->ntxchains > 1) 2375 tmp |= RT2860_PA_PE_G1_EN; 2376 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2377 tmp |= RT3593_PA_PE_G2_EN; 2378 } else { /* 5GHz */ 2379 tmp |= RT2860_PA_PE_A0_EN; 2380 if (sc->ntxchains > 1) 2381 tmp |= RT2860_PA_PE_A1_EN; 2382 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2383 tmp |= RT3593_PA_PE_A2_EN; 2384 } 2385 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2386 2387 if (sc->mac_ver == 0x3593) { 2388 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2389 if (sc->sc_flags & RT2860_PCIE) { 2390 tmp &= ~0x01010000; 2391 if (group == 0) 2392 tmp |= 0x00010000; 2393 } else { 2394 tmp &= ~0x00008080; 2395 if (group == 0) 2396 tmp |= 0x00000080; 2397 } 2398 tmp = (tmp & ~0x00001000) | 0x00000010; 2399 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2400 } 2401 2402 /* set initial AGC value */ 2403 if (group == 0) { /* 2GHz band */ 2404 if (sc->mac_ver >= 0x3071) 2405 agc = 0x1c + sc->lna[0] * 2; 2406 else 2407 agc = 0x2e + sc->lna[0]; 2408 } else { /* 5GHz band */ 2409 agc = 0x32 + (sc->lna[group] * 5) / 3; 2410 } 2411 rt2860_mcu_bbp_write(sc, 66, agc); 2412 2413 DELAY(1000); 2414 } 2415 2416 static void 2417 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2418 { 2419 const struct rfprog *rfprog = rt2860_rf2850; 2420 uint32_t r2, r3, r4; 2421 int8_t txpow1, txpow2; 2422 u_int i; 2423 2424 /* find the settings for this channel (we know it exists) */ 2425 for (i = 0; rfprog[i].chan != chan; i++); 2426 2427 r2 = rfprog[i].r2; 2428 if (sc->ntxchains == 1) 2429 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2430 if (sc->nrxchains == 1) 2431 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2432 else if (sc->nrxchains == 2) 2433 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2434 2435 /* use Tx power values from EEPROM */ 2436 txpow1 = sc->txpow1[i]; 2437 txpow2 = sc->txpow2[i]; 2438 if (chan > 14) { 2439 if (txpow1 >= 0) 2440 txpow1 = txpow1 << 1 | 1; 2441 else 2442 txpow1 = (7 + txpow1) << 1; 2443 if (txpow2 >= 0) 2444 txpow2 = txpow2 << 1 | 1; 2445 else 2446 txpow2 = (7 + txpow2) << 1; 2447 } 2448 r3 = rfprog[i].r3 | txpow1 << 7; 2449 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2450 2451 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2452 rt2860_rf_write(sc, RT2860_RF2, r2); 2453 rt2860_rf_write(sc, RT2860_RF3, r3); 2454 rt2860_rf_write(sc, RT2860_RF4, r4); 2455 2456 DELAY(200); 2457 2458 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2459 rt2860_rf_write(sc, RT2860_RF2, r2); 2460 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2461 rt2860_rf_write(sc, RT2860_RF4, r4); 2462 2463 DELAY(200); 2464 2465 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2466 rt2860_rf_write(sc, RT2860_RF2, r2); 2467 rt2860_rf_write(sc, RT2860_RF3, r3); 2468 rt2860_rf_write(sc, RT2860_RF4, r4); 2469 } 2470 2471 static void 2472 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2473 { 2474 int8_t txpow1, txpow2; 2475 uint8_t rf; 2476 int i; 2477 2478 /* RT3090 is 2GHz only */ 2479 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2480 2481 /* find the settings for this channel (we know it exists) */ 2482 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2483 2484 /* use Tx power values from EEPROM */ 2485 txpow1 = sc->txpow1[i]; 2486 txpow2 = sc->txpow2[i]; 2487 2488 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2489 rf = rt3090_rf_read(sc, 3); 2490 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2491 rt3090_rf_write(sc, 3, rf); 2492 rf = rt3090_rf_read(sc, 6); 2493 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2494 rt3090_rf_write(sc, 6, rf); 2495 2496 /* set Tx0 power */ 2497 rf = rt3090_rf_read(sc, 12); 2498 rf = (rf & ~0x1f) | txpow1; 2499 rt3090_rf_write(sc, 12, rf); 2500 2501 /* set Tx1 power */ 2502 rf = rt3090_rf_read(sc, 13); 2503 rf = (rf & ~0x1f) | txpow2; 2504 rt3090_rf_write(sc, 13, rf); 2505 2506 rf = rt3090_rf_read(sc, 1); 2507 rf &= ~0xfc; 2508 if (sc->ntxchains == 1) 2509 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2510 else if (sc->ntxchains == 2) 2511 rf |= RT3070_TX2_PD; 2512 if (sc->nrxchains == 1) 2513 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2514 else if (sc->nrxchains == 2) 2515 rf |= RT3070_RX2_PD; 2516 rt3090_rf_write(sc, 1, rf); 2517 2518 /* set RF offset */ 2519 rf = rt3090_rf_read(sc, 23); 2520 rf = (rf & ~0x7f) | sc->freq; 2521 rt3090_rf_write(sc, 23, rf); 2522 2523 /* program RF filter */ 2524 rf = rt3090_rf_read(sc, 24); /* Tx */ 2525 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2526 rt3090_rf_write(sc, 24, rf); 2527 rf = rt3090_rf_read(sc, 31); /* Rx */ 2528 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2529 rt3090_rf_write(sc, 31, rf); 2530 2531 /* enable RF tuning */ 2532 rf = rt3090_rf_read(sc, 7); 2533 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2534 } 2535 2536 static void 2537 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2538 { 2539 uint8_t h20mhz, rf, tmp; 2540 int8_t txpow1, txpow2; 2541 int i; 2542 2543 /* RT5390 is 2GHz only */ 2544 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2545 2546 /* find the settings for this channel (we know it exists) */ 2547 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2548 2549 /* use Tx power values from EEPROM */ 2550 txpow1 = sc->txpow1[i]; 2551 txpow2 = sc->txpow2[i]; 2552 2553 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2554 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2555 rf = rt3090_rf_read(sc, 11); 2556 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2557 rt3090_rf_write(sc, 11, rf); 2558 2559 rf = rt3090_rf_read(sc, 49); 2560 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2561 /* the valid range of the RF R49 is 0x00~0x27 */ 2562 if ((rf & 0x3f) > 0x27) 2563 rf = (rf & ~0x3f) | 0x27; 2564 rt3090_rf_write(sc, 49, rf); 2565 if (sc->mac_ver == 0x5392) { 2566 rf = rt3090_rf_read(sc, 50); 2567 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2568 /* the valid range of the RF R50 is 0x00~0x27 */ 2569 if ((rf & 0x3f) > 0x27) 2570 rf = (rf & ~0x3f) | 0x27; 2571 rt3090_rf_write(sc, 50, rf); 2572 } 2573 2574 rf = rt3090_rf_read(sc, 1); 2575 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2576 if (sc->mac_ver == 0x5392) 2577 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2578 rt3090_rf_write(sc, 1, rf); 2579 2580 rf = rt3090_rf_read(sc, 2); 2581 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2582 DELAY(1000); 2583 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2584 2585 rf = rt3090_rf_read(sc, 17); 2586 tmp = rf; 2587 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2588 rf = MIN(rf, 0x5f); 2589 if (tmp != rf) 2590 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2591 2592 if (sc->mac_ver == 0x5390) { 2593 if (chan <= 4) 2594 rf = 0x73; 2595 else if (chan >= 5 && chan <= 6) 2596 rf = 0x63; 2597 else if (chan >= 7 && chan <= 10) 2598 rf = 0x53; 2599 else 2600 rf = 43; 2601 rt3090_rf_write(sc, 55, rf); 2602 2603 if (chan == 1) 2604 rf = 0x0c; 2605 else if (chan == 2) 2606 rf = 0x0b; 2607 else if (chan == 3) 2608 rf = 0x0a; 2609 else if (chan >= 4 && chan <= 6) 2610 rf = 0x09; 2611 else if (chan >= 7 && chan <= 12) 2612 rf = 0x08; 2613 else if (chan == 13) 2614 rf = 0x07; 2615 else 2616 rf = 0x06; 2617 rt3090_rf_write(sc, 59, rf); 2618 } 2619 2620 /* Tx/Rx h20M */ 2621 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2622 rf = rt3090_rf_read(sc, 30); 2623 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2624 rt3090_rf_write(sc, 30, rf); 2625 2626 /* Rx BB filter VCM */ 2627 rf = rt3090_rf_read(sc, 30); 2628 rf = (rf & ~0x18) | 0x10; 2629 rt3090_rf_write(sc, 30, rf); 2630 2631 /* Initiate VCO calibration. */ 2632 rf = rt3090_rf_read(sc, 3); 2633 rf |= RT3593_VCOCAL; 2634 rt3090_rf_write(sc, 3, rf); 2635 } 2636 2637 static int 2638 rt3090_rf_init(struct rt2860_softc *sc) 2639 { 2640 uint32_t tmp; 2641 uint8_t rf, bbp; 2642 int i; 2643 2644 rf = rt3090_rf_read(sc, 30); 2645 /* toggle RF R30 bit 7 */ 2646 rt3090_rf_write(sc, 30, rf | 0x80); 2647 DELAY(1000); 2648 rt3090_rf_write(sc, 30, rf & ~0x80); 2649 2650 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2651 tmp &= ~0x1f000000; 2652 if (sc->patch_dac && sc->mac_rev < 0x0211) 2653 tmp |= 0x0d000000; /* 1.35V */ 2654 else 2655 tmp |= 0x01000000; /* 1.2V */ 2656 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2657 2658 /* patch LNA_PE_G1 */ 2659 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2660 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2661 2662 /* initialize RF registers to default value */ 2663 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2664 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2665 rt3090_def_rf[i].val); 2666 } 2667 2668 /* select 20MHz bandwidth */ 2669 rt3090_rf_write(sc, 31, 0x14); 2670 2671 rf = rt3090_rf_read(sc, 6); 2672 rt3090_rf_write(sc, 6, rf | 0x40); 2673 2674 if (sc->mac_ver != 0x3593) { 2675 /* calibrate filter for 20MHz bandwidth */ 2676 sc->rf24_20mhz = 0x1f; /* default value */ 2677 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2678 2679 /* select 40MHz bandwidth */ 2680 bbp = rt2860_mcu_bbp_read(sc, 4); 2681 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2682 rf = rt3090_rf_read(sc, 31); 2683 rt3090_rf_write(sc, 31, rf | 0x20); 2684 2685 /* calibrate filter for 40MHz bandwidth */ 2686 sc->rf24_40mhz = 0x2f; /* default value */ 2687 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2688 2689 /* go back to 20MHz bandwidth */ 2690 bbp = rt2860_mcu_bbp_read(sc, 4); 2691 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2692 } 2693 if (sc->mac_rev < 0x0211) 2694 rt3090_rf_write(sc, 27, 0x03); 2695 2696 tmp = RAL_READ(sc, RT3070_OPT_14); 2697 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2698 2699 if (sc->rf_rev == RT3070_RF_3020) 2700 rt3090_set_rx_antenna(sc, 0); 2701 2702 bbp = rt2860_mcu_bbp_read(sc, 138); 2703 if (sc->mac_ver == 0x3593) { 2704 if (sc->ntxchains == 1) 2705 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2706 else if (sc->ntxchains == 2) 2707 bbp |= 0x40; /* turn off DAC2 */ 2708 if (sc->nrxchains == 1) 2709 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2710 else if (sc->nrxchains == 2) 2711 bbp &= ~0x04; /* turn off ADC2 */ 2712 } else { 2713 if (sc->ntxchains == 1) 2714 bbp |= 0x20; /* turn off DAC1 */ 2715 if (sc->nrxchains == 1) 2716 bbp &= ~0x02; /* turn off ADC1 */ 2717 } 2718 rt2860_mcu_bbp_write(sc, 138, bbp); 2719 2720 rf = rt3090_rf_read(sc, 1); 2721 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2722 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2723 rt3090_rf_write(sc, 1, rf); 2724 2725 rf = rt3090_rf_read(sc, 15); 2726 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2727 2728 rf = rt3090_rf_read(sc, 17); 2729 rf &= ~RT3070_TX_LO1; 2730 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2731 rf |= 0x20; /* fix for long range Rx issue */ 2732 if (sc->txmixgain_2ghz >= 2) 2733 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2734 rt3090_rf_write(sc, 17, rf); 2735 2736 rf = rt3090_rf_read(sc, 20); 2737 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2738 2739 rf = rt3090_rf_read(sc, 21); 2740 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2741 2742 return (0); 2743 } 2744 2745 static void 2746 rt5390_rf_init(struct rt2860_softc *sc) 2747 { 2748 uint8_t rf, bbp; 2749 int i; 2750 2751 rf = rt3090_rf_read(sc, 2); 2752 /* Toggle RF R2 bit 7. */ 2753 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2754 DELAY(1000); 2755 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2756 2757 /* Initialize RF registers to default value. */ 2758 if (sc->mac_ver == 0x5392) { 2759 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2760 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2761 rt5392_def_rf[i].val); 2762 } 2763 } else { 2764 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2765 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2766 rt5390_def_rf[i].val); 2767 } 2768 } 2769 2770 sc->rf24_20mhz = 0x1f; 2771 sc->rf24_40mhz = 0x2f; 2772 2773 if (sc->mac_rev < 0x0211) 2774 rt3090_rf_write(sc, 27, 0x03); 2775 2776 /* Set led open drain enable. */ 2777 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2778 2779 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2780 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2781 2782 if (sc->mac_ver == 0x5390) 2783 rt3090_set_rx_antenna(sc, 0); 2784 2785 /* Patch RSSI inaccurate issue. */ 2786 rt2860_mcu_bbp_write(sc, 79, 0x13); 2787 rt2860_mcu_bbp_write(sc, 80, 0x05); 2788 rt2860_mcu_bbp_write(sc, 81, 0x33); 2789 2790 /* Enable DC filter. */ 2791 if (sc->mac_rev >= 0x0211) 2792 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2793 2794 bbp = rt2860_mcu_bbp_read(sc, 138); 2795 if (sc->ntxchains == 1) 2796 bbp |= 0x20; /* Turn off DAC1. */ 2797 if (sc->nrxchains == 1) 2798 bbp &= ~0x02; /* Turn off ADC1. */ 2799 rt2860_mcu_bbp_write(sc, 138, bbp); 2800 2801 /* Enable RX LO1 and LO2. */ 2802 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2803 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2804 2805 /* Avoid data lost and CRC error. */ 2806 rt2860_mcu_bbp_write(sc, 4, 2807 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2808 2809 rf = rt3090_rf_read(sc, 30); 2810 rf = (rf & ~0x18) | 0x10; 2811 rt3090_rf_write(sc, 30, rf); 2812 } 2813 2814 static void 2815 rt3090_rf_wakeup(struct rt2860_softc *sc) 2816 { 2817 uint32_t tmp; 2818 uint8_t rf; 2819 2820 if (sc->mac_ver == 0x3593) { 2821 /* enable VCO */ 2822 rf = rt3090_rf_read(sc, 1); 2823 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2824 2825 /* initiate VCO calibration */ 2826 rf = rt3090_rf_read(sc, 3); 2827 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2828 2829 /* enable VCO bias current control */ 2830 rf = rt3090_rf_read(sc, 6); 2831 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2832 2833 /* initiate res calibration */ 2834 rf = rt3090_rf_read(sc, 2); 2835 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2836 2837 /* set reference current control to 0.33 mA */ 2838 rf = rt3090_rf_read(sc, 22); 2839 rf &= ~RT3593_CP_IC_MASK; 2840 rf |= 1 << RT3593_CP_IC_SHIFT; 2841 rt3090_rf_write(sc, 22, rf); 2842 2843 /* enable RX CTB */ 2844 rf = rt3090_rf_read(sc, 46); 2845 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2846 2847 rf = rt3090_rf_read(sc, 20); 2848 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2849 rt3090_rf_write(sc, 20, rf); 2850 } else { 2851 /* enable RF block */ 2852 rf = rt3090_rf_read(sc, 1); 2853 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2854 2855 /* enable VCO bias current control */ 2856 rf = rt3090_rf_read(sc, 7); 2857 rt3090_rf_write(sc, 7, rf | 0x30); 2858 2859 rf = rt3090_rf_read(sc, 9); 2860 rt3090_rf_write(sc, 9, rf | 0x0e); 2861 2862 /* enable RX CTB */ 2863 rf = rt3090_rf_read(sc, 21); 2864 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2865 2866 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2867 rf = rt3090_rf_read(sc, 27); 2868 rf &= ~0x77; 2869 if (sc->mac_rev < 0x0211) 2870 rf |= 0x03; 2871 rt3090_rf_write(sc, 27, rf); 2872 } 2873 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2874 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2875 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2876 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2877 } 2878 } 2879 2880 static void 2881 rt5390_rf_wakeup(struct rt2860_softc *sc) 2882 { 2883 uint32_t tmp; 2884 uint8_t rf; 2885 2886 rf = rt3090_rf_read(sc, 1); 2887 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2888 RT3070_TX0_PD; 2889 if (sc->mac_ver == 0x5392) 2890 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2891 rt3090_rf_write(sc, 1, rf); 2892 2893 rf = rt3090_rf_read(sc, 6); 2894 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2895 if (sc->mac_ver == 0x5390) 2896 rf &= ~RT3593_VCO_IC; 2897 rt3090_rf_write(sc, 6, rf); 2898 2899 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2900 2901 rf = rt3090_rf_read(sc, 22); 2902 rf = (rf & ~0xe0) | 0x20; 2903 rt3090_rf_write(sc, 22, rf); 2904 2905 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2906 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2907 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2908 2909 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2910 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2911 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2912 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2913 } 2914 } 2915 2916 static int 2917 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2918 uint8_t *val) 2919 { 2920 uint8_t rf22, rf24; 2921 uint8_t bbp55_pb, bbp55_sb, delta; 2922 int ntries; 2923 2924 /* program filter */ 2925 rf24 = rt3090_rf_read(sc, 24); 2926 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2927 rt3090_rf_write(sc, 24, rf24); 2928 2929 /* enable baseband loopback mode */ 2930 rf22 = rt3090_rf_read(sc, 22); 2931 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2932 2933 /* set power and frequency of passband test tone */ 2934 rt2860_mcu_bbp_write(sc, 24, 0x00); 2935 for (ntries = 0; ntries < 100; ntries++) { 2936 /* transmit test tone */ 2937 rt2860_mcu_bbp_write(sc, 25, 0x90); 2938 DELAY(1000); 2939 /* read received power */ 2940 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2941 if (bbp55_pb != 0) 2942 break; 2943 } 2944 if (ntries == 100) 2945 return (ETIMEDOUT); 2946 2947 /* set power and frequency of stopband test tone */ 2948 rt2860_mcu_bbp_write(sc, 24, 0x06); 2949 for (ntries = 0; ntries < 100; ntries++) { 2950 /* transmit test tone */ 2951 rt2860_mcu_bbp_write(sc, 25, 0x90); 2952 DELAY(1000); 2953 /* read received power */ 2954 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2955 2956 delta = bbp55_pb - bbp55_sb; 2957 if (delta > target) 2958 break; 2959 2960 /* reprogram filter */ 2961 rf24++; 2962 rt3090_rf_write(sc, 24, rf24); 2963 } 2964 if (ntries < 100) { 2965 if (rf24 != init) 2966 rf24--; /* backtrack */ 2967 *val = rf24; 2968 rt3090_rf_write(sc, 24, rf24); 2969 } 2970 2971 /* restore initial state */ 2972 rt2860_mcu_bbp_write(sc, 24, 0x00); 2973 2974 /* disable baseband loopback mode */ 2975 rf22 = rt3090_rf_read(sc, 22); 2976 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2977 2978 return (0); 2979 } 2980 2981 static void 2982 rt3090_rf_setup(struct rt2860_softc *sc) 2983 { 2984 uint8_t bbp; 2985 int i; 2986 2987 if (sc->mac_rev >= 0x0211) { 2988 /* enable DC filter */ 2989 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2990 2991 /* improve power consumption */ 2992 bbp = rt2860_mcu_bbp_read(sc, 31); 2993 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2994 } 2995 2996 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2997 if (sc->mac_rev < 0x0211) { 2998 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2999 sc->patch_dac ? 0x2c : 0x0f); 3000 } else 3001 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3002 3003 /* initialize RF registers from ROM */ 3004 if (sc->mac_ver < 0x5390) { 3005 for (i = 0; i < 10; i++) { 3006 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3007 continue; 3008 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3009 } 3010 } 3011 } 3012 3013 static void 3014 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3015 { 3016 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3017 which | (sc->leds & 0x7f), 0); 3018 } 3019 3020 /* 3021 * Hardware has a general-purpose programmable timer interrupt that can 3022 * periodically raise MAC_INT_4. 3023 */ 3024 static void 3025 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3026 { 3027 uint32_t tmp; 3028 3029 /* disable GP timer before reprogramming it */ 3030 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3031 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3032 3033 if (ms == 0) 3034 return; 3035 3036 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3037 ms *= 16; /* Unit: 64us */ 3038 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3039 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3040 3041 /* enable GP timer */ 3042 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3043 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3044 } 3045 3046 static void 3047 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3048 { 3049 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3050 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3051 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3052 bssid[4] | bssid[5] << 8); 3053 } 3054 3055 static void 3056 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3057 { 3058 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3059 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3060 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3061 addr[4] | addr[5] << 8 | 0xff << 16); 3062 } 3063 3064 static void 3065 rt2860_updateslot(struct ieee80211com *ic) 3066 { 3067 struct rt2860_softc *sc = ic->ic_softc; 3068 uint32_t tmp; 3069 3070 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3071 tmp &= ~0xff; 3072 tmp |= IEEE80211_GET_SLOTTIME(ic); 3073 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3074 } 3075 3076 static void 3077 rt2860_updateprot(struct rt2860_softc *sc) 3078 { 3079 struct ieee80211com *ic = &sc->sc_ic; 3080 uint32_t tmp; 3081 3082 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3083 /* setup protection frame rate (MCS code) */ 3084 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3085 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3086 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3087 3088 /* CCK frames don't require protection */ 3089 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3090 3091 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3092 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3093 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3094 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3095 tmp |= RT2860_PROT_CTRL_CTS; 3096 } 3097 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3098 } 3099 3100 static void 3101 rt2860_update_promisc(struct ieee80211com *ic) 3102 { 3103 struct rt2860_softc *sc = ic->ic_softc; 3104 uint32_t tmp; 3105 3106 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3107 tmp &= ~RT2860_DROP_NOT_MYBSS; 3108 if (ic->ic_promisc == 0) 3109 tmp |= RT2860_DROP_NOT_MYBSS; 3110 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3111 } 3112 3113 static int 3114 rt2860_updateedca(struct ieee80211com *ic) 3115 { 3116 struct rt2860_softc *sc = ic->ic_softc; 3117 struct chanAccParams chp; 3118 const struct wmeParams *wmep; 3119 int aci; 3120 3121 ieee80211_wme_ic_getparams(ic, &chp); 3122 3123 wmep = chp.cap_wmeParams; 3124 3125 /* update MAC TX configuration registers */ 3126 for (aci = 0; aci < WME_NUM_AC; aci++) { 3127 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3128 wmep[aci].wmep_logcwmax << 16 | 3129 wmep[aci].wmep_logcwmin << 12 | 3130 wmep[aci].wmep_aifsn << 8 | 3131 wmep[aci].wmep_txopLimit); 3132 } 3133 3134 /* update SCH/DMA registers too */ 3135 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3136 wmep[WME_AC_VO].wmep_aifsn << 12 | 3137 wmep[WME_AC_VI].wmep_aifsn << 8 | 3138 wmep[WME_AC_BK].wmep_aifsn << 4 | 3139 wmep[WME_AC_BE].wmep_aifsn); 3140 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3141 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3142 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3143 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3144 wmep[WME_AC_BE].wmep_logcwmin); 3145 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3146 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3147 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3148 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3149 wmep[WME_AC_BE].wmep_logcwmax); 3150 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3151 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3152 wmep[WME_AC_BE].wmep_txopLimit); 3153 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3154 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3155 wmep[WME_AC_VI].wmep_txopLimit); 3156 3157 return 0; 3158 } 3159 3160 #ifdef HW_CRYPTO 3161 static int 3162 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3163 struct ieee80211_key *k) 3164 { 3165 struct rt2860_softc *sc = ic->ic_softc; 3166 bus_size_t base; 3167 uint32_t attr; 3168 uint8_t mode, wcid, iv[8]; 3169 3170 /* defer setting of WEP keys until interface is brought up */ 3171 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3172 (IFF_UP | IFF_RUNNING)) 3173 return 0; 3174 3175 /* map net80211 cipher to RT2860 security mode */ 3176 switch (k->k_cipher) { 3177 case IEEE80211_CIPHER_WEP40: 3178 mode = RT2860_MODE_WEP40; 3179 break; 3180 case IEEE80211_CIPHER_WEP104: 3181 mode = RT2860_MODE_WEP104; 3182 break; 3183 case IEEE80211_CIPHER_TKIP: 3184 mode = RT2860_MODE_TKIP; 3185 break; 3186 case IEEE80211_CIPHER_CCMP: 3187 mode = RT2860_MODE_AES_CCMP; 3188 break; 3189 default: 3190 return EINVAL; 3191 } 3192 3193 if (k->k_flags & IEEE80211_KEY_GROUP) { 3194 wcid = 0; /* NB: update WCID0 for group keys */ 3195 base = RT2860_SKEY(0, k->k_id); 3196 } else { 3197 wcid = ((struct rt2860_node *)ni)->wcid; 3198 base = RT2860_PKEY(wcid); 3199 } 3200 3201 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3202 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3203 #ifndef IEEE80211_STA_ONLY 3204 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3205 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3206 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3207 } else 3208 #endif 3209 { 3210 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3211 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3212 } 3213 } else 3214 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3215 3216 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3217 (k->k_flags & IEEE80211_KEY_TX)) { 3218 /* set initial packet number in IV+EIV */ 3219 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3220 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3221 uint32_t val = arc4random(); 3222 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3223 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3224 val += 0x000100; 3225 iv[0] = val; 3226 iv[1] = val >> 8; 3227 iv[2] = val >> 16; 3228 iv[3] = k->k_id << 6; 3229 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3230 } else { 3231 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3232 iv[0] = k->k_tsc >> 8; 3233 iv[1] = (iv[0] | 0x20) & 0x7f; 3234 iv[2] = k->k_tsc; 3235 } else /* CCMP */ { 3236 iv[0] = k->k_tsc; 3237 iv[1] = k->k_tsc >> 8; 3238 iv[2] = 0; 3239 } 3240 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3241 iv[4] = k->k_tsc >> 16; 3242 iv[5] = k->k_tsc >> 24; 3243 iv[6] = k->k_tsc >> 32; 3244 iv[7] = k->k_tsc >> 40; 3245 } 3246 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3247 } 3248 3249 if (k->k_flags & IEEE80211_KEY_GROUP) { 3250 /* install group key */ 3251 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3252 attr &= ~(0xf << (k->k_id * 4)); 3253 attr |= mode << (k->k_id * 4); 3254 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3255 } else { 3256 /* install pairwise key */ 3257 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3258 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3259 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3260 } 3261 return 0; 3262 } 3263 3264 static void 3265 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3266 struct ieee80211_key *k) 3267 { 3268 struct rt2860_softc *sc = ic->ic_softc; 3269 uint32_t attr; 3270 uint8_t wcid; 3271 3272 if (k->k_flags & IEEE80211_KEY_GROUP) { 3273 /* remove group key */ 3274 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3275 attr &= ~(0xf << (k->k_id * 4)); 3276 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3277 3278 } else { 3279 /* remove pairwise key */ 3280 wcid = ((struct rt2860_node *)ni)->wcid; 3281 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3282 attr &= ~0xf; 3283 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3284 } 3285 } 3286 #endif 3287 3288 static int8_t 3289 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3290 { 3291 struct ieee80211com *ic = &sc->sc_ic; 3292 struct ieee80211_channel *c = ic->ic_curchan; 3293 int delta; 3294 3295 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3296 u_int chan = ieee80211_chan2ieee(ic, c); 3297 delta = sc->rssi_5ghz[rxchain]; 3298 3299 /* determine channel group */ 3300 if (chan <= 64) 3301 delta -= sc->lna[1]; 3302 else if (chan <= 128) 3303 delta -= sc->lna[2]; 3304 else 3305 delta -= sc->lna[3]; 3306 } else 3307 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3308 3309 return -12 - delta - rssi; 3310 } 3311 3312 /* 3313 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3314 * Used to adjust per-rate Tx power registers. 3315 */ 3316 static __inline uint32_t 3317 b4inc(uint32_t b32, int8_t delta) 3318 { 3319 int8_t i, b4; 3320 3321 for (i = 0; i < 8; i++) { 3322 b4 = b32 & 0xf; 3323 b4 += delta; 3324 if (b4 < 0) 3325 b4 = 0; 3326 else if (b4 > 0xf) 3327 b4 = 0xf; 3328 b32 = b32 >> 4 | b4 << 28; 3329 } 3330 return b32; 3331 } 3332 3333 static const char * 3334 rt2860_get_rf(uint16_t rev) 3335 { 3336 switch (rev) { 3337 case RT2860_RF_2820: return "RT2820"; 3338 case RT2860_RF_2850: return "RT2850"; 3339 case RT2860_RF_2720: return "RT2720"; 3340 case RT2860_RF_2750: return "RT2750"; 3341 case RT3070_RF_3020: return "RT3020"; 3342 case RT3070_RF_2020: return "RT2020"; 3343 case RT3070_RF_3021: return "RT3021"; 3344 case RT3070_RF_3022: return "RT3022"; 3345 case RT3070_RF_3052: return "RT3052"; 3346 case RT3070_RF_3320: return "RT3320"; 3347 case RT3070_RF_3053: return "RT3053"; 3348 case RT5390_RF_5360: return "RT5360"; 3349 case RT5390_RF_5390: return "RT5390"; 3350 default: return "unknown"; 3351 } 3352 } 3353 3354 static int 3355 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3356 { 3357 int8_t delta_2ghz, delta_5ghz; 3358 uint32_t tmp; 3359 uint16_t val; 3360 int ridx, ant, i; 3361 3362 /* check whether the ROM is eFUSE ROM or EEPROM */ 3363 sc->sc_srom_read = rt2860_eeprom_read_2; 3364 if (sc->mac_ver >= 0x3071) { 3365 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3366 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3367 if (tmp & RT3070_SEL_EFUSE) 3368 sc->sc_srom_read = rt3090_efuse_read_2; 3369 } 3370 3371 #ifdef RAL_DEBUG 3372 /* read EEPROM version */ 3373 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3374 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3375 #endif 3376 3377 /* read MAC address */ 3378 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3379 macaddr[0] = val & 0xff; 3380 macaddr[1] = val >> 8; 3381 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3382 macaddr[2] = val & 0xff; 3383 macaddr[3] = val >> 8; 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3385 macaddr[4] = val & 0xff; 3386 macaddr[5] = val >> 8; 3387 3388 #ifdef RAL_DEBUG 3389 /* read country code */ 3390 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3391 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3392 #endif 3393 3394 /* read vendor BBP settings */ 3395 for (i = 0; i < 8; i++) { 3396 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3397 sc->bbp[i].val = val & 0xff; 3398 sc->bbp[i].reg = val >> 8; 3399 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3400 } 3401 if (sc->mac_ver >= 0x3071) { 3402 /* read vendor RF settings */ 3403 for (i = 0; i < 10; i++) { 3404 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3405 sc->rf[i].val = val & 0xff; 3406 sc->rf[i].reg = val >> 8; 3407 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3408 sc->rf[i].val)); 3409 } 3410 } 3411 3412 /* read RF frequency offset from EEPROM */ 3413 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3414 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3415 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3416 if ((val >> 8) != 0xff) { 3417 /* read LEDs operating mode */ 3418 sc->leds = val >> 8; 3419 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3420 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3421 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3422 } else { 3423 /* broken EEPROM, use default settings */ 3424 sc->leds = 0x01; 3425 sc->led[0] = 0x5555; 3426 sc->led[1] = 0x2221; 3427 sc->led[2] = 0xa9f8; 3428 } 3429 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3430 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3431 3432 /* read RF information */ 3433 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3434 if (sc->mac_ver >= 0x5390) 3435 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3436 else 3437 sc->rf_rev = (val >> 8) & 0xf; 3438 sc->ntxchains = (val >> 4) & 0xf; 3439 sc->nrxchains = val & 0xf; 3440 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3441 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3442 3443 /* check if RF supports automatic Tx access gain control */ 3444 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3445 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3446 /* check if driver should patch the DAC issue */ 3447 if ((val >> 8) != 0xff) 3448 sc->patch_dac = (val >> 15) & 1; 3449 if ((val & 0xff) != 0xff) { 3450 sc->ext_5ghz_lna = (val >> 3) & 1; 3451 sc->ext_2ghz_lna = (val >> 2) & 1; 3452 /* check if RF supports automatic Tx access gain control */ 3453 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3454 /* check if we have a hardware radio switch */ 3455 sc->rfswitch = val & 1; 3456 } 3457 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3458 /* read PCIe power save level */ 3459 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3460 if ((val & 0xff) != 0xff) { 3461 sc->pslevel = val & 0x3; 3462 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3463 if ((val & 0xff80) != 0x9280) 3464 sc->pslevel = MIN(sc->pslevel, 1); 3465 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3466 } 3467 } 3468 3469 /* read power settings for 2GHz channels */ 3470 for (i = 0; i < 14; i += 2) { 3471 val = rt2860_srom_read(sc, 3472 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3473 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3474 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3475 3476 if (sc->mac_ver != 0x5390) { 3477 val = rt2860_srom_read(sc, 3478 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3479 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3480 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3481 } 3482 } 3483 /* fix broken Tx power entries */ 3484 for (i = 0; i < 14; i++) { 3485 if (sc->txpow1[i] < 0 || 3486 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3487 sc->txpow1[i] = 5; 3488 if (sc->mac_ver != 0x5390) { 3489 if (sc->txpow2[i] < 0 || 3490 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3491 sc->txpow2[i] = 5; 3492 } 3493 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3494 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3495 } 3496 /* read power settings for 5GHz channels */ 3497 for (i = 0; i < 40; i += 2) { 3498 val = rt2860_srom_read(sc, 3499 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3500 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3501 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3502 3503 val = rt2860_srom_read(sc, 3504 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3505 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3506 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3507 } 3508 /* fix broken Tx power entries */ 3509 for (i = 0; i < 40; i++) { 3510 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3511 sc->txpow1[14 + i] = 5; 3512 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3513 sc->txpow2[14 + i] = 5; 3514 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3515 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3516 sc->txpow2[14 + i])); 3517 } 3518 3519 /* read Tx power compensation for each Tx rate */ 3520 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3521 delta_2ghz = delta_5ghz = 0; 3522 if ((val & 0xff) != 0xff && (val & 0x80)) { 3523 delta_2ghz = val & 0xf; 3524 if (!(val & 0x40)) /* negative number */ 3525 delta_2ghz = -delta_2ghz; 3526 } 3527 val >>= 8; 3528 if ((val & 0xff) != 0xff && (val & 0x80)) { 3529 delta_5ghz = val & 0xf; 3530 if (!(val & 0x40)) /* negative number */ 3531 delta_5ghz = -delta_5ghz; 3532 } 3533 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3534 delta_2ghz, delta_5ghz)); 3535 3536 for (ridx = 0; ridx < 5; ridx++) { 3537 uint32_t reg; 3538 3539 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3540 reg = val; 3541 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3542 reg |= (uint32_t)val << 16; 3543 3544 sc->txpow20mhz[ridx] = reg; 3545 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3546 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3547 3548 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3549 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3550 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3551 } 3552 3553 /* read factory-calibrated samples for temperature compensation */ 3554 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3555 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3556 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3557 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3558 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3559 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3560 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3561 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3562 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3563 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3564 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3565 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3566 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3567 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3568 sc->step_2ghz = val >> 8; 3569 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3570 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3571 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3572 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3573 sc->tssi_2ghz[8], sc->step_2ghz)); 3574 /* check that ref value is correct, otherwise disable calibration */ 3575 if (sc->tssi_2ghz[4] == 0xff) 3576 sc->calib_2ghz = 0; 3577 3578 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3579 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3580 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3581 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3582 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3583 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3584 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3585 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3586 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3587 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3588 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3589 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3590 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3591 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3592 sc->step_5ghz = val >> 8; 3593 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3594 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3595 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3596 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3597 sc->tssi_5ghz[8], sc->step_5ghz)); 3598 /* check that ref value is correct, otherwise disable calibration */ 3599 if (sc->tssi_5ghz[4] == 0xff) 3600 sc->calib_5ghz = 0; 3601 3602 /* read RSSI offsets and LNA gains from EEPROM */ 3603 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3604 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3605 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3606 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3607 if (sc->mac_ver >= 0x3071) { 3608 /* 3609 * On RT3090 chips (limited to 2 Rx chains), this ROM 3610 * field contains the Tx mixer gain for the 2GHz band. 3611 */ 3612 if ((val & 0xff) != 0xff) 3613 sc->txmixgain_2ghz = val & 0x7; 3614 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3615 } else 3616 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3617 sc->lna[2] = val >> 8; /* channel group 2 */ 3618 3619 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3620 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3621 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3622 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3623 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3624 sc->lna[3] = val >> 8; /* channel group 3 */ 3625 3626 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3627 if (sc->mac_ver >= 0x3071) 3628 sc->lna[0] = RT3090_DEF_LNA; 3629 else /* channel group 0 */ 3630 sc->lna[0] = val & 0xff; 3631 sc->lna[1] = val >> 8; /* channel group 1 */ 3632 3633 /* fix broken 5GHz LNA entries */ 3634 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3635 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3636 sc->lna[2] = sc->lna[1]; 3637 } 3638 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3639 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3640 sc->lna[3] = sc->lna[1]; 3641 } 3642 3643 /* fix broken RSSI offset entries */ 3644 for (ant = 0; ant < 3; ant++) { 3645 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3646 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3647 ant + 1, sc->rssi_2ghz[ant])); 3648 sc->rssi_2ghz[ant] = 0; 3649 } 3650 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3651 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3652 ant + 1, sc->rssi_5ghz[ant])); 3653 sc->rssi_5ghz[ant] = 0; 3654 } 3655 } 3656 3657 return 0; 3658 } 3659 3660 static int 3661 rt2860_bbp_init(struct rt2860_softc *sc) 3662 { 3663 int i, ntries; 3664 3665 /* wait for BBP to wake up */ 3666 for (ntries = 0; ntries < 20; ntries++) { 3667 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3668 if (bbp0 != 0 && bbp0 != 0xff) 3669 break; 3670 } 3671 if (ntries == 20) { 3672 device_printf(sc->sc_dev, 3673 "timeout waiting for BBP to wake up\n"); 3674 return (ETIMEDOUT); 3675 } 3676 3677 /* initialize BBP registers to default values */ 3678 if (sc->mac_ver >= 0x5390) 3679 rt5390_bbp_init(sc); 3680 else { 3681 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3682 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3683 rt2860_def_bbp[i].val); 3684 } 3685 } 3686 3687 /* fix BBP84 for RT2860E */ 3688 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3689 rt2860_mcu_bbp_write(sc, 84, 0x19); 3690 3691 if (sc->mac_ver >= 0x3071) { 3692 rt2860_mcu_bbp_write(sc, 79, 0x13); 3693 rt2860_mcu_bbp_write(sc, 80, 0x05); 3694 rt2860_mcu_bbp_write(sc, 81, 0x33); 3695 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3696 rt2860_mcu_bbp_write(sc, 69, 0x16); 3697 rt2860_mcu_bbp_write(sc, 73, 0x12); 3698 } 3699 3700 return 0; 3701 } 3702 3703 static void 3704 rt5390_bbp_init(struct rt2860_softc *sc) 3705 { 3706 uint8_t bbp; 3707 int i; 3708 3709 /* Apply maximum likelihood detection for 2 stream case. */ 3710 if (sc->nrxchains > 1) { 3711 bbp = rt2860_mcu_bbp_read(sc, 105); 3712 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3713 } 3714 3715 /* Avoid data lost and CRC error. */ 3716 bbp = rt2860_mcu_bbp_read(sc, 4); 3717 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3718 3719 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3720 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3721 rt5390_def_bbp[i].val); 3722 } 3723 3724 if (sc->mac_ver == 0x5392) { 3725 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3726 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3727 rt2860_mcu_bbp_write(sc, 98, 0x12); 3728 rt2860_mcu_bbp_write(sc, 106, 0x05); 3729 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3730 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3731 } 3732 3733 bbp = rt2860_mcu_bbp_read(sc, 152); 3734 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3735 3736 /* Disable hardware antenna diversity. */ 3737 if (sc->mac_ver == 0x5390) 3738 rt2860_mcu_bbp_write(sc, 154, 0); 3739 } 3740 3741 static int 3742 rt2860_txrx_enable(struct rt2860_softc *sc) 3743 { 3744 struct ieee80211com *ic = &sc->sc_ic; 3745 uint32_t tmp; 3746 int ntries; 3747 3748 /* enable Tx/Rx DMA engine */ 3749 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3750 RAL_BARRIER_READ_WRITE(sc); 3751 for (ntries = 0; ntries < 200; ntries++) { 3752 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3753 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3754 break; 3755 DELAY(1000); 3756 } 3757 if (ntries == 200) { 3758 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3759 return ETIMEDOUT; 3760 } 3761 3762 DELAY(50); 3763 3764 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3765 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3766 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3767 3768 /* set Rx filter */ 3769 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3770 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3771 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3772 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3773 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3774 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3775 if (ic->ic_opmode == IEEE80211_M_STA) 3776 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3777 } 3778 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3779 3780 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3781 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3782 3783 return 0; 3784 } 3785 3786 static void 3787 rt2860_init(void *arg) 3788 { 3789 struct rt2860_softc *sc = arg; 3790 struct ieee80211com *ic = &sc->sc_ic; 3791 3792 RAL_LOCK(sc); 3793 rt2860_init_locked(sc); 3794 RAL_UNLOCK(sc); 3795 3796 if (sc->sc_flags & RT2860_RUNNING) 3797 ieee80211_start_all(ic); 3798 } 3799 3800 static void 3801 rt2860_init_locked(struct rt2860_softc *sc) 3802 { 3803 struct ieee80211com *ic = &sc->sc_ic; 3804 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3805 uint32_t tmp; 3806 uint8_t bbp1, bbp3; 3807 int i, qid, ridx, ntries, error; 3808 3809 RAL_LOCK_ASSERT(sc); 3810 3811 if (sc->rfswitch) { 3812 /* hardware has a radio switch on GPIO pin 2 */ 3813 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3814 device_printf(sc->sc_dev, 3815 "radio is disabled by hardware switch\n"); 3816 #ifdef notyet 3817 rt2860_stop_locked(sc); 3818 return; 3819 #endif 3820 } 3821 } 3822 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3823 3824 /* disable DMA */ 3825 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3826 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3827 RT2860_TX_DMA_EN); 3828 tmp |= RT2860_TX_WB_DDONE; 3829 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3830 3831 /* reset DMA indexes */ 3832 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3833 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3834 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3835 3836 /* PBF hardware reset */ 3837 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3838 RAL_BARRIER_WRITE(sc); 3839 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3840 3841 if ((error = rt2860_load_microcode(sc)) != 0) { 3842 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3843 rt2860_stop_locked(sc); 3844 return; 3845 } 3846 3847 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3848 3849 /* init Tx power for all Tx rates (from EEPROM) */ 3850 for (ridx = 0; ridx < 5; ridx++) { 3851 if (sc->txpow20mhz[ridx] == 0xffffffff) 3852 continue; 3853 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3854 } 3855 3856 for (ntries = 0; ntries < 100; ntries++) { 3857 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3858 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3859 break; 3860 DELAY(1000); 3861 } 3862 if (ntries == 100) { 3863 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3864 rt2860_stop_locked(sc); 3865 return; 3866 } 3867 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3868 RT2860_TX_DMA_EN); 3869 tmp |= RT2860_TX_WB_DDONE; 3870 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3871 3872 /* reset Rx ring and all 6 Tx rings */ 3873 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3874 3875 /* PBF hardware reset */ 3876 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3877 RAL_BARRIER_WRITE(sc); 3878 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3879 3880 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3881 3882 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3883 RAL_BARRIER_WRITE(sc); 3884 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3885 3886 for (i = 0; i < nitems(rt2860_def_mac); i++) 3887 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3888 if (sc->mac_ver >= 0x5390) 3889 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3890 else if (sc->mac_ver >= 0x3071) { 3891 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3892 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3893 4 << RT2860_DLY_PAPE_EN_SHIFT); 3894 } 3895 3896 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3897 sc->sc_flags |= RT2860_PCIE; 3898 /* PCIe has different clock cycle count than PCI */ 3899 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3900 tmp = (tmp & ~0xff) | 0x7d; 3901 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3902 } 3903 3904 /* wait while MAC is busy */ 3905 for (ntries = 0; ntries < 100; ntries++) { 3906 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3907 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3908 break; 3909 DELAY(1000); 3910 } 3911 if (ntries == 100) { 3912 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3913 rt2860_stop_locked(sc); 3914 return; 3915 } 3916 3917 /* clear Host to MCU mailbox */ 3918 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3919 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3920 3921 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3922 DELAY(1000); 3923 3924 if ((error = rt2860_bbp_init(sc)) != 0) { 3925 rt2860_stop_locked(sc); 3926 return; 3927 } 3928 3929 /* clear RX WCID search table */ 3930 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3931 /* clear pairwise key table */ 3932 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3933 /* clear IV/EIV table */ 3934 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3935 /* clear WCID attribute table */ 3936 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3937 /* clear shared key table */ 3938 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3939 /* clear shared key mode */ 3940 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3941 3942 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3943 for (qid = 0; qid < 6; qid++) { 3944 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3945 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3946 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3947 } 3948 3949 /* init Rx ring */ 3950 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3951 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3952 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3953 3954 /* setup maximum buffer sizes */ 3955 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3956 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3957 3958 for (ntries = 0; ntries < 100; ntries++) { 3959 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3960 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3961 break; 3962 DELAY(1000); 3963 } 3964 if (ntries == 100) { 3965 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3966 rt2860_stop_locked(sc); 3967 return; 3968 } 3969 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3970 RT2860_TX_DMA_EN); 3971 tmp |= RT2860_TX_WB_DDONE; 3972 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3973 3974 /* disable interrupts mitigation */ 3975 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3976 3977 /* write vendor-specific BBP values (from EEPROM) */ 3978 for (i = 0; i < 8; i++) { 3979 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3980 continue; 3981 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3982 } 3983 3984 /* select Main antenna for 1T1R devices */ 3985 if (sc->rf_rev == RT3070_RF_2020 || 3986 sc->rf_rev == RT3070_RF_3020 || 3987 sc->rf_rev == RT3070_RF_3320 || 3988 sc->mac_ver == 0x5390) 3989 rt3090_set_rx_antenna(sc, 0); 3990 3991 /* send LEDs operating mode to microcontroller */ 3992 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3993 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3994 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3995 3996 if (sc->mac_ver >= 0x5390) 3997 rt5390_rf_init(sc); 3998 else if (sc->mac_ver >= 0x3071) { 3999 if ((error = rt3090_rf_init(sc)) != 0) { 4000 rt2860_stop_locked(sc); 4001 return; 4002 } 4003 } 4004 4005 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4006 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4007 4008 if (sc->mac_ver >= 0x5390) 4009 rt5390_rf_wakeup(sc); 4010 else if (sc->mac_ver >= 0x3071) 4011 rt3090_rf_wakeup(sc); 4012 4013 /* disable non-existing Rx chains */ 4014 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4015 bbp3 &= ~(1 << 3 | 1 << 4); 4016 if (sc->nrxchains == 2) 4017 bbp3 |= 1 << 3; 4018 else if (sc->nrxchains == 3) 4019 bbp3 |= 1 << 4; 4020 rt2860_mcu_bbp_write(sc, 3, bbp3); 4021 4022 /* disable non-existing Tx chains */ 4023 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4024 if (sc->ntxchains == 1) 4025 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4026 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4027 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4028 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4029 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4030 rt2860_mcu_bbp_write(sc, 1, bbp1); 4031 4032 if (sc->mac_ver >= 0x3071) 4033 rt3090_rf_setup(sc); 4034 4035 /* select default channel */ 4036 rt2860_switch_chan(sc, ic->ic_curchan); 4037 4038 /* reset RF from MCU */ 4039 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4040 4041 /* set RTS threshold */ 4042 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4043 tmp &= ~0xffff00; 4044 tmp |= IEEE80211_RTS_DEFAULT << 8; 4045 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4046 4047 /* setup initial protection mode */ 4048 rt2860_updateprot(sc); 4049 4050 /* turn radio LED on */ 4051 rt2860_set_leds(sc, RT2860_LED_RADIO); 4052 4053 /* enable Tx/Rx DMA engine */ 4054 if ((error = rt2860_txrx_enable(sc)) != 0) { 4055 rt2860_stop_locked(sc); 4056 return; 4057 } 4058 4059 /* clear pending interrupts */ 4060 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4061 /* enable interrupts */ 4062 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4063 4064 if (sc->sc_flags & RT2860_ADVANCED_PS) 4065 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4066 4067 sc->sc_flags |= RT2860_RUNNING; 4068 4069 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4070 } 4071 4072 static void 4073 rt2860_stop(void *arg) 4074 { 4075 struct rt2860_softc *sc = arg; 4076 4077 RAL_LOCK(sc); 4078 rt2860_stop_locked(sc); 4079 RAL_UNLOCK(sc); 4080 } 4081 4082 static void 4083 rt2860_stop_locked(struct rt2860_softc *sc) 4084 { 4085 uint32_t tmp; 4086 int qid; 4087 4088 if (sc->sc_flags & RT2860_RUNNING) 4089 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4090 4091 callout_stop(&sc->watchdog_ch); 4092 sc->sc_tx_timer = 0; 4093 sc->sc_flags &= ~RT2860_RUNNING; 4094 4095 /* disable interrupts */ 4096 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4097 4098 /* disable GP timer */ 4099 rt2860_set_gp_timer(sc, 0); 4100 4101 /* disable Rx */ 4102 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4103 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4104 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4105 4106 /* reset adapter */ 4107 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4108 RAL_BARRIER_WRITE(sc); 4109 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4110 4111 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4112 sc->qfullmsk = 0; 4113 for (qid = 0; qid < 6; qid++) 4114 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4115 rt2860_reset_rx_ring(sc, &sc->rxq); 4116 } 4117 4118 int 4119 rt2860_load_microcode(struct rt2860_softc *sc) 4120 { 4121 const struct firmware *fp; 4122 int ntries, error; 4123 4124 RAL_LOCK_ASSERT(sc); 4125 4126 RAL_UNLOCK(sc); 4127 fp = firmware_get("rt2860fw"); 4128 RAL_LOCK(sc); 4129 if (fp == NULL) { 4130 device_printf(sc->sc_dev, 4131 "unable to receive rt2860fw firmware image\n"); 4132 return EINVAL; 4133 } 4134 4135 /* set "host program ram write selection" bit */ 4136 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4137 /* write microcode image */ 4138 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4139 /* kick microcontroller unit */ 4140 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4141 RAL_BARRIER_WRITE(sc); 4142 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4143 4144 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4145 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4146 4147 /* wait until microcontroller is ready */ 4148 RAL_BARRIER_READ_WRITE(sc); 4149 for (ntries = 0; ntries < 1000; ntries++) { 4150 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4151 break; 4152 DELAY(1000); 4153 } 4154 if (ntries == 1000) { 4155 device_printf(sc->sc_dev, 4156 "timeout waiting for MCU to initialize\n"); 4157 error = ETIMEDOUT; 4158 } else 4159 error = 0; 4160 4161 firmware_put(fp, FIRMWARE_UNLOAD); 4162 return error; 4163 } 4164 4165 /* 4166 * This function is called periodically to adjust Tx power based on 4167 * temperature variation. 4168 */ 4169 #ifdef NOT_YET 4170 static void 4171 rt2860_calib(struct rt2860_softc *sc) 4172 { 4173 struct ieee80211com *ic = &sc->sc_ic; 4174 const uint8_t *tssi; 4175 uint8_t step, bbp49; 4176 int8_t ridx, d; 4177 4178 /* read current temperature */ 4179 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4180 4181 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4182 tssi = &sc->tssi_2ghz[4]; 4183 step = sc->step_2ghz; 4184 } else { 4185 tssi = &sc->tssi_5ghz[4]; 4186 step = sc->step_5ghz; 4187 } 4188 4189 if (bbp49 < tssi[0]) { /* lower than reference */ 4190 /* use higher Tx power than default */ 4191 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4192 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4193 /* use lower Tx power than default */ 4194 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4195 } else { 4196 /* use default Tx power */ 4197 d = 0; 4198 } 4199 d *= step; 4200 4201 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4202 4203 /* write adjusted Tx power values for each Tx rate */ 4204 for (ridx = 0; ridx < 5; ridx++) { 4205 if (sc->txpow20mhz[ridx] == 0xffffffff) 4206 continue; 4207 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4208 b4inc(sc->txpow20mhz[ridx], d)); 4209 } 4210 } 4211 #endif 4212 4213 static void 4214 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4215 { 4216 uint32_t tmp; 4217 4218 if (aux) { 4219 if (sc->mac_ver == 0x5390) { 4220 rt2860_mcu_bbp_write(sc, 152, 4221 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4222 } else { 4223 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4224 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4225 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4226 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4227 } 4228 } else { 4229 if (sc->mac_ver == 0x5390) { 4230 rt2860_mcu_bbp_write(sc, 152, 4231 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4232 } else { 4233 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4234 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4235 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4236 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4237 } 4238 } 4239 } 4240 4241 static void 4242 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4243 { 4244 struct ieee80211com *ic = &sc->sc_ic; 4245 u_int chan, group; 4246 4247 chan = ieee80211_chan2ieee(ic, c); 4248 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4249 return; 4250 4251 if (sc->mac_ver >= 0x5390) 4252 rt5390_set_chan(sc, chan); 4253 else if (sc->mac_ver >= 0x3071) 4254 rt3090_set_chan(sc, chan); 4255 else 4256 rt2860_set_chan(sc, chan); 4257 4258 /* determine channel group */ 4259 if (chan <= 14) 4260 group = 0; 4261 else if (chan <= 64) 4262 group = 1; 4263 else if (chan <= 128) 4264 group = 2; 4265 else 4266 group = 3; 4267 4268 /* XXX necessary only when group has changed! */ 4269 if (sc->mac_ver < 0x5390) 4270 rt2860_select_chan_group(sc, group); 4271 4272 DELAY(1000); 4273 } 4274 4275 static int 4276 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4277 { 4278 struct ieee80211com *ic = vap->iv_ic; 4279 struct rt2860_txwi txwi; 4280 struct mbuf *m; 4281 int ridx; 4282 4283 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4284 return ENOBUFS; 4285 4286 memset(&txwi, 0, sizeof txwi); 4287 txwi.wcid = 0xff; 4288 txwi.len = htole16(m->m_pkthdr.len); 4289 /* send beacons at the lowest available rate */ 4290 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4291 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4292 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4293 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4294 txwi.phy |= htole16(RT2860_PHY_OFDM); 4295 txwi.txop = RT2860_TX_TXOP_HT; 4296 txwi.flags = RT2860_TX_TS; 4297 txwi.xflags = RT2860_TX_NSEQ; 4298 4299 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4300 (uint8_t *)&txwi, sizeof txwi); 4301 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4302 mtod(m, uint8_t *), m->m_pkthdr.len); 4303 4304 m_freem(m); 4305 4306 return 0; 4307 } 4308 4309 static void 4310 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4311 { 4312 struct ieee80211com *ic = &sc->sc_ic; 4313 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4314 uint32_t tmp; 4315 4316 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4317 4318 tmp &= ~0x1fffff; 4319 tmp |= vap->iv_bss->ni_intval * 16; 4320 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4321 if (vap->iv_opmode == IEEE80211_M_STA) { 4322 /* 4323 * Local TSF is always updated with remote TSF on beacon 4324 * reception. 4325 */ 4326 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4327 } 4328 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4329 vap->iv_opmode == IEEE80211_M_MBSS) { 4330 tmp |= RT2860_BCN_TX_EN; 4331 /* 4332 * Local TSF is updated with remote TSF on beacon reception 4333 * only if the remote TSF is greater than local TSF. 4334 */ 4335 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4336 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4337 tmp |= RT2860_BCN_TX_EN; 4338 /* SYNC with nobody */ 4339 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4340 } 4341 4342 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4343 }
Cache object: ca3d5aae30aac95b240d19b239125cdb
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