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sys/dev/ral/rt2860.c
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1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_ratectl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2860reg.h> 68 #include <dev/ral/rt2860var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83 static void rt2860_vap_delete(struct ieee80211vap *); 84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92 static void rt2860_free_tx_pool(struct rt2860_softc *); 93 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_updatestats(struct rt2860_softc *); 100 static void rt2860_newassoc(struct ieee80211_node *, int); 101 static void rt2860_node_free(struct ieee80211_node *); 102 #ifdef IEEE80211_HT 103 static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107 #endif 108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112 static void rt2860_intr_coherent(struct rt2860_softc *); 113 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114 static void rt2860_tx_intr(struct rt2860_softc *, int); 115 static void rt2860_rx_intr(struct rt2860_softc *); 116 static void rt2860_tbtt_intr(struct rt2860_softc *); 117 static void rt2860_gp_intr(struct rt2860_softc *); 118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126 static void rt2860_start(struct rt2860_softc *); 127 static void rt2860_watchdog(void *); 128 static void rt2860_parent(struct ieee80211com *); 129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135 static void rt2860_enable_mrr(struct rt2860_softc *); 136 static void rt2860_set_txpreamble(struct rt2860_softc *); 137 static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2860_scan_start(struct ieee80211com *); 140 static void rt2860_scan_end(struct ieee80211com *); 141 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 142 struct ieee80211_channel[]); 143 static void rt2860_set_channel(struct ieee80211com *); 144 static void rt2860_select_chan_group(struct rt2860_softc *, int); 145 static void rt2860_set_chan(struct rt2860_softc *, u_int); 146 static void rt3090_set_chan(struct rt2860_softc *, u_int); 147 static void rt5390_set_chan(struct rt2860_softc *, u_int); 148 static int rt3090_rf_init(struct rt2860_softc *); 149 static void rt5390_rf_init(struct rt2860_softc *); 150 static void rt3090_rf_wakeup(struct rt2860_softc *); 151 static void rt5390_rf_wakeup(struct rt2860_softc *); 152 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 153 uint8_t *); 154 static void rt3090_rf_setup(struct rt2860_softc *); 155 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 156 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 157 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 158 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 159 static void rt2860_update_promisc(struct ieee80211com *); 160 static void rt2860_updateslot(struct ieee80211com *); 161 static void rt2860_updateprot(struct rt2860_softc *); 162 static int rt2860_updateedca(struct ieee80211com *); 163 #ifdef HW_CRYPTO 164 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 165 struct ieee80211_key *); 166 static void rt2860_delete_key(struct ieee80211com *, 167 struct ieee80211_node *, struct ieee80211_key *); 168 #endif 169 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 170 static const char *rt2860_get_rf(uint16_t); 171 static int rt2860_read_eeprom(struct rt2860_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173 static int rt2860_bbp_init(struct rt2860_softc *); 174 static void rt5390_bbp_init(struct rt2860_softc *); 175 static int rt2860_txrx_enable(struct rt2860_softc *); 176 static void rt2860_init(void *); 177 static void rt2860_init_locked(struct rt2860_softc *); 178 static void rt2860_stop(void *); 179 static void rt2860_stop_locked(struct rt2860_softc *); 180 static int rt2860_load_microcode(struct rt2860_softc *); 181 #ifdef NOT_YET 182 static void rt2860_calib(struct rt2860_softc *); 183 #endif 184 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 185 static void rt2860_switch_chan(struct rt2860_softc *, 186 struct ieee80211_channel *); 187 static int rt2860_setup_beacon(struct rt2860_softc *, 188 struct ieee80211vap *); 189 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 190 191 static const struct { 192 uint32_t reg; 193 uint32_t val; 194 } rt2860_def_mac[] = { 195 RT2860_DEF_MAC 196 }; 197 198 static const struct { 199 uint8_t reg; 200 uint8_t val; 201 } rt2860_def_bbp[] = { 202 RT2860_DEF_BBP 203 }, rt5390_def_bbp[] = { 204 RT5390_DEF_BBP 205 }; 206 207 static const struct rfprog { 208 uint8_t chan; 209 uint32_t r1, r2, r3, r4; 210 } rt2860_rf2850[] = { 211 RT2860_RF2850 212 }; 213 214 struct { 215 uint8_t n, r, k; 216 } rt3090_freqs[] = { 217 RT3070_RF3052 218 }; 219 220 static const struct { 221 uint8_t reg; 222 uint8_t val; 223 } rt3090_def_rf[] = { 224 RT3070_DEF_RF 225 }, rt5390_def_rf[] = { 226 RT5390_DEF_RF 227 }, rt5392_def_rf[] = { 228 RT5392_DEF_RF 229 }; 230 231 static const uint8_t rt2860_chan_5ghz[] = 232 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 233 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 234 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 235 236 int 237 rt2860_attach(device_t dev, int id) 238 { 239 struct rt2860_softc *sc = device_get_softc(dev); 240 struct ieee80211com *ic = &sc->sc_ic; 241 uint32_t tmp; 242 int error, ntries, qid; 243 244 sc->sc_dev = dev; 245 sc->sc_debug = 0; 246 247 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 248 MTX_DEF | MTX_RECURSE); 249 250 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 251 mbufq_init(&sc->sc_snd, ifqmaxlen); 252 253 /* wait for NIC to initialize */ 254 for (ntries = 0; ntries < 100; ntries++) { 255 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 256 if (tmp != 0 && tmp != 0xffffffff) 257 break; 258 DELAY(10); 259 } 260 if (ntries == 100) { 261 device_printf(sc->sc_dev, 262 "timeout waiting for NIC to initialize\n"); 263 error = EIO; 264 goto fail1; 265 } 266 sc->mac_ver = tmp >> 16; 267 sc->mac_rev = tmp & 0xffff; 268 269 if (sc->mac_ver != 0x2860 && 270 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 271 sc->sc_flags |= RT2860_ADVANCED_PS; 272 273 /* retrieve RF rev. no and various other things from EEPROM */ 274 rt2860_read_eeprom(sc, ic->ic_macaddr); 275 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 276 "RF %s (MIMO %dT%dR), address %6D\n", 277 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 278 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 279 280 /* 281 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 282 */ 283 for (qid = 0; qid < 6; qid++) { 284 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 285 device_printf(sc->sc_dev, 286 "could not allocate Tx ring %d\n", qid); 287 goto fail2; 288 } 289 } 290 291 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 292 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 293 goto fail2; 294 } 295 296 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 297 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 298 goto fail3; 299 } 300 301 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 302 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 303 WME_AC_VO : 5; 304 305 ic->ic_softc = sc; 306 ic->ic_name = device_get_nameunit(dev); 307 ic->ic_opmode = IEEE80211_M_STA; 308 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 309 310 /* set device capabilities */ 311 ic->ic_caps = 312 IEEE80211_C_STA /* station mode */ 313 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 314 | IEEE80211_C_HOSTAP /* hostap mode */ 315 | IEEE80211_C_MONITOR /* monitor mode */ 316 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 317 | IEEE80211_C_WDS /* 4-address traffic works */ 318 | IEEE80211_C_MBSS /* mesh point link mode */ 319 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 320 | IEEE80211_C_SHSLOT /* short slot time supported */ 321 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 322 #if 0 323 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 324 #endif 325 | IEEE80211_C_WME /* 802.11e */ 326 ; 327 328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 329 ic->ic_channels); 330 331 ieee80211_ifattach(ic); 332 333 ic->ic_wme.wme_update = rt2860_updateedca; 334 ic->ic_scan_start = rt2860_scan_start; 335 ic->ic_scan_end = rt2860_scan_end; 336 ic->ic_getradiocaps = rt2860_getradiocaps; 337 ic->ic_set_channel = rt2860_set_channel; 338 ic->ic_updateslot = rt2860_updateslot; 339 ic->ic_update_promisc = rt2860_update_promisc; 340 ic->ic_raw_xmit = rt2860_raw_xmit; 341 sc->sc_node_free = ic->ic_node_free; 342 ic->ic_node_free = rt2860_node_free; 343 ic->ic_newassoc = rt2860_newassoc; 344 ic->ic_transmit = rt2860_transmit; 345 ic->ic_parent = rt2860_parent; 346 ic->ic_vap_create = rt2860_vap_create; 347 ic->ic_vap_delete = rt2860_vap_delete; 348 349 ieee80211_radiotap_attach(ic, 350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 351 RT2860_TX_RADIOTAP_PRESENT, 352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 353 RT2860_RX_RADIOTAP_PRESENT); 354 355 #ifdef RAL_DEBUG 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 359 #endif 360 if (bootverbose) 361 ieee80211_announce(ic); 362 363 return 0; 364 365 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 366 fail2: while (--qid >= 0) 367 rt2860_free_tx_ring(sc, &sc->txq[qid]); 368 fail1: mtx_destroy(&sc->sc_mtx); 369 return error; 370 } 371 372 int 373 rt2860_detach(void *xsc) 374 { 375 struct rt2860_softc *sc = xsc; 376 struct ieee80211com *ic = &sc->sc_ic; 377 int qid; 378 379 RAL_LOCK(sc); 380 rt2860_stop_locked(sc); 381 RAL_UNLOCK(sc); 382 383 ieee80211_ifdetach(ic); 384 mbufq_drain(&sc->sc_snd); 385 for (qid = 0; qid < 6; qid++) 386 rt2860_free_tx_ring(sc, &sc->txq[qid]); 387 rt2860_free_rx_ring(sc, &sc->rxq); 388 rt2860_free_tx_pool(sc); 389 390 mtx_destroy(&sc->sc_mtx); 391 392 return 0; 393 } 394 395 void 396 rt2860_shutdown(void *xsc) 397 { 398 struct rt2860_softc *sc = xsc; 399 400 rt2860_stop(sc); 401 } 402 403 void 404 rt2860_suspend(void *xsc) 405 { 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409 } 410 411 void 412 rt2860_resume(void *xsc) 413 { 414 struct rt2860_softc *sc = xsc; 415 416 if (sc->sc_ic.ic_nrunning > 0) 417 rt2860_init(sc); 418 } 419 420 static struct ieee80211vap * 421 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 422 enum ieee80211_opmode opmode, int flags, 423 const uint8_t bssid[IEEE80211_ADDR_LEN], 424 const uint8_t mac[IEEE80211_ADDR_LEN]) 425 { 426 struct rt2860_softc *sc = ic->ic_softc; 427 struct rt2860_vap *rvp; 428 struct ieee80211vap *vap; 429 430 switch (opmode) { 431 case IEEE80211_M_STA: 432 case IEEE80211_M_IBSS: 433 case IEEE80211_M_AHDEMO: 434 case IEEE80211_M_MONITOR: 435 case IEEE80211_M_HOSTAP: 436 case IEEE80211_M_MBSS: 437 /* XXXRP: TBD */ 438 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 439 device_printf(sc->sc_dev, "only 1 vap supported\n"); 440 return NULL; 441 } 442 if (opmode == IEEE80211_M_STA) 443 flags |= IEEE80211_CLONE_NOBEACONS; 444 break; 445 case IEEE80211_M_WDS: 446 if (TAILQ_EMPTY(&ic->ic_vaps) || 447 ic->ic_opmode != IEEE80211_M_HOSTAP) { 448 device_printf(sc->sc_dev, 449 "wds only supported in ap mode\n"); 450 return NULL; 451 } 452 /* 453 * Silently remove any request for a unique 454 * bssid; WDS vap's always share the local 455 * mac address. 456 */ 457 flags &= ~IEEE80211_CLONE_BSSID; 458 break; 459 default: 460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 461 return NULL; 462 } 463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 464 vap = &rvp->ral_vap; 465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 466 467 /* override state transition machine */ 468 rvp->ral_newstate = vap->iv_newstate; 469 vap->iv_newstate = rt2860_newstate; 470 #if 0 471 vap->iv_update_beacon = rt2860_beacon_update; 472 #endif 473 474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 476 477 ieee80211_ratectl_init(vap); 478 /* complete setup */ 479 ieee80211_vap_attach(vap, ieee80211_media_change, 480 ieee80211_media_status, mac); 481 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 482 ic->ic_opmode = opmode; 483 return vap; 484 } 485 486 static void 487 rt2860_vap_delete(struct ieee80211vap *vap) 488 { 489 struct rt2860_vap *rvp = RT2860_VAP(vap); 490 491 ieee80211_ratectl_deinit(vap); 492 ieee80211_vap_detach(vap); 493 free(rvp, M_80211_VAP); 494 } 495 496 static void 497 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 498 { 499 if (error != 0) 500 return; 501 502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 503 504 *(bus_addr_t *)arg = segs[0].ds_addr; 505 } 506 507 static int 508 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 509 { 510 int size, error; 511 512 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 513 514 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 523 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 530 size, rt2860_dma_map_addr, &ring->paddr, 0); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 533 goto fail; 534 } 535 536 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 537 538 return 0; 539 540 fail: rt2860_free_tx_ring(sc, ring); 541 return error; 542 } 543 544 void 545 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 546 { 547 struct rt2860_tx_data *data; 548 int i; 549 550 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 551 if ((data = ring->data[i]) == NULL) 552 continue; /* nothing mapped in this slot */ 553 554 if (data->m != NULL) { 555 bus_dmamap_sync(sc->txwi_dmat, data->map, 556 BUS_DMASYNC_POSTWRITE); 557 bus_dmamap_unload(sc->txwi_dmat, data->map); 558 m_freem(data->m); 559 data->m = NULL; 560 } 561 if (data->ni != NULL) { 562 ieee80211_free_node(data->ni); 563 data->ni = NULL; 564 } 565 566 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 567 ring->data[i] = NULL; 568 } 569 570 ring->queued = 0; 571 ring->cur = ring->next = 0; 572 } 573 574 void 575 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 576 { 577 struct rt2860_tx_data *data; 578 int i; 579 580 if (ring->txd != NULL) { 581 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 582 BUS_DMASYNC_POSTWRITE); 583 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 584 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 585 } 586 if (ring->desc_dmat != NULL) 587 bus_dma_tag_destroy(ring->desc_dmat); 588 589 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 590 if ((data = ring->data[i]) == NULL) 591 continue; /* nothing mapped in this slot */ 592 593 if (data->m != NULL) { 594 bus_dmamap_sync(sc->txwi_dmat, data->map, 595 BUS_DMASYNC_POSTWRITE); 596 bus_dmamap_unload(sc->txwi_dmat, data->map); 597 m_freem(data->m); 598 } 599 if (data->ni != NULL) 600 ieee80211_free_node(data->ni); 601 602 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 603 } 604 } 605 606 /* 607 * Allocate a pool of TX Wireless Information blocks. 608 */ 609 int 610 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 611 { 612 caddr_t vaddr; 613 bus_addr_t paddr; 614 int i, size, error; 615 616 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 617 618 /* init data_pool early in case of failure.. */ 619 SLIST_INIT(&sc->data_pool); 620 621 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 622 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 623 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 624 if (error != 0) { 625 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 633 goto fail; 634 } 635 636 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 637 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 638 if (error != 0) { 639 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 640 goto fail; 641 } 642 643 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 644 645 vaddr = sc->txwi_vaddr; 646 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 647 struct rt2860_tx_data *data = &sc->data[i]; 648 649 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 650 if (error != 0) { 651 device_printf(sc->sc_dev, "could not create DMA map\n"); 652 goto fail; 653 } 654 data->txwi = (struct rt2860_txwi *)vaddr; 655 data->paddr = paddr; 656 vaddr += RT2860_TXWI_DMASZ; 657 paddr += RT2860_TXWI_DMASZ; 658 659 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 660 } 661 662 return 0; 663 664 fail: rt2860_free_tx_pool(sc); 665 return error; 666 } 667 668 void 669 rt2860_free_tx_pool(struct rt2860_softc *sc) 670 { 671 if (sc->txwi_vaddr != NULL) { 672 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 673 BUS_DMASYNC_POSTWRITE); 674 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 675 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 676 } 677 if (sc->txwi_dmat != NULL) 678 bus_dma_tag_destroy(sc->txwi_dmat); 679 680 while (!SLIST_EMPTY(&sc->data_pool)) { 681 struct rt2860_tx_data *data; 682 data = SLIST_FIRST(&sc->data_pool); 683 bus_dmamap_destroy(sc->txwi_dmat, data->map); 684 SLIST_REMOVE_HEAD(&sc->data_pool, next); 685 } 686 } 687 688 int 689 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 690 { 691 bus_addr_t physaddr; 692 int i, size, error; 693 694 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 695 696 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 698 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 699 if (error != 0) { 700 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 701 goto fail; 702 } 703 704 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 705 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 706 if (error != 0) { 707 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 708 goto fail; 709 } 710 711 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 712 size, rt2860_dma_map_addr, &ring->paddr, 0); 713 if (error != 0) { 714 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 715 goto fail; 716 } 717 718 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 719 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 720 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 721 if (error != 0) { 722 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 723 goto fail; 724 } 725 726 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 727 struct rt2860_rx_data *data = &ring->data[i]; 728 struct rt2860_rxd *rxd = &ring->rxd[i]; 729 730 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 731 if (error != 0) { 732 device_printf(sc->sc_dev, "could not create DMA map\n"); 733 goto fail; 734 } 735 736 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 737 if (data->m == NULL) { 738 device_printf(sc->sc_dev, 739 "could not allocate rx mbuf\n"); 740 error = ENOMEM; 741 goto fail; 742 } 743 744 error = bus_dmamap_load(ring->data_dmat, data->map, 745 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 746 &physaddr, 0); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "could not load rx buf DMA map"); 750 goto fail; 751 } 752 753 rxd->sdp0 = htole32(physaddr); 754 rxd->sdl0 = htole16(MCLBYTES); 755 } 756 757 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 758 759 return 0; 760 761 fail: rt2860_free_rx_ring(sc, ring); 762 return error; 763 } 764 765 void 766 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 767 { 768 int i; 769 770 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 771 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 772 773 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 774 775 ring->cur = 0; 776 } 777 778 void 779 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 780 { 781 int i; 782 783 if (ring->rxd != NULL) { 784 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 785 BUS_DMASYNC_POSTWRITE); 786 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 787 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 788 } 789 if (ring->desc_dmat != NULL) 790 bus_dma_tag_destroy(ring->desc_dmat); 791 792 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 793 struct rt2860_rx_data *data = &ring->data[i]; 794 795 if (data->m != NULL) { 796 bus_dmamap_sync(ring->data_dmat, data->map, 797 BUS_DMASYNC_POSTREAD); 798 bus_dmamap_unload(ring->data_dmat, data->map); 799 m_freem(data->m); 800 } 801 if (data->map != NULL) 802 bus_dmamap_destroy(ring->data_dmat, data->map); 803 } 804 if (ring->data_dmat != NULL) 805 bus_dma_tag_destroy(ring->data_dmat); 806 } 807 808 static void 809 rt2860_updatestats(struct rt2860_softc *sc) 810 { 811 struct ieee80211com *ic = &sc->sc_ic; 812 813 /* 814 * In IBSS or HostAP modes (when the hardware sends beacons), the 815 * MAC can run into a livelock and start sending CTS-to-self frames 816 * like crazy if protection is enabled. Fortunately, we can detect 817 * when such a situation occurs and reset the MAC. 818 */ 819 if (ic->ic_curmode != IEEE80211_M_STA) { 820 /* check if we're in a livelock situation.. */ 821 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 822 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 823 /* ..and reset MAC/BBP for a while.. */ 824 DPRINTF(("CTS-to-self livelock detected\n")); 825 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 826 RAL_BARRIER_WRITE(sc); 827 DELAY(1); 828 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 829 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 830 } 831 } 832 } 833 834 static void 835 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 836 { 837 struct ieee80211com *ic = ni->ni_ic; 838 struct rt2860_softc *sc = ic->ic_softc; 839 uint8_t wcid; 840 841 wcid = IEEE80211_AID(ni->ni_associd); 842 if (isnew && ni->ni_associd != 0) { 843 sc->wcid2ni[wcid] = ni; 844 845 /* init WCID table entry */ 846 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 847 ni->ni_macaddr, IEEE80211_ADDR_LEN); 848 } 849 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 850 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 851 } 852 853 static void 854 rt2860_node_free(struct ieee80211_node *ni) 855 { 856 struct ieee80211com *ic = ni->ni_ic; 857 struct rt2860_softc *sc = ic->ic_softc; 858 uint8_t wcid; 859 860 if (ni->ni_associd != 0) { 861 wcid = IEEE80211_AID(ni->ni_associd); 862 863 /* clear Rx WCID search table entry */ 864 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 865 } 866 sc->sc_node_free(ni); 867 } 868 869 #ifdef IEEE80211_HT 870 static int 871 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 872 uint8_t tid) 873 { 874 struct rt2860_softc *sc = ic->ic_softc; 875 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 876 uint32_t tmp; 877 878 /* update BA session mask */ 879 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 880 tmp |= (1 << tid) << 16; 881 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 882 return 0; 883 } 884 885 static void 886 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 887 uint8_t tid) 888 { 889 struct rt2860_softc *sc = ic->ic_softc; 890 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 891 uint32_t tmp; 892 893 /* update BA session mask */ 894 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 895 tmp &= ~((1 << tid) << 16); 896 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 897 } 898 #endif 899 900 static int 901 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 902 { 903 struct rt2860_vap *rvp = RT2860_VAP(vap); 904 struct ieee80211com *ic = vap->iv_ic; 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint32_t tmp; 907 int error; 908 909 if (vap->iv_state == IEEE80211_S_RUN) { 910 /* turn link LED off */ 911 rt2860_set_leds(sc, RT2860_LED_RADIO); 912 } 913 914 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 915 /* abort TSF synchronization */ 916 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 917 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 918 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 919 RT2860_TBTT_TIMER_EN)); 920 } 921 922 rt2860_set_gp_timer(sc, 0); 923 924 error = rvp->ral_newstate(vap, nstate, arg); 925 if (error != 0) 926 return (error); 927 928 if (nstate == IEEE80211_S_RUN) { 929 struct ieee80211_node *ni = vap->iv_bss; 930 931 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 932 rt2860_enable_mrr(sc); 933 rt2860_set_txpreamble(sc); 934 rt2860_set_basicrates(sc, &ni->ni_rates); 935 rt2860_set_bssid(sc, ni->ni_bssid); 936 } 937 938 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 939 vap->iv_opmode == IEEE80211_M_IBSS || 940 vap->iv_opmode == IEEE80211_M_MBSS) { 941 error = rt2860_setup_beacon(sc, vap); 942 if (error != 0) 943 return error; 944 } 945 946 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 947 rt2860_enable_tsf_sync(sc); 948 rt2860_set_gp_timer(sc, 500); 949 } 950 951 /* turn link LED on */ 952 rt2860_set_leds(sc, RT2860_LED_RADIO | 953 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 954 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 955 } 956 return error; 957 } 958 959 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 960 static uint16_t 961 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 962 { 963 uint32_t tmp; 964 uint16_t reg; 965 int ntries; 966 967 addr *= 2; 968 /*- 969 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 970 * DATA0: F E D C 971 * DATA1: B A 9 8 972 * DATA2: 7 6 5 4 973 * DATA3: 3 2 1 0 974 */ 975 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 976 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 977 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 978 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 979 for (ntries = 0; ntries < 500; ntries++) { 980 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 981 if (!(tmp & RT3070_EFSROM_KICK)) 982 break; 983 DELAY(2); 984 } 985 if (ntries == 500) 986 return 0xffff; 987 988 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 989 return 0xffff; /* address not found */ 990 991 /* determine to which 32-bit register our 16-bit word belongs */ 992 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 993 tmp = RAL_READ(sc, reg); 994 995 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 996 } 997 998 /* 999 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1000 * 93C66 or 93C86). 1001 */ 1002 static uint16_t 1003 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1004 { 1005 uint32_t tmp; 1006 uint16_t val; 1007 int n; 1008 1009 /* clock C once before the first command */ 1010 RT2860_EEPROM_CTL(sc, 0); 1011 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1014 RT2860_EEPROM_CTL(sc, RT2860_S); 1015 1016 /* write start bit (1) */ 1017 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1019 1020 /* write READ opcode (10) */ 1021 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1023 RT2860_EEPROM_CTL(sc, RT2860_S); 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1025 1026 /* write address (A5-A0 or A7-A0) */ 1027 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1028 for (; n >= 0; n--) { 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1031 RT2860_EEPROM_CTL(sc, RT2860_S | 1032 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1033 } 1034 1035 RT2860_EEPROM_CTL(sc, RT2860_S); 1036 1037 /* read data Q15-Q0 */ 1038 val = 0; 1039 for (n = 15; n >= 0; n--) { 1040 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1041 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1042 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1043 RT2860_EEPROM_CTL(sc, RT2860_S); 1044 } 1045 1046 RT2860_EEPROM_CTL(sc, 0); 1047 1048 /* clear Chip Select and clock C */ 1049 RT2860_EEPROM_CTL(sc, RT2860_S); 1050 RT2860_EEPROM_CTL(sc, 0); 1051 RT2860_EEPROM_CTL(sc, RT2860_C); 1052 1053 return val; 1054 } 1055 1056 static __inline uint16_t 1057 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1058 { 1059 /* either eFUSE ROM or EEPROM */ 1060 return sc->sc_srom_read(sc, addr); 1061 } 1062 1063 static void 1064 rt2860_intr_coherent(struct rt2860_softc *sc) 1065 { 1066 uint32_t tmp; 1067 1068 /* DMA finds data coherent event when checking the DDONE bit */ 1069 1070 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1071 1072 /* restart DMA engine */ 1073 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1074 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1075 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1076 1077 (void)rt2860_txrx_enable(sc); 1078 } 1079 1080 static void 1081 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1082 { 1083 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1084 struct ieee80211_node *ni; 1085 uint32_t stat; 1086 uint8_t wcid, mcs, pid; 1087 1088 /* drain Tx status FIFO (maxsize = 16) */ 1089 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1090 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1091 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1092 1093 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1094 if (wcid > RT2860_WCID_MAX) 1095 continue; 1096 ni = sc->wcid2ni[wcid]; 1097 1098 /* if no ACK was requested, no feedback is available */ 1099 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1100 continue; 1101 1102 /* update per-STA AMRR stats */ 1103 if (stat & RT2860_TXQ_OK) { 1104 /* 1105 * Check if there were retries, ie if the Tx success 1106 * rate is different from the requested rate. Note 1107 * that it works only because we do not allow rate 1108 * fallback from OFDM to CCK. 1109 */ 1110 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1111 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1112 if (mcs + 1 != pid) 1113 txs->long_retries = 1; 1114 else 1115 txs->long_retries = 0; 1116 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1117 ieee80211_ratectl_tx_complete(ni, txs); 1118 } else { 1119 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1120 txs->long_retries = 1; /* XXX */ 1121 ieee80211_ratectl_tx_complete(ni, txs); 1122 if_inc_counter(ni->ni_vap->iv_ifp, 1123 IFCOUNTER_OERRORS, 1); 1124 } 1125 } 1126 } 1127 1128 static void 1129 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1130 { 1131 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1132 uint32_t hw; 1133 1134 rt2860_drain_stats_fifo(sc); 1135 1136 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1137 while (ring->next != hw) { 1138 struct rt2860_tx_data *data = ring->data[ring->next]; 1139 1140 if (data != NULL) { 1141 bus_dmamap_sync(sc->txwi_dmat, data->map, 1142 BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->txwi_dmat, data->map); 1144 ieee80211_tx_complete(data->ni, data->m, 0); 1145 data->ni = NULL; 1146 data->m = NULL; 1147 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1148 ring->data[ring->next] = NULL; 1149 } 1150 ring->queued--; 1151 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1152 } 1153 1154 sc->sc_tx_timer = 0; 1155 if (ring->queued < RT2860_TX_RING_COUNT) 1156 sc->qfullmsk &= ~(1 << qid); 1157 rt2860_start(sc); 1158 } 1159 1160 /* 1161 * Return the Rx chain with the highest RSSI for a given frame. 1162 */ 1163 static __inline uint8_t 1164 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1165 { 1166 uint8_t rxchain = 0; 1167 1168 if (sc->nrxchains > 1) { 1169 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1170 rxchain = 1; 1171 if (sc->nrxchains > 2) 1172 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1173 rxchain = 2; 1174 } 1175 return rxchain; 1176 } 1177 1178 static void 1179 rt2860_rx_intr(struct rt2860_softc *sc) 1180 { 1181 struct epoch_tracker et; 1182 struct rt2860_rx_radiotap_header *tap; 1183 struct ieee80211com *ic = &sc->sc_ic; 1184 struct ieee80211_frame *wh; 1185 struct ieee80211_node *ni; 1186 struct mbuf *m, *m1; 1187 bus_addr_t physaddr; 1188 uint32_t hw; 1189 uint16_t phy; 1190 uint8_t ant; 1191 int8_t rssi, nf; 1192 int error; 1193 1194 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1195 while (sc->rxq.cur != hw) { 1196 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1197 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1198 struct rt2860_rxwi *rxwi; 1199 1200 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1201 BUS_DMASYNC_POSTREAD); 1202 1203 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1204 DPRINTF(("RXD DDONE bit not set!\n")); 1205 break; /* should not happen */ 1206 } 1207 1208 if (__predict_false(rxd->flags & 1209 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1210 counter_u64_add(ic->ic_ierrors, 1); 1211 goto skip; 1212 } 1213 1214 #ifdef HW_CRYPTO 1215 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1216 /* report MIC failures to net80211 for TKIP */ 1217 ic->ic_stats.is_rx_locmicfail++; 1218 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1219 counter_u64_add(ic->ic_ierrors, 1); 1220 goto skip; 1221 } 1222 #endif 1223 1224 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1225 if (__predict_false(m1 == NULL)) { 1226 counter_u64_add(ic->ic_ierrors, 1); 1227 goto skip; 1228 } 1229 1230 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1231 BUS_DMASYNC_POSTREAD); 1232 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1233 1234 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1235 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1236 &physaddr, 0); 1237 if (__predict_false(error != 0)) { 1238 m_freem(m1); 1239 1240 /* try to reload the old mbuf */ 1241 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1242 mtod(data->m, void *), MCLBYTES, 1243 rt2860_dma_map_addr, &physaddr, 0); 1244 if (__predict_false(error != 0)) { 1245 panic("%s: could not load old rx mbuf", 1246 device_get_name(sc->sc_dev)); 1247 } 1248 /* physical address may have changed */ 1249 rxd->sdp0 = htole32(physaddr); 1250 counter_u64_add(ic->ic_ierrors, 1); 1251 goto skip; 1252 } 1253 1254 /* 1255 * New mbuf successfully loaded, update Rx ring and continue 1256 * processing. 1257 */ 1258 m = data->m; 1259 data->m = m1; 1260 rxd->sdp0 = htole32(physaddr); 1261 1262 rxwi = mtod(m, struct rt2860_rxwi *); 1263 1264 /* finalize mbuf */ 1265 m->m_data = (caddr_t)(rxwi + 1); 1266 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1267 1268 wh = mtod(m, struct ieee80211_frame *); 1269 #ifdef HW_CRYPTO 1270 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1271 /* frame is decrypted by hardware */ 1272 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1273 } 1274 #endif 1275 1276 /* HW may insert 2 padding bytes after 802.11 header */ 1277 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1278 u_int hdrlen = ieee80211_hdrsize(wh); 1279 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1280 m->m_data += 2; 1281 wh = mtod(m, struct ieee80211_frame *); 1282 } 1283 1284 ant = rt2860_maxrssi_chain(sc, rxwi); 1285 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1286 nf = RT2860_NOISE_FLOOR; 1287 1288 if (ieee80211_radiotap_active(ic)) { 1289 tap = &sc->sc_rxtap; 1290 tap->wr_flags = 0; 1291 tap->wr_antenna = ant; 1292 tap->wr_antsignal = nf + rssi; 1293 tap->wr_antnoise = nf; 1294 /* in case it can't be found below */ 1295 tap->wr_rate = 2; 1296 phy = le16toh(rxwi->phy); 1297 switch (phy & RT2860_PHY_MODE) { 1298 case RT2860_PHY_CCK: 1299 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1300 case 0: tap->wr_rate = 2; break; 1301 case 1: tap->wr_rate = 4; break; 1302 case 2: tap->wr_rate = 11; break; 1303 case 3: tap->wr_rate = 22; break; 1304 } 1305 if (phy & RT2860_PHY_SHPRE) 1306 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1307 break; 1308 case RT2860_PHY_OFDM: 1309 switch (phy & RT2860_PHY_MCS) { 1310 case 0: tap->wr_rate = 12; break; 1311 case 1: tap->wr_rate = 18; break; 1312 case 2: tap->wr_rate = 24; break; 1313 case 3: tap->wr_rate = 36; break; 1314 case 4: tap->wr_rate = 48; break; 1315 case 5: tap->wr_rate = 72; break; 1316 case 6: tap->wr_rate = 96; break; 1317 case 7: tap->wr_rate = 108; break; 1318 } 1319 break; 1320 } 1321 } 1322 1323 RAL_UNLOCK(sc); 1324 wh = mtod(m, struct ieee80211_frame *); 1325 1326 /* send the frame to the 802.11 layer */ 1327 ni = ieee80211_find_rxnode(ic, 1328 (struct ieee80211_frame_min *)wh); 1329 NET_EPOCH_ENTER(et); 1330 if (ni != NULL) { 1331 (void)ieee80211_input(ni, m, rssi - nf, nf); 1332 ieee80211_free_node(ni); 1333 } else 1334 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1335 NET_EPOCH_EXIT(et); 1336 1337 RAL_LOCK(sc); 1338 1339 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1340 1341 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1342 BUS_DMASYNC_PREWRITE); 1343 1344 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1345 } 1346 1347 /* tell HW what we have processed */ 1348 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1349 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1350 } 1351 1352 static void 1353 rt2860_tbtt_intr(struct rt2860_softc *sc) 1354 { 1355 #if 0 1356 struct ieee80211com *ic = &sc->sc_ic; 1357 1358 #ifndef IEEE80211_STA_ONLY 1359 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1360 /* one less beacon until next DTIM */ 1361 if (ic->ic_dtim_count == 0) 1362 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1363 else 1364 ic->ic_dtim_count--; 1365 1366 /* update dynamic parts of beacon */ 1367 rt2860_setup_beacon(sc); 1368 1369 /* flush buffered multicast frames */ 1370 if (ic->ic_dtim_count == 0) 1371 ieee80211_notify_dtim(ic); 1372 } 1373 #endif 1374 /* check if protection mode has changed */ 1375 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1376 rt2860_updateprot(sc); 1377 sc->sc_ic_flags = ic->ic_flags; 1378 } 1379 #endif 1380 } 1381 1382 static void 1383 rt2860_gp_intr(struct rt2860_softc *sc) 1384 { 1385 struct ieee80211com *ic = &sc->sc_ic; 1386 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1387 1388 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1389 1390 if (vap->iv_state == IEEE80211_S_RUN) 1391 rt2860_updatestats(sc); 1392 } 1393 1394 void 1395 rt2860_intr(void *arg) 1396 { 1397 struct rt2860_softc *sc = arg; 1398 uint32_t r; 1399 1400 RAL_LOCK(sc); 1401 1402 r = RAL_READ(sc, RT2860_INT_STATUS); 1403 if (__predict_false(r == 0xffffffff)) { 1404 RAL_UNLOCK(sc); 1405 return; /* device likely went away */ 1406 } 1407 if (r == 0) { 1408 RAL_UNLOCK(sc); 1409 return; /* not for us */ 1410 } 1411 1412 /* acknowledge interrupts */ 1413 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1414 1415 if (r & RT2860_TX_RX_COHERENT) 1416 rt2860_intr_coherent(sc); 1417 1418 if (r & RT2860_MAC_INT_2) /* TX status */ 1419 rt2860_drain_stats_fifo(sc); 1420 1421 if (r & RT2860_TX_DONE_INT5) 1422 rt2860_tx_intr(sc, 5); 1423 1424 if (r & RT2860_RX_DONE_INT) 1425 rt2860_rx_intr(sc); 1426 1427 if (r & RT2860_TX_DONE_INT4) 1428 rt2860_tx_intr(sc, 4); 1429 1430 if (r & RT2860_TX_DONE_INT3) 1431 rt2860_tx_intr(sc, 3); 1432 1433 if (r & RT2860_TX_DONE_INT2) 1434 rt2860_tx_intr(sc, 2); 1435 1436 if (r & RT2860_TX_DONE_INT1) 1437 rt2860_tx_intr(sc, 1); 1438 1439 if (r & RT2860_TX_DONE_INT0) 1440 rt2860_tx_intr(sc, 0); 1441 1442 if (r & RT2860_MAC_INT_0) /* TBTT */ 1443 rt2860_tbtt_intr(sc); 1444 1445 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1446 /* TBD wakeup */; 1447 1448 if (r & RT2860_MAC_INT_4) /* GP timer */ 1449 rt2860_gp_intr(sc); 1450 1451 RAL_UNLOCK(sc); 1452 } 1453 1454 static int 1455 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1456 { 1457 struct ieee80211com *ic = &sc->sc_ic; 1458 struct ieee80211vap *vap = ni->ni_vap; 1459 struct rt2860_tx_ring *ring; 1460 struct rt2860_tx_data *data; 1461 struct rt2860_txd *txd; 1462 struct rt2860_txwi *txwi; 1463 struct ieee80211_frame *wh; 1464 const struct ieee80211_txparam *tp = ni->ni_txparms; 1465 struct ieee80211_key *k; 1466 struct mbuf *m1; 1467 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1468 bus_dma_segment_t *seg; 1469 u_int hdrlen; 1470 uint16_t qos, dur; 1471 uint8_t type, qsel, mcs, pid, tid, qid; 1472 int i, nsegs, ntxds, pad, rate, ridx, error; 1473 1474 /* the data pool contains at least one element, pick the first */ 1475 data = SLIST_FIRST(&sc->data_pool); 1476 1477 wh = mtod(m, struct ieee80211_frame *); 1478 1479 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1480 k = ieee80211_crypto_encap(ni, m); 1481 if (k == NULL) { 1482 m_freem(m); 1483 return ENOBUFS; 1484 } 1485 1486 /* packet header may have moved, reset our local pointer */ 1487 wh = mtod(m, struct ieee80211_frame *); 1488 } 1489 1490 hdrlen = ieee80211_anyhdrsize(wh); 1491 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1492 1493 if (m->m_flags & M_EAPOL) { 1494 rate = tp->mgmtrate; 1495 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1496 rate = tp->mcastrate; 1497 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1498 rate = tp->ucastrate; 1499 } else { 1500 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1501 rate = ni->ni_txrate; 1502 } 1503 rate &= IEEE80211_RATE_VAL; 1504 1505 qid = M_WME_GETAC(m); 1506 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1507 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1508 tid = qos & IEEE80211_QOS_TID; 1509 } else { 1510 qos = 0; 1511 tid = 0; 1512 } 1513 ring = &sc->txq[qid]; 1514 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1515 1516 /* get MCS code from rate index */ 1517 mcs = rt2860_rates[ridx].mcs; 1518 1519 /* setup TX Wireless Information */ 1520 txwi = data->txwi; 1521 txwi->flags = 0; 1522 /* let HW generate seq numbers for non-QoS frames */ 1523 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1524 if (type == IEEE80211_FC0_TYPE_DATA) 1525 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1526 else 1527 txwi->wcid = 0xff; 1528 txwi->len = htole16(m->m_pkthdr.len); 1529 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1530 txwi->phy = htole16(RT2860_PHY_CCK); 1531 if (ridx != RT2860_RIDX_CCK1 && 1532 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1533 mcs |= RT2860_PHY_SHPRE; 1534 } else 1535 txwi->phy = htole16(RT2860_PHY_OFDM); 1536 txwi->phy |= htole16(mcs); 1537 1538 /* 1539 * We store the MCS code into the driver-private PacketID field. 1540 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1541 * that we know at which initial rate the frame was transmitted. 1542 * We add 1 to the MCS code because setting the PacketID field to 1543 * 0 means that we don't want feedback in TX_STAT_FIFO. 1544 */ 1545 pid = (mcs + 1) & 0xf; 1546 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1547 1548 /* check if RTS/CTS or CTS-to-self protection is required */ 1549 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1550 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1551 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1552 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1553 txwi->txop = RT2860_TX_TXOP_HT; 1554 else 1555 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1556 1557 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1558 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1559 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1560 txwi->xflags |= RT2860_TX_ACK; 1561 1562 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1563 dur = rt2860_rates[ridx].sp_ack_dur; 1564 else 1565 dur = rt2860_rates[ridx].lp_ack_dur; 1566 *(uint16_t *)wh->i_dur = htole16(dur); 1567 } 1568 /* ask MAC to insert timestamp into probe responses */ 1569 if ((wh->i_fc[0] & 1570 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1571 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1572 /* NOTE: beacons do not pass through tx_data() */ 1573 txwi->flags |= RT2860_TX_TS; 1574 1575 if (ieee80211_radiotap_active_vap(vap)) { 1576 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1577 1578 tap->wt_flags = 0; 1579 tap->wt_rate = rate; 1580 if (mcs & RT2860_PHY_SHPRE) 1581 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1582 1583 ieee80211_radiotap_tx(vap, m); 1584 } 1585 1586 pad = (hdrlen + 3) & ~3; 1587 1588 /* copy and trim 802.11 header */ 1589 memcpy(txwi + 1, wh, hdrlen); 1590 m_adj(m, hdrlen); 1591 1592 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1593 &nsegs, 0); 1594 if (__predict_false(error != 0 && error != EFBIG)) { 1595 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1596 error); 1597 m_freem(m); 1598 return error; 1599 } 1600 if (__predict_true(error == 0)) { 1601 /* determine how many TXDs are required */ 1602 ntxds = 1 + (nsegs / 2); 1603 1604 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1605 /* not enough free TXDs, force mbuf defrag */ 1606 bus_dmamap_unload(sc->txwi_dmat, data->map); 1607 error = EFBIG; 1608 } 1609 } 1610 if (__predict_false(error != 0)) { 1611 m1 = m_defrag(m, M_NOWAIT); 1612 if (m1 == NULL) { 1613 device_printf(sc->sc_dev, 1614 "could not defragment mbuf\n"); 1615 m_freem(m); 1616 return ENOBUFS; 1617 } 1618 m = m1; 1619 1620 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1621 segs, &nsegs, 0); 1622 if (__predict_false(error != 0)) { 1623 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1624 error); 1625 m_freem(m); 1626 return error; 1627 } 1628 1629 /* determine how many TXDs are now required */ 1630 ntxds = 1 + (nsegs / 2); 1631 1632 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1633 /* this is a hopeless case, drop the mbuf! */ 1634 bus_dmamap_unload(sc->txwi_dmat, data->map); 1635 m_freem(m); 1636 return ENOBUFS; 1637 } 1638 } 1639 1640 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1641 1642 /* first segment is TXWI + 802.11 header */ 1643 txd = &ring->txd[ring->cur]; 1644 txd->sdp0 = htole32(data->paddr); 1645 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1646 txd->flags = qsel; 1647 1648 /* setup payload segments */ 1649 seg = &segs[0]; 1650 for (i = nsegs; i >= 2; i -= 2) { 1651 txd->sdp1 = htole32(seg->ds_addr); 1652 txd->sdl1 = htole16(seg->ds_len); 1653 seg++; 1654 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1655 /* grab a new Tx descriptor */ 1656 txd = &ring->txd[ring->cur]; 1657 txd->sdp0 = htole32(seg->ds_addr); 1658 txd->sdl0 = htole16(seg->ds_len); 1659 txd->flags = qsel; 1660 seg++; 1661 } 1662 /* finalize last segment */ 1663 if (i > 0) { 1664 txd->sdp1 = htole32(seg->ds_addr); 1665 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1666 } else { 1667 txd->sdl0 |= htole16(RT2860_TX_LS0); 1668 txd->sdl1 = 0; 1669 } 1670 1671 /* remove from the free pool and link it into the SW Tx slot */ 1672 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1673 data->m = m; 1674 data->ni = ni; 1675 ring->data[ring->cur] = data; 1676 1677 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1678 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1679 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1680 1681 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1682 qid, txwi->wcid, nsegs, ridx)); 1683 1684 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1685 ring->queued += ntxds; 1686 if (ring->queued >= RT2860_TX_RING_COUNT) 1687 sc->qfullmsk |= 1 << qid; 1688 1689 /* kick Tx */ 1690 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1691 1692 return 0; 1693 } 1694 1695 static int 1696 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1697 const struct ieee80211_bpf_params *params) 1698 { 1699 struct ieee80211com *ic = ni->ni_ic; 1700 struct rt2860_softc *sc = ic->ic_softc; 1701 int error; 1702 1703 RAL_LOCK(sc); 1704 1705 /* prevent management frames from being sent if we're not ready */ 1706 if (!(sc->sc_flags & RT2860_RUNNING)) { 1707 RAL_UNLOCK(sc); 1708 m_freem(m); 1709 return ENETDOWN; 1710 } 1711 if (params == NULL) { 1712 /* 1713 * Legacy path; interpret frame contents to decide 1714 * precisely how to send the frame. 1715 */ 1716 error = rt2860_tx(sc, m, ni); 1717 } else { 1718 /* 1719 * Caller supplied explicit parameters to use in 1720 * sending the frame. 1721 */ 1722 error = rt2860_tx_raw(sc, m, ni, params); 1723 } 1724 sc->sc_tx_timer = 5; 1725 RAL_UNLOCK(sc); 1726 return error; 1727 } 1728 1729 static int 1730 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1731 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1732 { 1733 struct ieee80211com *ic = &sc->sc_ic; 1734 struct ieee80211vap *vap = ni->ni_vap; 1735 struct rt2860_tx_ring *ring; 1736 struct rt2860_tx_data *data; 1737 struct rt2860_txd *txd; 1738 struct rt2860_txwi *txwi; 1739 struct ieee80211_frame *wh; 1740 struct mbuf *m1; 1741 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1742 bus_dma_segment_t *seg; 1743 u_int hdrlen; 1744 uint16_t dur; 1745 uint8_t type, qsel, mcs, pid, tid, qid; 1746 int i, nsegs, ntxds, pad, rate, ridx, error; 1747 1748 /* the data pool contains at least one element, pick the first */ 1749 data = SLIST_FIRST(&sc->data_pool); 1750 1751 wh = mtod(m, struct ieee80211_frame *); 1752 hdrlen = ieee80211_hdrsize(wh); 1753 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1754 1755 /* Choose a TX rate index. */ 1756 rate = params->ibp_rate0; 1757 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1758 rate & IEEE80211_RATE_VAL); 1759 if (ridx == (uint8_t)-1) { 1760 /* XXX fall back to mcast/mgmt rate? */ 1761 m_freem(m); 1762 return EINVAL; 1763 } 1764 1765 qid = params->ibp_pri & 3; 1766 tid = 0; 1767 ring = &sc->txq[qid]; 1768 1769 /* get MCS code from rate index */ 1770 mcs = rt2860_rates[ridx].mcs; 1771 1772 /* setup TX Wireless Information */ 1773 txwi = data->txwi; 1774 txwi->flags = 0; 1775 /* let HW generate seq numbers for non-QoS frames */ 1776 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1777 txwi->wcid = 0xff; 1778 txwi->len = htole16(m->m_pkthdr.len); 1779 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1780 txwi->phy = htole16(RT2860_PHY_CCK); 1781 if (ridx != RT2860_RIDX_CCK1 && 1782 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1783 mcs |= RT2860_PHY_SHPRE; 1784 } else 1785 txwi->phy = htole16(RT2860_PHY_OFDM); 1786 txwi->phy |= htole16(mcs); 1787 1788 /* 1789 * We store the MCS code into the driver-private PacketID field. 1790 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1791 * that we know at which initial rate the frame was transmitted. 1792 * We add 1 to the MCS code because setting the PacketID field to 1793 * 0 means that we don't want feedback in TX_STAT_FIFO. 1794 */ 1795 pid = (mcs + 1) & 0xf; 1796 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1797 1798 /* check if RTS/CTS or CTS-to-self protection is required */ 1799 if (params->ibp_flags & IEEE80211_BPF_RTS || 1800 params->ibp_flags & IEEE80211_BPF_CTS) 1801 txwi->txop = RT2860_TX_TXOP_HT; 1802 else 1803 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1804 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1805 txwi->xflags |= RT2860_TX_ACK; 1806 1807 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1808 dur = rt2860_rates[ridx].sp_ack_dur; 1809 else 1810 dur = rt2860_rates[ridx].lp_ack_dur; 1811 *(uint16_t *)wh->i_dur = htole16(dur); 1812 } 1813 /* ask MAC to insert timestamp into probe responses */ 1814 if ((wh->i_fc[0] & 1815 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1816 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1817 /* NOTE: beacons do not pass through tx_data() */ 1818 txwi->flags |= RT2860_TX_TS; 1819 1820 if (ieee80211_radiotap_active_vap(vap)) { 1821 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1822 1823 tap->wt_flags = 0; 1824 tap->wt_rate = rate; 1825 if (mcs & RT2860_PHY_SHPRE) 1826 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1827 1828 ieee80211_radiotap_tx(vap, m); 1829 } 1830 1831 pad = (hdrlen + 3) & ~3; 1832 1833 /* copy and trim 802.11 header */ 1834 memcpy(txwi + 1, wh, hdrlen); 1835 m_adj(m, hdrlen); 1836 1837 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1838 &nsegs, 0); 1839 if (__predict_false(error != 0 && error != EFBIG)) { 1840 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1841 error); 1842 m_freem(m); 1843 return error; 1844 } 1845 if (__predict_true(error == 0)) { 1846 /* determine how many TXDs are required */ 1847 ntxds = 1 + (nsegs / 2); 1848 1849 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1850 /* not enough free TXDs, force mbuf defrag */ 1851 bus_dmamap_unload(sc->txwi_dmat, data->map); 1852 error = EFBIG; 1853 } 1854 } 1855 if (__predict_false(error != 0)) { 1856 m1 = m_defrag(m, M_NOWAIT); 1857 if (m1 == NULL) { 1858 device_printf(sc->sc_dev, 1859 "could not defragment mbuf\n"); 1860 m_freem(m); 1861 return ENOBUFS; 1862 } 1863 m = m1; 1864 1865 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1866 segs, &nsegs, 0); 1867 if (__predict_false(error != 0)) { 1868 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1869 error); 1870 m_freem(m); 1871 return error; 1872 } 1873 1874 /* determine how many TXDs are now required */ 1875 ntxds = 1 + (nsegs / 2); 1876 1877 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1878 /* this is a hopeless case, drop the mbuf! */ 1879 bus_dmamap_unload(sc->txwi_dmat, data->map); 1880 m_freem(m); 1881 return ENOBUFS; 1882 } 1883 } 1884 1885 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1886 1887 /* first segment is TXWI + 802.11 header */ 1888 txd = &ring->txd[ring->cur]; 1889 txd->sdp0 = htole32(data->paddr); 1890 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1891 txd->flags = qsel; 1892 1893 /* setup payload segments */ 1894 seg = &segs[0]; 1895 for (i = nsegs; i >= 2; i -= 2) { 1896 txd->sdp1 = htole32(seg->ds_addr); 1897 txd->sdl1 = htole16(seg->ds_len); 1898 seg++; 1899 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1900 /* grab a new Tx descriptor */ 1901 txd = &ring->txd[ring->cur]; 1902 txd->sdp0 = htole32(seg->ds_addr); 1903 txd->sdl0 = htole16(seg->ds_len); 1904 txd->flags = qsel; 1905 seg++; 1906 } 1907 /* finalize last segment */ 1908 if (i > 0) { 1909 txd->sdp1 = htole32(seg->ds_addr); 1910 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1911 } else { 1912 txd->sdl0 |= htole16(RT2860_TX_LS0); 1913 txd->sdl1 = 0; 1914 } 1915 1916 /* remove from the free pool and link it into the SW Tx slot */ 1917 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1918 data->m = m; 1919 data->ni = ni; 1920 ring->data[ring->cur] = data; 1921 1922 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1923 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1924 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1925 1926 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1927 qid, txwi->wcid, nsegs, ridx)); 1928 1929 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1930 ring->queued += ntxds; 1931 if (ring->queued >= RT2860_TX_RING_COUNT) 1932 sc->qfullmsk |= 1 << qid; 1933 1934 /* kick Tx */ 1935 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1936 1937 return 0; 1938 } 1939 1940 static int 1941 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1942 { 1943 struct rt2860_softc *sc = ic->ic_softc; 1944 int error; 1945 1946 RAL_LOCK(sc); 1947 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1948 RAL_UNLOCK(sc); 1949 return (ENXIO); 1950 } 1951 error = mbufq_enqueue(&sc->sc_snd, m); 1952 if (error) { 1953 RAL_UNLOCK(sc); 1954 return (error); 1955 } 1956 rt2860_start(sc); 1957 RAL_UNLOCK(sc); 1958 1959 return (0); 1960 } 1961 1962 static void 1963 rt2860_start(struct rt2860_softc *sc) 1964 { 1965 struct ieee80211_node *ni; 1966 struct mbuf *m; 1967 1968 RAL_LOCK_ASSERT(sc); 1969 1970 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1971 return; 1972 1973 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1974 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1975 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1976 if (rt2860_tx(sc, m, ni) != 0) { 1977 if_inc_counter(ni->ni_vap->iv_ifp, 1978 IFCOUNTER_OERRORS, 1); 1979 ieee80211_free_node(ni); 1980 continue; 1981 } 1982 sc->sc_tx_timer = 5; 1983 } 1984 } 1985 1986 static void 1987 rt2860_watchdog(void *arg) 1988 { 1989 struct rt2860_softc *sc = arg; 1990 1991 RAL_LOCK_ASSERT(sc); 1992 1993 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1994 1995 if (sc->sc_invalid) /* card ejected */ 1996 return; 1997 1998 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1999 device_printf(sc->sc_dev, "device timeout\n"); 2000 rt2860_stop_locked(sc); 2001 rt2860_init_locked(sc); 2002 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2003 return; 2004 } 2005 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2006 } 2007 2008 static void 2009 rt2860_parent(struct ieee80211com *ic) 2010 { 2011 struct rt2860_softc *sc = ic->ic_softc; 2012 int startall = 0; 2013 2014 RAL_LOCK(sc); 2015 if (ic->ic_nrunning> 0) { 2016 if (!(sc->sc_flags & RT2860_RUNNING)) { 2017 rt2860_init_locked(sc); 2018 startall = 1; 2019 } else 2020 rt2860_update_promisc(ic); 2021 } else if (sc->sc_flags & RT2860_RUNNING) 2022 rt2860_stop_locked(sc); 2023 RAL_UNLOCK(sc); 2024 if (startall) 2025 ieee80211_start_all(ic); 2026 } 2027 2028 /* 2029 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2030 * We access the BBP through the 8051 microcontroller unit which means that 2031 * the microcode must be loaded first. 2032 */ 2033 void 2034 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2035 { 2036 int ntries; 2037 2038 for (ntries = 0; ntries < 100; ntries++) { 2039 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2040 break; 2041 DELAY(1); 2042 } 2043 if (ntries == 100) { 2044 device_printf(sc->sc_dev, 2045 "could not write to BBP through MCU\n"); 2046 return; 2047 } 2048 2049 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2050 RT2860_BBP_CSR_KICK | reg << 8 | val); 2051 RAL_BARRIER_WRITE(sc); 2052 2053 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2054 DELAY(1000); 2055 } 2056 2057 uint8_t 2058 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2059 { 2060 uint32_t val; 2061 int ntries; 2062 2063 for (ntries = 0; ntries < 100; ntries++) { 2064 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2065 break; 2066 DELAY(1); 2067 } 2068 if (ntries == 100) { 2069 device_printf(sc->sc_dev, 2070 "could not read from BBP through MCU\n"); 2071 return 0; 2072 } 2073 2074 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2075 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2076 RAL_BARRIER_WRITE(sc); 2077 2078 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2079 DELAY(1000); 2080 2081 for (ntries = 0; ntries < 100; ntries++) { 2082 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2083 if (!(val & RT2860_BBP_CSR_KICK)) 2084 return val & 0xff; 2085 DELAY(1); 2086 } 2087 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2088 2089 return 0; 2090 } 2091 2092 /* 2093 * Write to one of the 4 programmable 24-bit RF registers. 2094 */ 2095 static void 2096 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2097 { 2098 uint32_t tmp; 2099 int ntries; 2100 2101 for (ntries = 0; ntries < 100; ntries++) { 2102 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2103 break; 2104 DELAY(1); 2105 } 2106 if (ntries == 100) { 2107 device_printf(sc->sc_dev, "could not write to RF\n"); 2108 return; 2109 } 2110 2111 /* RF registers are 24-bit on the RT2860 */ 2112 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2113 (val & 0x3fffff) << 2 | (reg & 3); 2114 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2115 } 2116 2117 static uint8_t 2118 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2119 { 2120 uint32_t tmp; 2121 int ntries; 2122 2123 for (ntries = 0; ntries < 100; ntries++) { 2124 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2125 break; 2126 DELAY(1); 2127 } 2128 if (ntries == 100) { 2129 device_printf(sc->sc_dev, "could not read RF register\n"); 2130 return 0xff; 2131 } 2132 tmp = RT3070_RF_KICK | reg << 8; 2133 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2134 2135 for (ntries = 0; ntries < 100; ntries++) { 2136 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2137 if (!(tmp & RT3070_RF_KICK)) 2138 break; 2139 DELAY(1); 2140 } 2141 if (ntries == 100) { 2142 device_printf(sc->sc_dev, "could not read RF register\n"); 2143 return 0xff; 2144 } 2145 return tmp & 0xff; 2146 } 2147 2148 void 2149 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2150 { 2151 uint32_t tmp; 2152 int ntries; 2153 2154 for (ntries = 0; ntries < 10; ntries++) { 2155 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2156 break; 2157 DELAY(10); 2158 } 2159 if (ntries == 10) { 2160 device_printf(sc->sc_dev, "could not write to RF\n"); 2161 return; 2162 } 2163 2164 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2165 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2166 } 2167 2168 /* 2169 * Send a command to the 8051 microcontroller unit. 2170 */ 2171 int 2172 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2173 { 2174 int slot, ntries; 2175 uint32_t tmp; 2176 uint8_t cid; 2177 2178 for (ntries = 0; ntries < 100; ntries++) { 2179 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2180 break; 2181 DELAY(2); 2182 } 2183 if (ntries == 100) 2184 return EIO; 2185 2186 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2187 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2188 RAL_BARRIER_WRITE(sc); 2189 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2190 2191 if (!wait) 2192 return 0; 2193 /* wait for the command to complete */ 2194 for (ntries = 0; ntries < 200; ntries++) { 2195 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2196 /* find the command slot */ 2197 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2198 if ((tmp & 0xff) == cid) 2199 break; 2200 if (slot < 4) 2201 break; 2202 DELAY(100); 2203 } 2204 if (ntries == 200) { 2205 /* clear command and status */ 2206 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2208 return ETIMEDOUT; 2209 } 2210 /* get command status (1 means success) */ 2211 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2212 tmp = (tmp >> (slot * 8)) & 0xff; 2213 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2214 cmd, slot, tmp)); 2215 /* clear command and status */ 2216 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2217 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2218 return (tmp == 1) ? 0 : EIO; 2219 } 2220 2221 static void 2222 rt2860_enable_mrr(struct rt2860_softc *sc) 2223 { 2224 #define CCK(mcs) (mcs) 2225 #define OFDM(mcs) (1U << 3 | (mcs)) 2226 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2227 OFDM(6) << 28 | /* 54->48 */ 2228 OFDM(5) << 24 | /* 48->36 */ 2229 OFDM(4) << 20 | /* 36->24 */ 2230 OFDM(3) << 16 | /* 24->18 */ 2231 OFDM(2) << 12 | /* 18->12 */ 2232 OFDM(1) << 8 | /* 12-> 9 */ 2233 OFDM(0) << 4 | /* 9-> 6 */ 2234 OFDM(0)); /* 6-> 6 */ 2235 2236 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2237 CCK(2) << 12 | /* 11->5.5 */ 2238 CCK(1) << 8 | /* 5.5-> 2 */ 2239 CCK(0) << 4 | /* 2-> 1 */ 2240 CCK(0)); /* 1-> 1 */ 2241 #undef OFDM 2242 #undef CCK 2243 } 2244 2245 static void 2246 rt2860_set_txpreamble(struct rt2860_softc *sc) 2247 { 2248 struct ieee80211com *ic = &sc->sc_ic; 2249 uint32_t tmp; 2250 2251 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2252 tmp &= ~RT2860_CCK_SHORT_EN; 2253 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2254 tmp |= RT2860_CCK_SHORT_EN; 2255 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2256 } 2257 2258 void 2259 rt2860_set_basicrates(struct rt2860_softc *sc, 2260 const struct ieee80211_rateset *rs) 2261 { 2262 struct ieee80211com *ic = &sc->sc_ic; 2263 uint32_t mask = 0; 2264 uint8_t rate; 2265 int i; 2266 2267 for (i = 0; i < rs->rs_nrates; i++) { 2268 rate = rs->rs_rates[i]; 2269 2270 if (!(rate & IEEE80211_RATE_BASIC)) 2271 continue; 2272 2273 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2274 IEEE80211_RV(rate)); 2275 } 2276 2277 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2278 } 2279 2280 static void 2281 rt2860_scan_start(struct ieee80211com *ic) 2282 { 2283 struct rt2860_softc *sc = ic->ic_softc; 2284 uint32_t tmp; 2285 2286 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2287 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2288 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2289 RT2860_TBTT_TIMER_EN)); 2290 rt2860_set_gp_timer(sc, 0); 2291 } 2292 2293 static void 2294 rt2860_scan_end(struct ieee80211com *ic) 2295 { 2296 struct rt2860_softc *sc = ic->ic_softc; 2297 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2298 2299 if (vap->iv_state == IEEE80211_S_RUN) { 2300 rt2860_enable_tsf_sync(sc); 2301 rt2860_set_gp_timer(sc, 500); 2302 } 2303 } 2304 2305 static void 2306 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2307 struct ieee80211_channel chans[]) 2308 { 2309 struct rt2860_softc *sc = ic->ic_softc; 2310 uint8_t bands[IEEE80211_MODE_BYTES]; 2311 2312 memset(bands, 0, sizeof(bands)); 2313 setbit(bands, IEEE80211_MODE_11B); 2314 setbit(bands, IEEE80211_MODE_11G); 2315 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2316 2317 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2318 setbit(bands, IEEE80211_MODE_11A); 2319 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2320 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2321 } 2322 } 2323 2324 static void 2325 rt2860_set_channel(struct ieee80211com *ic) 2326 { 2327 struct rt2860_softc *sc = ic->ic_softc; 2328 2329 RAL_LOCK(sc); 2330 rt2860_switch_chan(sc, ic->ic_curchan); 2331 RAL_UNLOCK(sc); 2332 } 2333 2334 static void 2335 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2336 { 2337 uint32_t tmp; 2338 uint8_t agc; 2339 2340 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2341 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2342 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2343 rt2860_mcu_bbp_write(sc, 86, 0x00); 2344 2345 if (group == 0) { 2346 if (sc->ext_2ghz_lna) { 2347 rt2860_mcu_bbp_write(sc, 82, 0x62); 2348 rt2860_mcu_bbp_write(sc, 75, 0x46); 2349 } else { 2350 rt2860_mcu_bbp_write(sc, 82, 0x84); 2351 rt2860_mcu_bbp_write(sc, 75, 0x50); 2352 } 2353 } else { 2354 if (sc->ext_5ghz_lna) { 2355 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2356 rt2860_mcu_bbp_write(sc, 75, 0x46); 2357 } else { 2358 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2359 rt2860_mcu_bbp_write(sc, 75, 0x50); 2360 } 2361 } 2362 2363 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2364 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2365 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2366 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2367 2368 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2369 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2370 if (sc->nrxchains > 1) 2371 tmp |= RT2860_LNA_PE1_EN; 2372 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2373 tmp |= RT3593_LNA_PE2_EN; 2374 if (group == 0) { /* 2GHz */ 2375 tmp |= RT2860_PA_PE_G0_EN; 2376 if (sc->ntxchains > 1) 2377 tmp |= RT2860_PA_PE_G1_EN; 2378 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2379 tmp |= RT3593_PA_PE_G2_EN; 2380 } else { /* 5GHz */ 2381 tmp |= RT2860_PA_PE_A0_EN; 2382 if (sc->ntxchains > 1) 2383 tmp |= RT2860_PA_PE_A1_EN; 2384 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2385 tmp |= RT3593_PA_PE_A2_EN; 2386 } 2387 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2388 2389 if (sc->mac_ver == 0x3593) { 2390 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2391 if (sc->sc_flags & RT2860_PCIE) { 2392 tmp &= ~0x01010000; 2393 if (group == 0) 2394 tmp |= 0x00010000; 2395 } else { 2396 tmp &= ~0x00008080; 2397 if (group == 0) 2398 tmp |= 0x00000080; 2399 } 2400 tmp = (tmp & ~0x00001000) | 0x00000010; 2401 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2402 } 2403 2404 /* set initial AGC value */ 2405 if (group == 0) { /* 2GHz band */ 2406 if (sc->mac_ver >= 0x3071) 2407 agc = 0x1c + sc->lna[0] * 2; 2408 else 2409 agc = 0x2e + sc->lna[0]; 2410 } else { /* 5GHz band */ 2411 agc = 0x32 + (sc->lna[group] * 5) / 3; 2412 } 2413 rt2860_mcu_bbp_write(sc, 66, agc); 2414 2415 DELAY(1000); 2416 } 2417 2418 static void 2419 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2420 { 2421 const struct rfprog *rfprog = rt2860_rf2850; 2422 uint32_t r2, r3, r4; 2423 int8_t txpow1, txpow2; 2424 u_int i; 2425 2426 /* find the settings for this channel (we know it exists) */ 2427 for (i = 0; rfprog[i].chan != chan; i++); 2428 2429 r2 = rfprog[i].r2; 2430 if (sc->ntxchains == 1) 2431 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2432 if (sc->nrxchains == 1) 2433 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2434 else if (sc->nrxchains == 2) 2435 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2436 2437 /* use Tx power values from EEPROM */ 2438 txpow1 = sc->txpow1[i]; 2439 txpow2 = sc->txpow2[i]; 2440 if (chan > 14) { 2441 if (txpow1 >= 0) 2442 txpow1 = txpow1 << 1 | 1; 2443 else 2444 txpow1 = (7 + txpow1) << 1; 2445 if (txpow2 >= 0) 2446 txpow2 = txpow2 << 1 | 1; 2447 else 2448 txpow2 = (7 + txpow2) << 1; 2449 } 2450 r3 = rfprog[i].r3 | txpow1 << 7; 2451 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2452 2453 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2454 rt2860_rf_write(sc, RT2860_RF2, r2); 2455 rt2860_rf_write(sc, RT2860_RF3, r3); 2456 rt2860_rf_write(sc, RT2860_RF4, r4); 2457 2458 DELAY(200); 2459 2460 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2461 rt2860_rf_write(sc, RT2860_RF2, r2); 2462 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2463 rt2860_rf_write(sc, RT2860_RF4, r4); 2464 2465 DELAY(200); 2466 2467 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2468 rt2860_rf_write(sc, RT2860_RF2, r2); 2469 rt2860_rf_write(sc, RT2860_RF3, r3); 2470 rt2860_rf_write(sc, RT2860_RF4, r4); 2471 } 2472 2473 static void 2474 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2475 { 2476 int8_t txpow1, txpow2; 2477 uint8_t rf; 2478 int i; 2479 2480 /* RT3090 is 2GHz only */ 2481 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2482 2483 /* find the settings for this channel (we know it exists) */ 2484 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2485 2486 /* use Tx power values from EEPROM */ 2487 txpow1 = sc->txpow1[i]; 2488 txpow2 = sc->txpow2[i]; 2489 2490 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2491 rf = rt3090_rf_read(sc, 3); 2492 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2493 rt3090_rf_write(sc, 3, rf); 2494 rf = rt3090_rf_read(sc, 6); 2495 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2496 rt3090_rf_write(sc, 6, rf); 2497 2498 /* set Tx0 power */ 2499 rf = rt3090_rf_read(sc, 12); 2500 rf = (rf & ~0x1f) | txpow1; 2501 rt3090_rf_write(sc, 12, rf); 2502 2503 /* set Tx1 power */ 2504 rf = rt3090_rf_read(sc, 13); 2505 rf = (rf & ~0x1f) | txpow2; 2506 rt3090_rf_write(sc, 13, rf); 2507 2508 rf = rt3090_rf_read(sc, 1); 2509 rf &= ~0xfc; 2510 if (sc->ntxchains == 1) 2511 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2512 else if (sc->ntxchains == 2) 2513 rf |= RT3070_TX2_PD; 2514 if (sc->nrxchains == 1) 2515 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2516 else if (sc->nrxchains == 2) 2517 rf |= RT3070_RX2_PD; 2518 rt3090_rf_write(sc, 1, rf); 2519 2520 /* set RF offset */ 2521 rf = rt3090_rf_read(sc, 23); 2522 rf = (rf & ~0x7f) | sc->freq; 2523 rt3090_rf_write(sc, 23, rf); 2524 2525 /* program RF filter */ 2526 rf = rt3090_rf_read(sc, 24); /* Tx */ 2527 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2528 rt3090_rf_write(sc, 24, rf); 2529 rf = rt3090_rf_read(sc, 31); /* Rx */ 2530 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2531 rt3090_rf_write(sc, 31, rf); 2532 2533 /* enable RF tuning */ 2534 rf = rt3090_rf_read(sc, 7); 2535 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2536 } 2537 2538 static void 2539 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2540 { 2541 uint8_t h20mhz, rf, tmp; 2542 int8_t txpow1, txpow2; 2543 int i; 2544 2545 /* RT5390 is 2GHz only */ 2546 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2547 2548 /* find the settings for this channel (we know it exists) */ 2549 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2550 2551 /* use Tx power values from EEPROM */ 2552 txpow1 = sc->txpow1[i]; 2553 txpow2 = sc->txpow2[i]; 2554 2555 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2556 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2557 rf = rt3090_rf_read(sc, 11); 2558 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2559 rt3090_rf_write(sc, 11, rf); 2560 2561 rf = rt3090_rf_read(sc, 49); 2562 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2563 /* the valid range of the RF R49 is 0x00~0x27 */ 2564 if ((rf & 0x3f) > 0x27) 2565 rf = (rf & ~0x3f) | 0x27; 2566 rt3090_rf_write(sc, 49, rf); 2567 if (sc->mac_ver == 0x5392) { 2568 rf = rt3090_rf_read(sc, 50); 2569 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2570 /* the valid range of the RF R50 is 0x00~0x27 */ 2571 if ((rf & 0x3f) > 0x27) 2572 rf = (rf & ~0x3f) | 0x27; 2573 rt3090_rf_write(sc, 50, rf); 2574 } 2575 2576 rf = rt3090_rf_read(sc, 1); 2577 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2578 if (sc->mac_ver == 0x5392) 2579 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2580 rt3090_rf_write(sc, 1, rf); 2581 2582 rf = rt3090_rf_read(sc, 2); 2583 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2584 DELAY(1000); 2585 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2586 2587 rf = rt3090_rf_read(sc, 17); 2588 tmp = rf; 2589 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2590 rf = MIN(rf, 0x5f); 2591 if (tmp != rf) 2592 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2593 2594 if (sc->mac_ver == 0x5390) { 2595 if (chan <= 4) 2596 rf = 0x73; 2597 else if (chan >= 5 && chan <= 6) 2598 rf = 0x63; 2599 else if (chan >= 7 && chan <= 10) 2600 rf = 0x53; 2601 else 2602 rf = 43; 2603 rt3090_rf_write(sc, 55, rf); 2604 2605 if (chan == 1) 2606 rf = 0x0c; 2607 else if (chan == 2) 2608 rf = 0x0b; 2609 else if (chan == 3) 2610 rf = 0x0a; 2611 else if (chan >= 4 && chan <= 6) 2612 rf = 0x09; 2613 else if (chan >= 7 && chan <= 12) 2614 rf = 0x08; 2615 else if (chan == 13) 2616 rf = 0x07; 2617 else 2618 rf = 0x06; 2619 rt3090_rf_write(sc, 59, rf); 2620 } 2621 2622 /* Tx/Rx h20M */ 2623 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2624 rf = rt3090_rf_read(sc, 30); 2625 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2626 rt3090_rf_write(sc, 30, rf); 2627 2628 /* Rx BB filter VCM */ 2629 rf = rt3090_rf_read(sc, 30); 2630 rf = (rf & ~0x18) | 0x10; 2631 rt3090_rf_write(sc, 30, rf); 2632 2633 /* Initiate VCO calibration. */ 2634 rf = rt3090_rf_read(sc, 3); 2635 rf |= RT3593_VCOCAL; 2636 rt3090_rf_write(sc, 3, rf); 2637 } 2638 2639 static int 2640 rt3090_rf_init(struct rt2860_softc *sc) 2641 { 2642 uint32_t tmp; 2643 uint8_t rf, bbp; 2644 int i; 2645 2646 rf = rt3090_rf_read(sc, 30); 2647 /* toggle RF R30 bit 7 */ 2648 rt3090_rf_write(sc, 30, rf | 0x80); 2649 DELAY(1000); 2650 rt3090_rf_write(sc, 30, rf & ~0x80); 2651 2652 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2653 tmp &= ~0x1f000000; 2654 if (sc->patch_dac && sc->mac_rev < 0x0211) 2655 tmp |= 0x0d000000; /* 1.35V */ 2656 else 2657 tmp |= 0x01000000; /* 1.2V */ 2658 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2659 2660 /* patch LNA_PE_G1 */ 2661 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2662 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2663 2664 /* initialize RF registers to default value */ 2665 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2666 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2667 rt3090_def_rf[i].val); 2668 } 2669 2670 /* select 20MHz bandwidth */ 2671 rt3090_rf_write(sc, 31, 0x14); 2672 2673 rf = rt3090_rf_read(sc, 6); 2674 rt3090_rf_write(sc, 6, rf | 0x40); 2675 2676 if (sc->mac_ver != 0x3593) { 2677 /* calibrate filter for 20MHz bandwidth */ 2678 sc->rf24_20mhz = 0x1f; /* default value */ 2679 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2680 2681 /* select 40MHz bandwidth */ 2682 bbp = rt2860_mcu_bbp_read(sc, 4); 2683 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2684 rf = rt3090_rf_read(sc, 31); 2685 rt3090_rf_write(sc, 31, rf | 0x20); 2686 2687 /* calibrate filter for 40MHz bandwidth */ 2688 sc->rf24_40mhz = 0x2f; /* default value */ 2689 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2690 2691 /* go back to 20MHz bandwidth */ 2692 bbp = rt2860_mcu_bbp_read(sc, 4); 2693 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2694 } 2695 if (sc->mac_rev < 0x0211) 2696 rt3090_rf_write(sc, 27, 0x03); 2697 2698 tmp = RAL_READ(sc, RT3070_OPT_14); 2699 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2700 2701 if (sc->rf_rev == RT3070_RF_3020) 2702 rt3090_set_rx_antenna(sc, 0); 2703 2704 bbp = rt2860_mcu_bbp_read(sc, 138); 2705 if (sc->mac_ver == 0x3593) { 2706 if (sc->ntxchains == 1) 2707 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2708 else if (sc->ntxchains == 2) 2709 bbp |= 0x40; /* turn off DAC2 */ 2710 if (sc->nrxchains == 1) 2711 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2712 else if (sc->nrxchains == 2) 2713 bbp &= ~0x04; /* turn off ADC2 */ 2714 } else { 2715 if (sc->ntxchains == 1) 2716 bbp |= 0x20; /* turn off DAC1 */ 2717 if (sc->nrxchains == 1) 2718 bbp &= ~0x02; /* turn off ADC1 */ 2719 } 2720 rt2860_mcu_bbp_write(sc, 138, bbp); 2721 2722 rf = rt3090_rf_read(sc, 1); 2723 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2724 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2725 rt3090_rf_write(sc, 1, rf); 2726 2727 rf = rt3090_rf_read(sc, 15); 2728 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2729 2730 rf = rt3090_rf_read(sc, 17); 2731 rf &= ~RT3070_TX_LO1; 2732 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2733 rf |= 0x20; /* fix for long range Rx issue */ 2734 if (sc->txmixgain_2ghz >= 2) 2735 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2736 rt3090_rf_write(sc, 17, rf); 2737 2738 rf = rt3090_rf_read(sc, 20); 2739 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2740 2741 rf = rt3090_rf_read(sc, 21); 2742 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2743 2744 return (0); 2745 } 2746 2747 static void 2748 rt5390_rf_init(struct rt2860_softc *sc) 2749 { 2750 uint8_t rf, bbp; 2751 int i; 2752 2753 rf = rt3090_rf_read(sc, 2); 2754 /* Toggle RF R2 bit 7. */ 2755 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2756 DELAY(1000); 2757 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2758 2759 /* Initialize RF registers to default value. */ 2760 if (sc->mac_ver == 0x5392) { 2761 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2762 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2763 rt5392_def_rf[i].val); 2764 } 2765 } else { 2766 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2767 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2768 rt5390_def_rf[i].val); 2769 } 2770 } 2771 2772 sc->rf24_20mhz = 0x1f; 2773 sc->rf24_40mhz = 0x2f; 2774 2775 if (sc->mac_rev < 0x0211) 2776 rt3090_rf_write(sc, 27, 0x03); 2777 2778 /* Set led open drain enable. */ 2779 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2780 2781 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2782 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2783 2784 if (sc->mac_ver == 0x5390) 2785 rt3090_set_rx_antenna(sc, 0); 2786 2787 /* Patch RSSI inaccurate issue. */ 2788 rt2860_mcu_bbp_write(sc, 79, 0x13); 2789 rt2860_mcu_bbp_write(sc, 80, 0x05); 2790 rt2860_mcu_bbp_write(sc, 81, 0x33); 2791 2792 /* Enable DC filter. */ 2793 if (sc->mac_rev >= 0x0211) 2794 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2795 2796 bbp = rt2860_mcu_bbp_read(sc, 138); 2797 if (sc->ntxchains == 1) 2798 bbp |= 0x20; /* Turn off DAC1. */ 2799 if (sc->nrxchains == 1) 2800 bbp &= ~0x02; /* Turn off ADC1. */ 2801 rt2860_mcu_bbp_write(sc, 138, bbp); 2802 2803 /* Enable RX LO1 and LO2. */ 2804 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2805 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2806 2807 /* Avoid data lost and CRC error. */ 2808 rt2860_mcu_bbp_write(sc, 4, 2809 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2810 2811 rf = rt3090_rf_read(sc, 30); 2812 rf = (rf & ~0x18) | 0x10; 2813 rt3090_rf_write(sc, 30, rf); 2814 } 2815 2816 static void 2817 rt3090_rf_wakeup(struct rt2860_softc *sc) 2818 { 2819 uint32_t tmp; 2820 uint8_t rf; 2821 2822 if (sc->mac_ver == 0x3593) { 2823 /* enable VCO */ 2824 rf = rt3090_rf_read(sc, 1); 2825 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2826 2827 /* initiate VCO calibration */ 2828 rf = rt3090_rf_read(sc, 3); 2829 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2830 2831 /* enable VCO bias current control */ 2832 rf = rt3090_rf_read(sc, 6); 2833 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2834 2835 /* initiate res calibration */ 2836 rf = rt3090_rf_read(sc, 2); 2837 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2838 2839 /* set reference current control to 0.33 mA */ 2840 rf = rt3090_rf_read(sc, 22); 2841 rf &= ~RT3593_CP_IC_MASK; 2842 rf |= 1 << RT3593_CP_IC_SHIFT; 2843 rt3090_rf_write(sc, 22, rf); 2844 2845 /* enable RX CTB */ 2846 rf = rt3090_rf_read(sc, 46); 2847 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2848 2849 rf = rt3090_rf_read(sc, 20); 2850 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2851 rt3090_rf_write(sc, 20, rf); 2852 } else { 2853 /* enable RF block */ 2854 rf = rt3090_rf_read(sc, 1); 2855 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2856 2857 /* enable VCO bias current control */ 2858 rf = rt3090_rf_read(sc, 7); 2859 rt3090_rf_write(sc, 7, rf | 0x30); 2860 2861 rf = rt3090_rf_read(sc, 9); 2862 rt3090_rf_write(sc, 9, rf | 0x0e); 2863 2864 /* enable RX CTB */ 2865 rf = rt3090_rf_read(sc, 21); 2866 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2867 2868 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2869 rf = rt3090_rf_read(sc, 27); 2870 rf &= ~0x77; 2871 if (sc->mac_rev < 0x0211) 2872 rf |= 0x03; 2873 rt3090_rf_write(sc, 27, rf); 2874 } 2875 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2876 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2877 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2878 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2879 } 2880 } 2881 2882 static void 2883 rt5390_rf_wakeup(struct rt2860_softc *sc) 2884 { 2885 uint32_t tmp; 2886 uint8_t rf; 2887 2888 rf = rt3090_rf_read(sc, 1); 2889 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2890 RT3070_TX0_PD; 2891 if (sc->mac_ver == 0x5392) 2892 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2893 rt3090_rf_write(sc, 1, rf); 2894 2895 rf = rt3090_rf_read(sc, 6); 2896 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2897 if (sc->mac_ver == 0x5390) 2898 rf &= ~RT3593_VCO_IC; 2899 rt3090_rf_write(sc, 6, rf); 2900 2901 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2902 2903 rf = rt3090_rf_read(sc, 22); 2904 rf = (rf & ~0xe0) | 0x20; 2905 rt3090_rf_write(sc, 22, rf); 2906 2907 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2908 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2909 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2910 2911 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2912 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2913 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2914 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2915 } 2916 } 2917 2918 static int 2919 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2920 uint8_t *val) 2921 { 2922 uint8_t rf22, rf24; 2923 uint8_t bbp55_pb, bbp55_sb, delta; 2924 int ntries; 2925 2926 /* program filter */ 2927 rf24 = rt3090_rf_read(sc, 24); 2928 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2929 rt3090_rf_write(sc, 24, rf24); 2930 2931 /* enable baseband loopback mode */ 2932 rf22 = rt3090_rf_read(sc, 22); 2933 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2934 2935 /* set power and frequency of passband test tone */ 2936 rt2860_mcu_bbp_write(sc, 24, 0x00); 2937 for (ntries = 0; ntries < 100; ntries++) { 2938 /* transmit test tone */ 2939 rt2860_mcu_bbp_write(sc, 25, 0x90); 2940 DELAY(1000); 2941 /* read received power */ 2942 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2943 if (bbp55_pb != 0) 2944 break; 2945 } 2946 if (ntries == 100) 2947 return (ETIMEDOUT); 2948 2949 /* set power and frequency of stopband test tone */ 2950 rt2860_mcu_bbp_write(sc, 24, 0x06); 2951 for (ntries = 0; ntries < 100; ntries++) { 2952 /* transmit test tone */ 2953 rt2860_mcu_bbp_write(sc, 25, 0x90); 2954 DELAY(1000); 2955 /* read received power */ 2956 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2957 2958 delta = bbp55_pb - bbp55_sb; 2959 if (delta > target) 2960 break; 2961 2962 /* reprogram filter */ 2963 rf24++; 2964 rt3090_rf_write(sc, 24, rf24); 2965 } 2966 if (ntries < 100) { 2967 if (rf24 != init) 2968 rf24--; /* backtrack */ 2969 *val = rf24; 2970 rt3090_rf_write(sc, 24, rf24); 2971 } 2972 2973 /* restore initial state */ 2974 rt2860_mcu_bbp_write(sc, 24, 0x00); 2975 2976 /* disable baseband loopback mode */ 2977 rf22 = rt3090_rf_read(sc, 22); 2978 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2979 2980 return (0); 2981 } 2982 2983 static void 2984 rt3090_rf_setup(struct rt2860_softc *sc) 2985 { 2986 uint8_t bbp; 2987 int i; 2988 2989 if (sc->mac_rev >= 0x0211) { 2990 /* enable DC filter */ 2991 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2992 2993 /* improve power consumption */ 2994 bbp = rt2860_mcu_bbp_read(sc, 31); 2995 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2996 } 2997 2998 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2999 if (sc->mac_rev < 0x0211) { 3000 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 3001 sc->patch_dac ? 0x2c : 0x0f); 3002 } else 3003 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3004 3005 /* initialize RF registers from ROM */ 3006 if (sc->mac_ver < 0x5390) { 3007 for (i = 0; i < 10; i++) { 3008 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3009 continue; 3010 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3011 } 3012 } 3013 } 3014 3015 static void 3016 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3017 { 3018 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3019 which | (sc->leds & 0x7f), 0); 3020 } 3021 3022 /* 3023 * Hardware has a general-purpose programmable timer interrupt that can 3024 * periodically raise MAC_INT_4. 3025 */ 3026 static void 3027 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3028 { 3029 uint32_t tmp; 3030 3031 /* disable GP timer before reprogramming it */ 3032 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3033 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3034 3035 if (ms == 0) 3036 return; 3037 3038 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3039 ms *= 16; /* Unit: 64us */ 3040 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3041 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3042 3043 /* enable GP timer */ 3044 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3045 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3046 } 3047 3048 static void 3049 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3050 { 3051 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3052 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3053 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3054 bssid[4] | bssid[5] << 8); 3055 } 3056 3057 static void 3058 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3059 { 3060 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3061 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3062 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3063 addr[4] | addr[5] << 8 | 0xff << 16); 3064 } 3065 3066 static void 3067 rt2860_updateslot(struct ieee80211com *ic) 3068 { 3069 struct rt2860_softc *sc = ic->ic_softc; 3070 uint32_t tmp; 3071 3072 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3073 tmp &= ~0xff; 3074 tmp |= IEEE80211_GET_SLOTTIME(ic); 3075 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3076 } 3077 3078 static void 3079 rt2860_updateprot(struct rt2860_softc *sc) 3080 { 3081 struct ieee80211com *ic = &sc->sc_ic; 3082 uint32_t tmp; 3083 3084 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3085 /* setup protection frame rate (MCS code) */ 3086 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3087 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3088 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3089 3090 /* CCK frames don't require protection */ 3091 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3092 3093 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3094 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3095 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3096 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3097 tmp |= RT2860_PROT_CTRL_CTS; 3098 } 3099 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3100 } 3101 3102 static void 3103 rt2860_update_promisc(struct ieee80211com *ic) 3104 { 3105 struct rt2860_softc *sc = ic->ic_softc; 3106 uint32_t tmp; 3107 3108 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3109 tmp &= ~RT2860_DROP_NOT_MYBSS; 3110 if (ic->ic_promisc == 0) 3111 tmp |= RT2860_DROP_NOT_MYBSS; 3112 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3113 } 3114 3115 static int 3116 rt2860_updateedca(struct ieee80211com *ic) 3117 { 3118 struct rt2860_softc *sc = ic->ic_softc; 3119 struct chanAccParams chp; 3120 const struct wmeParams *wmep; 3121 int aci; 3122 3123 ieee80211_wme_ic_getparams(ic, &chp); 3124 3125 wmep = chp.cap_wmeParams; 3126 3127 /* update MAC TX configuration registers */ 3128 for (aci = 0; aci < WME_NUM_AC; aci++) { 3129 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3130 wmep[aci].wmep_logcwmax << 16 | 3131 wmep[aci].wmep_logcwmin << 12 | 3132 wmep[aci].wmep_aifsn << 8 | 3133 wmep[aci].wmep_txopLimit); 3134 } 3135 3136 /* update SCH/DMA registers too */ 3137 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3138 wmep[WME_AC_VO].wmep_aifsn << 12 | 3139 wmep[WME_AC_VI].wmep_aifsn << 8 | 3140 wmep[WME_AC_BK].wmep_aifsn << 4 | 3141 wmep[WME_AC_BE].wmep_aifsn); 3142 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3143 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3144 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3145 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3146 wmep[WME_AC_BE].wmep_logcwmin); 3147 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3148 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3149 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3150 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3151 wmep[WME_AC_BE].wmep_logcwmax); 3152 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3153 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3154 wmep[WME_AC_BE].wmep_txopLimit); 3155 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3156 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3157 wmep[WME_AC_VI].wmep_txopLimit); 3158 3159 return 0; 3160 } 3161 3162 #ifdef HW_CRYPTO 3163 static int 3164 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3165 struct ieee80211_key *k) 3166 { 3167 struct rt2860_softc *sc = ic->ic_softc; 3168 bus_size_t base; 3169 uint32_t attr; 3170 uint8_t mode, wcid, iv[8]; 3171 3172 /* defer setting of WEP keys until interface is brought up */ 3173 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3174 (IFF_UP | IFF_RUNNING)) 3175 return 0; 3176 3177 /* map net80211 cipher to RT2860 security mode */ 3178 switch (k->k_cipher) { 3179 case IEEE80211_CIPHER_WEP40: 3180 mode = RT2860_MODE_WEP40; 3181 break; 3182 case IEEE80211_CIPHER_WEP104: 3183 mode = RT2860_MODE_WEP104; 3184 break; 3185 case IEEE80211_CIPHER_TKIP: 3186 mode = RT2860_MODE_TKIP; 3187 break; 3188 case IEEE80211_CIPHER_CCMP: 3189 mode = RT2860_MODE_AES_CCMP; 3190 break; 3191 default: 3192 return EINVAL; 3193 } 3194 3195 if (k->k_flags & IEEE80211_KEY_GROUP) { 3196 wcid = 0; /* NB: update WCID0 for group keys */ 3197 base = RT2860_SKEY(0, k->k_id); 3198 } else { 3199 wcid = ((struct rt2860_node *)ni)->wcid; 3200 base = RT2860_PKEY(wcid); 3201 } 3202 3203 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3204 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3205 #ifndef IEEE80211_STA_ONLY 3206 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3207 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3208 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3209 } else 3210 #endif 3211 { 3212 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3213 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3214 } 3215 } else 3216 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3217 3218 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3219 (k->k_flags & IEEE80211_KEY_TX)) { 3220 /* set initial packet number in IV+EIV */ 3221 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3222 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3223 uint32_t val = arc4random(); 3224 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3225 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3226 val += 0x000100; 3227 iv[0] = val; 3228 iv[1] = val >> 8; 3229 iv[2] = val >> 16; 3230 iv[3] = k->k_id << 6; 3231 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3232 } else { 3233 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3234 iv[0] = k->k_tsc >> 8; 3235 iv[1] = (iv[0] | 0x20) & 0x7f; 3236 iv[2] = k->k_tsc; 3237 } else /* CCMP */ { 3238 iv[0] = k->k_tsc; 3239 iv[1] = k->k_tsc >> 8; 3240 iv[2] = 0; 3241 } 3242 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3243 iv[4] = k->k_tsc >> 16; 3244 iv[5] = k->k_tsc >> 24; 3245 iv[6] = k->k_tsc >> 32; 3246 iv[7] = k->k_tsc >> 40; 3247 } 3248 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3249 } 3250 3251 if (k->k_flags & IEEE80211_KEY_GROUP) { 3252 /* install group key */ 3253 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3254 attr &= ~(0xf << (k->k_id * 4)); 3255 attr |= mode << (k->k_id * 4); 3256 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3257 } else { 3258 /* install pairwise key */ 3259 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3260 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3261 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3262 } 3263 return 0; 3264 } 3265 3266 static void 3267 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3268 struct ieee80211_key *k) 3269 { 3270 struct rt2860_softc *sc = ic->ic_softc; 3271 uint32_t attr; 3272 uint8_t wcid; 3273 3274 if (k->k_flags & IEEE80211_KEY_GROUP) { 3275 /* remove group key */ 3276 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3277 attr &= ~(0xf << (k->k_id * 4)); 3278 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3279 3280 } else { 3281 /* remove pairwise key */ 3282 wcid = ((struct rt2860_node *)ni)->wcid; 3283 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3284 attr &= ~0xf; 3285 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3286 } 3287 } 3288 #endif 3289 3290 static int8_t 3291 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3292 { 3293 struct ieee80211com *ic = &sc->sc_ic; 3294 struct ieee80211_channel *c = ic->ic_curchan; 3295 int delta; 3296 3297 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3298 u_int chan = ieee80211_chan2ieee(ic, c); 3299 delta = sc->rssi_5ghz[rxchain]; 3300 3301 /* determine channel group */ 3302 if (chan <= 64) 3303 delta -= sc->lna[1]; 3304 else if (chan <= 128) 3305 delta -= sc->lna[2]; 3306 else 3307 delta -= sc->lna[3]; 3308 } else 3309 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3310 3311 return -12 - delta - rssi; 3312 } 3313 3314 /* 3315 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3316 * Used to adjust per-rate Tx power registers. 3317 */ 3318 static __inline uint32_t 3319 b4inc(uint32_t b32, int8_t delta) 3320 { 3321 int8_t i, b4; 3322 3323 for (i = 0; i < 8; i++) { 3324 b4 = b32 & 0xf; 3325 b4 += delta; 3326 if (b4 < 0) 3327 b4 = 0; 3328 else if (b4 > 0xf) 3329 b4 = 0xf; 3330 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3331 } 3332 return b32; 3333 } 3334 3335 static const char * 3336 rt2860_get_rf(uint16_t rev) 3337 { 3338 switch (rev) { 3339 case RT2860_RF_2820: return "RT2820"; 3340 case RT2860_RF_2850: return "RT2850"; 3341 case RT2860_RF_2720: return "RT2720"; 3342 case RT2860_RF_2750: return "RT2750"; 3343 case RT3070_RF_3020: return "RT3020"; 3344 case RT3070_RF_2020: return "RT2020"; 3345 case RT3070_RF_3021: return "RT3021"; 3346 case RT3070_RF_3022: return "RT3022"; 3347 case RT3070_RF_3052: return "RT3052"; 3348 case RT3070_RF_3320: return "RT3320"; 3349 case RT3070_RF_3053: return "RT3053"; 3350 case RT5390_RF_5360: return "RT5360"; 3351 case RT5390_RF_5390: return "RT5390"; 3352 default: return "unknown"; 3353 } 3354 } 3355 3356 static int 3357 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3358 { 3359 int8_t delta_2ghz, delta_5ghz; 3360 uint32_t tmp; 3361 uint16_t val; 3362 int ridx, ant, i; 3363 3364 /* check whether the ROM is eFUSE ROM or EEPROM */ 3365 sc->sc_srom_read = rt2860_eeprom_read_2; 3366 if (sc->mac_ver >= 0x3071) { 3367 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3368 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3369 if (tmp & RT3070_SEL_EFUSE) 3370 sc->sc_srom_read = rt3090_efuse_read_2; 3371 } 3372 3373 #ifdef RAL_DEBUG 3374 /* read EEPROM version */ 3375 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3376 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3377 #endif 3378 3379 /* read MAC address */ 3380 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3381 macaddr[0] = val & 0xff; 3382 macaddr[1] = val >> 8; 3383 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3384 macaddr[2] = val & 0xff; 3385 macaddr[3] = val >> 8; 3386 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3387 macaddr[4] = val & 0xff; 3388 macaddr[5] = val >> 8; 3389 3390 #ifdef RAL_DEBUG 3391 /* read country code */ 3392 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3393 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3394 #endif 3395 3396 /* read vendor BBP settings */ 3397 for (i = 0; i < 8; i++) { 3398 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3399 sc->bbp[i].val = val & 0xff; 3400 sc->bbp[i].reg = val >> 8; 3401 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3402 } 3403 if (sc->mac_ver >= 0x3071) { 3404 /* read vendor RF settings */ 3405 for (i = 0; i < 10; i++) { 3406 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3407 sc->rf[i].val = val & 0xff; 3408 sc->rf[i].reg = val >> 8; 3409 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3410 sc->rf[i].val)); 3411 } 3412 } 3413 3414 /* read RF frequency offset from EEPROM */ 3415 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3416 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3417 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3418 if ((val >> 8) != 0xff) { 3419 /* read LEDs operating mode */ 3420 sc->leds = val >> 8; 3421 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3422 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3423 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3424 } else { 3425 /* broken EEPROM, use default settings */ 3426 sc->leds = 0x01; 3427 sc->led[0] = 0x5555; 3428 sc->led[1] = 0x2221; 3429 sc->led[2] = 0xa9f8; 3430 } 3431 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3432 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3433 3434 /* read RF information */ 3435 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3436 if (sc->mac_ver >= 0x5390) 3437 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3438 else 3439 sc->rf_rev = (val >> 8) & 0xf; 3440 sc->ntxchains = (val >> 4) & 0xf; 3441 sc->nrxchains = val & 0xf; 3442 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3443 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3444 3445 /* check if RF supports automatic Tx access gain control */ 3446 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3447 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3448 /* check if driver should patch the DAC issue */ 3449 if ((val >> 8) != 0xff) 3450 sc->patch_dac = (val >> 15) & 1; 3451 if ((val & 0xff) != 0xff) { 3452 sc->ext_5ghz_lna = (val >> 3) & 1; 3453 sc->ext_2ghz_lna = (val >> 2) & 1; 3454 /* check if RF supports automatic Tx access gain control */ 3455 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3456 /* check if we have a hardware radio switch */ 3457 sc->rfswitch = val & 1; 3458 } 3459 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3460 /* read PCIe power save level */ 3461 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3462 if ((val & 0xff) != 0xff) { 3463 sc->pslevel = val & 0x3; 3464 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3465 if ((val & 0xff80) != 0x9280) 3466 sc->pslevel = MIN(sc->pslevel, 1); 3467 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3468 } 3469 } 3470 3471 /* read power settings for 2GHz channels */ 3472 for (i = 0; i < 14; i += 2) { 3473 val = rt2860_srom_read(sc, 3474 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3475 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3476 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3477 3478 if (sc->mac_ver != 0x5390) { 3479 val = rt2860_srom_read(sc, 3480 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3481 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3482 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3483 } 3484 } 3485 /* fix broken Tx power entries */ 3486 for (i = 0; i < 14; i++) { 3487 if (sc->txpow1[i] < 0 || 3488 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3489 sc->txpow1[i] = 5; 3490 if (sc->mac_ver != 0x5390) { 3491 if (sc->txpow2[i] < 0 || 3492 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3493 sc->txpow2[i] = 5; 3494 } 3495 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3496 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3497 } 3498 /* read power settings for 5GHz channels */ 3499 for (i = 0; i < 40; i += 2) { 3500 val = rt2860_srom_read(sc, 3501 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3502 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3503 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3504 3505 val = rt2860_srom_read(sc, 3506 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3507 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3508 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3509 } 3510 /* fix broken Tx power entries */ 3511 for (i = 0; i < 40; i++) { 3512 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3513 sc->txpow1[14 + i] = 5; 3514 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3515 sc->txpow2[14 + i] = 5; 3516 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3517 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3518 sc->txpow2[14 + i])); 3519 } 3520 3521 /* read Tx power compensation for each Tx rate */ 3522 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3523 delta_2ghz = delta_5ghz = 0; 3524 if ((val & 0xff) != 0xff && (val & 0x80)) { 3525 delta_2ghz = val & 0xf; 3526 if (!(val & 0x40)) /* negative number */ 3527 delta_2ghz = -delta_2ghz; 3528 } 3529 val >>= 8; 3530 if ((val & 0xff) != 0xff && (val & 0x80)) { 3531 delta_5ghz = val & 0xf; 3532 if (!(val & 0x40)) /* negative number */ 3533 delta_5ghz = -delta_5ghz; 3534 } 3535 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3536 delta_2ghz, delta_5ghz)); 3537 3538 for (ridx = 0; ridx < 5; ridx++) { 3539 uint32_t reg; 3540 3541 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3542 reg = val; 3543 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3544 reg |= (uint32_t)val << 16; 3545 3546 sc->txpow20mhz[ridx] = reg; 3547 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3548 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3549 3550 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3551 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3552 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3553 } 3554 3555 /* read factory-calibrated samples for temperature compensation */ 3556 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3557 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3558 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3559 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3560 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3561 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3562 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3563 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3564 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3565 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3566 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3567 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3568 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3569 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3570 sc->step_2ghz = val >> 8; 3571 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3572 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3573 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3574 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3575 sc->tssi_2ghz[8], sc->step_2ghz)); 3576 /* check that ref value is correct, otherwise disable calibration */ 3577 if (sc->tssi_2ghz[4] == 0xff) 3578 sc->calib_2ghz = 0; 3579 3580 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3581 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3582 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3583 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3584 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3585 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3586 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3587 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3588 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3589 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3590 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3591 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3592 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3593 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3594 sc->step_5ghz = val >> 8; 3595 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3596 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3597 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3598 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3599 sc->tssi_5ghz[8], sc->step_5ghz)); 3600 /* check that ref value is correct, otherwise disable calibration */ 3601 if (sc->tssi_5ghz[4] == 0xff) 3602 sc->calib_5ghz = 0; 3603 3604 /* read RSSI offsets and LNA gains from EEPROM */ 3605 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3606 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3607 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3608 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3609 if (sc->mac_ver >= 0x3071) { 3610 /* 3611 * On RT3090 chips (limited to 2 Rx chains), this ROM 3612 * field contains the Tx mixer gain for the 2GHz band. 3613 */ 3614 if ((val & 0xff) != 0xff) 3615 sc->txmixgain_2ghz = val & 0x7; 3616 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3617 } else 3618 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3619 sc->lna[2] = val >> 8; /* channel group 2 */ 3620 3621 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3622 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3623 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3624 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3625 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3626 sc->lna[3] = val >> 8; /* channel group 3 */ 3627 3628 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3629 if (sc->mac_ver >= 0x3071) 3630 sc->lna[0] = RT3090_DEF_LNA; 3631 else /* channel group 0 */ 3632 sc->lna[0] = val & 0xff; 3633 sc->lna[1] = val >> 8; /* channel group 1 */ 3634 3635 /* fix broken 5GHz LNA entries */ 3636 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3637 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3638 sc->lna[2] = sc->lna[1]; 3639 } 3640 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3641 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3642 sc->lna[3] = sc->lna[1]; 3643 } 3644 3645 /* fix broken RSSI offset entries */ 3646 for (ant = 0; ant < 3; ant++) { 3647 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3648 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3649 ant + 1, sc->rssi_2ghz[ant])); 3650 sc->rssi_2ghz[ant] = 0; 3651 } 3652 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3653 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3654 ant + 1, sc->rssi_5ghz[ant])); 3655 sc->rssi_5ghz[ant] = 0; 3656 } 3657 } 3658 3659 return 0; 3660 } 3661 3662 static int 3663 rt2860_bbp_init(struct rt2860_softc *sc) 3664 { 3665 int i, ntries; 3666 3667 /* wait for BBP to wake up */ 3668 for (ntries = 0; ntries < 20; ntries++) { 3669 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3670 if (bbp0 != 0 && bbp0 != 0xff) 3671 break; 3672 } 3673 if (ntries == 20) { 3674 device_printf(sc->sc_dev, 3675 "timeout waiting for BBP to wake up\n"); 3676 return (ETIMEDOUT); 3677 } 3678 3679 /* initialize BBP registers to default values */ 3680 if (sc->mac_ver >= 0x5390) 3681 rt5390_bbp_init(sc); 3682 else { 3683 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3684 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3685 rt2860_def_bbp[i].val); 3686 } 3687 } 3688 3689 /* fix BBP84 for RT2860E */ 3690 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3691 rt2860_mcu_bbp_write(sc, 84, 0x19); 3692 3693 if (sc->mac_ver >= 0x3071) { 3694 rt2860_mcu_bbp_write(sc, 79, 0x13); 3695 rt2860_mcu_bbp_write(sc, 80, 0x05); 3696 rt2860_mcu_bbp_write(sc, 81, 0x33); 3697 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3698 rt2860_mcu_bbp_write(sc, 69, 0x16); 3699 rt2860_mcu_bbp_write(sc, 73, 0x12); 3700 } 3701 3702 return 0; 3703 } 3704 3705 static void 3706 rt5390_bbp_init(struct rt2860_softc *sc) 3707 { 3708 uint8_t bbp; 3709 int i; 3710 3711 /* Apply maximum likelihood detection for 2 stream case. */ 3712 if (sc->nrxchains > 1) { 3713 bbp = rt2860_mcu_bbp_read(sc, 105); 3714 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3715 } 3716 3717 /* Avoid data lost and CRC error. */ 3718 bbp = rt2860_mcu_bbp_read(sc, 4); 3719 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3720 3721 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3722 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3723 rt5390_def_bbp[i].val); 3724 } 3725 3726 if (sc->mac_ver == 0x5392) { 3727 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3728 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3729 rt2860_mcu_bbp_write(sc, 98, 0x12); 3730 rt2860_mcu_bbp_write(sc, 106, 0x05); 3731 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3732 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3733 } 3734 3735 bbp = rt2860_mcu_bbp_read(sc, 152); 3736 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3737 3738 /* Disable hardware antenna diversity. */ 3739 if (sc->mac_ver == 0x5390) 3740 rt2860_mcu_bbp_write(sc, 154, 0); 3741 } 3742 3743 static int 3744 rt2860_txrx_enable(struct rt2860_softc *sc) 3745 { 3746 struct ieee80211com *ic = &sc->sc_ic; 3747 uint32_t tmp; 3748 int ntries; 3749 3750 /* enable Tx/Rx DMA engine */ 3751 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3752 RAL_BARRIER_READ_WRITE(sc); 3753 for (ntries = 0; ntries < 200; ntries++) { 3754 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3755 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3756 break; 3757 DELAY(1000); 3758 } 3759 if (ntries == 200) { 3760 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3761 return ETIMEDOUT; 3762 } 3763 3764 DELAY(50); 3765 3766 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3767 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3768 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3769 3770 /* set Rx filter */ 3771 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3772 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3773 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3774 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3775 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3776 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3777 if (ic->ic_opmode == IEEE80211_M_STA) 3778 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3779 } 3780 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3781 3782 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3783 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3784 3785 return 0; 3786 } 3787 3788 static void 3789 rt2860_init(void *arg) 3790 { 3791 struct rt2860_softc *sc = arg; 3792 struct ieee80211com *ic = &sc->sc_ic; 3793 3794 RAL_LOCK(sc); 3795 rt2860_init_locked(sc); 3796 RAL_UNLOCK(sc); 3797 3798 if (sc->sc_flags & RT2860_RUNNING) 3799 ieee80211_start_all(ic); 3800 } 3801 3802 static void 3803 rt2860_init_locked(struct rt2860_softc *sc) 3804 { 3805 struct ieee80211com *ic = &sc->sc_ic; 3806 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3807 uint32_t tmp; 3808 uint8_t bbp1, bbp3; 3809 int i, qid, ridx, ntries, error; 3810 3811 RAL_LOCK_ASSERT(sc); 3812 3813 if (sc->rfswitch) { 3814 /* hardware has a radio switch on GPIO pin 2 */ 3815 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3816 device_printf(sc->sc_dev, 3817 "radio is disabled by hardware switch\n"); 3818 #ifdef notyet 3819 rt2860_stop_locked(sc); 3820 return; 3821 #endif 3822 } 3823 } 3824 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3825 3826 /* disable DMA */ 3827 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3828 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3829 RT2860_TX_DMA_EN); 3830 tmp |= RT2860_TX_WB_DDONE; 3831 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3832 3833 /* reset DMA indexes */ 3834 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3835 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3836 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3837 3838 /* PBF hardware reset */ 3839 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3840 RAL_BARRIER_WRITE(sc); 3841 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3842 3843 if ((error = rt2860_load_microcode(sc)) != 0) { 3844 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3845 rt2860_stop_locked(sc); 3846 return; 3847 } 3848 3849 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3850 3851 /* init Tx power for all Tx rates (from EEPROM) */ 3852 for (ridx = 0; ridx < 5; ridx++) { 3853 if (sc->txpow20mhz[ridx] == 0xffffffff) 3854 continue; 3855 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3856 } 3857 3858 for (ntries = 0; ntries < 100; ntries++) { 3859 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3860 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3861 break; 3862 DELAY(1000); 3863 } 3864 if (ntries == 100) { 3865 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3866 rt2860_stop_locked(sc); 3867 return; 3868 } 3869 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3870 RT2860_TX_DMA_EN); 3871 tmp |= RT2860_TX_WB_DDONE; 3872 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3873 3874 /* reset Rx ring and all 6 Tx rings */ 3875 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3876 3877 /* PBF hardware reset */ 3878 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3879 RAL_BARRIER_WRITE(sc); 3880 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3881 3882 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3883 3884 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3885 RAL_BARRIER_WRITE(sc); 3886 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3887 3888 for (i = 0; i < nitems(rt2860_def_mac); i++) 3889 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3890 if (sc->mac_ver >= 0x5390) 3891 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3892 else if (sc->mac_ver >= 0x3071) { 3893 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3894 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3895 4 << RT2860_DLY_PAPE_EN_SHIFT); 3896 } 3897 3898 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3899 sc->sc_flags |= RT2860_PCIE; 3900 /* PCIe has different clock cycle count than PCI */ 3901 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3902 tmp = (tmp & ~0xff) | 0x7d; 3903 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3904 } 3905 3906 /* wait while MAC is busy */ 3907 for (ntries = 0; ntries < 100; ntries++) { 3908 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3909 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3910 break; 3911 DELAY(1000); 3912 } 3913 if (ntries == 100) { 3914 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3915 rt2860_stop_locked(sc); 3916 return; 3917 } 3918 3919 /* clear Host to MCU mailbox */ 3920 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3921 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3922 3923 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3924 DELAY(1000); 3925 3926 if ((error = rt2860_bbp_init(sc)) != 0) { 3927 rt2860_stop_locked(sc); 3928 return; 3929 } 3930 3931 /* clear RX WCID search table */ 3932 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3933 /* clear pairwise key table */ 3934 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3935 /* clear IV/EIV table */ 3936 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3937 /* clear WCID attribute table */ 3938 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3939 /* clear shared key table */ 3940 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3941 /* clear shared key mode */ 3942 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3943 3944 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3945 for (qid = 0; qid < 6; qid++) { 3946 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3947 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3948 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3949 } 3950 3951 /* init Rx ring */ 3952 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3953 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3954 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3955 3956 /* setup maximum buffer sizes */ 3957 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3958 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3959 3960 for (ntries = 0; ntries < 100; ntries++) { 3961 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3962 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3963 break; 3964 DELAY(1000); 3965 } 3966 if (ntries == 100) { 3967 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3968 rt2860_stop_locked(sc); 3969 return; 3970 } 3971 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3972 RT2860_TX_DMA_EN); 3973 tmp |= RT2860_TX_WB_DDONE; 3974 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3975 3976 /* disable interrupts mitigation */ 3977 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3978 3979 /* write vendor-specific BBP values (from EEPROM) */ 3980 for (i = 0; i < 8; i++) { 3981 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3982 continue; 3983 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3984 } 3985 3986 /* select Main antenna for 1T1R devices */ 3987 if (sc->rf_rev == RT3070_RF_2020 || 3988 sc->rf_rev == RT3070_RF_3020 || 3989 sc->rf_rev == RT3070_RF_3320 || 3990 sc->mac_ver == 0x5390) 3991 rt3090_set_rx_antenna(sc, 0); 3992 3993 /* send LEDs operating mode to microcontroller */ 3994 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3995 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3996 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3997 3998 if (sc->mac_ver >= 0x5390) 3999 rt5390_rf_init(sc); 4000 else if (sc->mac_ver >= 0x3071) { 4001 if ((error = rt3090_rf_init(sc)) != 0) { 4002 rt2860_stop_locked(sc); 4003 return; 4004 } 4005 } 4006 4007 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4008 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4009 4010 if (sc->mac_ver >= 0x5390) 4011 rt5390_rf_wakeup(sc); 4012 else if (sc->mac_ver >= 0x3071) 4013 rt3090_rf_wakeup(sc); 4014 4015 /* disable non-existing Rx chains */ 4016 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4017 bbp3 &= ~(1 << 3 | 1 << 4); 4018 if (sc->nrxchains == 2) 4019 bbp3 |= 1 << 3; 4020 else if (sc->nrxchains == 3) 4021 bbp3 |= 1 << 4; 4022 rt2860_mcu_bbp_write(sc, 3, bbp3); 4023 4024 /* disable non-existing Tx chains */ 4025 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4026 if (sc->ntxchains == 1) 4027 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4028 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4029 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4030 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4031 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4032 rt2860_mcu_bbp_write(sc, 1, bbp1); 4033 4034 if (sc->mac_ver >= 0x3071) 4035 rt3090_rf_setup(sc); 4036 4037 /* select default channel */ 4038 rt2860_switch_chan(sc, ic->ic_curchan); 4039 4040 /* reset RF from MCU */ 4041 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4042 4043 /* set RTS threshold */ 4044 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4045 tmp &= ~0xffff00; 4046 tmp |= IEEE80211_RTS_DEFAULT << 8; 4047 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4048 4049 /* setup initial protection mode */ 4050 rt2860_updateprot(sc); 4051 4052 /* turn radio LED on */ 4053 rt2860_set_leds(sc, RT2860_LED_RADIO); 4054 4055 /* enable Tx/Rx DMA engine */ 4056 if ((error = rt2860_txrx_enable(sc)) != 0) { 4057 rt2860_stop_locked(sc); 4058 return; 4059 } 4060 4061 /* clear pending interrupts */ 4062 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4063 /* enable interrupts */ 4064 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4065 4066 if (sc->sc_flags & RT2860_ADVANCED_PS) 4067 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4068 4069 sc->sc_flags |= RT2860_RUNNING; 4070 4071 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4072 } 4073 4074 static void 4075 rt2860_stop(void *arg) 4076 { 4077 struct rt2860_softc *sc = arg; 4078 4079 RAL_LOCK(sc); 4080 rt2860_stop_locked(sc); 4081 RAL_UNLOCK(sc); 4082 } 4083 4084 static void 4085 rt2860_stop_locked(struct rt2860_softc *sc) 4086 { 4087 uint32_t tmp; 4088 int qid; 4089 4090 if (sc->sc_flags & RT2860_RUNNING) 4091 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4092 4093 callout_stop(&sc->watchdog_ch); 4094 sc->sc_tx_timer = 0; 4095 sc->sc_flags &= ~RT2860_RUNNING; 4096 4097 /* disable interrupts */ 4098 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4099 4100 /* disable GP timer */ 4101 rt2860_set_gp_timer(sc, 0); 4102 4103 /* disable Rx */ 4104 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4105 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4106 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4107 4108 /* reset adapter */ 4109 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4110 RAL_BARRIER_WRITE(sc); 4111 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4112 4113 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4114 sc->qfullmsk = 0; 4115 for (qid = 0; qid < 6; qid++) 4116 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4117 rt2860_reset_rx_ring(sc, &sc->rxq); 4118 } 4119 4120 int 4121 rt2860_load_microcode(struct rt2860_softc *sc) 4122 { 4123 const struct firmware *fp; 4124 int ntries, error; 4125 4126 RAL_LOCK_ASSERT(sc); 4127 4128 RAL_UNLOCK(sc); 4129 fp = firmware_get("rt2860fw"); 4130 RAL_LOCK(sc); 4131 if (fp == NULL) { 4132 device_printf(sc->sc_dev, 4133 "unable to receive rt2860fw firmware image\n"); 4134 return EINVAL; 4135 } 4136 4137 /* set "host program ram write selection" bit */ 4138 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4139 /* write microcode image */ 4140 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4141 /* kick microcontroller unit */ 4142 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4143 RAL_BARRIER_WRITE(sc); 4144 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4145 4146 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4147 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4148 4149 /* wait until microcontroller is ready */ 4150 RAL_BARRIER_READ_WRITE(sc); 4151 for (ntries = 0; ntries < 1000; ntries++) { 4152 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4153 break; 4154 DELAY(1000); 4155 } 4156 if (ntries == 1000) { 4157 device_printf(sc->sc_dev, 4158 "timeout waiting for MCU to initialize\n"); 4159 error = ETIMEDOUT; 4160 } else 4161 error = 0; 4162 4163 firmware_put(fp, FIRMWARE_UNLOAD); 4164 return error; 4165 } 4166 4167 /* 4168 * This function is called periodically to adjust Tx power based on 4169 * temperature variation. 4170 */ 4171 #ifdef NOT_YET 4172 static void 4173 rt2860_calib(struct rt2860_softc *sc) 4174 { 4175 struct ieee80211com *ic = &sc->sc_ic; 4176 const uint8_t *tssi; 4177 uint8_t step, bbp49; 4178 int8_t ridx, d; 4179 4180 /* read current temperature */ 4181 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4182 4183 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4184 tssi = &sc->tssi_2ghz[4]; 4185 step = sc->step_2ghz; 4186 } else { 4187 tssi = &sc->tssi_5ghz[4]; 4188 step = sc->step_5ghz; 4189 } 4190 4191 if (bbp49 < tssi[0]) { /* lower than reference */ 4192 /* use higher Tx power than default */ 4193 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4194 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4195 /* use lower Tx power than default */ 4196 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4197 } else { 4198 /* use default Tx power */ 4199 d = 0; 4200 } 4201 d *= step; 4202 4203 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4204 4205 /* write adjusted Tx power values for each Tx rate */ 4206 for (ridx = 0; ridx < 5; ridx++) { 4207 if (sc->txpow20mhz[ridx] == 0xffffffff) 4208 continue; 4209 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4210 b4inc(sc->txpow20mhz[ridx], d)); 4211 } 4212 } 4213 #endif 4214 4215 static void 4216 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4217 { 4218 uint32_t tmp; 4219 4220 if (aux) { 4221 if (sc->mac_ver == 0x5390) { 4222 rt2860_mcu_bbp_write(sc, 152, 4223 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4224 } else { 4225 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4226 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4227 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4228 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4229 } 4230 } else { 4231 if (sc->mac_ver == 0x5390) { 4232 rt2860_mcu_bbp_write(sc, 152, 4233 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4234 } else { 4235 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4236 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4237 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4238 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4239 } 4240 } 4241 } 4242 4243 static void 4244 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4245 { 4246 struct ieee80211com *ic = &sc->sc_ic; 4247 u_int chan, group; 4248 4249 chan = ieee80211_chan2ieee(ic, c); 4250 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4251 return; 4252 4253 if (sc->mac_ver >= 0x5390) 4254 rt5390_set_chan(sc, chan); 4255 else if (sc->mac_ver >= 0x3071) 4256 rt3090_set_chan(sc, chan); 4257 else 4258 rt2860_set_chan(sc, chan); 4259 4260 /* determine channel group */ 4261 if (chan <= 14) 4262 group = 0; 4263 else if (chan <= 64) 4264 group = 1; 4265 else if (chan <= 128) 4266 group = 2; 4267 else 4268 group = 3; 4269 4270 /* XXX necessary only when group has changed! */ 4271 if (sc->mac_ver < 0x5390) 4272 rt2860_select_chan_group(sc, group); 4273 4274 DELAY(1000); 4275 } 4276 4277 static int 4278 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4279 { 4280 struct ieee80211com *ic = vap->iv_ic; 4281 struct rt2860_txwi txwi; 4282 struct mbuf *m; 4283 int ridx; 4284 4285 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4286 return ENOBUFS; 4287 4288 memset(&txwi, 0, sizeof txwi); 4289 txwi.wcid = 0xff; 4290 txwi.len = htole16(m->m_pkthdr.len); 4291 /* send beacons at the lowest available rate */ 4292 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4293 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4294 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4295 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4296 txwi.phy |= htole16(RT2860_PHY_OFDM); 4297 txwi.txop = RT2860_TX_TXOP_HT; 4298 txwi.flags = RT2860_TX_TS; 4299 txwi.xflags = RT2860_TX_NSEQ; 4300 4301 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4302 (uint8_t *)&txwi, sizeof txwi); 4303 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4304 mtod(m, uint8_t *), m->m_pkthdr.len); 4305 4306 m_freem(m); 4307 4308 return 0; 4309 } 4310 4311 static void 4312 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4313 { 4314 struct ieee80211com *ic = &sc->sc_ic; 4315 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4316 uint32_t tmp; 4317 4318 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4319 4320 tmp &= ~0x1fffff; 4321 tmp |= vap->iv_bss->ni_intval * 16; 4322 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4323 if (vap->iv_opmode == IEEE80211_M_STA) { 4324 /* 4325 * Local TSF is always updated with remote TSF on beacon 4326 * reception. 4327 */ 4328 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4329 } 4330 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4331 vap->iv_opmode == IEEE80211_M_MBSS) { 4332 tmp |= RT2860_BCN_TX_EN; 4333 /* 4334 * Local TSF is updated with remote TSF on beacon reception 4335 * only if the remote TSF is greater than local TSF. 4336 */ 4337 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4338 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4339 tmp |= RT2860_BCN_TX_EN; 4340 /* SYNC with nobody */ 4341 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4342 } 4343 4344 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4345 }
Cache object: 32f3a17b79b3ec8e72f48ea08cba7f96
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