FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
48 * and the RTL8110S.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #include <sys/param.h>
112 #include <sys/endian.h>
113 #include <sys/systm.h>
114 #include <sys/sockio.h>
115 #include <sys/mbuf.h>
116 #include <sys/malloc.h>
117 #include <sys/module.h>
118 #include <sys/kernel.h>
119 #include <sys/socket.h>
120
121 #include <net/if.h>
122 #include <net/if_arp.h>
123 #include <net/ethernet.h>
124 #include <net/if_dl.h>
125 #include <net/if_media.h>
126 #include <net/if_vlan_var.h>
127
128 #include <net/bpf.h>
129
130 #include <machine/bus_pio.h>
131 #include <machine/bus_memio.h>
132 #include <machine/bus.h>
133 #include <machine/resource.h>
134 #include <sys/bus.h>
135 #include <sys/rman.h>
136
137 #include <dev/mii/mii.h>
138 #include <dev/mii/miivar.h>
139
140 #include <dev/pci/pcireg.h>
141 #include <dev/pci/pcivar.h>
142
143 MODULE_DEPEND(re, pci, 1, 1, 1);
144 MODULE_DEPEND(re, ether, 1, 1, 1);
145 MODULE_DEPEND(re, miibus, 1, 1, 1);
146
147 /* "controller miibus0" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
149
150 /*
151 * Default to using PIO access for this driver.
152 */
153 #define RE_USEIOSPACE
154
155 #include <pci/if_rlreg.h>
156
157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
158
159 /*
160 * Various supported device vendors/types and their names.
161 */
162 static struct rl_type re_devs[] = {
163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
166 "RealTek 8169 Gigabit Ethernet" },
167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
168 "RealTek 8169S Single-chip Gigabit Ethernet" },
169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
170 "RealTek 8169SB Single-chip Gigabit Ethernet" },
171 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
172 "RealTek 8110S Single-chip Gigabit Ethernet" },
173 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
174 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
175 { 0, 0, 0, NULL }
176 };
177
178 static struct rl_hwrev re_hwrevs[] = {
179 { RL_HWREV_8139, RL_8139, "" },
180 { RL_HWREV_8139A, RL_8139, "A" },
181 { RL_HWREV_8139AG, RL_8139, "A-G" },
182 { RL_HWREV_8139B, RL_8139, "B" },
183 { RL_HWREV_8130, RL_8139, "8130" },
184 { RL_HWREV_8139C, RL_8139, "C" },
185 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
186 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
187 { RL_HWREV_8169, RL_8169, "8169"},
188 { RL_HWREV_8169S, RL_8169, "8169S"},
189 { RL_HWREV_8169SB, RL_8169, "8169SB"},
190 { RL_HWREV_8110S, RL_8169, "8110S"},
191 { RL_HWREV_8100, RL_8139, "8100"},
192 { RL_HWREV_8101, RL_8139, "8101"},
193 { 0, 0, NULL }
194 };
195
196 static int re_probe (device_t);
197 static int re_attach (device_t);
198 static int re_detach (device_t);
199
200 static int re_encap (struct rl_softc *, struct mbuf **, int *);
201
202 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
203 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
204 bus_size_t, int);
205 static int re_allocmem (device_t, struct rl_softc *);
206 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
207 static int re_rx_list_init (struct rl_softc *);
208 static int re_tx_list_init (struct rl_softc *);
209 #ifdef RE_FIXUP_RX
210 static __inline void re_fixup_rx
211 (struct mbuf *);
212 #endif
213 static void re_rxeof (struct rl_softc *);
214 static void re_txeof (struct rl_softc *);
215 #ifdef DEVICE_POLLING
216 static void re_poll (struct ifnet *, enum poll_cmd, int);
217 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
218 #endif
219 static void re_intr (void *);
220 static void re_tick (void *);
221 static void re_tick_locked (struct rl_softc *);
222 static void re_start (struct ifnet *);
223 static void re_start_locked (struct ifnet *);
224 static int re_ioctl (struct ifnet *, u_long, caddr_t);
225 static void re_init (void *);
226 static void re_init_locked (struct rl_softc *);
227 static void re_stop (struct rl_softc *);
228 static void re_watchdog (struct ifnet *);
229 static int re_suspend (device_t);
230 static int re_resume (device_t);
231 static void re_shutdown (device_t);
232 static int re_ifmedia_upd (struct ifnet *);
233 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
234
235 static void re_eeprom_putbyte (struct rl_softc *, int);
236 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
237 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
238 static int re_gmii_readreg (device_t, int, int);
239 static int re_gmii_writereg (device_t, int, int, int);
240
241 static int re_miibus_readreg (device_t, int, int);
242 static int re_miibus_writereg (device_t, int, int, int);
243 static void re_miibus_statchg (device_t);
244
245 static void re_setmulti (struct rl_softc *);
246 static void re_reset (struct rl_softc *);
247
248 static int re_diag (struct rl_softc *);
249
250 #ifdef RE_USEIOSPACE
251 #define RL_RES SYS_RES_IOPORT
252 #define RL_RID RL_PCI_LOIO
253 #else
254 #define RL_RES SYS_RES_MEMORY
255 #define RL_RID RL_PCI_LOMEM
256 #endif
257
258 static device_method_t re_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, re_probe),
261 DEVMETHOD(device_attach, re_attach),
262 DEVMETHOD(device_detach, re_detach),
263 DEVMETHOD(device_suspend, re_suspend),
264 DEVMETHOD(device_resume, re_resume),
265 DEVMETHOD(device_shutdown, re_shutdown),
266
267 /* bus interface */
268 DEVMETHOD(bus_print_child, bus_generic_print_child),
269 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
270
271 /* MII interface */
272 DEVMETHOD(miibus_readreg, re_miibus_readreg),
273 DEVMETHOD(miibus_writereg, re_miibus_writereg),
274 DEVMETHOD(miibus_statchg, re_miibus_statchg),
275
276 { 0, 0 }
277 };
278
279 static driver_t re_driver = {
280 "re",
281 re_methods,
282 sizeof(struct rl_softc)
283 };
284
285 static devclass_t re_devclass;
286
287 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
288 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
289 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
290
291 #define EE_SET(x) \
292 CSR_WRITE_1(sc, RL_EECMD, \
293 CSR_READ_1(sc, RL_EECMD) | x)
294
295 #define EE_CLR(x) \
296 CSR_WRITE_1(sc, RL_EECMD, \
297 CSR_READ_1(sc, RL_EECMD) & ~x)
298
299 /*
300 * Send a read command and address to the EEPROM, check for ACK.
301 */
302 static void
303 re_eeprom_putbyte(sc, addr)
304 struct rl_softc *sc;
305 int addr;
306 {
307 register int d, i;
308
309 d = addr | sc->rl_eecmd_read;
310
311 /*
312 * Feed in each bit and strobe the clock.
313 */
314 for (i = 0x400; i; i >>= 1) {
315 if (d & i) {
316 EE_SET(RL_EE_DATAIN);
317 } else {
318 EE_CLR(RL_EE_DATAIN);
319 }
320 DELAY(100);
321 EE_SET(RL_EE_CLK);
322 DELAY(150);
323 EE_CLR(RL_EE_CLK);
324 DELAY(100);
325 }
326 }
327
328 /*
329 * Read a word of data stored in the EEPROM at address 'addr.'
330 */
331 static void
332 re_eeprom_getword(sc, addr, dest)
333 struct rl_softc *sc;
334 int addr;
335 u_int16_t *dest;
336 {
337 register int i;
338 u_int16_t word = 0;
339
340 /* Enter EEPROM access mode. */
341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
342
343 /*
344 * Send address of word we want to read.
345 */
346 re_eeprom_putbyte(sc, addr);
347
348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
349
350 /*
351 * Start reading bits from EEPROM.
352 */
353 for (i = 0x8000; i; i >>= 1) {
354 EE_SET(RL_EE_CLK);
355 DELAY(100);
356 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
357 word |= i;
358 EE_CLR(RL_EE_CLK);
359 DELAY(100);
360 }
361
362 /* Turn off EEPROM access mode. */
363 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
364
365 *dest = word;
366 }
367
368 /*
369 * Read a sequence of words from the EEPROM.
370 */
371 static void
372 re_read_eeprom(sc, dest, off, cnt, swap)
373 struct rl_softc *sc;
374 caddr_t dest;
375 int off;
376 int cnt;
377 int swap;
378 {
379 int i;
380 u_int16_t word = 0, *ptr;
381
382 for (i = 0; i < cnt; i++) {
383 re_eeprom_getword(sc, off + i, &word);
384 ptr = (u_int16_t *)(dest + (i * 2));
385 if (swap)
386 *ptr = ntohs(word);
387 else
388 *ptr = word;
389 }
390 }
391
392 static int
393 re_gmii_readreg(dev, phy, reg)
394 device_t dev;
395 int phy, reg;
396 {
397 struct rl_softc *sc;
398 u_int32_t rval;
399 int i;
400
401 if (phy != 1)
402 return (0);
403
404 sc = device_get_softc(dev);
405
406 /* Let the rgephy driver read the GMEDIASTAT register */
407
408 if (reg == RL_GMEDIASTAT) {
409 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
410 return (rval);
411 }
412
413 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
414 DELAY(1000);
415
416 for (i = 0; i < RL_TIMEOUT; i++) {
417 rval = CSR_READ_4(sc, RL_PHYAR);
418 if (rval & RL_PHYAR_BUSY)
419 break;
420 DELAY(100);
421 }
422
423 if (i == RL_TIMEOUT) {
424 printf ("re%d: PHY read failed\n", sc->rl_unit);
425 return (0);
426 }
427
428 return (rval & RL_PHYAR_PHYDATA);
429 }
430
431 static int
432 re_gmii_writereg(dev, phy, reg, data)
433 device_t dev;
434 int phy, reg, data;
435 {
436 struct rl_softc *sc;
437 u_int32_t rval;
438 int i;
439
440 sc = device_get_softc(dev);
441
442 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
443 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
444 DELAY(1000);
445
446 for (i = 0; i < RL_TIMEOUT; i++) {
447 rval = CSR_READ_4(sc, RL_PHYAR);
448 if (!(rval & RL_PHYAR_BUSY))
449 break;
450 DELAY(100);
451 }
452
453 if (i == RL_TIMEOUT) {
454 printf ("re%d: PHY write failed\n", sc->rl_unit);
455 return (0);
456 }
457
458 return (0);
459 }
460
461 static int
462 re_miibus_readreg(dev, phy, reg)
463 device_t dev;
464 int phy, reg;
465 {
466 struct rl_softc *sc;
467 u_int16_t rval = 0;
468 u_int16_t re8139_reg = 0;
469
470 sc = device_get_softc(dev);
471
472 if (sc->rl_type == RL_8169) {
473 rval = re_gmii_readreg(dev, phy, reg);
474 return (rval);
475 }
476
477 /* Pretend the internal PHY is only at address 0 */
478 if (phy) {
479 return (0);
480 }
481 switch (reg) {
482 case MII_BMCR:
483 re8139_reg = RL_BMCR;
484 break;
485 case MII_BMSR:
486 re8139_reg = RL_BMSR;
487 break;
488 case MII_ANAR:
489 re8139_reg = RL_ANAR;
490 break;
491 case MII_ANER:
492 re8139_reg = RL_ANER;
493 break;
494 case MII_ANLPAR:
495 re8139_reg = RL_LPAR;
496 break;
497 case MII_PHYIDR1:
498 case MII_PHYIDR2:
499 return (0);
500 /*
501 * Allow the rlphy driver to read the media status
502 * register. If we have a link partner which does not
503 * support NWAY, this is the register which will tell
504 * us the results of parallel detection.
505 */
506 case RL_MEDIASTAT:
507 rval = CSR_READ_1(sc, RL_MEDIASTAT);
508 return (rval);
509 default:
510 printf("re%d: bad phy register\n", sc->rl_unit);
511 return (0);
512 }
513 rval = CSR_READ_2(sc, re8139_reg);
514 return (rval);
515 }
516
517 static int
518 re_miibus_writereg(dev, phy, reg, data)
519 device_t dev;
520 int phy, reg, data;
521 {
522 struct rl_softc *sc;
523 u_int16_t re8139_reg = 0;
524 int rval = 0;
525
526 sc = device_get_softc(dev);
527
528 if (sc->rl_type == RL_8169) {
529 rval = re_gmii_writereg(dev, phy, reg, data);
530 return (rval);
531 }
532
533 /* Pretend the internal PHY is only at address 0 */
534 if (phy)
535 return (0);
536
537 switch (reg) {
538 case MII_BMCR:
539 re8139_reg = RL_BMCR;
540 break;
541 case MII_BMSR:
542 re8139_reg = RL_BMSR;
543 break;
544 case MII_ANAR:
545 re8139_reg = RL_ANAR;
546 break;
547 case MII_ANER:
548 re8139_reg = RL_ANER;
549 break;
550 case MII_ANLPAR:
551 re8139_reg = RL_LPAR;
552 break;
553 case MII_PHYIDR1:
554 case MII_PHYIDR2:
555 return (0);
556 break;
557 default:
558 printf("re%d: bad phy register\n", sc->rl_unit);
559 return (0);
560 }
561 CSR_WRITE_2(sc, re8139_reg, data);
562 return (0);
563 }
564
565 static void
566 re_miibus_statchg(dev)
567 device_t dev;
568 {
569
570 }
571
572 /*
573 * Program the 64-bit multicast hash filter.
574 */
575 static void
576 re_setmulti(sc)
577 struct rl_softc *sc;
578 {
579 struct ifnet *ifp;
580 int h = 0;
581 u_int32_t hashes[2] = { 0, 0 };
582 struct ifmultiaddr *ifma;
583 u_int32_t rxfilt;
584 int mcnt = 0;
585
586 RL_LOCK_ASSERT(sc);
587
588 ifp = &sc->arpcom.ac_if;
589
590 rxfilt = CSR_READ_4(sc, RL_RXCFG);
591
592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
593 rxfilt |= RL_RXCFG_RX_MULTI;
594 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
595 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
596 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
597 return;
598 }
599
600 /* first, zot all the existing hash bits */
601 CSR_WRITE_4(sc, RL_MAR0, 0);
602 CSR_WRITE_4(sc, RL_MAR4, 0);
603
604 /* now program new ones */
605 IF_ADDR_LOCK(ifp);
606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
607 if (ifma->ifma_addr->sa_family != AF_LINK)
608 continue;
609 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
610 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
611 if (h < 32)
612 hashes[0] |= (1 << h);
613 else
614 hashes[1] |= (1 << (h - 32));
615 mcnt++;
616 }
617 IF_ADDR_UNLOCK(ifp);
618
619 if (mcnt)
620 rxfilt |= RL_RXCFG_RX_MULTI;
621 else
622 rxfilt &= ~RL_RXCFG_RX_MULTI;
623
624 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
625 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
626 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
627 }
628
629 static void
630 re_reset(sc)
631 struct rl_softc *sc;
632 {
633 register int i;
634
635 RL_LOCK_ASSERT(sc);
636
637 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
638
639 for (i = 0; i < RL_TIMEOUT; i++) {
640 DELAY(10);
641 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
642 break;
643 }
644 if (i == RL_TIMEOUT)
645 printf("re%d: reset never completed!\n", sc->rl_unit);
646
647 CSR_WRITE_1(sc, 0x82, 1);
648 }
649
650 /*
651 * The following routine is designed to test for a defect on some
652 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
653 * lines connected to the bus, however for a 32-bit only card, they
654 * should be pulled high. The result of this defect is that the
655 * NIC will not work right if you plug it into a 64-bit slot: DMA
656 * operations will be done with 64-bit transfers, which will fail
657 * because the 64-bit data lines aren't connected.
658 *
659 * There's no way to work around this (short of talking a soldering
660 * iron to the board), however we can detect it. The method we use
661 * here is to put the NIC into digital loopback mode, set the receiver
662 * to promiscuous mode, and then try to send a frame. We then compare
663 * the frame data we sent to what was received. If the data matches,
664 * then the NIC is working correctly, otherwise we know the user has
665 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
666 * slot. In the latter case, there's no way the NIC can work correctly,
667 * so we print out a message on the console and abort the device attach.
668 */
669
670 static int
671 re_diag(sc)
672 struct rl_softc *sc;
673 {
674 struct ifnet *ifp = &sc->arpcom.ac_if;
675 struct mbuf *m0;
676 struct ether_header *eh;
677 struct rl_desc *cur_rx;
678 u_int16_t status;
679 u_int32_t rxstat;
680 int total_len, i, error = 0;
681 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
682 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
683
684 /* Allocate a single mbuf */
685 MGETHDR(m0, M_DONTWAIT, MT_DATA);
686 if (m0 == NULL)
687 return (ENOBUFS);
688
689 RL_LOCK(sc);
690
691 /*
692 * Initialize the NIC in test mode. This sets the chip up
693 * so that it can send and receive frames, but performs the
694 * following special functions:
695 * - Puts receiver in promiscuous mode
696 * - Enables digital loopback mode
697 * - Leaves interrupts turned off
698 */
699
700 ifp->if_flags |= IFF_PROMISC;
701 sc->rl_testmode = 1;
702 re_init_locked(sc);
703 re_stop(sc);
704 DELAY(100000);
705 re_init_locked(sc);
706
707 /* Put some data in the mbuf */
708
709 eh = mtod(m0, struct ether_header *);
710 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
711 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
712 eh->ether_type = htons(ETHERTYPE_IP);
713 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
714
715 /*
716 * Queue the packet, start transmission.
717 * Note: IF_HANDOFF() ultimately calls re_start() for us.
718 */
719
720 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
721 RL_UNLOCK(sc);
722 /* XXX: re_diag must not be called when in ALTQ mode */
723 IF_HANDOFF(&ifp->if_snd, m0, ifp);
724 RL_LOCK(sc);
725 m0 = NULL;
726
727 /* Wait for it to propagate through the chip */
728
729 DELAY(100000);
730 for (i = 0; i < RL_TIMEOUT; i++) {
731 status = CSR_READ_2(sc, RL_ISR);
732 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
733 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
734 break;
735 DELAY(10);
736 }
737
738 if (i == RL_TIMEOUT) {
739 printf("re%d: diagnostic failed, failed to receive packet "
740 "in loopback mode\n", sc->rl_unit);
741 error = EIO;
742 goto done;
743 }
744
745 /*
746 * The packet should have been dumped into the first
747 * entry in the RX DMA ring. Grab it from there.
748 */
749
750 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
751 sc->rl_ldata.rl_rx_list_map,
752 BUS_DMASYNC_POSTREAD);
753 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
754 sc->rl_ldata.rl_rx_dmamap[0],
755 BUS_DMASYNC_POSTWRITE);
756 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
757 sc->rl_ldata.rl_rx_dmamap[0]);
758
759 m0 = sc->rl_ldata.rl_rx_mbuf[0];
760 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
761 eh = mtod(m0, struct ether_header *);
762
763 cur_rx = &sc->rl_ldata.rl_rx_list[0];
764 total_len = RL_RXBYTES(cur_rx);
765 rxstat = le32toh(cur_rx->rl_cmdstat);
766
767 if (total_len != ETHER_MIN_LEN) {
768 printf("re%d: diagnostic failed, received short packet\n",
769 sc->rl_unit);
770 error = EIO;
771 goto done;
772 }
773
774 /* Test that the received packet data matches what we sent. */
775
776 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
777 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
778 ntohs(eh->ether_type) != ETHERTYPE_IP) {
779 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit);
780 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit,
781 dst, ":", src, ":", ETHERTYPE_IP);
782 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit,
783 eh->ether_dhost, ":", eh->ether_shost, ":",
784 ntohs(eh->ether_type));
785 printf("re%d: You may have a defective 32-bit NIC plugged "
786 "into a 64-bit PCI slot.\n", sc->rl_unit);
787 printf("re%d: Please re-install the NIC in a 32-bit slot "
788 "for proper operation.\n", sc->rl_unit);
789 printf("re%d: Read the re(4) man page for more details.\n",
790 sc->rl_unit);
791 error = EIO;
792 }
793
794 done:
795 /* Turn interface off, release resources */
796
797 sc->rl_testmode = 0;
798 ifp->if_flags &= ~IFF_PROMISC;
799 re_stop(sc);
800 if (m0 != NULL)
801 m_freem(m0);
802
803 RL_UNLOCK(sc);
804
805 return (error);
806 }
807
808 /*
809 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
810 * IDs against our list and return a device name if we find a match.
811 */
812 static int
813 re_probe(dev)
814 device_t dev;
815 {
816 struct rl_type *t;
817 struct rl_softc *sc;
818 int rid;
819 u_int32_t hwrev;
820
821 t = re_devs;
822 sc = device_get_softc(dev);
823
824 while (t->rl_name != NULL) {
825 if ((pci_get_vendor(dev) == t->rl_vid) &&
826 (pci_get_device(dev) == t->rl_did)) {
827
828 /*
829 * Temporarily map the I/O space
830 * so we can read the chip ID register.
831 */
832 rid = RL_RID;
833 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
834 RF_ACTIVE);
835 if (sc->rl_res == NULL) {
836 device_printf(dev,
837 "couldn't map ports/memory\n");
838 return (ENXIO);
839 }
840 sc->rl_btag = rman_get_bustag(sc->rl_res);
841 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
842 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
843 bus_release_resource(dev, RL_RES,
844 RL_RID, sc->rl_res);
845 if (t->rl_basetype == hwrev) {
846 device_set_desc(dev, t->rl_name);
847 return (0);
848 }
849 }
850 t++;
851 }
852
853 return (ENXIO);
854 }
855
856 /*
857 * This routine takes the segment list provided as the result of
858 * a bus_dma_map_load() operation and assigns the addresses/lengths
859 * to RealTek DMA descriptors. This can be called either by the RX
860 * code or the TX code. In the RX case, we'll probably wind up mapping
861 * at most one segment. For the TX case, there could be any number of
862 * segments since TX packets may span multiple mbufs. In either case,
863 * if the number of segments is larger than the rl_maxsegs limit
864 * specified by the caller, we abort the mapping operation. Sadly,
865 * whoever designed the buffer mapping API did not provide a way to
866 * return an error from here, so we have to fake it a bit.
867 */
868
869 static void
870 re_dma_map_desc(arg, segs, nseg, mapsize, error)
871 void *arg;
872 bus_dma_segment_t *segs;
873 int nseg;
874 bus_size_t mapsize;
875 int error;
876 {
877 struct rl_dmaload_arg *ctx;
878 struct rl_desc *d = NULL;
879 int i = 0, idx;
880
881 if (error)
882 return;
883
884 ctx = arg;
885
886 /* Signal error to caller if there's too many segments */
887 if (nseg > ctx->rl_maxsegs) {
888 ctx->rl_maxsegs = 0;
889 return;
890 }
891
892 /*
893 * Map the segment array into descriptors. Note that we set the
894 * start-of-frame and end-of-frame markers for either TX or RX, but
895 * they really only have meaning in the TX case. (In the RX case,
896 * it's the chip that tells us where packets begin and end.)
897 * We also keep track of the end of the ring and set the
898 * end-of-ring bits as needed, and we set the ownership bits
899 * in all except the very first descriptor. (The caller will
900 * set this descriptor later when it start transmission or
901 * reception.)
902 */
903 idx = ctx->rl_idx;
904 for (;;) {
905 u_int32_t cmdstat;
906 d = &ctx->rl_ring[idx];
907 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
908 ctx->rl_maxsegs = 0;
909 return;
910 }
911 cmdstat = segs[i].ds_len;
912 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
913 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
914 if (i == 0)
915 cmdstat |= RL_TDESC_CMD_SOF;
916 else
917 cmdstat |= RL_TDESC_CMD_OWN;
918 if (idx == (RL_RX_DESC_CNT - 1))
919 cmdstat |= RL_TDESC_CMD_EOR;
920 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
921 i++;
922 if (i == nseg)
923 break;
924 RL_DESC_INC(idx);
925 }
926
927 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
928 ctx->rl_maxsegs = nseg;
929 ctx->rl_idx = idx;
930 }
931
932 /*
933 * Map a single buffer address.
934 */
935
936 static void
937 re_dma_map_addr(arg, segs, nseg, error)
938 void *arg;
939 bus_dma_segment_t *segs;
940 int nseg;
941 int error;
942 {
943 bus_addr_t *addr;
944
945 if (error)
946 return;
947
948 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
949 addr = arg;
950 *addr = segs->ds_addr;
951 }
952
953 static int
954 re_allocmem(dev, sc)
955 device_t dev;
956 struct rl_softc *sc;
957 {
958 int error;
959 int nseg;
960 int i;
961
962 /*
963 * Allocate map for RX mbufs.
964 */
965 nseg = 32;
966 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
967 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
968 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
969 NULL, NULL, &sc->rl_ldata.rl_mtag);
970 if (error) {
971 device_printf(dev, "could not allocate dma tag\n");
972 return (ENOMEM);
973 }
974
975 /*
976 * Allocate map for TX descriptor list.
977 */
978 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
979 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
980 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
981 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
982 if (error) {
983 device_printf(dev, "could not allocate dma tag\n");
984 return (ENOMEM);
985 }
986
987 /* Allocate DMA'able memory for the TX ring */
988
989 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
990 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
991 &sc->rl_ldata.rl_tx_list_map);
992 if (error)
993 return (ENOMEM);
994
995 /* Load the map for the TX ring. */
996
997 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
998 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
999 RL_TX_LIST_SZ, re_dma_map_addr,
1000 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1001
1002 /* Create DMA maps for TX buffers */
1003
1004 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1005 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1006 &sc->rl_ldata.rl_tx_dmamap[i]);
1007 if (error) {
1008 device_printf(dev, "can't create DMA map for TX\n");
1009 return (ENOMEM);
1010 }
1011 }
1012
1013 /*
1014 * Allocate map for RX descriptor list.
1015 */
1016 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1017 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1018 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1019 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1020 if (error) {
1021 device_printf(dev, "could not allocate dma tag\n");
1022 return (ENOMEM);
1023 }
1024
1025 /* Allocate DMA'able memory for the RX ring */
1026
1027 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1028 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1029 &sc->rl_ldata.rl_rx_list_map);
1030 if (error)
1031 return (ENOMEM);
1032
1033 /* Load the map for the RX ring. */
1034
1035 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1036 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1037 RL_RX_LIST_SZ, re_dma_map_addr,
1038 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1039
1040 /* Create DMA maps for RX buffers */
1041
1042 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1043 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1044 &sc->rl_ldata.rl_rx_dmamap[i]);
1045 if (error) {
1046 device_printf(dev, "can't create DMA map for RX\n");
1047 return (ENOMEM);
1048 }
1049 }
1050
1051 return (0);
1052 }
1053
1054 /*
1055 * Attach the interface. Allocate softc structures, do ifmedia
1056 * setup and ethernet/BPF attach.
1057 */
1058 static int
1059 re_attach(dev)
1060 device_t dev;
1061 {
1062 u_char eaddr[ETHER_ADDR_LEN];
1063 u_int16_t as[3];
1064 struct rl_softc *sc;
1065 struct ifnet *ifp;
1066 struct rl_hwrev *hw_rev;
1067 int hwrev;
1068 u_int16_t re_did = 0;
1069 int unit, error = 0, rid, i;
1070
1071 sc = device_get_softc(dev);
1072 unit = device_get_unit(dev);
1073
1074 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1075 MTX_DEF);
1076 /*
1077 * Map control/status registers.
1078 */
1079 pci_enable_busmaster(dev);
1080
1081 rid = RL_RID;
1082 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1083 RF_ACTIVE);
1084
1085 if (sc->rl_res == NULL) {
1086 printf ("re%d: couldn't map ports/memory\n", unit);
1087 error = ENXIO;
1088 goto fail;
1089 }
1090
1091 sc->rl_btag = rman_get_bustag(sc->rl_res);
1092 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1093
1094 /* Allocate interrupt */
1095 rid = 0;
1096 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1097 RF_SHAREABLE | RF_ACTIVE);
1098
1099 if (sc->rl_irq == NULL) {
1100 printf("re%d: couldn't map interrupt\n", unit);
1101 error = ENXIO;
1102 goto fail;
1103 }
1104
1105 /* Reset the adapter. */
1106 RL_LOCK(sc);
1107 re_reset(sc);
1108 RL_UNLOCK(sc);
1109
1110 hw_rev = re_hwrevs;
1111 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1112 while (hw_rev->rl_desc != NULL) {
1113 if (hw_rev->rl_rev == hwrev) {
1114 sc->rl_type = hw_rev->rl_type;
1115 break;
1116 }
1117 hw_rev++;
1118 }
1119
1120 if (sc->rl_type == RL_8169) {
1121
1122 /* Set RX length mask */
1123
1124 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1125
1126 /* Force station address autoload from the EEPROM */
1127
1128 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1129 for (i = 0; i < RL_TIMEOUT; i++) {
1130 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1131 break;
1132 DELAY(100);
1133 }
1134 if (i == RL_TIMEOUT)
1135 printf ("re%d: eeprom autoload timed out\n", unit);
1136
1137 for (i = 0; i < ETHER_ADDR_LEN; i++)
1138 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1139 } else {
1140
1141 /* Set RX length mask */
1142
1143 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1144
1145 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1146 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1147 if (re_did != 0x8129)
1148 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1149
1150 /*
1151 * Get station address from the EEPROM.
1152 */
1153 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1154 for (i = 0; i < 3; i++) {
1155 eaddr[(i * 2) + 0] = as[i] & 0xff;
1156 eaddr[(i * 2) + 1] = as[i] >> 8;
1157 }
1158 }
1159
1160 sc->rl_unit = unit;
1161 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1162
1163 /*
1164 * Allocate the parent bus DMA tag appropriate for PCI.
1165 */
1166 #define RL_NSEG_NEW 32
1167 error = bus_dma_tag_create(NULL, /* parent */
1168 1, 0, /* alignment, boundary */
1169 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1170 BUS_SPACE_MAXADDR, /* highaddr */
1171 NULL, NULL, /* filter, filterarg */
1172 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1173 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1174 BUS_DMA_ALLOCNOW, /* flags */
1175 NULL, NULL, /* lockfunc, lockarg */
1176 &sc->rl_parent_tag);
1177 if (error)
1178 goto fail;
1179
1180 error = re_allocmem(dev, sc);
1181
1182 if (error)
1183 goto fail;
1184
1185 /* Do MII setup */
1186 if (mii_phy_probe(dev, &sc->rl_miibus,
1187 re_ifmedia_upd, re_ifmedia_sts)) {
1188 printf("re%d: MII without any phy!\n", sc->rl_unit);
1189 error = ENXIO;
1190 goto fail;
1191 }
1192
1193 ifp = &sc->arpcom.ac_if;
1194 ifp->if_softc = sc;
1195 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1196 ifp->if_mtu = ETHERMTU;
1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1198 ifp->if_ioctl = re_ioctl;
1199 ifp->if_capabilities = IFCAP_VLAN_MTU;
1200 ifp->if_start = re_start;
1201 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1202 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1203 #ifdef DEVICE_POLLING
1204 ifp->if_capabilities |= IFCAP_POLLING;
1205 #endif
1206 ifp->if_watchdog = re_watchdog;
1207 ifp->if_init = re_init;
1208 if (sc->rl_type == RL_8169)
1209 ifp->if_baudrate = 1000000000;
1210 else
1211 ifp->if_baudrate = 100000000;
1212 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1213 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1214 IFQ_SET_READY(&ifp->if_snd);
1215 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1216
1217 callout_handle_init(&sc->rl_stat_ch);
1218
1219 /*
1220 * Call MI attach routine.
1221 */
1222 ether_ifattach(ifp, eaddr);
1223
1224 /* Perform hardware diagnostic. */
1225 error = re_diag(sc);
1226
1227 if (error) {
1228 printf("re%d: attach aborted due to hardware diag failure\n",
1229 unit);
1230 ether_ifdetach(ifp);
1231 goto fail;
1232 }
1233
1234 /* Hook interrupt last to avoid having to lock softc */
1235 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1236 re_intr, sc, &sc->rl_intrhand);
1237 if (error) {
1238 printf("re%d: couldn't set up irq\n", unit);
1239 ether_ifdetach(ifp);
1240 }
1241
1242 fail:
1243 if (error)
1244 re_detach(dev);
1245
1246 return (error);
1247 }
1248
1249 /*
1250 * Shutdown hardware and free up resources. This can be called any
1251 * time after the mutex has been initialized. It is called in both
1252 * the error case in attach and the normal detach case so it needs
1253 * to be careful about only freeing resources that have actually been
1254 * allocated.
1255 */
1256 static int
1257 re_detach(dev)
1258 device_t dev;
1259 {
1260 struct rl_softc *sc;
1261 struct ifnet *ifp;
1262 int i;
1263 int attached;
1264
1265 sc = device_get_softc(dev);
1266 ifp = &sc->arpcom.ac_if;
1267 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1268
1269 attached = device_is_attached(dev);
1270 /* These should only be active if attach succeeded */
1271 if (attached)
1272 ether_ifdetach(ifp);
1273
1274 RL_LOCK(sc);
1275 #if 0
1276 sc->suspended = 1;
1277 #endif
1278
1279 /* These should only be active if attach succeeded */
1280 if (attached) {
1281 re_stop(sc);
1282 /*
1283 * Force off the IFF_UP flag here, in case someone
1284 * still had a BPF descriptor attached to this
1285 * interface. If they do, ether_ifdetach() will cause
1286 * the BPF code to try and clear the promisc mode
1287 * flag, which will bubble down to re_ioctl(),
1288 * which will try to call re_init() again. This will
1289 * turn the NIC back on and restart the MII ticker,
1290 * which will panic the system when the kernel tries
1291 * to invoke the re_tick() function that isn't there
1292 * anymore.
1293 */
1294 ifp->if_flags &= ~IFF_UP;
1295 }
1296 if (sc->rl_miibus)
1297 device_delete_child(dev, sc->rl_miibus);
1298 bus_generic_detach(dev);
1299
1300 /*
1301 * The rest is resource deallocation, so we should already be
1302 * stopped here.
1303 */
1304 RL_UNLOCK(sc);
1305
1306 if (sc->rl_intrhand)
1307 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1308 if (sc->rl_irq)
1309 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1310 if (sc->rl_res)
1311 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1312
1313
1314 /* Unload and free the RX DMA ring memory and map */
1315
1316 if (sc->rl_ldata.rl_rx_list_tag) {
1317 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1318 sc->rl_ldata.rl_rx_list_map);
1319 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1320 sc->rl_ldata.rl_rx_list,
1321 sc->rl_ldata.rl_rx_list_map);
1322 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1323 }
1324
1325 /* Unload and free the TX DMA ring memory and map */
1326
1327 if (sc->rl_ldata.rl_tx_list_tag) {
1328 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1329 sc->rl_ldata.rl_tx_list_map);
1330 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1331 sc->rl_ldata.rl_tx_list,
1332 sc->rl_ldata.rl_tx_list_map);
1333 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1334 }
1335
1336 /* Destroy all the RX and TX buffer maps */
1337
1338 if (sc->rl_ldata.rl_mtag) {
1339 for (i = 0; i < RL_TX_DESC_CNT; i++)
1340 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1341 sc->rl_ldata.rl_tx_dmamap[i]);
1342 for (i = 0; i < RL_RX_DESC_CNT; i++)
1343 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1344 sc->rl_ldata.rl_rx_dmamap[i]);
1345 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1346 }
1347
1348 /* Unload and free the stats buffer and map */
1349
1350 if (sc->rl_ldata.rl_stag) {
1351 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1352 sc->rl_ldata.rl_rx_list_map);
1353 bus_dmamem_free(sc->rl_ldata.rl_stag,
1354 sc->rl_ldata.rl_stats,
1355 sc->rl_ldata.rl_smap);
1356 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1357 }
1358
1359 if (sc->rl_parent_tag)
1360 bus_dma_tag_destroy(sc->rl_parent_tag);
1361
1362 mtx_destroy(&sc->rl_mtx);
1363
1364 return (0);
1365 }
1366
1367 static int
1368 re_newbuf(sc, idx, m)
1369 struct rl_softc *sc;
1370 int idx;
1371 struct mbuf *m;
1372 {
1373 struct rl_dmaload_arg arg;
1374 struct mbuf *n = NULL;
1375 int error;
1376
1377 if (m == NULL) {
1378 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1379 if (n == NULL)
1380 return (ENOBUFS);
1381 m = n;
1382 } else
1383 m->m_data = m->m_ext.ext_buf;
1384
1385 m->m_len = m->m_pkthdr.len = MCLBYTES;
1386 #ifdef RE_FIXUP_RX
1387 /*
1388 * This is part of an evil trick to deal with non-x86 platforms.
1389 * The RealTek chip requires RX buffers to be aligned on 64-bit
1390 * boundaries, but that will hose non-x86 machines. To get around
1391 * this, we leave some empty space at the start of each buffer
1392 * and for non-x86 hosts, we copy the buffer back six bytes
1393 * to achieve word alignment. This is slightly more efficient
1394 * than allocating a new buffer, copying the contents, and
1395 * discarding the old buffer.
1396 */
1397 m_adj(m, RE_ETHER_ALIGN);
1398 #endif
1399 arg.sc = sc;
1400 arg.rl_idx = idx;
1401 arg.rl_maxsegs = 1;
1402 arg.rl_flags = 0;
1403 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1404
1405 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1406 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1407 &arg, BUS_DMA_NOWAIT);
1408 if (error || arg.rl_maxsegs != 1) {
1409 if (n != NULL)
1410 m_freem(n);
1411 return (ENOMEM);
1412 }
1413
1414 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1415 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1416
1417 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1418 sc->rl_ldata.rl_rx_dmamap[idx],
1419 BUS_DMASYNC_PREREAD);
1420
1421 return (0);
1422 }
1423
1424 #ifdef RE_FIXUP_RX
1425 static __inline void
1426 re_fixup_rx(m)
1427 struct mbuf *m;
1428 {
1429 int i;
1430 uint16_t *src, *dst;
1431
1432 src = mtod(m, uint16_t *);
1433 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1434
1435 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1436 *dst++ = *src++;
1437
1438 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1439
1440 return;
1441 }
1442 #endif
1443
1444 static int
1445 re_tx_list_init(sc)
1446 struct rl_softc *sc;
1447 {
1448
1449 RL_LOCK_ASSERT(sc);
1450
1451 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1452 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1453 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1454
1455 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1456 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1457 sc->rl_ldata.rl_tx_prodidx = 0;
1458 sc->rl_ldata.rl_tx_considx = 0;
1459 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1460
1461 return (0);
1462 }
1463
1464 static int
1465 re_rx_list_init(sc)
1466 struct rl_softc *sc;
1467 {
1468 int i;
1469
1470 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1471 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1472 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1473
1474 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1475 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1476 return (ENOBUFS);
1477 }
1478
1479 /* Flush the RX descriptors */
1480
1481 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1482 sc->rl_ldata.rl_rx_list_map,
1483 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1484
1485 sc->rl_ldata.rl_rx_prodidx = 0;
1486 sc->rl_head = sc->rl_tail = NULL;
1487
1488 return (0);
1489 }
1490
1491 /*
1492 * RX handler for C+ and 8169. For the gigE chips, we support
1493 * the reception of jumbo frames that have been fragmented
1494 * across multiple 2K mbuf cluster buffers.
1495 */
1496 static void
1497 re_rxeof(sc)
1498 struct rl_softc *sc;
1499 {
1500 struct mbuf *m;
1501 struct ifnet *ifp;
1502 int i, total_len;
1503 struct rl_desc *cur_rx;
1504 u_int32_t rxstat, rxvlan;
1505
1506 RL_LOCK_ASSERT(sc);
1507
1508 ifp = &sc->arpcom.ac_if;
1509 i = sc->rl_ldata.rl_rx_prodidx;
1510
1511 /* Invalidate the descriptor memory */
1512
1513 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1514 sc->rl_ldata.rl_rx_list_map,
1515 BUS_DMASYNC_POSTREAD);
1516
1517 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1518 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1519 m = sc->rl_ldata.rl_rx_mbuf[i];
1520 total_len = RL_RXBYTES(cur_rx);
1521 rxstat = le32toh(cur_rx->rl_cmdstat);
1522 rxvlan = le32toh(cur_rx->rl_vlanctl);
1523
1524 /* Invalidate the RX mbuf and unload its map */
1525
1526 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1527 sc->rl_ldata.rl_rx_dmamap[i],
1528 BUS_DMASYNC_POSTWRITE);
1529 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1530 sc->rl_ldata.rl_rx_dmamap[i]);
1531
1532 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1533 m->m_len = RE_RX_DESC_BUFLEN;
1534 if (sc->rl_head == NULL)
1535 sc->rl_head = sc->rl_tail = m;
1536 else {
1537 m->m_flags &= ~M_PKTHDR;
1538 sc->rl_tail->m_next = m;
1539 sc->rl_tail = m;
1540 }
1541 re_newbuf(sc, i, NULL);
1542 RL_DESC_INC(i);
1543 continue;
1544 }
1545
1546 /*
1547 * NOTE: for the 8139C+, the frame length field
1548 * is always 12 bits in size, but for the gigE chips,
1549 * it is 13 bits (since the max RX frame length is 16K).
1550 * Unfortunately, all 32 bits in the status word
1551 * were already used, so to make room for the extra
1552 * length bit, RealTek took out the 'frame alignment
1553 * error' bit and shifted the other status bits
1554 * over one slot. The OWN, EOR, FS and LS bits are
1555 * still in the same places. We have already extracted
1556 * the frame length and checked the OWN bit, so rather
1557 * than using an alternate bit mapping, we shift the
1558 * status bits one space to the right so we can evaluate
1559 * them using the 8169 status as though it was in the
1560 * same format as that of the 8139C+.
1561 */
1562 if (sc->rl_type == RL_8169)
1563 rxstat >>= 1;
1564
1565 /*
1566 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1567 * set, but if CRC is clear, it will still be a valid frame.
1568 */
1569 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1570 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1571 ifp->if_ierrors++;
1572 /*
1573 * If this is part of a multi-fragment packet,
1574 * discard all the pieces.
1575 */
1576 if (sc->rl_head != NULL) {
1577 m_freem(sc->rl_head);
1578 sc->rl_head = sc->rl_tail = NULL;
1579 }
1580 re_newbuf(sc, i, m);
1581 RL_DESC_INC(i);
1582 continue;
1583 }
1584
1585 /*
1586 * If allocating a replacement mbuf fails,
1587 * reload the current one.
1588 */
1589
1590 if (re_newbuf(sc, i, NULL)) {
1591 ifp->if_ierrors++;
1592 if (sc->rl_head != NULL) {
1593 m_freem(sc->rl_head);
1594 sc->rl_head = sc->rl_tail = NULL;
1595 }
1596 re_newbuf(sc, i, m);
1597 RL_DESC_INC(i);
1598 continue;
1599 }
1600
1601 RL_DESC_INC(i);
1602
1603 if (sc->rl_head != NULL) {
1604 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1605 if (m->m_len == 0)
1606 m->m_len = RE_RX_DESC_BUFLEN;
1607 /*
1608 * Special case: if there's 4 bytes or less
1609 * in this buffer, the mbuf can be discarded:
1610 * the last 4 bytes is the CRC, which we don't
1611 * care about anyway.
1612 */
1613 if (m->m_len <= ETHER_CRC_LEN) {
1614 sc->rl_tail->m_len -=
1615 (ETHER_CRC_LEN - m->m_len);
1616 m_freem(m);
1617 } else {
1618 m->m_len -= ETHER_CRC_LEN;
1619 m->m_flags &= ~M_PKTHDR;
1620 sc->rl_tail->m_next = m;
1621 }
1622 m = sc->rl_head;
1623 sc->rl_head = sc->rl_tail = NULL;
1624 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1625 } else
1626 m->m_pkthdr.len = m->m_len =
1627 (total_len - ETHER_CRC_LEN);
1628
1629 #ifdef RE_FIXUP_RX
1630 re_fixup_rx(m);
1631 #endif
1632 ifp->if_ipackets++;
1633 m->m_pkthdr.rcvif = ifp;
1634
1635 /* Do RX checksumming if enabled */
1636
1637 if (ifp->if_capenable & IFCAP_RXCSUM) {
1638
1639 /* Check IP header checksum */
1640 if (rxstat & RL_RDESC_STAT_PROTOID)
1641 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1642 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1643 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1644
1645 /* Check TCP/UDP checksum */
1646 if ((RL_TCPPKT(rxstat) &&
1647 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1648 (RL_UDPPKT(rxstat) &&
1649 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1650 m->m_pkthdr.csum_flags |=
1651 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1652 m->m_pkthdr.csum_data = 0xffff;
1653 }
1654 }
1655
1656 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1657 VLAN_INPUT_TAG(ifp, m,
1658 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1659 RL_UNLOCK(sc);
1660 (*ifp->if_input)(ifp, m);
1661 RL_LOCK(sc);
1662 }
1663
1664 /* Flush the RX DMA ring */
1665
1666 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1667 sc->rl_ldata.rl_rx_list_map,
1668 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1669
1670 sc->rl_ldata.rl_rx_prodidx = i;
1671 }
1672
1673 static void
1674 re_txeof(sc)
1675 struct rl_softc *sc;
1676 {
1677 struct ifnet *ifp;
1678 u_int32_t txstat;
1679 int idx;
1680
1681 ifp = &sc->arpcom.ac_if;
1682 idx = sc->rl_ldata.rl_tx_considx;
1683
1684 /* Invalidate the TX descriptor list */
1685
1686 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1687 sc->rl_ldata.rl_tx_list_map,
1688 BUS_DMASYNC_POSTREAD);
1689
1690 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1691
1692 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1693 if (txstat & RL_TDESC_CMD_OWN)
1694 break;
1695
1696 /*
1697 * We only stash mbufs in the last descriptor
1698 * in a fragment chain, which also happens to
1699 * be the only place where the TX status bits
1700 * are valid.
1701 */
1702
1703 if (txstat & RL_TDESC_CMD_EOF) {
1704 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1705 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1706 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1707 sc->rl_ldata.rl_tx_dmamap[idx]);
1708 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1709 RL_TDESC_STAT_COLCNT))
1710 ifp->if_collisions++;
1711 if (txstat & RL_TDESC_STAT_TXERRSUM)
1712 ifp->if_oerrors++;
1713 else
1714 ifp->if_opackets++;
1715 }
1716 sc->rl_ldata.rl_tx_free++;
1717 RL_DESC_INC(idx);
1718 }
1719
1720 /* No changes made to the TX ring, so no flush needed */
1721
1722 if (idx != sc->rl_ldata.rl_tx_considx) {
1723 sc->rl_ldata.rl_tx_considx = idx;
1724 ifp->if_flags &= ~IFF_OACTIVE;
1725 ifp->if_timer = 0;
1726 }
1727
1728 /*
1729 * If not all descriptors have been released reaped yet,
1730 * reload the timer so that we will eventually get another
1731 * interrupt that will cause us to re-enter this routine.
1732 * This is done in case the transmitter has gone idle.
1733 */
1734 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1735 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1736 }
1737
1738 static void
1739 re_tick(xsc)
1740 void *xsc;
1741 {
1742 struct rl_softc *sc;
1743
1744 sc = xsc;
1745 RL_LOCK(sc);
1746 re_tick_locked(sc);
1747 RL_UNLOCK(sc);
1748 }
1749
1750 static void
1751 re_tick_locked(sc)
1752 struct rl_softc *sc;
1753 {
1754 struct mii_data *mii;
1755
1756 RL_LOCK_ASSERT(sc);
1757
1758 mii = device_get_softc(sc->rl_miibus);
1759
1760 mii_tick(mii);
1761
1762 sc->rl_stat_ch = timeout(re_tick, sc, hz);
1763 }
1764
1765 #ifdef DEVICE_POLLING
1766 static void
1767 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1768 {
1769 struct rl_softc *sc = ifp->if_softc;
1770
1771 RL_LOCK(sc);
1772 re_poll_locked(ifp, cmd, count);
1773 RL_UNLOCK(sc);
1774 }
1775
1776 static void
1777 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1778 {
1779 struct rl_softc *sc = ifp->if_softc;
1780
1781 RL_LOCK_ASSERT(sc);
1782
1783 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1784 ether_poll_deregister(ifp);
1785 cmd = POLL_DEREGISTER;
1786 }
1787 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1788 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1789 return;
1790 }
1791
1792 sc->rxcycles = count;
1793 re_rxeof(sc);
1794 re_txeof(sc);
1795
1796 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1797 re_start_locked(ifp);
1798
1799 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1800 u_int16_t status;
1801
1802 status = CSR_READ_2(sc, RL_ISR);
1803 if (status == 0xffff)
1804 return;
1805 if (status)
1806 CSR_WRITE_2(sc, RL_ISR, status);
1807
1808 /*
1809 * XXX check behaviour on receiver stalls.
1810 */
1811
1812 if (status & RL_ISR_SYSTEM_ERR) {
1813 re_reset(sc);
1814 re_init_locked(sc);
1815 }
1816 }
1817 }
1818 #endif /* DEVICE_POLLING */
1819
1820 static void
1821 re_intr(arg)
1822 void *arg;
1823 {
1824 struct rl_softc *sc;
1825 struct ifnet *ifp;
1826 u_int16_t status;
1827
1828 sc = arg;
1829
1830 RL_LOCK(sc);
1831
1832 ifp = &sc->arpcom.ac_if;
1833
1834 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1835 goto done_locked;
1836
1837 #ifdef DEVICE_POLLING
1838 if (ifp->if_flags & IFF_POLLING)
1839 goto done_locked;
1840 if ((ifp->if_capenable & IFCAP_POLLING) &&
1841 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1842 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1843 re_poll_locked(ifp, 0, 1);
1844 goto done_locked;
1845 }
1846 #endif /* DEVICE_POLLING */
1847
1848 for (;;) {
1849
1850 status = CSR_READ_2(sc, RL_ISR);
1851 /* If the card has gone away the read returns 0xffff. */
1852 if (status == 0xffff)
1853 break;
1854 if (status)
1855 CSR_WRITE_2(sc, RL_ISR, status);
1856
1857 if ((status & RL_INTRS_CPLUS) == 0)
1858 break;
1859
1860 if ((status & RL_ISR_RX_OK) ||
1861 (status & RL_ISR_RX_ERR))
1862 re_rxeof(sc);
1863
1864 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1865 (status & RL_ISR_TX_ERR) ||
1866 (status & RL_ISR_TX_DESC_UNAVAIL))
1867 re_txeof(sc);
1868
1869 if (status & RL_ISR_SYSTEM_ERR) {
1870 re_reset(sc);
1871 re_init_locked(sc);
1872 }
1873
1874 if (status & RL_ISR_LINKCHG) {
1875 untimeout(re_tick, sc, sc->rl_stat_ch);
1876 re_tick_locked(sc);
1877 }
1878 }
1879
1880 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1881 re_start_locked(ifp);
1882
1883 done_locked:
1884 RL_UNLOCK(sc);
1885 }
1886
1887 static int
1888 re_encap(sc, m_head, idx)
1889 struct rl_softc *sc;
1890 struct mbuf **m_head;
1891 int *idx;
1892 {
1893 struct mbuf *m_new = NULL;
1894 struct rl_dmaload_arg arg;
1895 bus_dmamap_t map;
1896 int error;
1897 struct m_tag *mtag;
1898
1899 RL_LOCK_ASSERT(sc);
1900
1901 if (sc->rl_ldata.rl_tx_free <= 4)
1902 return (EFBIG);
1903
1904 /*
1905 * Set up checksum offload. Note: checksum offload bits must
1906 * appear in all descriptors of a multi-descriptor transmit
1907 * attempt. This is according to testing done with an 8169
1908 * chip. This is a requirement.
1909 */
1910
1911 arg.rl_flags = 0;
1912
1913 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1914 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1915 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1916 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1917 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1918 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1919
1920 arg.sc = sc;
1921 arg.rl_idx = *idx;
1922 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1923 if (arg.rl_maxsegs > 4)
1924 arg.rl_maxsegs -= 4;
1925 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1926
1927 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1928 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1929 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1930
1931 if (error && error != EFBIG) {
1932 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error);
1933 return (ENOBUFS);
1934 }
1935
1936 /* Too many segments to map, coalesce into a single mbuf */
1937
1938 if (error || arg.rl_maxsegs == 0) {
1939 m_new = m_defrag(*m_head, M_DONTWAIT);
1940 if (m_new == NULL)
1941 return (ENOBUFS);
1942 else
1943 *m_head = m_new;
1944
1945 arg.sc = sc;
1946 arg.rl_idx = *idx;
1947 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1948 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1949
1950 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1951 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1952 if (error) {
1953 printf("re%d: can't map mbuf (error %d)\n",
1954 sc->rl_unit, error);
1955 return (EFBIG);
1956 }
1957 }
1958
1959 /*
1960 * Insure that the map for this transmission
1961 * is placed at the array index of the last descriptor
1962 * in this chain. (Swap last and first dmamaps.)
1963 */
1964 sc->rl_ldata.rl_tx_dmamap[*idx] =
1965 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1966 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1967
1968 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1969 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1970
1971 /*
1972 * Set up hardware VLAN tagging. Note: vlan tag info must
1973 * appear in the first descriptor of a multi-descriptor
1974 * transmission attempt.
1975 */
1976
1977 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, *m_head);
1978 if (mtag != NULL)
1979 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1980 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1981
1982 /* Transfer ownership of packet to the chip. */
1983
1984 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1985 htole32(RL_TDESC_CMD_OWN);
1986 if (*idx != arg.rl_idx)
1987 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1988 htole32(RL_TDESC_CMD_OWN);
1989
1990 RL_DESC_INC(arg.rl_idx);
1991 *idx = arg.rl_idx;
1992
1993 return (0);
1994 }
1995
1996 static void
1997 re_start(ifp)
1998 struct ifnet *ifp;
1999 {
2000 struct rl_softc *sc;
2001
2002 sc = ifp->if_softc;
2003 RL_LOCK(sc);
2004 re_start_locked(ifp);
2005 RL_UNLOCK(sc);
2006 }
2007
2008 /*
2009 * Main transmit routine for C+ and gigE NICs.
2010 */
2011 static void
2012 re_start_locked(ifp)
2013 struct ifnet *ifp;
2014 {
2015 struct rl_softc *sc;
2016 struct mbuf *m_head = NULL;
2017 int idx, queued = 0;
2018
2019 sc = ifp->if_softc;
2020
2021 RL_LOCK_ASSERT(sc);
2022
2023 idx = sc->rl_ldata.rl_tx_prodidx;
2024
2025 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2026 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2027 if (m_head == NULL)
2028 break;
2029
2030 if (re_encap(sc, &m_head, &idx)) {
2031 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2032 ifp->if_flags |= IFF_OACTIVE;
2033 break;
2034 }
2035
2036 /*
2037 * If there's a BPF listener, bounce a copy of this frame
2038 * to him.
2039 */
2040 BPF_MTAP(ifp, m_head);
2041
2042 queued++;
2043 }
2044
2045 if (queued == 0)
2046 return;
2047
2048 /* Flush the TX descriptors */
2049
2050 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2051 sc->rl_ldata.rl_tx_list_map,
2052 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2053
2054 sc->rl_ldata.rl_tx_prodidx = idx;
2055
2056 /*
2057 * RealTek put the TX poll request register in a different
2058 * location on the 8169 gigE chip. I don't know why.
2059 */
2060
2061 if (sc->rl_type == RL_8169)
2062 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2063 else
2064 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2065
2066 /*
2067 * Use the countdown timer for interrupt moderation.
2068 * 'TX done' interrupts are disabled. Instead, we reset the
2069 * countdown timer, which will begin counting until it hits
2070 * the value in the TIMERINT register, and then trigger an
2071 * interrupt. Each time we write to the TIMERCNT register,
2072 * the timer count is reset to 0.
2073 */
2074 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2075
2076 /*
2077 * Set a timeout in case the chip goes out to lunch.
2078 */
2079 ifp->if_timer = 5;
2080 }
2081
2082 static void
2083 re_init(xsc)
2084 void *xsc;
2085 {
2086 struct rl_softc *sc = xsc;
2087
2088 RL_LOCK(sc);
2089 re_init_locked(sc);
2090 RL_UNLOCK(sc);
2091 }
2092
2093 static void
2094 re_init_locked(sc)
2095 struct rl_softc *sc;
2096 {
2097 struct ifnet *ifp = &sc->arpcom.ac_if;
2098 struct mii_data *mii;
2099 u_int32_t rxcfg = 0;
2100
2101 RL_LOCK_ASSERT(sc);
2102
2103 mii = device_get_softc(sc->rl_miibus);
2104
2105 /*
2106 * Cancel pending I/O and free all RX/TX buffers.
2107 */
2108 re_stop(sc);
2109
2110 /*
2111 * Enable C+ RX and TX mode, as well as VLAN stripping and
2112 * RX checksum offload. We must configure the C+ register
2113 * before all others.
2114 */
2115 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2116 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2117 RL_CPLUSCMD_VLANSTRIP|
2118 (ifp->if_capenable & IFCAP_RXCSUM ?
2119 RL_CPLUSCMD_RXCSUM_ENB : 0));
2120
2121 /*
2122 * Init our MAC address. Even though the chipset
2123 * documentation doesn't mention it, we need to enter "Config
2124 * register write enable" mode to modify the ID registers.
2125 */
2126 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2127 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2128 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
2129 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2130 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
2131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2132
2133 /*
2134 * For C+ mode, initialize the RX descriptors and mbufs.
2135 */
2136 re_rx_list_init(sc);
2137 re_tx_list_init(sc);
2138
2139 /*
2140 * Enable transmit and receive.
2141 */
2142 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2143
2144 /*
2145 * Set the initial TX and RX configuration.
2146 */
2147 if (sc->rl_testmode) {
2148 if (sc->rl_type == RL_8169)
2149 CSR_WRITE_4(sc, RL_TXCFG,
2150 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2151 else
2152 CSR_WRITE_4(sc, RL_TXCFG,
2153 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2154 } else
2155 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2156 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2157
2158 /* Set the individual bit to receive frames for this host only. */
2159 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2160 rxcfg |= RL_RXCFG_RX_INDIV;
2161
2162 /* If we want promiscuous mode, set the allframes bit. */
2163 if (ifp->if_flags & IFF_PROMISC)
2164 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2165 else
2166 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2167 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2168
2169 /*
2170 * Set capture broadcast bit to capture broadcast frames.
2171 */
2172 if (ifp->if_flags & IFF_BROADCAST)
2173 rxcfg |= RL_RXCFG_RX_BROAD;
2174 else
2175 rxcfg &= ~RL_RXCFG_RX_BROAD;
2176 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2177
2178 /*
2179 * Program the multicast filter, if necessary.
2180 */
2181 re_setmulti(sc);
2182
2183 #ifdef DEVICE_POLLING
2184 /*
2185 * Disable interrupts if we are polling.
2186 */
2187 if (ifp->if_flags & IFF_POLLING)
2188 CSR_WRITE_2(sc, RL_IMR, 0);
2189 else /* otherwise ... */
2190 #endif /* DEVICE_POLLING */
2191 /*
2192 * Enable interrupts.
2193 */
2194 if (sc->rl_testmode)
2195 CSR_WRITE_2(sc, RL_IMR, 0);
2196 else
2197 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2198
2199 /* Set initial TX threshold */
2200 sc->rl_txthresh = RL_TX_THRESH_INIT;
2201
2202 /* Start RX/TX process. */
2203 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2204 #ifdef notdef
2205 /* Enable receiver and transmitter. */
2206 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2207 #endif
2208 /*
2209 * Load the addresses of the RX and TX lists into the chip.
2210 */
2211
2212 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2213 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2214 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2215 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2216
2217 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2218 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2219 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2220 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2221
2222 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2223
2224 /*
2225 * Initialize the timer interrupt register so that
2226 * a timer interrupt will be generated once the timer
2227 * reaches a certain number of ticks. The timer is
2228 * reloaded on each transmit. This gives us TX interrupt
2229 * moderation, which dramatically improves TX frame rate.
2230 */
2231 if (sc->rl_type == RL_8169)
2232 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2233 else
2234 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2235
2236 /*
2237 * For 8169 gigE NICs, set the max allowed RX packet
2238 * size so we can receive jumbo frames.
2239 */
2240 if (sc->rl_type == RL_8169)
2241 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2242
2243 if (sc->rl_testmode)
2244 return;
2245
2246 mii_mediachg(mii);
2247
2248 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2249
2250 ifp->if_flags |= IFF_RUNNING;
2251 ifp->if_flags &= ~IFF_OACTIVE;
2252
2253 sc->rl_stat_ch = timeout(re_tick, sc, hz);
2254 }
2255
2256 /*
2257 * Set media options.
2258 */
2259 static int
2260 re_ifmedia_upd(ifp)
2261 struct ifnet *ifp;
2262 {
2263 struct rl_softc *sc;
2264 struct mii_data *mii;
2265
2266 sc = ifp->if_softc;
2267 mii = device_get_softc(sc->rl_miibus);
2268 mii_mediachg(mii);
2269
2270 return (0);
2271 }
2272
2273 /*
2274 * Report current media status.
2275 */
2276 static void
2277 re_ifmedia_sts(ifp, ifmr)
2278 struct ifnet *ifp;
2279 struct ifmediareq *ifmr;
2280 {
2281 struct rl_softc *sc;
2282 struct mii_data *mii;
2283
2284 sc = ifp->if_softc;
2285 mii = device_get_softc(sc->rl_miibus);
2286
2287 mii_pollstat(mii);
2288 ifmr->ifm_active = mii->mii_media_active;
2289 ifmr->ifm_status = mii->mii_media_status;
2290 }
2291
2292 static int
2293 re_ioctl(ifp, command, data)
2294 struct ifnet *ifp;
2295 u_long command;
2296 caddr_t data;
2297 {
2298 struct rl_softc *sc = ifp->if_softc;
2299 struct ifreq *ifr = (struct ifreq *) data;
2300 struct mii_data *mii;
2301 int error = 0;
2302
2303 switch (command) {
2304 case SIOCSIFMTU:
2305 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2306 error = EINVAL;
2307 ifp->if_mtu = ifr->ifr_mtu;
2308 break;
2309 case SIOCSIFFLAGS:
2310 RL_LOCK(sc);
2311 if (ifp->if_flags & IFF_UP)
2312 re_init_locked(sc);
2313 else if (ifp->if_flags & IFF_RUNNING)
2314 re_stop(sc);
2315 RL_UNLOCK(sc);
2316 error = 0;
2317 break;
2318 case SIOCADDMULTI:
2319 case SIOCDELMULTI:
2320 RL_LOCK(sc);
2321 re_setmulti(sc);
2322 RL_UNLOCK(sc);
2323 error = 0;
2324 break;
2325 case SIOCGIFMEDIA:
2326 case SIOCSIFMEDIA:
2327 mii = device_get_softc(sc->rl_miibus);
2328 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2329 break;
2330 case SIOCSIFCAP:
2331 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2332 ifp->if_capenable |=
2333 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2334 if (ifp->if_capenable & IFCAP_TXCSUM)
2335 ifp->if_hwassist = RE_CSUM_FEATURES;
2336 else
2337 ifp->if_hwassist = 0;
2338 if (ifp->if_flags & IFF_RUNNING)
2339 re_init(sc);
2340 break;
2341 default:
2342 error = ether_ioctl(ifp, command, data);
2343 break;
2344 }
2345
2346 return (error);
2347 }
2348
2349 static void
2350 re_watchdog(ifp)
2351 struct ifnet *ifp;
2352 {
2353 struct rl_softc *sc;
2354
2355 sc = ifp->if_softc;
2356 RL_LOCK(sc);
2357 printf("re%d: watchdog timeout\n", sc->rl_unit);
2358 ifp->if_oerrors++;
2359
2360 re_txeof(sc);
2361 re_rxeof(sc);
2362 re_init_locked(sc);
2363
2364 RL_UNLOCK(sc);
2365 }
2366
2367 /*
2368 * Stop the adapter and free any mbufs allocated to the
2369 * RX and TX lists.
2370 */
2371 static void
2372 re_stop(sc)
2373 struct rl_softc *sc;
2374 {
2375 register int i;
2376 struct ifnet *ifp;
2377
2378 RL_LOCK_ASSERT(sc);
2379
2380 ifp = &sc->arpcom.ac_if;
2381 ifp->if_timer = 0;
2382
2383 untimeout(re_tick, sc, sc->rl_stat_ch);
2384 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2385 #ifdef DEVICE_POLLING
2386 ether_poll_deregister(ifp);
2387 #endif /* DEVICE_POLLING */
2388
2389 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2390 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2391
2392 if (sc->rl_head != NULL) {
2393 m_freem(sc->rl_head);
2394 sc->rl_head = sc->rl_tail = NULL;
2395 }
2396
2397 /* Free the TX list buffers. */
2398
2399 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2400 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2401 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2402 sc->rl_ldata.rl_tx_dmamap[i]);
2403 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2404 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2405 }
2406 }
2407
2408 /* Free the RX list buffers. */
2409
2410 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2411 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2412 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2413 sc->rl_ldata.rl_rx_dmamap[i]);
2414 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2415 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2416 }
2417 }
2418 }
2419
2420 /*
2421 * Device suspend routine. Stop the interface and save some PCI
2422 * settings in case the BIOS doesn't restore them properly on
2423 * resume.
2424 */
2425 static int
2426 re_suspend(dev)
2427 device_t dev;
2428 {
2429 struct rl_softc *sc;
2430
2431 sc = device_get_softc(dev);
2432
2433 RL_LOCK(sc);
2434 re_stop(sc);
2435 sc->suspended = 1;
2436 RL_UNLOCK(sc);
2437
2438 return (0);
2439 }
2440
2441 /*
2442 * Device resume routine. Restore some PCI settings in case the BIOS
2443 * doesn't, re-enable busmastering, and restart the interface if
2444 * appropriate.
2445 */
2446 static int
2447 re_resume(dev)
2448 device_t dev;
2449 {
2450 struct rl_softc *sc;
2451 struct ifnet *ifp;
2452
2453 sc = device_get_softc(dev);
2454
2455 RL_LOCK(sc);
2456
2457 ifp = &sc->arpcom.ac_if;
2458
2459 /* reinitialize interface if necessary */
2460 if (ifp->if_flags & IFF_UP)
2461 re_init_locked(sc);
2462
2463 sc->suspended = 0;
2464 RL_UNLOCK(sc);
2465
2466 return (0);
2467 }
2468
2469 /*
2470 * Stop all chip I/O so that the kernel's probe routines don't
2471 * get confused by errant DMAs when rebooting.
2472 */
2473 static void
2474 re_shutdown(dev)
2475 device_t dev;
2476 {
2477 struct rl_softc *sc;
2478
2479 sc = device_get_softc(dev);
2480
2481 RL_LOCK(sc);
2482 re_stop(sc);
2483 RL_UNLOCK(sc);
2484 }
Cache object: 47ecf81ef23ca3a53be9a64df46cc34d
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