FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.28.2.5 2004/10/12 21:51:20 jmg Exp $");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
48 * and the RTL8110S.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #include <sys/param.h>
112 #include <sys/endian.h>
113 #include <sys/systm.h>
114 #include <sys/sockio.h>
115 #include <sys/mbuf.h>
116 #include <sys/malloc.h>
117 #include <sys/module.h>
118 #include <sys/kernel.h>
119 #include <sys/socket.h>
120
121 #include <net/if.h>
122 #include <net/if_arp.h>
123 #include <net/ethernet.h>
124 #include <net/if_dl.h>
125 #include <net/if_media.h>
126 #include <net/if_vlan_var.h>
127
128 #include <net/bpf.h>
129
130 #include <machine/bus_pio.h>
131 #include <machine/bus_memio.h>
132 #include <machine/bus.h>
133 #include <machine/resource.h>
134 #include <sys/bus.h>
135 #include <sys/rman.h>
136
137 #include <dev/mii/mii.h>
138 #include <dev/mii/miivar.h>
139
140 #include <dev/pci/pcireg.h>
141 #include <dev/pci/pcivar.h>
142
143 MODULE_DEPEND(re, pci, 1, 1, 1);
144 MODULE_DEPEND(re, ether, 1, 1, 1);
145 MODULE_DEPEND(re, miibus, 1, 1, 1);
146
147 /* "controller miibus0" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
149
150 /*
151 * Default to using PIO access for this driver.
152 */
153 #define RE_USEIOSPACE
154
155 #include <pci/if_rlreg.h>
156
157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
158
159 /*
160 * Various supported device vendors/types and their names.
161 */
162 static struct rl_type re_devs[] = {
163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
166 "RealTek 8169 Gigabit Ethernet" },
167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
168 "RealTek 8169S Single-chip Gigabit Ethernet" },
169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
170 "RealTek 8110S Single-chip Gigabit Ethernet" },
171 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
172 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
173 { 0, 0, 0, NULL }
174 };
175
176 static struct rl_hwrev re_hwrevs[] = {
177 { RL_HWREV_8139, RL_8139, "" },
178 { RL_HWREV_8139A, RL_8139, "A" },
179 { RL_HWREV_8139AG, RL_8139, "A-G" },
180 { RL_HWREV_8139B, RL_8139, "B" },
181 { RL_HWREV_8130, RL_8139, "8130" },
182 { RL_HWREV_8139C, RL_8139, "C" },
183 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
184 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
185 { RL_HWREV_8169, RL_8169, "8169"},
186 { RL_HWREV_8169S, RL_8169, "8169S"},
187 { RL_HWREV_8110S, RL_8169, "8110S"},
188 { RL_HWREV_8100, RL_8139, "8100"},
189 { RL_HWREV_8101, RL_8139, "8101"},
190 { 0, 0, NULL }
191 };
192
193 static int re_probe (device_t);
194 static int re_attach (device_t);
195 static int re_detach (device_t);
196
197 static int re_encap (struct rl_softc *, struct mbuf **, int *);
198
199 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
200 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
201 bus_size_t, int);
202 static int re_allocmem (device_t, struct rl_softc *);
203 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
204 static int re_rx_list_init (struct rl_softc *);
205 static int re_tx_list_init (struct rl_softc *);
206 #ifdef RE_FIXUP_RX
207 static __inline void re_fixup_rx
208 (struct mbuf *);
209 #endif
210 static void re_rxeof (struct rl_softc *);
211 static void re_txeof (struct rl_softc *);
212 #ifdef DEVICE_POLLING
213 static void re_poll (struct ifnet *, enum poll_cmd, int);
214 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
215 #endif
216 static void re_intr (void *);
217 static void re_tick (void *);
218 static void re_tick_locked (struct rl_softc *);
219 static void re_start (struct ifnet *);
220 static void re_start_locked (struct ifnet *);
221 static int re_ioctl (struct ifnet *, u_long, caddr_t);
222 static void re_init (void *);
223 static void re_init_locked (struct rl_softc *);
224 static void re_stop (struct rl_softc *);
225 static void re_watchdog (struct ifnet *);
226 static int re_suspend (device_t);
227 static int re_resume (device_t);
228 static void re_shutdown (device_t);
229 static int re_ifmedia_upd (struct ifnet *);
230 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
231
232 static void re_eeprom_putbyte (struct rl_softc *, int);
233 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
234 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
235 static int re_gmii_readreg (device_t, int, int);
236 static int re_gmii_writereg (device_t, int, int, int);
237
238 static int re_miibus_readreg (device_t, int, int);
239 static int re_miibus_writereg (device_t, int, int, int);
240 static void re_miibus_statchg (device_t);
241
242 static void re_setmulti (struct rl_softc *);
243 static void re_reset (struct rl_softc *);
244
245 static int re_diag (struct rl_softc *);
246
247 #ifdef RE_USEIOSPACE
248 #define RL_RES SYS_RES_IOPORT
249 #define RL_RID RL_PCI_LOIO
250 #else
251 #define RL_RES SYS_RES_MEMORY
252 #define RL_RID RL_PCI_LOMEM
253 #endif
254
255 static device_method_t re_methods[] = {
256 /* Device interface */
257 DEVMETHOD(device_probe, re_probe),
258 DEVMETHOD(device_attach, re_attach),
259 DEVMETHOD(device_detach, re_detach),
260 DEVMETHOD(device_suspend, re_suspend),
261 DEVMETHOD(device_resume, re_resume),
262 DEVMETHOD(device_shutdown, re_shutdown),
263
264 /* bus interface */
265 DEVMETHOD(bus_print_child, bus_generic_print_child),
266 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
267
268 /* MII interface */
269 DEVMETHOD(miibus_readreg, re_miibus_readreg),
270 DEVMETHOD(miibus_writereg, re_miibus_writereg),
271 DEVMETHOD(miibus_statchg, re_miibus_statchg),
272
273 { 0, 0 }
274 };
275
276 static driver_t re_driver = {
277 "re",
278 re_methods,
279 sizeof(struct rl_softc)
280 };
281
282 static devclass_t re_devclass;
283
284 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
285 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
286 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
287
288 #define EE_SET(x) \
289 CSR_WRITE_1(sc, RL_EECMD, \
290 CSR_READ_1(sc, RL_EECMD) | x)
291
292 #define EE_CLR(x) \
293 CSR_WRITE_1(sc, RL_EECMD, \
294 CSR_READ_1(sc, RL_EECMD) & ~x)
295
296 /*
297 * Send a read command and address to the EEPROM, check for ACK.
298 */
299 static void
300 re_eeprom_putbyte(sc, addr)
301 struct rl_softc *sc;
302 int addr;
303 {
304 register int d, i;
305
306 d = addr | sc->rl_eecmd_read;
307
308 /*
309 * Feed in each bit and strobe the clock.
310 */
311 for (i = 0x400; i; i >>= 1) {
312 if (d & i) {
313 EE_SET(RL_EE_DATAIN);
314 } else {
315 EE_CLR(RL_EE_DATAIN);
316 }
317 DELAY(100);
318 EE_SET(RL_EE_CLK);
319 DELAY(150);
320 EE_CLR(RL_EE_CLK);
321 DELAY(100);
322 }
323 }
324
325 /*
326 * Read a word of data stored in the EEPROM at address 'addr.'
327 */
328 static void
329 re_eeprom_getword(sc, addr, dest)
330 struct rl_softc *sc;
331 int addr;
332 u_int16_t *dest;
333 {
334 register int i;
335 u_int16_t word = 0;
336
337 /* Enter EEPROM access mode. */
338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
339
340 /*
341 * Send address of word we want to read.
342 */
343 re_eeprom_putbyte(sc, addr);
344
345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
346
347 /*
348 * Start reading bits from EEPROM.
349 */
350 for (i = 0x8000; i; i >>= 1) {
351 EE_SET(RL_EE_CLK);
352 DELAY(100);
353 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
354 word |= i;
355 EE_CLR(RL_EE_CLK);
356 DELAY(100);
357 }
358
359 /* Turn off EEPROM access mode. */
360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
361
362 *dest = word;
363 }
364
365 /*
366 * Read a sequence of words from the EEPROM.
367 */
368 static void
369 re_read_eeprom(sc, dest, off, cnt, swap)
370 struct rl_softc *sc;
371 caddr_t dest;
372 int off;
373 int cnt;
374 int swap;
375 {
376 int i;
377 u_int16_t word = 0, *ptr;
378
379 for (i = 0; i < cnt; i++) {
380 re_eeprom_getword(sc, off + i, &word);
381 ptr = (u_int16_t *)(dest + (i * 2));
382 if (swap)
383 *ptr = ntohs(word);
384 else
385 *ptr = word;
386 }
387 }
388
389 static int
390 re_gmii_readreg(dev, phy, reg)
391 device_t dev;
392 int phy, reg;
393 {
394 struct rl_softc *sc;
395 u_int32_t rval;
396 int i;
397
398 if (phy != 1)
399 return (0);
400
401 sc = device_get_softc(dev);
402
403 /* Let the rgephy driver read the GMEDIASTAT register */
404
405 if (reg == RL_GMEDIASTAT) {
406 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
407 return (rval);
408 }
409
410 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
411 DELAY(1000);
412
413 for (i = 0; i < RL_TIMEOUT; i++) {
414 rval = CSR_READ_4(sc, RL_PHYAR);
415 if (rval & RL_PHYAR_BUSY)
416 break;
417 DELAY(100);
418 }
419
420 if (i == RL_TIMEOUT) {
421 printf ("re%d: PHY read failed\n", sc->rl_unit);
422 return (0);
423 }
424
425 return (rval & RL_PHYAR_PHYDATA);
426 }
427
428 static int
429 re_gmii_writereg(dev, phy, reg, data)
430 device_t dev;
431 int phy, reg, data;
432 {
433 struct rl_softc *sc;
434 u_int32_t rval;
435 int i;
436
437 sc = device_get_softc(dev);
438
439 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
440 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
441 DELAY(1000);
442
443 for (i = 0; i < RL_TIMEOUT; i++) {
444 rval = CSR_READ_4(sc, RL_PHYAR);
445 if (!(rval & RL_PHYAR_BUSY))
446 break;
447 DELAY(100);
448 }
449
450 if (i == RL_TIMEOUT) {
451 printf ("re%d: PHY write failed\n", sc->rl_unit);
452 return (0);
453 }
454
455 return (0);
456 }
457
458 static int
459 re_miibus_readreg(dev, phy, reg)
460 device_t dev;
461 int phy, reg;
462 {
463 struct rl_softc *sc;
464 u_int16_t rval = 0;
465 u_int16_t re8139_reg = 0;
466
467 sc = device_get_softc(dev);
468
469 if (sc->rl_type == RL_8169) {
470 rval = re_gmii_readreg(dev, phy, reg);
471 return (rval);
472 }
473
474 /* Pretend the internal PHY is only at address 0 */
475 if (phy) {
476 return (0);
477 }
478 switch (reg) {
479 case MII_BMCR:
480 re8139_reg = RL_BMCR;
481 break;
482 case MII_BMSR:
483 re8139_reg = RL_BMSR;
484 break;
485 case MII_ANAR:
486 re8139_reg = RL_ANAR;
487 break;
488 case MII_ANER:
489 re8139_reg = RL_ANER;
490 break;
491 case MII_ANLPAR:
492 re8139_reg = RL_LPAR;
493 break;
494 case MII_PHYIDR1:
495 case MII_PHYIDR2:
496 return (0);
497 /*
498 * Allow the rlphy driver to read the media status
499 * register. If we have a link partner which does not
500 * support NWAY, this is the register which will tell
501 * us the results of parallel detection.
502 */
503 case RL_MEDIASTAT:
504 rval = CSR_READ_1(sc, RL_MEDIASTAT);
505 return (rval);
506 default:
507 printf("re%d: bad phy register\n", sc->rl_unit);
508 return (0);
509 }
510 rval = CSR_READ_2(sc, re8139_reg);
511 return (rval);
512 }
513
514 static int
515 re_miibus_writereg(dev, phy, reg, data)
516 device_t dev;
517 int phy, reg, data;
518 {
519 struct rl_softc *sc;
520 u_int16_t re8139_reg = 0;
521 int rval = 0;
522
523 sc = device_get_softc(dev);
524
525 if (sc->rl_type == RL_8169) {
526 rval = re_gmii_writereg(dev, phy, reg, data);
527 return (rval);
528 }
529
530 /* Pretend the internal PHY is only at address 0 */
531 if (phy)
532 return (0);
533
534 switch (reg) {
535 case MII_BMCR:
536 re8139_reg = RL_BMCR;
537 break;
538 case MII_BMSR:
539 re8139_reg = RL_BMSR;
540 break;
541 case MII_ANAR:
542 re8139_reg = RL_ANAR;
543 break;
544 case MII_ANER:
545 re8139_reg = RL_ANER;
546 break;
547 case MII_ANLPAR:
548 re8139_reg = RL_LPAR;
549 break;
550 case MII_PHYIDR1:
551 case MII_PHYIDR2:
552 return (0);
553 break;
554 default:
555 printf("re%d: bad phy register\n", sc->rl_unit);
556 return (0);
557 }
558 CSR_WRITE_2(sc, re8139_reg, data);
559 return (0);
560 }
561
562 static void
563 re_miibus_statchg(dev)
564 device_t dev;
565 {
566
567 }
568
569 /*
570 * Program the 64-bit multicast hash filter.
571 */
572 static void
573 re_setmulti(sc)
574 struct rl_softc *sc;
575 {
576 struct ifnet *ifp;
577 int h = 0;
578 u_int32_t hashes[2] = { 0, 0 };
579 struct ifmultiaddr *ifma;
580 u_int32_t rxfilt;
581 int mcnt = 0;
582
583 RL_LOCK_ASSERT(sc);
584
585 ifp = &sc->arpcom.ac_if;
586
587 rxfilt = CSR_READ_4(sc, RL_RXCFG);
588
589 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
590 rxfilt |= RL_RXCFG_RX_MULTI;
591 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
592 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
593 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
594 return;
595 }
596
597 /* first, zot all the existing hash bits */
598 CSR_WRITE_4(sc, RL_MAR0, 0);
599 CSR_WRITE_4(sc, RL_MAR4, 0);
600
601 /* now program new ones */
602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
603 if (ifma->ifma_addr->sa_family != AF_LINK)
604 continue;
605 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
606 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
607 if (h < 32)
608 hashes[0] |= (1 << h);
609 else
610 hashes[1] |= (1 << (h - 32));
611 mcnt++;
612 }
613
614 if (mcnt)
615 rxfilt |= RL_RXCFG_RX_MULTI;
616 else
617 rxfilt &= ~RL_RXCFG_RX_MULTI;
618
619 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
620 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
621 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
622 }
623
624 static void
625 re_reset(sc)
626 struct rl_softc *sc;
627 {
628 register int i;
629
630 RL_LOCK_ASSERT(sc);
631
632 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
633
634 for (i = 0; i < RL_TIMEOUT; i++) {
635 DELAY(10);
636 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
637 break;
638 }
639 if (i == RL_TIMEOUT)
640 printf("re%d: reset never completed!\n", sc->rl_unit);
641
642 CSR_WRITE_1(sc, 0x82, 1);
643 }
644
645 /*
646 * The following routine is designed to test for a defect on some
647 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
648 * lines connected to the bus, however for a 32-bit only card, they
649 * should be pulled high. The result of this defect is that the
650 * NIC will not work right if you plug it into a 64-bit slot: DMA
651 * operations will be done with 64-bit transfers, which will fail
652 * because the 64-bit data lines aren't connected.
653 *
654 * There's no way to work around this (short of talking a soldering
655 * iron to the board), however we can detect it. The method we use
656 * here is to put the NIC into digital loopback mode, set the receiver
657 * to promiscuous mode, and then try to send a frame. We then compare
658 * the frame data we sent to what was received. If the data matches,
659 * then the NIC is working correctly, otherwise we know the user has
660 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
661 * slot. In the latter case, there's no way the NIC can work correctly,
662 * so we print out a message on the console and abort the device attach.
663 */
664
665 static int
666 re_diag(sc)
667 struct rl_softc *sc;
668 {
669 struct ifnet *ifp = &sc->arpcom.ac_if;
670 struct mbuf *m0;
671 struct ether_header *eh;
672 struct rl_desc *cur_rx;
673 u_int16_t status;
674 u_int32_t rxstat;
675 int total_len, i, error = 0;
676 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
677 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
678
679 /* Allocate a single mbuf */
680 MGETHDR(m0, M_DONTWAIT, MT_DATA);
681 if (m0 == NULL)
682 return (ENOBUFS);
683
684 RL_LOCK(sc);
685
686 /*
687 * Initialize the NIC in test mode. This sets the chip up
688 * so that it can send and receive frames, but performs the
689 * following special functions:
690 * - Puts receiver in promiscuous mode
691 * - Enables digital loopback mode
692 * - Leaves interrupts turned off
693 */
694
695 ifp->if_flags |= IFF_PROMISC;
696 sc->rl_testmode = 1;
697 re_init_locked(sc);
698 re_stop(sc);
699 DELAY(100000);
700 re_init_locked(sc);
701
702 /* Put some data in the mbuf */
703
704 eh = mtod(m0, struct ether_header *);
705 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
706 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
707 eh->ether_type = htons(ETHERTYPE_IP);
708 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
709
710 /*
711 * Queue the packet, start transmission.
712 * Note: IF_HANDOFF() ultimately calls re_start() for us.
713 */
714
715 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
716 RL_UNLOCK(sc);
717 IF_HANDOFF(&ifp->if_snd, m0, ifp);
718 RL_LOCK(sc);
719 m0 = NULL;
720
721 /* Wait for it to propagate through the chip */
722
723 DELAY(100000);
724 for (i = 0; i < RL_TIMEOUT; i++) {
725 status = CSR_READ_2(sc, RL_ISR);
726 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
727 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
728 break;
729 DELAY(10);
730 }
731
732 if (i == RL_TIMEOUT) {
733 printf("re%d: diagnostic failed, failed to receive packet "
734 "in loopback mode\n", sc->rl_unit);
735 error = EIO;
736 goto done;
737 }
738
739 /*
740 * The packet should have been dumped into the first
741 * entry in the RX DMA ring. Grab it from there.
742 */
743
744 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
745 sc->rl_ldata.rl_rx_list_map,
746 BUS_DMASYNC_POSTREAD);
747 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
748 sc->rl_ldata.rl_rx_dmamap[0],
749 BUS_DMASYNC_POSTWRITE);
750 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
751 sc->rl_ldata.rl_rx_dmamap[0]);
752
753 m0 = sc->rl_ldata.rl_rx_mbuf[0];
754 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
755 eh = mtod(m0, struct ether_header *);
756
757 cur_rx = &sc->rl_ldata.rl_rx_list[0];
758 total_len = RL_RXBYTES(cur_rx);
759 rxstat = le32toh(cur_rx->rl_cmdstat);
760
761 if (total_len != ETHER_MIN_LEN) {
762 printf("re%d: diagnostic failed, received short packet\n",
763 sc->rl_unit);
764 error = EIO;
765 goto done;
766 }
767
768 /* Test that the received packet data matches what we sent. */
769
770 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
771 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
772 ntohs(eh->ether_type) != ETHERTYPE_IP) {
773 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit);
774 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit,
775 dst, ":", src, ":", ETHERTYPE_IP);
776 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit,
777 eh->ether_dhost, ":", eh->ether_shost, ":",
778 ntohs(eh->ether_type));
779 printf("re%d: You may have a defective 32-bit NIC plugged "
780 "into a 64-bit PCI slot.\n", sc->rl_unit);
781 printf("re%d: Please re-install the NIC in a 32-bit slot "
782 "for proper operation.\n", sc->rl_unit);
783 printf("re%d: Read the re(4) man page for more details.\n",
784 sc->rl_unit);
785 error = EIO;
786 }
787
788 done:
789 /* Turn interface off, release resources */
790
791 sc->rl_testmode = 0;
792 ifp->if_flags &= ~IFF_PROMISC;
793 re_stop(sc);
794 if (m0 != NULL)
795 m_freem(m0);
796
797 RL_UNLOCK(sc);
798
799 return (error);
800 }
801
802 /*
803 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
804 * IDs against our list and return a device name if we find a match.
805 */
806 static int
807 re_probe(dev)
808 device_t dev;
809 {
810 struct rl_type *t;
811 struct rl_softc *sc;
812 int rid;
813 u_int32_t hwrev;
814
815 t = re_devs;
816 sc = device_get_softc(dev);
817
818 while (t->rl_name != NULL) {
819 if ((pci_get_vendor(dev) == t->rl_vid) &&
820 (pci_get_device(dev) == t->rl_did)) {
821
822 /*
823 * Temporarily map the I/O space
824 * so we can read the chip ID register.
825 */
826 rid = RL_RID;
827 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
828 RF_ACTIVE);
829 if (sc->rl_res == NULL) {
830 device_printf(dev,
831 "couldn't map ports/memory\n");
832 return (ENXIO);
833 }
834 sc->rl_btag = rman_get_bustag(sc->rl_res);
835 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
836 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
837 bus_release_resource(dev, RL_RES,
838 RL_RID, sc->rl_res);
839 if (t->rl_basetype == hwrev) {
840 device_set_desc(dev, t->rl_name);
841 return (0);
842 }
843 }
844 t++;
845 }
846
847 return (ENXIO);
848 }
849
850 /*
851 * This routine takes the segment list provided as the result of
852 * a bus_dma_map_load() operation and assigns the addresses/lengths
853 * to RealTek DMA descriptors. This can be called either by the RX
854 * code or the TX code. In the RX case, we'll probably wind up mapping
855 * at most one segment. For the TX case, there could be any number of
856 * segments since TX packets may span multiple mbufs. In either case,
857 * if the number of segments is larger than the rl_maxsegs limit
858 * specified by the caller, we abort the mapping operation. Sadly,
859 * whoever designed the buffer mapping API did not provide a way to
860 * return an error from here, so we have to fake it a bit.
861 */
862
863 static void
864 re_dma_map_desc(arg, segs, nseg, mapsize, error)
865 void *arg;
866 bus_dma_segment_t *segs;
867 int nseg;
868 bus_size_t mapsize;
869 int error;
870 {
871 struct rl_dmaload_arg *ctx;
872 struct rl_desc *d = NULL;
873 int i = 0, idx;
874
875 if (error)
876 return;
877
878 ctx = arg;
879
880 /* Signal error to caller if there's too many segments */
881 if (nseg > ctx->rl_maxsegs) {
882 ctx->rl_maxsegs = 0;
883 return;
884 }
885
886 /*
887 * Map the segment array into descriptors. Note that we set the
888 * start-of-frame and end-of-frame markers for either TX or RX, but
889 * they really only have meaning in the TX case. (In the RX case,
890 * it's the chip that tells us where packets begin and end.)
891 * We also keep track of the end of the ring and set the
892 * end-of-ring bits as needed, and we set the ownership bits
893 * in all except the very first descriptor. (The caller will
894 * set this descriptor later when it start transmission or
895 * reception.)
896 */
897 idx = ctx->rl_idx;
898 for (;;) {
899 u_int32_t cmdstat;
900 d = &ctx->rl_ring[idx];
901 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
902 ctx->rl_maxsegs = 0;
903 return;
904 }
905 cmdstat = segs[i].ds_len;
906 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
907 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
908 if (i == 0)
909 cmdstat |= RL_TDESC_CMD_SOF;
910 else
911 cmdstat |= RL_TDESC_CMD_OWN;
912 if (idx == (RL_RX_DESC_CNT - 1))
913 cmdstat |= RL_TDESC_CMD_EOR;
914 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
915 i++;
916 if (i == nseg)
917 break;
918 RL_DESC_INC(idx);
919 }
920
921 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
922 ctx->rl_maxsegs = nseg;
923 ctx->rl_idx = idx;
924 }
925
926 /*
927 * Map a single buffer address.
928 */
929
930 static void
931 re_dma_map_addr(arg, segs, nseg, error)
932 void *arg;
933 bus_dma_segment_t *segs;
934 int nseg;
935 int error;
936 {
937 u_int32_t *addr;
938
939 if (error)
940 return;
941
942 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
943 addr = arg;
944 *addr = segs->ds_addr;
945 }
946
947 static int
948 re_allocmem(dev, sc)
949 device_t dev;
950 struct rl_softc *sc;
951 {
952 int error;
953 int nseg;
954 int i;
955
956 /*
957 * Allocate map for RX mbufs.
958 */
959 nseg = 32;
960 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
961 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
962 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
963 NULL, NULL, &sc->rl_ldata.rl_mtag);
964 if (error) {
965 device_printf(dev, "could not allocate dma tag\n");
966 return (ENOMEM);
967 }
968
969 /*
970 * Allocate map for TX descriptor list.
971 */
972 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
973 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
974 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
975 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
976 if (error) {
977 device_printf(dev, "could not allocate dma tag\n");
978 return (ENOMEM);
979 }
980
981 /* Allocate DMA'able memory for the TX ring */
982
983 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
984 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
985 &sc->rl_ldata.rl_tx_list_map);
986 if (error)
987 return (ENOMEM);
988
989 /* Load the map for the TX ring. */
990
991 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
992 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
993 RL_TX_LIST_SZ, re_dma_map_addr,
994 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
995
996 /* Create DMA maps for TX buffers */
997
998 for (i = 0; i < RL_TX_DESC_CNT; i++) {
999 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1000 &sc->rl_ldata.rl_tx_dmamap[i]);
1001 if (error) {
1002 device_printf(dev, "can't create DMA map for TX\n");
1003 return (ENOMEM);
1004 }
1005 }
1006
1007 /*
1008 * Allocate map for RX descriptor list.
1009 */
1010 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1011 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1012 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1013 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1014 if (error) {
1015 device_printf(dev, "could not allocate dma tag\n");
1016 return (ENOMEM);
1017 }
1018
1019 /* Allocate DMA'able memory for the RX ring */
1020
1021 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1022 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1023 &sc->rl_ldata.rl_rx_list_map);
1024 if (error)
1025 return (ENOMEM);
1026
1027 /* Load the map for the RX ring. */
1028
1029 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1030 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1031 RL_RX_LIST_SZ, re_dma_map_addr,
1032 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1033
1034 /* Create DMA maps for RX buffers */
1035
1036 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1037 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1038 &sc->rl_ldata.rl_rx_dmamap[i]);
1039 if (error) {
1040 device_printf(dev, "can't create DMA map for RX\n");
1041 return (ENOMEM);
1042 }
1043 }
1044
1045 return (0);
1046 }
1047
1048 /*
1049 * Attach the interface. Allocate softc structures, do ifmedia
1050 * setup and ethernet/BPF attach.
1051 */
1052 static int
1053 re_attach(dev)
1054 device_t dev;
1055 {
1056 u_char eaddr[ETHER_ADDR_LEN];
1057 u_int16_t as[3];
1058 struct rl_softc *sc;
1059 struct ifnet *ifp;
1060 struct rl_hwrev *hw_rev;
1061 int hwrev;
1062 u_int16_t re_did = 0;
1063 int unit, error = 0, rid, i;
1064
1065 sc = device_get_softc(dev);
1066 unit = device_get_unit(dev);
1067
1068 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1069 MTX_DEF);
1070 /*
1071 * Map control/status registers.
1072 */
1073 pci_enable_busmaster(dev);
1074
1075 rid = RL_RID;
1076 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1077 RF_ACTIVE);
1078
1079 if (sc->rl_res == NULL) {
1080 printf ("re%d: couldn't map ports/memory\n", unit);
1081 error = ENXIO;
1082 goto fail;
1083 }
1084
1085 sc->rl_btag = rman_get_bustag(sc->rl_res);
1086 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1087
1088 /* Allocate interrupt */
1089 rid = 0;
1090 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1091 RF_SHAREABLE | RF_ACTIVE);
1092
1093 if (sc->rl_irq == NULL) {
1094 printf("re%d: couldn't map interrupt\n", unit);
1095 error = ENXIO;
1096 goto fail;
1097 }
1098
1099 /* Reset the adapter. */
1100 RL_LOCK(sc);
1101 re_reset(sc);
1102 RL_UNLOCK(sc);
1103
1104 hw_rev = re_hwrevs;
1105 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1106 while (hw_rev->rl_desc != NULL) {
1107 if (hw_rev->rl_rev == hwrev) {
1108 sc->rl_type = hw_rev->rl_type;
1109 break;
1110 }
1111 hw_rev++;
1112 }
1113
1114 if (sc->rl_type == RL_8169) {
1115
1116 /* Set RX length mask */
1117
1118 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1119
1120 /* Force station address autoload from the EEPROM */
1121
1122 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1123 for (i = 0; i < RL_TIMEOUT; i++) {
1124 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1125 break;
1126 DELAY(100);
1127 }
1128 if (i == RL_TIMEOUT)
1129 printf ("re%d: eeprom autoload timed out\n", unit);
1130
1131 for (i = 0; i < ETHER_ADDR_LEN; i++)
1132 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1133 } else {
1134
1135 /* Set RX length mask */
1136
1137 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1138
1139 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1140 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1141 if (re_did != 0x8129)
1142 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1143
1144 /*
1145 * Get station address from the EEPROM.
1146 */
1147 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1148 for (i = 0; i < 3; i++) {
1149 eaddr[(i * 2) + 0] = as[i] & 0xff;
1150 eaddr[(i * 2) + 1] = as[i] >> 8;
1151 }
1152 }
1153
1154 sc->rl_unit = unit;
1155 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1156
1157 /*
1158 * Allocate the parent bus DMA tag appropriate for PCI.
1159 */
1160 #define RL_NSEG_NEW 32
1161 error = bus_dma_tag_create(NULL, /* parent */
1162 1, 0, /* alignment, boundary */
1163 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1164 BUS_SPACE_MAXADDR, /* highaddr */
1165 NULL, NULL, /* filter, filterarg */
1166 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1167 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1168 BUS_DMA_ALLOCNOW, /* flags */
1169 NULL, NULL, /* lockfunc, lockarg */
1170 &sc->rl_parent_tag);
1171 if (error)
1172 goto fail;
1173
1174 error = re_allocmem(dev, sc);
1175
1176 if (error)
1177 goto fail;
1178
1179 /* Do MII setup */
1180 if (mii_phy_probe(dev, &sc->rl_miibus,
1181 re_ifmedia_upd, re_ifmedia_sts)) {
1182 printf("re%d: MII without any phy!\n", sc->rl_unit);
1183 error = ENXIO;
1184 goto fail;
1185 }
1186
1187 ifp = &sc->arpcom.ac_if;
1188 ifp->if_softc = sc;
1189 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1190 ifp->if_mtu = ETHERMTU;
1191 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1192 ifp->if_ioctl = re_ioctl;
1193 ifp->if_capabilities = IFCAP_VLAN_MTU;
1194 ifp->if_start = re_start;
1195 ifp->if_hwassist = RE_CSUM_FEATURES;
1196 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1197 #ifdef DEVICE_POLLING
1198 ifp->if_capabilities |= IFCAP_POLLING;
1199 #endif
1200 ifp->if_watchdog = re_watchdog;
1201 ifp->if_init = re_init;
1202 if (sc->rl_type == RL_8169)
1203 ifp->if_baudrate = 1000000000;
1204 else
1205 ifp->if_baudrate = 100000000;
1206 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN;
1207 ifp->if_capenable = ifp->if_capabilities;
1208
1209 callout_handle_init(&sc->rl_stat_ch);
1210
1211 /*
1212 * Call MI attach routine.
1213 */
1214 ether_ifattach(ifp, eaddr);
1215
1216 /* Perform hardware diagnostic. */
1217 error = re_diag(sc);
1218
1219 if (error) {
1220 printf("re%d: attach aborted due to hardware diag failure\n",
1221 unit);
1222 ether_ifdetach(ifp);
1223 goto fail;
1224 }
1225
1226 /* Hook interrupt last to avoid having to lock softc */
1227 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1228 re_intr, sc, &sc->rl_intrhand);
1229 if (error) {
1230 printf("re%d: couldn't set up irq\n", unit);
1231 ether_ifdetach(ifp);
1232 }
1233
1234 fail:
1235 if (error)
1236 re_detach(dev);
1237
1238 return (error);
1239 }
1240
1241 /*
1242 * Shutdown hardware and free up resources. This can be called any
1243 * time after the mutex has been initialized. It is called in both
1244 * the error case in attach and the normal detach case so it needs
1245 * to be careful about only freeing resources that have actually been
1246 * allocated.
1247 */
1248 static int
1249 re_detach(dev)
1250 device_t dev;
1251 {
1252 struct rl_softc *sc;
1253 struct ifnet *ifp;
1254 int i;
1255 int attached;
1256
1257 sc = device_get_softc(dev);
1258 ifp = &sc->arpcom.ac_if;
1259 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1260
1261 attached = device_is_attached(dev);
1262 /* These should only be active if attach succeeded */
1263 if (attached)
1264 ether_ifdetach(ifp);
1265
1266 RL_LOCK(sc);
1267 #if 0
1268 sc->suspended = 1;
1269 #endif
1270
1271 /* These should only be active if attach succeeded */
1272 if (attached) {
1273 re_stop(sc);
1274 /*
1275 * Force off the IFF_UP flag here, in case someone
1276 * still had a BPF descriptor attached to this
1277 * interface. If they do, ether_ifdetach() will cause
1278 * the BPF code to try and clear the promisc mode
1279 * flag, which will bubble down to re_ioctl(),
1280 * which will try to call re_init() again. This will
1281 * turn the NIC back on and restart the MII ticker,
1282 * which will panic the system when the kernel tries
1283 * to invoke the re_tick() function that isn't there
1284 * anymore.
1285 */
1286 ifp->if_flags &= ~IFF_UP;
1287 ether_ifdetach(ifp);
1288 }
1289 if (sc->rl_miibus)
1290 device_delete_child(dev, sc->rl_miibus);
1291 bus_generic_detach(dev);
1292
1293 /*
1294 * The rest is resource deallocation, so we should already be
1295 * stopped here.
1296 */
1297 RL_UNLOCK(sc);
1298
1299 if (sc->rl_intrhand)
1300 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1301 if (sc->rl_irq)
1302 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1303 if (sc->rl_res)
1304 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1305
1306
1307 /* Unload and free the RX DMA ring memory and map */
1308
1309 if (sc->rl_ldata.rl_rx_list_tag) {
1310 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1311 sc->rl_ldata.rl_rx_list_map);
1312 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1313 sc->rl_ldata.rl_rx_list,
1314 sc->rl_ldata.rl_rx_list_map);
1315 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1316 }
1317
1318 /* Unload and free the TX DMA ring memory and map */
1319
1320 if (sc->rl_ldata.rl_tx_list_tag) {
1321 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1322 sc->rl_ldata.rl_tx_list_map);
1323 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1324 sc->rl_ldata.rl_tx_list,
1325 sc->rl_ldata.rl_tx_list_map);
1326 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1327 }
1328
1329 /* Destroy all the RX and TX buffer maps */
1330
1331 if (sc->rl_ldata.rl_mtag) {
1332 for (i = 0; i < RL_TX_DESC_CNT; i++)
1333 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1334 sc->rl_ldata.rl_tx_dmamap[i]);
1335 for (i = 0; i < RL_RX_DESC_CNT; i++)
1336 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1337 sc->rl_ldata.rl_rx_dmamap[i]);
1338 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1339 }
1340
1341 /* Unload and free the stats buffer and map */
1342
1343 if (sc->rl_ldata.rl_stag) {
1344 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1345 sc->rl_ldata.rl_rx_list_map);
1346 bus_dmamem_free(sc->rl_ldata.rl_stag,
1347 sc->rl_ldata.rl_stats,
1348 sc->rl_ldata.rl_smap);
1349 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1350 }
1351
1352 if (sc->rl_parent_tag)
1353 bus_dma_tag_destroy(sc->rl_parent_tag);
1354
1355 mtx_destroy(&sc->rl_mtx);
1356
1357 return (0);
1358 }
1359
1360 static int
1361 re_newbuf(sc, idx, m)
1362 struct rl_softc *sc;
1363 int idx;
1364 struct mbuf *m;
1365 {
1366 struct rl_dmaload_arg arg;
1367 struct mbuf *n = NULL;
1368 int error;
1369
1370 if (m == NULL) {
1371 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1372 if (n == NULL)
1373 return (ENOBUFS);
1374 m = n;
1375 } else
1376 m->m_data = m->m_ext.ext_buf;
1377
1378 m->m_len = m->m_pkthdr.len = MCLBYTES;
1379 #ifdef RE_FIXUP_RX
1380 /*
1381 * This is part of an evil trick to deal with non-x86 platforms.
1382 * The RealTek chip requires RX buffers to be aligned on 64-bit
1383 * boundaries, but that will hose non-x86 machines. To get around
1384 * this, we leave some empty space at the start of each buffer
1385 * and for non-x86 hosts, we copy the buffer back six bytes
1386 * to achieve word alignment. This is slightly more efficient
1387 * than allocating a new buffer, copying the contents, and
1388 * discarding the old buffer.
1389 */
1390 m_adj(m, RE_ETHER_ALIGN);
1391 #endif
1392 arg.sc = sc;
1393 arg.rl_idx = idx;
1394 arg.rl_maxsegs = 1;
1395 arg.rl_flags = 0;
1396 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1397
1398 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1399 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1400 &arg, BUS_DMA_NOWAIT);
1401 if (error || arg.rl_maxsegs != 1) {
1402 if (n != NULL)
1403 m_freem(n);
1404 return (ENOMEM);
1405 }
1406
1407 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1408 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1409
1410 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1411 sc->rl_ldata.rl_rx_dmamap[idx],
1412 BUS_DMASYNC_PREREAD);
1413
1414 return (0);
1415 }
1416
1417 #ifdef RE_FIXUP_RX
1418 static __inline void
1419 re_fixup_rx(m)
1420 struct mbuf *m;
1421 {
1422 int i;
1423 uint16_t *src, *dst;
1424
1425 src = mtod(m, uint16_t *);
1426 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1427
1428 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1429 *dst++ = *src++;
1430
1431 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1432
1433 return;
1434 }
1435 #endif
1436
1437 static int
1438 re_tx_list_init(sc)
1439 struct rl_softc *sc;
1440 {
1441
1442 RL_LOCK_ASSERT(sc);
1443
1444 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1445 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1446 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1447
1448 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1449 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1450 sc->rl_ldata.rl_tx_prodidx = 0;
1451 sc->rl_ldata.rl_tx_considx = 0;
1452 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1453
1454 return (0);
1455 }
1456
1457 static int
1458 re_rx_list_init(sc)
1459 struct rl_softc *sc;
1460 {
1461 int i;
1462
1463 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1464 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1465 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1466
1467 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1468 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1469 return (ENOBUFS);
1470 }
1471
1472 /* Flush the RX descriptors */
1473
1474 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1475 sc->rl_ldata.rl_rx_list_map,
1476 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1477
1478 sc->rl_ldata.rl_rx_prodidx = 0;
1479 sc->rl_head = sc->rl_tail = NULL;
1480
1481 return (0);
1482 }
1483
1484 /*
1485 * RX handler for C+ and 8169. For the gigE chips, we support
1486 * the reception of jumbo frames that have been fragmented
1487 * across multiple 2K mbuf cluster buffers.
1488 */
1489 static void
1490 re_rxeof(sc)
1491 struct rl_softc *sc;
1492 {
1493 struct mbuf *m;
1494 struct ifnet *ifp;
1495 int i, total_len;
1496 struct rl_desc *cur_rx;
1497 u_int32_t rxstat, rxvlan;
1498
1499 RL_LOCK_ASSERT(sc);
1500
1501 ifp = &sc->arpcom.ac_if;
1502 i = sc->rl_ldata.rl_rx_prodidx;
1503
1504 /* Invalidate the descriptor memory */
1505
1506 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1507 sc->rl_ldata.rl_rx_list_map,
1508 BUS_DMASYNC_POSTREAD);
1509
1510 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1511 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1512 m = sc->rl_ldata.rl_rx_mbuf[i];
1513 total_len = RL_RXBYTES(cur_rx);
1514 rxstat = le32toh(cur_rx->rl_cmdstat);
1515 rxvlan = le32toh(cur_rx->rl_vlanctl);
1516
1517 /* Invalidate the RX mbuf and unload its map */
1518
1519 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1520 sc->rl_ldata.rl_rx_dmamap[i],
1521 BUS_DMASYNC_POSTWRITE);
1522 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1523 sc->rl_ldata.rl_rx_dmamap[i]);
1524
1525 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1526 m->m_len = RE_RX_DESC_BUFLEN;
1527 if (sc->rl_head == NULL)
1528 sc->rl_head = sc->rl_tail = m;
1529 else {
1530 m->m_flags &= ~M_PKTHDR;
1531 sc->rl_tail->m_next = m;
1532 sc->rl_tail = m;
1533 }
1534 re_newbuf(sc, i, NULL);
1535 RL_DESC_INC(i);
1536 continue;
1537 }
1538
1539 /*
1540 * NOTE: for the 8139C+, the frame length field
1541 * is always 12 bits in size, but for the gigE chips,
1542 * it is 13 bits (since the max RX frame length is 16K).
1543 * Unfortunately, all 32 bits in the status word
1544 * were already used, so to make room for the extra
1545 * length bit, RealTek took out the 'frame alignment
1546 * error' bit and shifted the other status bits
1547 * over one slot. The OWN, EOR, FS and LS bits are
1548 * still in the same places. We have already extracted
1549 * the frame length and checked the OWN bit, so rather
1550 * than using an alternate bit mapping, we shift the
1551 * status bits one space to the right so we can evaluate
1552 * them using the 8169 status as though it was in the
1553 * same format as that of the 8139C+.
1554 */
1555 if (sc->rl_type == RL_8169)
1556 rxstat >>= 1;
1557
1558 /*
1559 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1560 * set, but if CRC is clear, it will still be a valid frame.
1561 */
1562 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1563 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1564 ifp->if_ierrors++;
1565 /*
1566 * If this is part of a multi-fragment packet,
1567 * discard all the pieces.
1568 */
1569 if (sc->rl_head != NULL) {
1570 m_freem(sc->rl_head);
1571 sc->rl_head = sc->rl_tail = NULL;
1572 }
1573 re_newbuf(sc, i, m);
1574 RL_DESC_INC(i);
1575 continue;
1576 }
1577
1578 /*
1579 * If allocating a replacement mbuf fails,
1580 * reload the current one.
1581 */
1582
1583 if (re_newbuf(sc, i, NULL)) {
1584 ifp->if_ierrors++;
1585 if (sc->rl_head != NULL) {
1586 m_freem(sc->rl_head);
1587 sc->rl_head = sc->rl_tail = NULL;
1588 }
1589 re_newbuf(sc, i, m);
1590 RL_DESC_INC(i);
1591 continue;
1592 }
1593
1594 RL_DESC_INC(i);
1595
1596 if (sc->rl_head != NULL) {
1597 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1598 if (m->m_len == 0)
1599 m->m_len = RE_RX_DESC_BUFLEN;
1600 /*
1601 * Special case: if there's 4 bytes or less
1602 * in this buffer, the mbuf can be discarded:
1603 * the last 4 bytes is the CRC, which we don't
1604 * care about anyway.
1605 */
1606 if (m->m_len <= ETHER_CRC_LEN) {
1607 sc->rl_tail->m_len -=
1608 (ETHER_CRC_LEN - m->m_len);
1609 m_freem(m);
1610 } else {
1611 m->m_len -= ETHER_CRC_LEN;
1612 m->m_flags &= ~M_PKTHDR;
1613 sc->rl_tail->m_next = m;
1614 }
1615 m = sc->rl_head;
1616 sc->rl_head = sc->rl_tail = NULL;
1617 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1618 } else
1619 m->m_pkthdr.len = m->m_len =
1620 (total_len - ETHER_CRC_LEN);
1621
1622 #ifdef RE_FIXUP_RX
1623 re_fixup_rx(m);
1624 #endif
1625 ifp->if_ipackets++;
1626 m->m_pkthdr.rcvif = ifp;
1627
1628 /* Do RX checksumming if enabled */
1629
1630 if (ifp->if_capenable & IFCAP_RXCSUM) {
1631
1632 /* Check IP header checksum */
1633 if (rxstat & RL_RDESC_STAT_PROTOID)
1634 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1635 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1636 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1637
1638 /* Check TCP/UDP checksum */
1639 if ((RL_TCPPKT(rxstat) &&
1640 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1641 (RL_UDPPKT(rxstat) &&
1642 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1643 m->m_pkthdr.csum_flags |=
1644 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1645 m->m_pkthdr.csum_data = 0xffff;
1646 }
1647 }
1648
1649 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1650 VLAN_INPUT_TAG(ifp, m,
1651 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1652 RL_UNLOCK(sc);
1653 (*ifp->if_input)(ifp, m);
1654 RL_LOCK(sc);
1655 }
1656
1657 /* Flush the RX DMA ring */
1658
1659 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1660 sc->rl_ldata.rl_rx_list_map,
1661 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1662
1663 sc->rl_ldata.rl_rx_prodidx = i;
1664 }
1665
1666 static void
1667 re_txeof(sc)
1668 struct rl_softc *sc;
1669 {
1670 struct ifnet *ifp;
1671 u_int32_t txstat;
1672 int idx;
1673
1674 ifp = &sc->arpcom.ac_if;
1675 idx = sc->rl_ldata.rl_tx_considx;
1676
1677 /* Invalidate the TX descriptor list */
1678
1679 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1680 sc->rl_ldata.rl_tx_list_map,
1681 BUS_DMASYNC_POSTREAD);
1682
1683 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1684
1685 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1686 if (txstat & RL_TDESC_CMD_OWN)
1687 break;
1688
1689 /*
1690 * We only stash mbufs in the last descriptor
1691 * in a fragment chain, which also happens to
1692 * be the only place where the TX status bits
1693 * are valid.
1694 */
1695
1696 if (txstat & RL_TDESC_CMD_EOF) {
1697 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1698 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1699 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1700 sc->rl_ldata.rl_tx_dmamap[idx]);
1701 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1702 RL_TDESC_STAT_COLCNT))
1703 ifp->if_collisions++;
1704 if (txstat & RL_TDESC_STAT_TXERRSUM)
1705 ifp->if_oerrors++;
1706 else
1707 ifp->if_opackets++;
1708 }
1709 sc->rl_ldata.rl_tx_free++;
1710 RL_DESC_INC(idx);
1711 }
1712
1713 /* No changes made to the TX ring, so no flush needed */
1714
1715 if (idx != sc->rl_ldata.rl_tx_considx) {
1716 sc->rl_ldata.rl_tx_considx = idx;
1717 ifp->if_flags &= ~IFF_OACTIVE;
1718 ifp->if_timer = 0;
1719 }
1720
1721 /*
1722 * If not all descriptors have been released reaped yet,
1723 * reload the timer so that we will eventually get another
1724 * interrupt that will cause us to re-enter this routine.
1725 * This is done in case the transmitter has gone idle.
1726 */
1727 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1728 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1729 }
1730
1731 static void
1732 re_tick(xsc)
1733 void *xsc;
1734 {
1735 struct rl_softc *sc;
1736
1737 sc = xsc;
1738 RL_LOCK(sc);
1739 re_tick_locked(sc);
1740 RL_UNLOCK(sc);
1741 }
1742
1743 static void
1744 re_tick_locked(sc)
1745 struct rl_softc *sc;
1746 {
1747 struct mii_data *mii;
1748
1749 RL_LOCK_ASSERT(sc);
1750
1751 mii = device_get_softc(sc->rl_miibus);
1752
1753 mii_tick(mii);
1754
1755 sc->rl_stat_ch = timeout(re_tick, sc, hz);
1756 }
1757
1758 #ifdef DEVICE_POLLING
1759 static void
1760 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1761 {
1762 struct rl_softc *sc = ifp->if_softc;
1763
1764 RL_LOCK(sc);
1765 re_poll_locked(ifp, cmd, count);
1766 RL_UNLOCK(sc);
1767 }
1768
1769 static void
1770 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1771 {
1772 struct rl_softc *sc = ifp->if_softc;
1773
1774 RL_LOCK_ASSERT(sc);
1775
1776 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1777 ether_poll_deregister(ifp);
1778 cmd = POLL_DEREGISTER;
1779 }
1780 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1781 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1782 return;
1783 }
1784
1785 sc->rxcycles = count;
1786 re_rxeof(sc);
1787 re_txeof(sc);
1788
1789 if (ifp->if_snd.ifq_head != NULL)
1790 re_start_locked(ifp);
1791
1792 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1793 u_int16_t status;
1794
1795 status = CSR_READ_2(sc, RL_ISR);
1796 if (status == 0xffff)
1797 return;
1798 if (status)
1799 CSR_WRITE_2(sc, RL_ISR, status);
1800
1801 /*
1802 * XXX check behaviour on receiver stalls.
1803 */
1804
1805 if (status & RL_ISR_SYSTEM_ERR) {
1806 re_reset(sc);
1807 re_init_locked(sc);
1808 }
1809 }
1810 }
1811 #endif /* DEVICE_POLLING */
1812
1813 static void
1814 re_intr(arg)
1815 void *arg;
1816 {
1817 struct rl_softc *sc;
1818 struct ifnet *ifp;
1819 u_int16_t status;
1820
1821 sc = arg;
1822
1823 RL_LOCK(sc);
1824
1825 ifp = &sc->arpcom.ac_if;
1826
1827 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1828 goto done_locked;
1829
1830 #ifdef DEVICE_POLLING
1831 if (ifp->if_flags & IFF_POLLING)
1832 goto done_locked;
1833 if ((ifp->if_capenable & IFCAP_POLLING) &&
1834 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1835 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1836 re_poll_locked(ifp, 0, 1);
1837 goto done_locked;
1838 }
1839 #endif /* DEVICE_POLLING */
1840
1841 for (;;) {
1842
1843 status = CSR_READ_2(sc, RL_ISR);
1844 /* If the card has gone away the read returns 0xffff. */
1845 if (status == 0xffff)
1846 break;
1847 if (status)
1848 CSR_WRITE_2(sc, RL_ISR, status);
1849
1850 if ((status & RL_INTRS_CPLUS) == 0)
1851 break;
1852
1853 if ((status & RL_ISR_RX_OK) ||
1854 (status & RL_ISR_RX_ERR))
1855 re_rxeof(sc);
1856
1857 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1858 (status & RL_ISR_TX_ERR) ||
1859 (status & RL_ISR_TX_DESC_UNAVAIL))
1860 re_txeof(sc);
1861
1862 if (status & RL_ISR_SYSTEM_ERR) {
1863 re_reset(sc);
1864 re_init_locked(sc);
1865 }
1866
1867 if (status & RL_ISR_LINKCHG) {
1868 untimeout(re_tick, sc, sc->rl_stat_ch);
1869 re_tick_locked(sc);
1870 }
1871 }
1872
1873 if (ifp->if_snd.ifq_head != NULL)
1874 re_start_locked(ifp);
1875
1876 done_locked:
1877 RL_UNLOCK(sc);
1878 }
1879
1880 static int
1881 re_encap(sc, m_head, idx)
1882 struct rl_softc *sc;
1883 struct mbuf **m_head;
1884 int *idx;
1885 {
1886 struct mbuf *m_new = NULL;
1887 struct rl_dmaload_arg arg;
1888 bus_dmamap_t map;
1889 int error;
1890 struct m_tag *mtag;
1891
1892 RL_LOCK_ASSERT(sc);
1893
1894 if (sc->rl_ldata.rl_tx_free <= 4)
1895 return (EFBIG);
1896
1897 /*
1898 * Set up checksum offload. Note: checksum offload bits must
1899 * appear in all descriptors of a multi-descriptor transmit
1900 * attempt. This is according to testing done with an 8169
1901 * chip. This is a requirement.
1902 */
1903
1904 arg.rl_flags = 0;
1905
1906 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1907 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1908 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1909 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1910 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1911 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1912
1913 arg.sc = sc;
1914 arg.rl_idx = *idx;
1915 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1916 if (arg.rl_maxsegs > 4)
1917 arg.rl_maxsegs -= 4;
1918 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1919
1920 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1921 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1922 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1923
1924 if (error && error != EFBIG) {
1925 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error);
1926 return (ENOBUFS);
1927 }
1928
1929 /* Too many segments to map, coalesce into a single mbuf */
1930
1931 if (error || arg.rl_maxsegs == 0) {
1932 m_new = m_defrag(*m_head, M_DONTWAIT);
1933 if (m_new == NULL)
1934 return (ENOBUFS);
1935 else
1936 *m_head = m_new;
1937
1938 arg.sc = sc;
1939 arg.rl_idx = *idx;
1940 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1941 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1942
1943 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1944 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1945 if (error) {
1946 printf("re%d: can't map mbuf (error %d)\n",
1947 sc->rl_unit, error);
1948 return (EFBIG);
1949 }
1950 }
1951
1952 /*
1953 * Insure that the map for this transmission
1954 * is placed at the array index of the last descriptor
1955 * in this chain. (Swap last and first dmamaps.)
1956 */
1957 sc->rl_ldata.rl_tx_dmamap[*idx] =
1958 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1959 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1960
1961 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1962 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1963
1964 /*
1965 * Set up hardware VLAN tagging. Note: vlan tag info must
1966 * appear in the first descriptor of a multi-descriptor
1967 * transmission attempt.
1968 */
1969
1970 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, *m_head);
1971 if (mtag != NULL)
1972 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1973 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1974
1975 /* Transfer ownership of packet to the chip. */
1976
1977 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1978 htole32(RL_TDESC_CMD_OWN);
1979 if (*idx != arg.rl_idx)
1980 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1981 htole32(RL_TDESC_CMD_OWN);
1982
1983 RL_DESC_INC(arg.rl_idx);
1984 *idx = arg.rl_idx;
1985
1986 return (0);
1987 }
1988
1989 static void
1990 re_start(ifp)
1991 struct ifnet *ifp;
1992 {
1993 struct rl_softc *sc;
1994
1995 sc = ifp->if_softc;
1996 RL_LOCK(sc);
1997 re_start_locked(ifp);
1998 RL_UNLOCK(sc);
1999 }
2000
2001 /*
2002 * Main transmit routine for C+ and gigE NICs.
2003 */
2004 static void
2005 re_start_locked(ifp)
2006 struct ifnet *ifp;
2007 {
2008 struct rl_softc *sc;
2009 struct mbuf *m_head = NULL;
2010 int idx;
2011
2012 sc = ifp->if_softc;
2013
2014 RL_LOCK_ASSERT(sc);
2015
2016 idx = sc->rl_ldata.rl_tx_prodidx;
2017
2018 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2019 IF_DEQUEUE(&ifp->if_snd, m_head);
2020 if (m_head == NULL)
2021 break;
2022
2023 if (re_encap(sc, &m_head, &idx)) {
2024 IF_PREPEND(&ifp->if_snd, m_head);
2025 ifp->if_flags |= IFF_OACTIVE;
2026 break;
2027 }
2028
2029 /*
2030 * If there's a BPF listener, bounce a copy of this frame
2031 * to him.
2032 */
2033 BPF_MTAP(ifp, m_head);
2034 }
2035
2036 /* Flush the TX descriptors */
2037
2038 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2039 sc->rl_ldata.rl_tx_list_map,
2040 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2041
2042 sc->rl_ldata.rl_tx_prodidx = idx;
2043
2044 /*
2045 * RealTek put the TX poll request register in a different
2046 * location on the 8169 gigE chip. I don't know why.
2047 */
2048
2049 if (sc->rl_type == RL_8169)
2050 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2051 else
2052 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2053
2054 /*
2055 * Use the countdown timer for interrupt moderation.
2056 * 'TX done' interrupts are disabled. Instead, we reset the
2057 * countdown timer, which will begin counting until it hits
2058 * the value in the TIMERINT register, and then trigger an
2059 * interrupt. Each time we write to the TIMERCNT register,
2060 * the timer count is reset to 0.
2061 */
2062 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2063
2064 /*
2065 * Set a timeout in case the chip goes out to lunch.
2066 */
2067 ifp->if_timer = 5;
2068 }
2069
2070 static void
2071 re_init(xsc)
2072 void *xsc;
2073 {
2074 struct rl_softc *sc = xsc;
2075
2076 RL_LOCK(sc);
2077 re_init_locked(sc);
2078 RL_UNLOCK(sc);
2079 }
2080
2081 static void
2082 re_init_locked(sc)
2083 struct rl_softc *sc;
2084 {
2085 struct ifnet *ifp = &sc->arpcom.ac_if;
2086 struct mii_data *mii;
2087 u_int32_t rxcfg = 0;
2088
2089 RL_LOCK_ASSERT(sc);
2090
2091 mii = device_get_softc(sc->rl_miibus);
2092
2093 /*
2094 * Cancel pending I/O and free all RX/TX buffers.
2095 */
2096 re_stop(sc);
2097
2098 /*
2099 * Enable C+ RX and TX mode, as well as VLAN stripping and
2100 * RX checksum offload. We must configure the C+ register
2101 * before all others.
2102 */
2103 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2104 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2105 RL_CPLUSCMD_VLANSTRIP|
2106 (ifp->if_capenable & IFCAP_RXCSUM ?
2107 RL_CPLUSCMD_RXCSUM_ENB : 0));
2108
2109 /*
2110 * Init our MAC address. Even though the chipset
2111 * documentation doesn't mention it, we need to enter "Config
2112 * register write enable" mode to modify the ID registers.
2113 */
2114 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2115 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2116 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
2117 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2118 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
2119 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2120
2121 /*
2122 * For C+ mode, initialize the RX descriptors and mbufs.
2123 */
2124 re_rx_list_init(sc);
2125 re_tx_list_init(sc);
2126
2127 /*
2128 * Enable transmit and receive.
2129 */
2130 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2131
2132 /*
2133 * Set the initial TX and RX configuration.
2134 */
2135 if (sc->rl_testmode) {
2136 if (sc->rl_type == RL_8169)
2137 CSR_WRITE_4(sc, RL_TXCFG,
2138 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2139 else
2140 CSR_WRITE_4(sc, RL_TXCFG,
2141 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2142 } else
2143 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2144 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2145
2146 /* Set the individual bit to receive frames for this host only. */
2147 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2148 rxcfg |= RL_RXCFG_RX_INDIV;
2149
2150 /* If we want promiscuous mode, set the allframes bit. */
2151 if (ifp->if_flags & IFF_PROMISC)
2152 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2153 else
2154 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2155 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2156
2157 /*
2158 * Set capture broadcast bit to capture broadcast frames.
2159 */
2160 if (ifp->if_flags & IFF_BROADCAST)
2161 rxcfg |= RL_RXCFG_RX_BROAD;
2162 else
2163 rxcfg &= ~RL_RXCFG_RX_BROAD;
2164 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2165
2166 /*
2167 * Program the multicast filter, if necessary.
2168 */
2169 re_setmulti(sc);
2170
2171 #ifdef DEVICE_POLLING
2172 /*
2173 * Disable interrupts if we are polling.
2174 */
2175 if (ifp->if_flags & IFF_POLLING)
2176 CSR_WRITE_2(sc, RL_IMR, 0);
2177 else /* otherwise ... */
2178 #endif /* DEVICE_POLLING */
2179 /*
2180 * Enable interrupts.
2181 */
2182 if (sc->rl_testmode)
2183 CSR_WRITE_2(sc, RL_IMR, 0);
2184 else
2185 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2186
2187 /* Set initial TX threshold */
2188 sc->rl_txthresh = RL_TX_THRESH_INIT;
2189
2190 /* Start RX/TX process. */
2191 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2192 #ifdef notdef
2193 /* Enable receiver and transmitter. */
2194 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2195 #endif
2196 /*
2197 * Load the addresses of the RX and TX lists into the chip.
2198 */
2199
2200 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2201 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2202 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2203 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2204
2205 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2206 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2207 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2208 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2209
2210 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2211
2212 /*
2213 * Initialize the timer interrupt register so that
2214 * a timer interrupt will be generated once the timer
2215 * reaches a certain number of ticks. The timer is
2216 * reloaded on each transmit. This gives us TX interrupt
2217 * moderation, which dramatically improves TX frame rate.
2218 */
2219 if (sc->rl_type == RL_8169)
2220 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2221 else
2222 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2223
2224 /*
2225 * For 8169 gigE NICs, set the max allowed RX packet
2226 * size so we can receive jumbo frames.
2227 */
2228 if (sc->rl_type == RL_8169)
2229 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2230
2231 if (sc->rl_testmode)
2232 return;
2233
2234 mii_mediachg(mii);
2235
2236 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2237
2238 ifp->if_flags |= IFF_RUNNING;
2239 ifp->if_flags &= ~IFF_OACTIVE;
2240
2241 sc->rl_stat_ch = timeout(re_tick, sc, hz);
2242 }
2243
2244 /*
2245 * Set media options.
2246 */
2247 static int
2248 re_ifmedia_upd(ifp)
2249 struct ifnet *ifp;
2250 {
2251 struct rl_softc *sc;
2252 struct mii_data *mii;
2253
2254 sc = ifp->if_softc;
2255 mii = device_get_softc(sc->rl_miibus);
2256 mii_mediachg(mii);
2257
2258 return (0);
2259 }
2260
2261 /*
2262 * Report current media status.
2263 */
2264 static void
2265 re_ifmedia_sts(ifp, ifmr)
2266 struct ifnet *ifp;
2267 struct ifmediareq *ifmr;
2268 {
2269 struct rl_softc *sc;
2270 struct mii_data *mii;
2271
2272 sc = ifp->if_softc;
2273 mii = device_get_softc(sc->rl_miibus);
2274
2275 mii_pollstat(mii);
2276 ifmr->ifm_active = mii->mii_media_active;
2277 ifmr->ifm_status = mii->mii_media_status;
2278 }
2279
2280 static int
2281 re_ioctl(ifp, command, data)
2282 struct ifnet *ifp;
2283 u_long command;
2284 caddr_t data;
2285 {
2286 struct rl_softc *sc = ifp->if_softc;
2287 struct ifreq *ifr = (struct ifreq *) data;
2288 struct mii_data *mii;
2289 int error = 0;
2290
2291 switch (command) {
2292 case SIOCSIFMTU:
2293 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2294 error = EINVAL;
2295 ifp->if_mtu = ifr->ifr_mtu;
2296 break;
2297 case SIOCSIFFLAGS:
2298 RL_LOCK(sc);
2299 if (ifp->if_flags & IFF_UP)
2300 re_init_locked(sc);
2301 else if (ifp->if_flags & IFF_RUNNING)
2302 re_stop(sc);
2303 RL_UNLOCK(sc);
2304 error = 0;
2305 break;
2306 case SIOCADDMULTI:
2307 case SIOCDELMULTI:
2308 RL_LOCK(sc);
2309 re_setmulti(sc);
2310 RL_UNLOCK(sc);
2311 error = 0;
2312 break;
2313 case SIOCGIFMEDIA:
2314 case SIOCSIFMEDIA:
2315 mii = device_get_softc(sc->rl_miibus);
2316 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2317 break;
2318 case SIOCSIFCAP:
2319 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2320 ifp->if_capenable |=
2321 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2322 if (ifp->if_capenable & IFCAP_TXCSUM)
2323 ifp->if_hwassist = RE_CSUM_FEATURES;
2324 else
2325 ifp->if_hwassist = 0;
2326 if (ifp->if_flags & IFF_RUNNING)
2327 re_init(sc);
2328 break;
2329 default:
2330 error = ether_ioctl(ifp, command, data);
2331 break;
2332 }
2333
2334 return (error);
2335 }
2336
2337 static void
2338 re_watchdog(ifp)
2339 struct ifnet *ifp;
2340 {
2341 struct rl_softc *sc;
2342
2343 sc = ifp->if_softc;
2344 RL_LOCK(sc);
2345 printf("re%d: watchdog timeout\n", sc->rl_unit);
2346 ifp->if_oerrors++;
2347
2348 re_txeof(sc);
2349 re_rxeof(sc);
2350 re_init_locked(sc);
2351
2352 RL_UNLOCK(sc);
2353 }
2354
2355 /*
2356 * Stop the adapter and free any mbufs allocated to the
2357 * RX and TX lists.
2358 */
2359 static void
2360 re_stop(sc)
2361 struct rl_softc *sc;
2362 {
2363 register int i;
2364 struct ifnet *ifp;
2365
2366 RL_LOCK_ASSERT(sc);
2367
2368 ifp = &sc->arpcom.ac_if;
2369 ifp->if_timer = 0;
2370
2371 untimeout(re_tick, sc, sc->rl_stat_ch);
2372 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2373 #ifdef DEVICE_POLLING
2374 ether_poll_deregister(ifp);
2375 #endif /* DEVICE_POLLING */
2376
2377 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2378 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2379
2380 if (sc->rl_head != NULL) {
2381 m_freem(sc->rl_head);
2382 sc->rl_head = sc->rl_tail = NULL;
2383 }
2384
2385 /* Free the TX list buffers. */
2386
2387 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2388 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2389 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2390 sc->rl_ldata.rl_tx_dmamap[i]);
2391 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2392 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2393 }
2394 }
2395
2396 /* Free the RX list buffers. */
2397
2398 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2399 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2400 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2401 sc->rl_ldata.rl_rx_dmamap[i]);
2402 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2403 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2404 }
2405 }
2406 }
2407
2408 /*
2409 * Device suspend routine. Stop the interface and save some PCI
2410 * settings in case the BIOS doesn't restore them properly on
2411 * resume.
2412 */
2413 static int
2414 re_suspend(dev)
2415 device_t dev;
2416 {
2417 struct rl_softc *sc;
2418
2419 sc = device_get_softc(dev);
2420
2421 RL_LOCK(sc);
2422 re_stop(sc);
2423 sc->suspended = 1;
2424 RL_UNLOCK(sc);
2425
2426 return (0);
2427 }
2428
2429 /*
2430 * Device resume routine. Restore some PCI settings in case the BIOS
2431 * doesn't, re-enable busmastering, and restart the interface if
2432 * appropriate.
2433 */
2434 static int
2435 re_resume(dev)
2436 device_t dev;
2437 {
2438 struct rl_softc *sc;
2439 struct ifnet *ifp;
2440
2441 sc = device_get_softc(dev);
2442
2443 RL_LOCK(sc);
2444
2445 ifp = &sc->arpcom.ac_if;
2446
2447 /* reinitialize interface if necessary */
2448 if (ifp->if_flags & IFF_UP)
2449 re_init_locked(sc);
2450
2451 sc->suspended = 0;
2452 RL_UNLOCK(sc);
2453
2454 return (0);
2455 }
2456
2457 /*
2458 * Stop all chip I/O so that the kernel's probe routines don't
2459 * get confused by errant DMAs when rebooting.
2460 */
2461 static void
2462 re_shutdown(dev)
2463 device_t dev;
2464 {
2465 struct rl_softc *sc;
2466
2467 sc = device_get_softc(dev);
2468
2469 RL_LOCK(sc);
2470 re_stop(sc);
2471 RL_UNLOCK(sc);
2472 }
Cache object: c5deea6616c56dc248a22c707dce3c61
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