FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.46.2.7 2005/10/08 07:35:10 glebius Exp $");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
48 * and the RTL8110S.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124
125 #include <net/if.h>
126 #include <net/if_arp.h>
127 #include <net/ethernet.h>
128 #include <net/if_dl.h>
129 #include <net/if_media.h>
130 #include <net/if_types.h>
131 #include <net/if_vlan_var.h>
132
133 #include <net/bpf.h>
134
135 #include <machine/bus.h>
136 #include <machine/resource.h>
137 #include <sys/bus.h>
138 #include <sys/rman.h>
139
140 #include <dev/mii/mii.h>
141 #include <dev/mii/miivar.h>
142
143 #include <dev/pci/pcireg.h>
144 #include <dev/pci/pcivar.h>
145
146 MODULE_DEPEND(re, pci, 1, 1, 1);
147 MODULE_DEPEND(re, ether, 1, 1, 1);
148 MODULE_DEPEND(re, miibus, 1, 1, 1);
149
150 /* "controller miibus0" required. See GENERIC if you get errors here. */
151 #include "miibus_if.h"
152
153 /*
154 * Default to using PIO access for this driver.
155 */
156 #define RE_USEIOSPACE
157
158 #include <pci/if_rlreg.h>
159
160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161
162 /*
163 * Various supported device vendors/types and their names.
164 */
165 static struct rl_type re_devs[] = {
166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
169 "RealTek 8139C+ 10/100BaseTX" },
170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
171 "RealTek 8169 Gigabit Ethernet" },
172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
173 "RealTek 8169S Single-chip Gigabit Ethernet" },
174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
175 "RealTek 8169SB Single-chip Gigabit Ethernet" },
176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
177 "RealTek 8110S Single-chip Gigabit Ethernet" },
178 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
179 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
180 { 0, 0, 0, NULL }
181 };
182
183 static struct rl_hwrev re_hwrevs[] = {
184 { RL_HWREV_8139, RL_8139, "" },
185 { RL_HWREV_8139A, RL_8139, "A" },
186 { RL_HWREV_8139AG, RL_8139, "A-G" },
187 { RL_HWREV_8139B, RL_8139, "B" },
188 { RL_HWREV_8130, RL_8139, "8130" },
189 { RL_HWREV_8139C, RL_8139, "C" },
190 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
191 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
192 { RL_HWREV_8169, RL_8169, "8169"},
193 { RL_HWREV_8169S, RL_8169, "8169S"},
194 { RL_HWREV_8169SB, RL_8169, "8169SB"},
195 { RL_HWREV_8110S, RL_8169, "8110S"},
196 { RL_HWREV_8100, RL_8139, "8100"},
197 { RL_HWREV_8101, RL_8139, "8101"},
198 { 0, 0, NULL }
199 };
200
201 static int re_probe (device_t);
202 static int re_attach (device_t);
203 static int re_detach (device_t);
204
205 static int re_encap (struct rl_softc *, struct mbuf **, int *);
206
207 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
208 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
209 bus_size_t, int);
210 static int re_allocmem (device_t, struct rl_softc *);
211 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
212 static int re_rx_list_init (struct rl_softc *);
213 static int re_tx_list_init (struct rl_softc *);
214 #ifdef RE_FIXUP_RX
215 static __inline void re_fixup_rx
216 (struct mbuf *);
217 #endif
218 static void re_rxeof (struct rl_softc *);
219 static void re_txeof (struct rl_softc *);
220 #ifdef DEVICE_POLLING
221 static void re_poll (struct ifnet *, enum poll_cmd, int);
222 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
223 #endif
224 static void re_intr (void *);
225 static void re_tick (void *);
226 static void re_start (struct ifnet *);
227 static void re_start_locked (struct ifnet *);
228 static int re_ioctl (struct ifnet *, u_long, caddr_t);
229 static void re_init (void *);
230 static void re_init_locked (struct rl_softc *);
231 static void re_stop (struct rl_softc *);
232 static void re_watchdog (struct ifnet *);
233 static int re_suspend (device_t);
234 static int re_resume (device_t);
235 static void re_shutdown (device_t);
236 static int re_ifmedia_upd (struct ifnet *);
237 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
238
239 static void re_eeprom_putbyte (struct rl_softc *, int);
240 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
241 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
242 static int re_gmii_readreg (device_t, int, int);
243 static int re_gmii_writereg (device_t, int, int, int);
244
245 static int re_miibus_readreg (device_t, int, int);
246 static int re_miibus_writereg (device_t, int, int, int);
247 static void re_miibus_statchg (device_t);
248
249 static void re_setmulti (struct rl_softc *);
250 static void re_reset (struct rl_softc *);
251
252 static int re_diag (struct rl_softc *);
253
254 #ifdef RE_USEIOSPACE
255 #define RL_RES SYS_RES_IOPORT
256 #define RL_RID RL_PCI_LOIO
257 #else
258 #define RL_RES SYS_RES_MEMORY
259 #define RL_RID RL_PCI_LOMEM
260 #endif
261
262 static device_method_t re_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, re_probe),
265 DEVMETHOD(device_attach, re_attach),
266 DEVMETHOD(device_detach, re_detach),
267 DEVMETHOD(device_suspend, re_suspend),
268 DEVMETHOD(device_resume, re_resume),
269 DEVMETHOD(device_shutdown, re_shutdown),
270
271 /* bus interface */
272 DEVMETHOD(bus_print_child, bus_generic_print_child),
273 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
274
275 /* MII interface */
276 DEVMETHOD(miibus_readreg, re_miibus_readreg),
277 DEVMETHOD(miibus_writereg, re_miibus_writereg),
278 DEVMETHOD(miibus_statchg, re_miibus_statchg),
279
280 { 0, 0 }
281 };
282
283 static driver_t re_driver = {
284 "re",
285 re_methods,
286 sizeof(struct rl_softc)
287 };
288
289 static devclass_t re_devclass;
290
291 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
292 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
293 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
294
295 #define EE_SET(x) \
296 CSR_WRITE_1(sc, RL_EECMD, \
297 CSR_READ_1(sc, RL_EECMD) | x)
298
299 #define EE_CLR(x) \
300 CSR_WRITE_1(sc, RL_EECMD, \
301 CSR_READ_1(sc, RL_EECMD) & ~x)
302
303 /*
304 * Send a read command and address to the EEPROM, check for ACK.
305 */
306 static void
307 re_eeprom_putbyte(sc, addr)
308 struct rl_softc *sc;
309 int addr;
310 {
311 register int d, i;
312
313 d = addr | sc->rl_eecmd_read;
314
315 /*
316 * Feed in each bit and strobe the clock.
317 */
318 for (i = 0x400; i; i >>= 1) {
319 if (d & i) {
320 EE_SET(RL_EE_DATAIN);
321 } else {
322 EE_CLR(RL_EE_DATAIN);
323 }
324 DELAY(100);
325 EE_SET(RL_EE_CLK);
326 DELAY(150);
327 EE_CLR(RL_EE_CLK);
328 DELAY(100);
329 }
330 }
331
332 /*
333 * Read a word of data stored in the EEPROM at address 'addr.'
334 */
335 static void
336 re_eeprom_getword(sc, addr, dest)
337 struct rl_softc *sc;
338 int addr;
339 u_int16_t *dest;
340 {
341 register int i;
342 u_int16_t word = 0;
343
344 /* Enter EEPROM access mode. */
345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
346
347 /*
348 * Send address of word we want to read.
349 */
350 re_eeprom_putbyte(sc, addr);
351
352 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
353
354 /*
355 * Start reading bits from EEPROM.
356 */
357 for (i = 0x8000; i; i >>= 1) {
358 EE_SET(RL_EE_CLK);
359 DELAY(100);
360 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
361 word |= i;
362 EE_CLR(RL_EE_CLK);
363 DELAY(100);
364 }
365
366 /* Turn off EEPROM access mode. */
367 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
368
369 *dest = word;
370 }
371
372 /*
373 * Read a sequence of words from the EEPROM.
374 */
375 static void
376 re_read_eeprom(sc, dest, off, cnt, swap)
377 struct rl_softc *sc;
378 caddr_t dest;
379 int off;
380 int cnt;
381 int swap;
382 {
383 int i;
384 u_int16_t word = 0, *ptr;
385
386 for (i = 0; i < cnt; i++) {
387 re_eeprom_getword(sc, off + i, &word);
388 ptr = (u_int16_t *)(dest + (i * 2));
389 if (swap)
390 *ptr = ntohs(word);
391 else
392 *ptr = word;
393 }
394 }
395
396 static int
397 re_gmii_readreg(dev, phy, reg)
398 device_t dev;
399 int phy, reg;
400 {
401 struct rl_softc *sc;
402 u_int32_t rval;
403 int i;
404
405 if (phy != 1)
406 return (0);
407
408 sc = device_get_softc(dev);
409
410 /* Let the rgephy driver read the GMEDIASTAT register */
411
412 if (reg == RL_GMEDIASTAT) {
413 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
414 return (rval);
415 }
416
417 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
418 DELAY(1000);
419
420 for (i = 0; i < RL_TIMEOUT; i++) {
421 rval = CSR_READ_4(sc, RL_PHYAR);
422 if (rval & RL_PHYAR_BUSY)
423 break;
424 DELAY(100);
425 }
426
427 if (i == RL_TIMEOUT) {
428 if_printf(sc->rl_ifp, "PHY read failed\n");
429 return (0);
430 }
431
432 return (rval & RL_PHYAR_PHYDATA);
433 }
434
435 static int
436 re_gmii_writereg(dev, phy, reg, data)
437 device_t dev;
438 int phy, reg, data;
439 {
440 struct rl_softc *sc;
441 u_int32_t rval;
442 int i;
443
444 sc = device_get_softc(dev);
445
446 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
447 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
448 DELAY(1000);
449
450 for (i = 0; i < RL_TIMEOUT; i++) {
451 rval = CSR_READ_4(sc, RL_PHYAR);
452 if (!(rval & RL_PHYAR_BUSY))
453 break;
454 DELAY(100);
455 }
456
457 if (i == RL_TIMEOUT) {
458 if_printf(sc->rl_ifp, "PHY write failed\n");
459 return (0);
460 }
461
462 return (0);
463 }
464
465 static int
466 re_miibus_readreg(dev, phy, reg)
467 device_t dev;
468 int phy, reg;
469 {
470 struct rl_softc *sc;
471 u_int16_t rval = 0;
472 u_int16_t re8139_reg = 0;
473
474 sc = device_get_softc(dev);
475
476 if (sc->rl_type == RL_8169) {
477 rval = re_gmii_readreg(dev, phy, reg);
478 return (rval);
479 }
480
481 /* Pretend the internal PHY is only at address 0 */
482 if (phy) {
483 return (0);
484 }
485 switch (reg) {
486 case MII_BMCR:
487 re8139_reg = RL_BMCR;
488 break;
489 case MII_BMSR:
490 re8139_reg = RL_BMSR;
491 break;
492 case MII_ANAR:
493 re8139_reg = RL_ANAR;
494 break;
495 case MII_ANER:
496 re8139_reg = RL_ANER;
497 break;
498 case MII_ANLPAR:
499 re8139_reg = RL_LPAR;
500 break;
501 case MII_PHYIDR1:
502 case MII_PHYIDR2:
503 return (0);
504 /*
505 * Allow the rlphy driver to read the media status
506 * register. If we have a link partner which does not
507 * support NWAY, this is the register which will tell
508 * us the results of parallel detection.
509 */
510 case RL_MEDIASTAT:
511 rval = CSR_READ_1(sc, RL_MEDIASTAT);
512 return (rval);
513 default:
514 if_printf(sc->rl_ifp, "bad phy register\n");
515 return (0);
516 }
517 rval = CSR_READ_2(sc, re8139_reg);
518 return (rval);
519 }
520
521 static int
522 re_miibus_writereg(dev, phy, reg, data)
523 device_t dev;
524 int phy, reg, data;
525 {
526 struct rl_softc *sc;
527 u_int16_t re8139_reg = 0;
528 int rval = 0;
529
530 sc = device_get_softc(dev);
531
532 if (sc->rl_type == RL_8169) {
533 rval = re_gmii_writereg(dev, phy, reg, data);
534 return (rval);
535 }
536
537 /* Pretend the internal PHY is only at address 0 */
538 if (phy)
539 return (0);
540
541 switch (reg) {
542 case MII_BMCR:
543 re8139_reg = RL_BMCR;
544 break;
545 case MII_BMSR:
546 re8139_reg = RL_BMSR;
547 break;
548 case MII_ANAR:
549 re8139_reg = RL_ANAR;
550 break;
551 case MII_ANER:
552 re8139_reg = RL_ANER;
553 break;
554 case MII_ANLPAR:
555 re8139_reg = RL_LPAR;
556 break;
557 case MII_PHYIDR1:
558 case MII_PHYIDR2:
559 return (0);
560 break;
561 default:
562 if_printf(sc->rl_ifp, "bad phy register\n");
563 return (0);
564 }
565 CSR_WRITE_2(sc, re8139_reg, data);
566 return (0);
567 }
568
569 static void
570 re_miibus_statchg(dev)
571 device_t dev;
572 {
573
574 }
575
576 /*
577 * Program the 64-bit multicast hash filter.
578 */
579 static void
580 re_setmulti(sc)
581 struct rl_softc *sc;
582 {
583 struct ifnet *ifp;
584 int h = 0;
585 u_int32_t hashes[2] = { 0, 0 };
586 struct ifmultiaddr *ifma;
587 u_int32_t rxfilt;
588 int mcnt = 0;
589
590 RL_LOCK_ASSERT(sc);
591
592 ifp = sc->rl_ifp;
593
594 rxfilt = CSR_READ_4(sc, RL_RXCFG);
595
596 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
597 rxfilt |= RL_RXCFG_RX_MULTI;
598 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
599 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
600 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
601 return;
602 }
603
604 /* first, zot all the existing hash bits */
605 CSR_WRITE_4(sc, RL_MAR0, 0);
606 CSR_WRITE_4(sc, RL_MAR4, 0);
607
608 /* now program new ones */
609 IF_ADDR_LOCK(ifp);
610 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
611 if (ifma->ifma_addr->sa_family != AF_LINK)
612 continue;
613 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
614 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
615 if (h < 32)
616 hashes[0] |= (1 << h);
617 else
618 hashes[1] |= (1 << (h - 32));
619 mcnt++;
620 }
621 IF_ADDR_UNLOCK(ifp);
622
623 if (mcnt)
624 rxfilt |= RL_RXCFG_RX_MULTI;
625 else
626 rxfilt &= ~RL_RXCFG_RX_MULTI;
627
628 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
629 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
630 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
631 }
632
633 static void
634 re_reset(sc)
635 struct rl_softc *sc;
636 {
637 register int i;
638
639 RL_LOCK_ASSERT(sc);
640
641 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
642
643 for (i = 0; i < RL_TIMEOUT; i++) {
644 DELAY(10);
645 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
646 break;
647 }
648 if (i == RL_TIMEOUT)
649 if_printf(sc->rl_ifp, "reset never completed!\n");
650
651 CSR_WRITE_1(sc, 0x82, 1);
652 }
653
654 /*
655 * The following routine is designed to test for a defect on some
656 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
657 * lines connected to the bus, however for a 32-bit only card, they
658 * should be pulled high. The result of this defect is that the
659 * NIC will not work right if you plug it into a 64-bit slot: DMA
660 * operations will be done with 64-bit transfers, which will fail
661 * because the 64-bit data lines aren't connected.
662 *
663 * There's no way to work around this (short of talking a soldering
664 * iron to the board), however we can detect it. The method we use
665 * here is to put the NIC into digital loopback mode, set the receiver
666 * to promiscuous mode, and then try to send a frame. We then compare
667 * the frame data we sent to what was received. If the data matches,
668 * then the NIC is working correctly, otherwise we know the user has
669 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
670 * slot. In the latter case, there's no way the NIC can work correctly,
671 * so we print out a message on the console and abort the device attach.
672 */
673
674 static int
675 re_diag(sc)
676 struct rl_softc *sc;
677 {
678 struct ifnet *ifp = sc->rl_ifp;
679 struct mbuf *m0;
680 struct ether_header *eh;
681 struct rl_desc *cur_rx;
682 u_int16_t status;
683 u_int32_t rxstat;
684 int total_len, i, error = 0;
685 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
686 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
687
688 /* Allocate a single mbuf */
689 MGETHDR(m0, M_DONTWAIT, MT_DATA);
690 if (m0 == NULL)
691 return (ENOBUFS);
692
693 RL_LOCK(sc);
694
695 /*
696 * Initialize the NIC in test mode. This sets the chip up
697 * so that it can send and receive frames, but performs the
698 * following special functions:
699 * - Puts receiver in promiscuous mode
700 * - Enables digital loopback mode
701 * - Leaves interrupts turned off
702 */
703
704 ifp->if_flags |= IFF_PROMISC;
705 sc->rl_testmode = 1;
706 re_init_locked(sc);
707 re_stop(sc);
708 DELAY(100000);
709 re_init_locked(sc);
710
711 /* Put some data in the mbuf */
712
713 eh = mtod(m0, struct ether_header *);
714 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
715 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
716 eh->ether_type = htons(ETHERTYPE_IP);
717 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
718
719 /*
720 * Queue the packet, start transmission.
721 * Note: IF_HANDOFF() ultimately calls re_start() for us.
722 */
723
724 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
725 RL_UNLOCK(sc);
726 /* XXX: re_diag must not be called when in ALTQ mode */
727 IF_HANDOFF(&ifp->if_snd, m0, ifp);
728 RL_LOCK(sc);
729 m0 = NULL;
730
731 /* Wait for it to propagate through the chip */
732
733 DELAY(100000);
734 for (i = 0; i < RL_TIMEOUT; i++) {
735 status = CSR_READ_2(sc, RL_ISR);
736 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
737 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
738 break;
739 DELAY(10);
740 }
741
742 if (i == RL_TIMEOUT) {
743 if_printf(ifp, "diagnostic failed, failed to receive packet "
744 "in loopback mode\n");
745 error = EIO;
746 goto done;
747 }
748
749 /*
750 * The packet should have been dumped into the first
751 * entry in the RX DMA ring. Grab it from there.
752 */
753
754 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
755 sc->rl_ldata.rl_rx_list_map,
756 BUS_DMASYNC_POSTREAD);
757 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
758 sc->rl_ldata.rl_rx_dmamap[0],
759 BUS_DMASYNC_POSTWRITE);
760 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
761 sc->rl_ldata.rl_rx_dmamap[0]);
762
763 m0 = sc->rl_ldata.rl_rx_mbuf[0];
764 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
765 eh = mtod(m0, struct ether_header *);
766
767 cur_rx = &sc->rl_ldata.rl_rx_list[0];
768 total_len = RL_RXBYTES(cur_rx);
769 rxstat = le32toh(cur_rx->rl_cmdstat);
770
771 if (total_len != ETHER_MIN_LEN) {
772 if_printf(ifp, "diagnostic failed, received short packet\n");
773 error = EIO;
774 goto done;
775 }
776
777 /* Test that the received packet data matches what we sent. */
778
779 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
780 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
781 ntohs(eh->ether_type) != ETHERTYPE_IP) {
782 if_printf(ifp, "WARNING, DMA FAILURE!\n");
783 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
784 dst, ":", src, ":", ETHERTYPE_IP);
785 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
786 eh->ether_dhost, ":", eh->ether_shost, ":",
787 ntohs(eh->ether_type));
788 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
789 "into a 64-bit PCI slot.\n");
790 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
791 "for proper operation.\n");
792 if_printf(ifp, "Read the re(4) man page for more details.\n");
793 error = EIO;
794 }
795
796 done:
797 /* Turn interface off, release resources */
798
799 sc->rl_testmode = 0;
800 ifp->if_flags &= ~IFF_PROMISC;
801 re_stop(sc);
802 if (m0 != NULL)
803 m_freem(m0);
804
805 RL_UNLOCK(sc);
806
807 return (error);
808 }
809
810 /*
811 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
812 * IDs against our list and return a device name if we find a match.
813 */
814 static int
815 re_probe(dev)
816 device_t dev;
817 {
818 struct rl_type *t;
819 struct rl_softc *sc;
820 int rid;
821 u_int32_t hwrev;
822
823 t = re_devs;
824 sc = device_get_softc(dev);
825
826 while (t->rl_name != NULL) {
827 if ((pci_get_vendor(dev) == t->rl_vid) &&
828 (pci_get_device(dev) == t->rl_did)) {
829
830 /*
831 * Temporarily map the I/O space
832 * so we can read the chip ID register.
833 */
834 rid = RL_RID;
835 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
836 RF_ACTIVE);
837 if (sc->rl_res == NULL) {
838 device_printf(dev,
839 "couldn't map ports/memory\n");
840 return (ENXIO);
841 }
842 sc->rl_btag = rman_get_bustag(sc->rl_res);
843 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
844 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
845 bus_release_resource(dev, RL_RES,
846 RL_RID, sc->rl_res);
847 if (t->rl_basetype == hwrev) {
848 device_set_desc(dev, t->rl_name);
849 return (BUS_PROBE_DEFAULT);
850 }
851 }
852 t++;
853 }
854
855 return (ENXIO);
856 }
857
858 /*
859 * This routine takes the segment list provided as the result of
860 * a bus_dma_map_load() operation and assigns the addresses/lengths
861 * to RealTek DMA descriptors. This can be called either by the RX
862 * code or the TX code. In the RX case, we'll probably wind up mapping
863 * at most one segment. For the TX case, there could be any number of
864 * segments since TX packets may span multiple mbufs. In either case,
865 * if the number of segments is larger than the rl_maxsegs limit
866 * specified by the caller, we abort the mapping operation. Sadly,
867 * whoever designed the buffer mapping API did not provide a way to
868 * return an error from here, so we have to fake it a bit.
869 */
870
871 static void
872 re_dma_map_desc(arg, segs, nseg, mapsize, error)
873 void *arg;
874 bus_dma_segment_t *segs;
875 int nseg;
876 bus_size_t mapsize;
877 int error;
878 {
879 struct rl_dmaload_arg *ctx;
880 struct rl_desc *d = NULL;
881 int i = 0, idx;
882
883 if (error)
884 return;
885
886 ctx = arg;
887
888 /* Signal error to caller if there's too many segments */
889 if (nseg > ctx->rl_maxsegs) {
890 ctx->rl_maxsegs = 0;
891 return;
892 }
893
894 /*
895 * Map the segment array into descriptors. Note that we set the
896 * start-of-frame and end-of-frame markers for either TX or RX, but
897 * they really only have meaning in the TX case. (In the RX case,
898 * it's the chip that tells us where packets begin and end.)
899 * We also keep track of the end of the ring and set the
900 * end-of-ring bits as needed, and we set the ownership bits
901 * in all except the very first descriptor. (The caller will
902 * set this descriptor later when it start transmission or
903 * reception.)
904 */
905 idx = ctx->rl_idx;
906 for (;;) {
907 u_int32_t cmdstat;
908 d = &ctx->rl_ring[idx];
909 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
910 ctx->rl_maxsegs = 0;
911 return;
912 }
913 cmdstat = segs[i].ds_len;
914 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
915 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
916 if (i == 0)
917 cmdstat |= RL_TDESC_CMD_SOF;
918 else
919 cmdstat |= RL_TDESC_CMD_OWN;
920 if (idx == (RL_RX_DESC_CNT - 1))
921 cmdstat |= RL_TDESC_CMD_EOR;
922 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
923 i++;
924 if (i == nseg)
925 break;
926 RL_DESC_INC(idx);
927 }
928
929 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
930 ctx->rl_maxsegs = nseg;
931 ctx->rl_idx = idx;
932 }
933
934 /*
935 * Map a single buffer address.
936 */
937
938 static void
939 re_dma_map_addr(arg, segs, nseg, error)
940 void *arg;
941 bus_dma_segment_t *segs;
942 int nseg;
943 int error;
944 {
945 bus_addr_t *addr;
946
947 if (error)
948 return;
949
950 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
951 addr = arg;
952 *addr = segs->ds_addr;
953 }
954
955 static int
956 re_allocmem(dev, sc)
957 device_t dev;
958 struct rl_softc *sc;
959 {
960 int error;
961 int nseg;
962 int i;
963
964 /*
965 * Allocate map for RX mbufs.
966 */
967 nseg = 32;
968 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
969 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
970 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
971 NULL, NULL, &sc->rl_ldata.rl_mtag);
972 if (error) {
973 device_printf(dev, "could not allocate dma tag\n");
974 return (ENOMEM);
975 }
976
977 /*
978 * Allocate map for TX descriptor list.
979 */
980 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
981 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
982 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
983 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
984 if (error) {
985 device_printf(dev, "could not allocate dma tag\n");
986 return (ENOMEM);
987 }
988
989 /* Allocate DMA'able memory for the TX ring */
990
991 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
992 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
993 &sc->rl_ldata.rl_tx_list_map);
994 if (error)
995 return (ENOMEM);
996
997 /* Load the map for the TX ring. */
998
999 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1000 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1001 RL_TX_LIST_SZ, re_dma_map_addr,
1002 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1003
1004 /* Create DMA maps for TX buffers */
1005
1006 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1007 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1008 &sc->rl_ldata.rl_tx_dmamap[i]);
1009 if (error) {
1010 device_printf(dev, "can't create DMA map for TX\n");
1011 return (ENOMEM);
1012 }
1013 }
1014
1015 /*
1016 * Allocate map for RX descriptor list.
1017 */
1018 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1019 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1020 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1021 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1022 if (error) {
1023 device_printf(dev, "could not allocate dma tag\n");
1024 return (ENOMEM);
1025 }
1026
1027 /* Allocate DMA'able memory for the RX ring */
1028
1029 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1030 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1031 &sc->rl_ldata.rl_rx_list_map);
1032 if (error)
1033 return (ENOMEM);
1034
1035 /* Load the map for the RX ring. */
1036
1037 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1038 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1039 RL_RX_LIST_SZ, re_dma_map_addr,
1040 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1041
1042 /* Create DMA maps for RX buffers */
1043
1044 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1045 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1046 &sc->rl_ldata.rl_rx_dmamap[i]);
1047 if (error) {
1048 device_printf(dev, "can't create DMA map for RX\n");
1049 return (ENOMEM);
1050 }
1051 }
1052
1053 return (0);
1054 }
1055
1056 /*
1057 * Attach the interface. Allocate softc structures, do ifmedia
1058 * setup and ethernet/BPF attach.
1059 */
1060 static int
1061 re_attach(dev)
1062 device_t dev;
1063 {
1064 u_char eaddr[ETHER_ADDR_LEN];
1065 u_int16_t as[3];
1066 struct rl_softc *sc;
1067 struct ifnet *ifp;
1068 struct rl_hwrev *hw_rev;
1069 int hwrev;
1070 u_int16_t re_did = 0;
1071 int error = 0, rid, i;
1072
1073 sc = device_get_softc(dev);
1074
1075 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1076 MTX_DEF);
1077 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1078
1079 /*
1080 * Map control/status registers.
1081 */
1082 pci_enable_busmaster(dev);
1083
1084 rid = RL_RID;
1085 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1086 RF_ACTIVE);
1087
1088 if (sc->rl_res == NULL) {
1089 device_printf(dev, "couldn't map ports/memory\n");
1090 error = ENXIO;
1091 goto fail;
1092 }
1093
1094 sc->rl_btag = rman_get_bustag(sc->rl_res);
1095 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1096
1097 /* Allocate interrupt */
1098 rid = 0;
1099 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1100 RF_SHAREABLE | RF_ACTIVE);
1101
1102 if (sc->rl_irq == NULL) {
1103 device_printf(dev, "couldn't map interrupt\n");
1104 error = ENXIO;
1105 goto fail;
1106 }
1107
1108 /* Reset the adapter. */
1109 RL_LOCK(sc);
1110 re_reset(sc);
1111 RL_UNLOCK(sc);
1112
1113 hw_rev = re_hwrevs;
1114 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1115 while (hw_rev->rl_desc != NULL) {
1116 if (hw_rev->rl_rev == hwrev) {
1117 sc->rl_type = hw_rev->rl_type;
1118 break;
1119 }
1120 hw_rev++;
1121 }
1122
1123 if (sc->rl_type == RL_8169) {
1124
1125 /* Set RX length mask */
1126
1127 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1128
1129 /* Force station address autoload from the EEPROM */
1130
1131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1132 for (i = 0; i < RL_TIMEOUT; i++) {
1133 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1134 break;
1135 DELAY(100);
1136 }
1137 if (i == RL_TIMEOUT)
1138 device_printf(dev, "eeprom autoload timed out\n");
1139
1140 for (i = 0; i < ETHER_ADDR_LEN; i++)
1141 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1142 } else {
1143
1144 /* Set RX length mask */
1145
1146 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1147
1148 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1149 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1150 if (re_did != 0x8129)
1151 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1152
1153 /*
1154 * Get station address from the EEPROM.
1155 */
1156 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1157 for (i = 0; i < 3; i++) {
1158 eaddr[(i * 2) + 0] = as[i] & 0xff;
1159 eaddr[(i * 2) + 1] = as[i] >> 8;
1160 }
1161 }
1162
1163 /*
1164 * Allocate the parent bus DMA tag appropriate for PCI.
1165 */
1166 #define RL_NSEG_NEW 32
1167 error = bus_dma_tag_create(NULL, /* parent */
1168 1, 0, /* alignment, boundary */
1169 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1170 BUS_SPACE_MAXADDR, /* highaddr */
1171 NULL, NULL, /* filter, filterarg */
1172 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1173 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1174 BUS_DMA_ALLOCNOW, /* flags */
1175 NULL, NULL, /* lockfunc, lockarg */
1176 &sc->rl_parent_tag);
1177 if (error)
1178 goto fail;
1179
1180 error = re_allocmem(dev, sc);
1181
1182 if (error)
1183 goto fail;
1184
1185 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1186 if (ifp == NULL) {
1187 device_printf(dev, "can not if_alloc()\n");
1188 error = ENOSPC;
1189 goto fail;
1190 }
1191
1192 /* Do MII setup */
1193 if (mii_phy_probe(dev, &sc->rl_miibus,
1194 re_ifmedia_upd, re_ifmedia_sts)) {
1195 device_printf(dev, "MII without any phy!\n");
1196 error = ENXIO;
1197 goto fail;
1198 }
1199
1200 ifp->if_softc = sc;
1201 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1202 ifp->if_mtu = ETHERMTU;
1203 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1204 ifp->if_ioctl = re_ioctl;
1205 ifp->if_capabilities = IFCAP_VLAN_MTU;
1206 ifp->if_start = re_start;
1207 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1208 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1209 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1210 #ifdef DEVICE_POLLING
1211 ifp->if_capabilities |= IFCAP_POLLING;
1212 #endif
1213 ifp->if_watchdog = re_watchdog;
1214 ifp->if_init = re_init;
1215 if (sc->rl_type == RL_8169)
1216 ifp->if_baudrate = 1000000000;
1217 else
1218 ifp->if_baudrate = 100000000;
1219 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1220 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1221 IFQ_SET_READY(&ifp->if_snd);
1222
1223 /*
1224 * Call MI attach routine.
1225 */
1226 ether_ifattach(ifp, eaddr);
1227
1228 /* Perform hardware diagnostic. */
1229 error = re_diag(sc);
1230
1231 if (error) {
1232 device_printf(dev, "attach aborted due to hardware diag failure\n");
1233 ether_ifdetach(ifp);
1234 goto fail;
1235 }
1236
1237 /* Hook interrupt last to avoid having to lock softc */
1238 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1239 re_intr, sc, &sc->rl_intrhand);
1240 if (error) {
1241 device_printf(dev, "couldn't set up irq\n");
1242 ether_ifdetach(ifp);
1243 }
1244
1245 fail:
1246 if (error)
1247 re_detach(dev);
1248
1249 return (error);
1250 }
1251
1252 /*
1253 * Shutdown hardware and free up resources. This can be called any
1254 * time after the mutex has been initialized. It is called in both
1255 * the error case in attach and the normal detach case so it needs
1256 * to be careful about only freeing resources that have actually been
1257 * allocated.
1258 */
1259 static int
1260 re_detach(dev)
1261 device_t dev;
1262 {
1263 struct rl_softc *sc;
1264 struct ifnet *ifp;
1265 int i;
1266
1267 sc = device_get_softc(dev);
1268 ifp = sc->rl_ifp;
1269 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1270
1271 #ifdef DEVICE_POLLING
1272 if (ifp->if_capenable & IFCAP_POLLING)
1273 ether_poll_deregister(ifp);
1274 #endif
1275 /* These should only be active if attach succeeded */
1276 if (device_is_attached(dev)) {
1277 RL_LOCK(sc);
1278 #if 0
1279 sc->suspended = 1;
1280 #endif
1281 re_stop(sc);
1282 RL_UNLOCK(sc);
1283 callout_drain(&sc->rl_stat_callout);
1284 /*
1285 * Force off the IFF_UP flag here, in case someone
1286 * still had a BPF descriptor attached to this
1287 * interface. If they do, ether_ifdetach() will cause
1288 * the BPF code to try and clear the promisc mode
1289 * flag, which will bubble down to re_ioctl(),
1290 * which will try to call re_init() again. This will
1291 * turn the NIC back on and restart the MII ticker,
1292 * which will panic the system when the kernel tries
1293 * to invoke the re_tick() function that isn't there
1294 * anymore.
1295 */
1296 ifp->if_flags &= ~IFF_UP;
1297 ether_ifdetach(ifp);
1298 }
1299 if (sc->rl_miibus)
1300 device_delete_child(dev, sc->rl_miibus);
1301 bus_generic_detach(dev);
1302
1303 /*
1304 * The rest is resource deallocation, so we should already be
1305 * stopped here.
1306 */
1307
1308 if (sc->rl_intrhand)
1309 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1310 if (ifp != NULL)
1311 if_free(ifp);
1312 if (sc->rl_irq)
1313 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1314 if (sc->rl_res)
1315 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1316
1317
1318 /* Unload and free the RX DMA ring memory and map */
1319
1320 if (sc->rl_ldata.rl_rx_list_tag) {
1321 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1322 sc->rl_ldata.rl_rx_list_map);
1323 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1324 sc->rl_ldata.rl_rx_list,
1325 sc->rl_ldata.rl_rx_list_map);
1326 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1327 }
1328
1329 /* Unload and free the TX DMA ring memory and map */
1330
1331 if (sc->rl_ldata.rl_tx_list_tag) {
1332 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1333 sc->rl_ldata.rl_tx_list_map);
1334 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1335 sc->rl_ldata.rl_tx_list,
1336 sc->rl_ldata.rl_tx_list_map);
1337 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1338 }
1339
1340 /* Destroy all the RX and TX buffer maps */
1341
1342 if (sc->rl_ldata.rl_mtag) {
1343 for (i = 0; i < RL_TX_DESC_CNT; i++)
1344 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1345 sc->rl_ldata.rl_tx_dmamap[i]);
1346 for (i = 0; i < RL_RX_DESC_CNT; i++)
1347 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1348 sc->rl_ldata.rl_rx_dmamap[i]);
1349 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1350 }
1351
1352 /* Unload and free the stats buffer and map */
1353
1354 if (sc->rl_ldata.rl_stag) {
1355 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1356 sc->rl_ldata.rl_rx_list_map);
1357 bus_dmamem_free(sc->rl_ldata.rl_stag,
1358 sc->rl_ldata.rl_stats,
1359 sc->rl_ldata.rl_smap);
1360 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1361 }
1362
1363 if (sc->rl_parent_tag)
1364 bus_dma_tag_destroy(sc->rl_parent_tag);
1365
1366 mtx_destroy(&sc->rl_mtx);
1367
1368 return (0);
1369 }
1370
1371 static int
1372 re_newbuf(sc, idx, m)
1373 struct rl_softc *sc;
1374 int idx;
1375 struct mbuf *m;
1376 {
1377 struct rl_dmaload_arg arg;
1378 struct mbuf *n = NULL;
1379 int error;
1380
1381 if (m == NULL) {
1382 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1383 if (n == NULL)
1384 return (ENOBUFS);
1385 m = n;
1386 } else
1387 m->m_data = m->m_ext.ext_buf;
1388
1389 m->m_len = m->m_pkthdr.len = MCLBYTES;
1390 #ifdef RE_FIXUP_RX
1391 /*
1392 * This is part of an evil trick to deal with non-x86 platforms.
1393 * The RealTek chip requires RX buffers to be aligned on 64-bit
1394 * boundaries, but that will hose non-x86 machines. To get around
1395 * this, we leave some empty space at the start of each buffer
1396 * and for non-x86 hosts, we copy the buffer back six bytes
1397 * to achieve word alignment. This is slightly more efficient
1398 * than allocating a new buffer, copying the contents, and
1399 * discarding the old buffer.
1400 */
1401 m_adj(m, RE_ETHER_ALIGN);
1402 #endif
1403 arg.sc = sc;
1404 arg.rl_idx = idx;
1405 arg.rl_maxsegs = 1;
1406 arg.rl_flags = 0;
1407 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1408
1409 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1410 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1411 &arg, BUS_DMA_NOWAIT);
1412 if (error || arg.rl_maxsegs != 1) {
1413 if (n != NULL)
1414 m_freem(n);
1415 return (ENOMEM);
1416 }
1417
1418 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1419 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1420
1421 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1422 sc->rl_ldata.rl_rx_dmamap[idx],
1423 BUS_DMASYNC_PREREAD);
1424
1425 return (0);
1426 }
1427
1428 #ifdef RE_FIXUP_RX
1429 static __inline void
1430 re_fixup_rx(m)
1431 struct mbuf *m;
1432 {
1433 int i;
1434 uint16_t *src, *dst;
1435
1436 src = mtod(m, uint16_t *);
1437 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1438
1439 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1440 *dst++ = *src++;
1441
1442 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1443
1444 return;
1445 }
1446 #endif
1447
1448 static int
1449 re_tx_list_init(sc)
1450 struct rl_softc *sc;
1451 {
1452
1453 RL_LOCK_ASSERT(sc);
1454
1455 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1456 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1457 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1458
1459 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1460 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1461 sc->rl_ldata.rl_tx_prodidx = 0;
1462 sc->rl_ldata.rl_tx_considx = 0;
1463 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1464
1465 return (0);
1466 }
1467
1468 static int
1469 re_rx_list_init(sc)
1470 struct rl_softc *sc;
1471 {
1472 int i;
1473
1474 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1475 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1476 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1477
1478 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1479 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1480 return (ENOBUFS);
1481 }
1482
1483 /* Flush the RX descriptors */
1484
1485 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1486 sc->rl_ldata.rl_rx_list_map,
1487 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1488
1489 sc->rl_ldata.rl_rx_prodidx = 0;
1490 sc->rl_head = sc->rl_tail = NULL;
1491
1492 return (0);
1493 }
1494
1495 /*
1496 * RX handler for C+ and 8169. For the gigE chips, we support
1497 * the reception of jumbo frames that have been fragmented
1498 * across multiple 2K mbuf cluster buffers.
1499 */
1500 static void
1501 re_rxeof(sc)
1502 struct rl_softc *sc;
1503 {
1504 struct mbuf *m;
1505 struct ifnet *ifp;
1506 int i, total_len;
1507 struct rl_desc *cur_rx;
1508 u_int32_t rxstat, rxvlan;
1509
1510 RL_LOCK_ASSERT(sc);
1511
1512 ifp = sc->rl_ifp;
1513 i = sc->rl_ldata.rl_rx_prodidx;
1514
1515 /* Invalidate the descriptor memory */
1516
1517 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1518 sc->rl_ldata.rl_rx_list_map,
1519 BUS_DMASYNC_POSTREAD);
1520
1521 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1522 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1523 m = sc->rl_ldata.rl_rx_mbuf[i];
1524 total_len = RL_RXBYTES(cur_rx);
1525 rxstat = le32toh(cur_rx->rl_cmdstat);
1526 rxvlan = le32toh(cur_rx->rl_vlanctl);
1527
1528 /* Invalidate the RX mbuf and unload its map */
1529
1530 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1531 sc->rl_ldata.rl_rx_dmamap[i],
1532 BUS_DMASYNC_POSTWRITE);
1533 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1534 sc->rl_ldata.rl_rx_dmamap[i]);
1535
1536 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1537 m->m_len = RE_RX_DESC_BUFLEN;
1538 if (sc->rl_head == NULL)
1539 sc->rl_head = sc->rl_tail = m;
1540 else {
1541 m->m_flags &= ~M_PKTHDR;
1542 sc->rl_tail->m_next = m;
1543 sc->rl_tail = m;
1544 }
1545 re_newbuf(sc, i, NULL);
1546 RL_DESC_INC(i);
1547 continue;
1548 }
1549
1550 /*
1551 * NOTE: for the 8139C+, the frame length field
1552 * is always 12 bits in size, but for the gigE chips,
1553 * it is 13 bits (since the max RX frame length is 16K).
1554 * Unfortunately, all 32 bits in the status word
1555 * were already used, so to make room for the extra
1556 * length bit, RealTek took out the 'frame alignment
1557 * error' bit and shifted the other status bits
1558 * over one slot. The OWN, EOR, FS and LS bits are
1559 * still in the same places. We have already extracted
1560 * the frame length and checked the OWN bit, so rather
1561 * than using an alternate bit mapping, we shift the
1562 * status bits one space to the right so we can evaluate
1563 * them using the 8169 status as though it was in the
1564 * same format as that of the 8139C+.
1565 */
1566 if (sc->rl_type == RL_8169)
1567 rxstat >>= 1;
1568
1569 /*
1570 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1571 * set, but if CRC is clear, it will still be a valid frame.
1572 */
1573 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1574 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1575 ifp->if_ierrors++;
1576 /*
1577 * If this is part of a multi-fragment packet,
1578 * discard all the pieces.
1579 */
1580 if (sc->rl_head != NULL) {
1581 m_freem(sc->rl_head);
1582 sc->rl_head = sc->rl_tail = NULL;
1583 }
1584 re_newbuf(sc, i, m);
1585 RL_DESC_INC(i);
1586 continue;
1587 }
1588
1589 /*
1590 * If allocating a replacement mbuf fails,
1591 * reload the current one.
1592 */
1593
1594 if (re_newbuf(sc, i, NULL)) {
1595 ifp->if_ierrors++;
1596 if (sc->rl_head != NULL) {
1597 m_freem(sc->rl_head);
1598 sc->rl_head = sc->rl_tail = NULL;
1599 }
1600 re_newbuf(sc, i, m);
1601 RL_DESC_INC(i);
1602 continue;
1603 }
1604
1605 RL_DESC_INC(i);
1606
1607 if (sc->rl_head != NULL) {
1608 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1609 if (m->m_len == 0)
1610 m->m_len = RE_RX_DESC_BUFLEN;
1611 /*
1612 * Special case: if there's 4 bytes or less
1613 * in this buffer, the mbuf can be discarded:
1614 * the last 4 bytes is the CRC, which we don't
1615 * care about anyway.
1616 */
1617 if (m->m_len <= ETHER_CRC_LEN) {
1618 sc->rl_tail->m_len -=
1619 (ETHER_CRC_LEN - m->m_len);
1620 m_freem(m);
1621 } else {
1622 m->m_len -= ETHER_CRC_LEN;
1623 m->m_flags &= ~M_PKTHDR;
1624 sc->rl_tail->m_next = m;
1625 }
1626 m = sc->rl_head;
1627 sc->rl_head = sc->rl_tail = NULL;
1628 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1629 } else
1630 m->m_pkthdr.len = m->m_len =
1631 (total_len - ETHER_CRC_LEN);
1632
1633 #ifdef RE_FIXUP_RX
1634 re_fixup_rx(m);
1635 #endif
1636 ifp->if_ipackets++;
1637 m->m_pkthdr.rcvif = ifp;
1638
1639 /* Do RX checksumming if enabled */
1640
1641 if (ifp->if_capenable & IFCAP_RXCSUM) {
1642
1643 /* Check IP header checksum */
1644 if (rxstat & RL_RDESC_STAT_PROTOID)
1645 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1646 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1647 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1648
1649 /* Check TCP/UDP checksum */
1650 if ((RL_TCPPKT(rxstat) &&
1651 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1652 (RL_UDPPKT(rxstat) &&
1653 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1654 m->m_pkthdr.csum_flags |=
1655 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1656 m->m_pkthdr.csum_data = 0xffff;
1657 }
1658 }
1659
1660 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1661 VLAN_INPUT_TAG(ifp, m,
1662 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1663 RL_UNLOCK(sc);
1664 (*ifp->if_input)(ifp, m);
1665 RL_LOCK(sc);
1666 }
1667
1668 /* Flush the RX DMA ring */
1669
1670 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1671 sc->rl_ldata.rl_rx_list_map,
1672 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1673
1674 sc->rl_ldata.rl_rx_prodidx = i;
1675 }
1676
1677 static void
1678 re_txeof(sc)
1679 struct rl_softc *sc;
1680 {
1681 struct ifnet *ifp;
1682 u_int32_t txstat;
1683 int idx;
1684
1685 ifp = sc->rl_ifp;
1686 idx = sc->rl_ldata.rl_tx_considx;
1687
1688 /* Invalidate the TX descriptor list */
1689
1690 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1691 sc->rl_ldata.rl_tx_list_map,
1692 BUS_DMASYNC_POSTREAD);
1693
1694 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1695
1696 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1697 if (txstat & RL_TDESC_CMD_OWN)
1698 break;
1699
1700 /*
1701 * We only stash mbufs in the last descriptor
1702 * in a fragment chain, which also happens to
1703 * be the only place where the TX status bits
1704 * are valid.
1705 */
1706
1707 if (txstat & RL_TDESC_CMD_EOF) {
1708 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1709 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1710 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1711 sc->rl_ldata.rl_tx_dmamap[idx]);
1712 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1713 RL_TDESC_STAT_COLCNT))
1714 ifp->if_collisions++;
1715 if (txstat & RL_TDESC_STAT_TXERRSUM)
1716 ifp->if_oerrors++;
1717 else
1718 ifp->if_opackets++;
1719 }
1720 sc->rl_ldata.rl_tx_free++;
1721 RL_DESC_INC(idx);
1722 }
1723
1724 /* No changes made to the TX ring, so no flush needed */
1725
1726 if (idx != sc->rl_ldata.rl_tx_considx) {
1727 sc->rl_ldata.rl_tx_considx = idx;
1728 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1729 ifp->if_timer = 0;
1730 }
1731
1732 /*
1733 * If not all descriptors have been released reaped yet,
1734 * reload the timer so that we will eventually get another
1735 * interrupt that will cause us to re-enter this routine.
1736 * This is done in case the transmitter has gone idle.
1737 */
1738 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1739 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1740 }
1741
1742 static void
1743 re_tick(xsc)
1744 void *xsc;
1745 {
1746 struct rl_softc *sc;
1747 struct mii_data *mii;
1748
1749 sc = xsc;
1750
1751 RL_LOCK_ASSERT(sc);
1752
1753 mii = device_get_softc(sc->rl_miibus);
1754
1755 mii_tick(mii);
1756
1757 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1758 }
1759
1760 #ifdef DEVICE_POLLING
1761 static void
1762 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1763 {
1764 struct rl_softc *sc = ifp->if_softc;
1765
1766 RL_LOCK(sc);
1767 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1768 re_poll_locked(ifp, cmd, count);
1769 RL_UNLOCK(sc);
1770 }
1771
1772 static void
1773 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1774 {
1775 struct rl_softc *sc = ifp->if_softc;
1776
1777 RL_LOCK_ASSERT(sc);
1778
1779 sc->rxcycles = count;
1780 re_rxeof(sc);
1781 re_txeof(sc);
1782
1783 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1784 re_start_locked(ifp);
1785
1786 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1787 u_int16_t status;
1788
1789 status = CSR_READ_2(sc, RL_ISR);
1790 if (status == 0xffff)
1791 return;
1792 if (status)
1793 CSR_WRITE_2(sc, RL_ISR, status);
1794
1795 /*
1796 * XXX check behaviour on receiver stalls.
1797 */
1798
1799 if (status & RL_ISR_SYSTEM_ERR) {
1800 re_reset(sc);
1801 re_init_locked(sc);
1802 }
1803 }
1804 }
1805 #endif /* DEVICE_POLLING */
1806
1807 static void
1808 re_intr(arg)
1809 void *arg;
1810 {
1811 struct rl_softc *sc;
1812 struct ifnet *ifp;
1813 u_int16_t status;
1814
1815 sc = arg;
1816
1817 RL_LOCK(sc);
1818
1819 ifp = sc->rl_ifp;
1820
1821 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1822 goto done_locked;
1823
1824 #ifdef DEVICE_POLLING
1825 if (ifp->if_capenable & IFCAP_POLLING)
1826 goto done_locked;
1827 #endif
1828
1829 for (;;) {
1830
1831 status = CSR_READ_2(sc, RL_ISR);
1832 /* If the card has gone away the read returns 0xffff. */
1833 if (status == 0xffff)
1834 break;
1835 if (status)
1836 CSR_WRITE_2(sc, RL_ISR, status);
1837
1838 if ((status & RL_INTRS_CPLUS) == 0)
1839 break;
1840
1841 if ((status & RL_ISR_RX_OK) ||
1842 (status & RL_ISR_RX_ERR))
1843 re_rxeof(sc);
1844
1845 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1846 (status & RL_ISR_TX_ERR) ||
1847 (status & RL_ISR_TX_DESC_UNAVAIL))
1848 re_txeof(sc);
1849
1850 if (status & RL_ISR_SYSTEM_ERR) {
1851 re_reset(sc);
1852 re_init_locked(sc);
1853 }
1854
1855 if (status & RL_ISR_LINKCHG) {
1856 callout_stop(&sc->rl_stat_callout);
1857 re_tick(sc);
1858 }
1859 }
1860
1861 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1862 re_start_locked(ifp);
1863
1864 done_locked:
1865 RL_UNLOCK(sc);
1866 }
1867
1868 static int
1869 re_encap(sc, m_head, idx)
1870 struct rl_softc *sc;
1871 struct mbuf **m_head;
1872 int *idx;
1873 {
1874 struct mbuf *m_new = NULL;
1875 struct rl_dmaload_arg arg;
1876 bus_dmamap_t map;
1877 int error;
1878 struct m_tag *mtag;
1879
1880 RL_LOCK_ASSERT(sc);
1881
1882 if (sc->rl_ldata.rl_tx_free <= 4)
1883 return (EFBIG);
1884
1885 /*
1886 * Set up checksum offload. Note: checksum offload bits must
1887 * appear in all descriptors of a multi-descriptor transmit
1888 * attempt. This is according to testing done with an 8169
1889 * chip. This is a requirement.
1890 */
1891
1892 arg.rl_flags = 0;
1893
1894 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1895 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1896 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1897 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1898 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1899 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1900
1901 arg.sc = sc;
1902 arg.rl_idx = *idx;
1903 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1904 if (arg.rl_maxsegs > 4)
1905 arg.rl_maxsegs -= 4;
1906 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1907
1908 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1909 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1910 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1911
1912 if (error && error != EFBIG) {
1913 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error);
1914 return (ENOBUFS);
1915 }
1916
1917 /* Too many segments to map, coalesce into a single mbuf */
1918
1919 if (error || arg.rl_maxsegs == 0) {
1920 m_new = m_defrag(*m_head, M_DONTWAIT);
1921 if (m_new == NULL)
1922 return (ENOBUFS);
1923 else
1924 *m_head = m_new;
1925
1926 arg.sc = sc;
1927 arg.rl_idx = *idx;
1928 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1929 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1930
1931 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1932 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1933 if (error) {
1934 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n",
1935 error);
1936 return (EFBIG);
1937 }
1938 }
1939
1940 /*
1941 * Insure that the map for this transmission
1942 * is placed at the array index of the last descriptor
1943 * in this chain. (Swap last and first dmamaps.)
1944 */
1945 sc->rl_ldata.rl_tx_dmamap[*idx] =
1946 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1947 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1948
1949 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1950 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1951
1952 /*
1953 * Set up hardware VLAN tagging. Note: vlan tag info must
1954 * appear in the first descriptor of a multi-descriptor
1955 * transmission attempt.
1956 */
1957
1958 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
1959 if (mtag != NULL)
1960 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1961 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1962
1963 /* Transfer ownership of packet to the chip. */
1964
1965 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1966 htole32(RL_TDESC_CMD_OWN);
1967 if (*idx != arg.rl_idx)
1968 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1969 htole32(RL_TDESC_CMD_OWN);
1970
1971 RL_DESC_INC(arg.rl_idx);
1972 *idx = arg.rl_idx;
1973
1974 return (0);
1975 }
1976
1977 static void
1978 re_start(ifp)
1979 struct ifnet *ifp;
1980 {
1981 struct rl_softc *sc;
1982
1983 sc = ifp->if_softc;
1984 RL_LOCK(sc);
1985 re_start_locked(ifp);
1986 RL_UNLOCK(sc);
1987 }
1988
1989 /*
1990 * Main transmit routine for C+ and gigE NICs.
1991 */
1992 static void
1993 re_start_locked(ifp)
1994 struct ifnet *ifp;
1995 {
1996 struct rl_softc *sc;
1997 struct mbuf *m_head = NULL;
1998 int idx, queued = 0;
1999
2000 sc = ifp->if_softc;
2001
2002 RL_LOCK_ASSERT(sc);
2003
2004 idx = sc->rl_ldata.rl_tx_prodidx;
2005
2006 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2007 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2008 if (m_head == NULL)
2009 break;
2010
2011 if (re_encap(sc, &m_head, &idx)) {
2012 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2013 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2014 break;
2015 }
2016
2017 /*
2018 * If there's a BPF listener, bounce a copy of this frame
2019 * to him.
2020 */
2021 BPF_MTAP(ifp, m_head);
2022
2023 queued++;
2024 }
2025
2026 if (queued == 0)
2027 return;
2028
2029 /* Flush the TX descriptors */
2030
2031 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2032 sc->rl_ldata.rl_tx_list_map,
2033 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2034
2035 sc->rl_ldata.rl_tx_prodidx = idx;
2036
2037 /*
2038 * RealTek put the TX poll request register in a different
2039 * location on the 8169 gigE chip. I don't know why.
2040 */
2041
2042 if (sc->rl_type == RL_8169)
2043 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2044 else
2045 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2046
2047 /*
2048 * Use the countdown timer for interrupt moderation.
2049 * 'TX done' interrupts are disabled. Instead, we reset the
2050 * countdown timer, which will begin counting until it hits
2051 * the value in the TIMERINT register, and then trigger an
2052 * interrupt. Each time we write to the TIMERCNT register,
2053 * the timer count is reset to 0.
2054 */
2055 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2056
2057 /*
2058 * Set a timeout in case the chip goes out to lunch.
2059 */
2060 ifp->if_timer = 5;
2061 }
2062
2063 static void
2064 re_init(xsc)
2065 void *xsc;
2066 {
2067 struct rl_softc *sc = xsc;
2068
2069 RL_LOCK(sc);
2070 re_init_locked(sc);
2071 RL_UNLOCK(sc);
2072 }
2073
2074 static void
2075 re_init_locked(sc)
2076 struct rl_softc *sc;
2077 {
2078 struct ifnet *ifp = sc->rl_ifp;
2079 struct mii_data *mii;
2080 u_int32_t rxcfg = 0;
2081
2082 RL_LOCK_ASSERT(sc);
2083
2084 mii = device_get_softc(sc->rl_miibus);
2085
2086 /*
2087 * Cancel pending I/O and free all RX/TX buffers.
2088 */
2089 re_stop(sc);
2090
2091 /*
2092 * Enable C+ RX and TX mode, as well as VLAN stripping and
2093 * RX checksum offload. We must configure the C+ register
2094 * before all others.
2095 */
2096 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2097 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2098 RL_CPLUSCMD_VLANSTRIP|
2099 (ifp->if_capenable & IFCAP_RXCSUM ?
2100 RL_CPLUSCMD_RXCSUM_ENB : 0));
2101
2102 /*
2103 * Init our MAC address. Even though the chipset
2104 * documentation doesn't mention it, we need to enter "Config
2105 * register write enable" mode to modify the ID registers.
2106 */
2107 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2108 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2109 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
2110 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2111 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
2112 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2113
2114 /*
2115 * For C+ mode, initialize the RX descriptors and mbufs.
2116 */
2117 re_rx_list_init(sc);
2118 re_tx_list_init(sc);
2119
2120 /*
2121 * Enable transmit and receive.
2122 */
2123 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2124
2125 /*
2126 * Set the initial TX and RX configuration.
2127 */
2128 if (sc->rl_testmode) {
2129 if (sc->rl_type == RL_8169)
2130 CSR_WRITE_4(sc, RL_TXCFG,
2131 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2132 else
2133 CSR_WRITE_4(sc, RL_TXCFG,
2134 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2135 } else
2136 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2137 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2138
2139 /* Set the individual bit to receive frames for this host only. */
2140 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2141 rxcfg |= RL_RXCFG_RX_INDIV;
2142
2143 /* If we want promiscuous mode, set the allframes bit. */
2144 if (ifp->if_flags & IFF_PROMISC)
2145 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2146 else
2147 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2148 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2149
2150 /*
2151 * Set capture broadcast bit to capture broadcast frames.
2152 */
2153 if (ifp->if_flags & IFF_BROADCAST)
2154 rxcfg |= RL_RXCFG_RX_BROAD;
2155 else
2156 rxcfg &= ~RL_RXCFG_RX_BROAD;
2157 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2158
2159 /*
2160 * Program the multicast filter, if necessary.
2161 */
2162 re_setmulti(sc);
2163
2164 #ifdef DEVICE_POLLING
2165 /*
2166 * Disable interrupts if we are polling.
2167 */
2168 if (ifp->if_capenable & IFCAP_POLLING)
2169 CSR_WRITE_2(sc, RL_IMR, 0);
2170 else /* otherwise ... */
2171 #endif
2172 /*
2173 * Enable interrupts.
2174 */
2175 if (sc->rl_testmode)
2176 CSR_WRITE_2(sc, RL_IMR, 0);
2177 else
2178 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2179
2180 /* Set initial TX threshold */
2181 sc->rl_txthresh = RL_TX_THRESH_INIT;
2182
2183 /* Start RX/TX process. */
2184 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2185 #ifdef notdef
2186 /* Enable receiver and transmitter. */
2187 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2188 #endif
2189 /*
2190 * Load the addresses of the RX and TX lists into the chip.
2191 */
2192
2193 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2194 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2195 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2196 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2197
2198 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2199 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2200 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2201 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2202
2203 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2204
2205 /*
2206 * Initialize the timer interrupt register so that
2207 * a timer interrupt will be generated once the timer
2208 * reaches a certain number of ticks. The timer is
2209 * reloaded on each transmit. This gives us TX interrupt
2210 * moderation, which dramatically improves TX frame rate.
2211 */
2212 if (sc->rl_type == RL_8169)
2213 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2214 else
2215 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2216
2217 /*
2218 * For 8169 gigE NICs, set the max allowed RX packet
2219 * size so we can receive jumbo frames.
2220 */
2221 if (sc->rl_type == RL_8169)
2222 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2223
2224 if (sc->rl_testmode)
2225 return;
2226
2227 mii_mediachg(mii);
2228
2229 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2230
2231 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2232 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2233
2234 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2235 }
2236
2237 /*
2238 * Set media options.
2239 */
2240 static int
2241 re_ifmedia_upd(ifp)
2242 struct ifnet *ifp;
2243 {
2244 struct rl_softc *sc;
2245 struct mii_data *mii;
2246
2247 sc = ifp->if_softc;
2248 mii = device_get_softc(sc->rl_miibus);
2249 RL_LOCK(sc);
2250 mii_mediachg(mii);
2251 RL_UNLOCK(sc);
2252
2253 return (0);
2254 }
2255
2256 /*
2257 * Report current media status.
2258 */
2259 static void
2260 re_ifmedia_sts(ifp, ifmr)
2261 struct ifnet *ifp;
2262 struct ifmediareq *ifmr;
2263 {
2264 struct rl_softc *sc;
2265 struct mii_data *mii;
2266
2267 sc = ifp->if_softc;
2268 mii = device_get_softc(sc->rl_miibus);
2269
2270 RL_LOCK(sc);
2271 mii_pollstat(mii);
2272 RL_UNLOCK(sc);
2273 ifmr->ifm_active = mii->mii_media_active;
2274 ifmr->ifm_status = mii->mii_media_status;
2275 }
2276
2277 static int
2278 re_ioctl(ifp, command, data)
2279 struct ifnet *ifp;
2280 u_long command;
2281 caddr_t data;
2282 {
2283 struct rl_softc *sc = ifp->if_softc;
2284 struct ifreq *ifr = (struct ifreq *) data;
2285 struct mii_data *mii;
2286 int error = 0;
2287
2288 switch (command) {
2289 case SIOCSIFMTU:
2290 RL_LOCK(sc);
2291 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2292 error = EINVAL;
2293 ifp->if_mtu = ifr->ifr_mtu;
2294 RL_UNLOCK(sc);
2295 break;
2296 case SIOCSIFFLAGS:
2297 RL_LOCK(sc);
2298 if (ifp->if_flags & IFF_UP)
2299 re_init_locked(sc);
2300 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2301 re_stop(sc);
2302 RL_UNLOCK(sc);
2303 break;
2304 case SIOCADDMULTI:
2305 case SIOCDELMULTI:
2306 RL_LOCK(sc);
2307 re_setmulti(sc);
2308 RL_UNLOCK(sc);
2309 break;
2310 case SIOCGIFMEDIA:
2311 case SIOCSIFMEDIA:
2312 mii = device_get_softc(sc->rl_miibus);
2313 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2314 break;
2315 case SIOCSIFCAP:
2316 {
2317 int mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2318 #ifdef DEVICE_POLLING
2319 if (mask & IFCAP_POLLING) {
2320 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2321 error = ether_poll_register(re_poll, ifp);
2322 if (error)
2323 return(error);
2324 RL_LOCK(sc);
2325 /* Disable interrupts */
2326 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2327 ifp->if_capenable |= IFCAP_POLLING;
2328 RL_UNLOCK(sc);
2329
2330 } else {
2331 error = ether_poll_deregister(ifp);
2332 /* Enable interrupts. */
2333 RL_LOCK(sc);
2334 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2335 ifp->if_capenable &= ~IFCAP_POLLING;
2336 RL_UNLOCK(sc);
2337 }
2338 }
2339 #endif /* DEVICE_POLLING */
2340 if (mask & IFCAP_HWCSUM) {
2341 RL_LOCK(sc);
2342 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_HWCSUM;
2343 if (ifp->if_capenable & IFCAP_TXCSUM)
2344 ifp->if_hwassist = RE_CSUM_FEATURES;
2345 else
2346 ifp->if_hwassist = 0;
2347 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2348 re_init_locked(sc);
2349 RL_UNLOCK(sc);
2350 }
2351 }
2352 break;
2353 default:
2354 error = ether_ioctl(ifp, command, data);
2355 break;
2356 }
2357
2358 return (error);
2359 }
2360
2361 static void
2362 re_watchdog(ifp)
2363 struct ifnet *ifp;
2364 {
2365 struct rl_softc *sc;
2366
2367 sc = ifp->if_softc;
2368 RL_LOCK(sc);
2369 if_printf(ifp, "watchdog timeout\n");
2370 ifp->if_oerrors++;
2371
2372 re_txeof(sc);
2373 re_rxeof(sc);
2374 re_init_locked(sc);
2375
2376 RL_UNLOCK(sc);
2377 }
2378
2379 /*
2380 * Stop the adapter and free any mbufs allocated to the
2381 * RX and TX lists.
2382 */
2383 static void
2384 re_stop(sc)
2385 struct rl_softc *sc;
2386 {
2387 register int i;
2388 struct ifnet *ifp;
2389
2390 RL_LOCK_ASSERT(sc);
2391
2392 ifp = sc->rl_ifp;
2393 ifp->if_timer = 0;
2394
2395 callout_stop(&sc->rl_stat_callout);
2396 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2397
2398 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2399 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2400
2401 if (sc->rl_head != NULL) {
2402 m_freem(sc->rl_head);
2403 sc->rl_head = sc->rl_tail = NULL;
2404 }
2405
2406 /* Free the TX list buffers. */
2407
2408 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2409 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2410 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2411 sc->rl_ldata.rl_tx_dmamap[i]);
2412 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2413 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2414 }
2415 }
2416
2417 /* Free the RX list buffers. */
2418
2419 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2420 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2421 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2422 sc->rl_ldata.rl_rx_dmamap[i]);
2423 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2424 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2425 }
2426 }
2427 }
2428
2429 /*
2430 * Device suspend routine. Stop the interface and save some PCI
2431 * settings in case the BIOS doesn't restore them properly on
2432 * resume.
2433 */
2434 static int
2435 re_suspend(dev)
2436 device_t dev;
2437 {
2438 struct rl_softc *sc;
2439
2440 sc = device_get_softc(dev);
2441
2442 RL_LOCK(sc);
2443 re_stop(sc);
2444 sc->suspended = 1;
2445 RL_UNLOCK(sc);
2446
2447 return (0);
2448 }
2449
2450 /*
2451 * Device resume routine. Restore some PCI settings in case the BIOS
2452 * doesn't, re-enable busmastering, and restart the interface if
2453 * appropriate.
2454 */
2455 static int
2456 re_resume(dev)
2457 device_t dev;
2458 {
2459 struct rl_softc *sc;
2460 struct ifnet *ifp;
2461
2462 sc = device_get_softc(dev);
2463
2464 RL_LOCK(sc);
2465
2466 ifp = sc->rl_ifp;
2467
2468 /* reinitialize interface if necessary */
2469 if (ifp->if_flags & IFF_UP)
2470 re_init_locked(sc);
2471
2472 sc->suspended = 0;
2473 RL_UNLOCK(sc);
2474
2475 return (0);
2476 }
2477
2478 /*
2479 * Stop all chip I/O so that the kernel's probe routines don't
2480 * get confused by errant DMAs when rebooting.
2481 */
2482 static void
2483 re_shutdown(dev)
2484 device_t dev;
2485 {
2486 struct rl_softc *sc;
2487
2488 sc = device_get_softc(dev);
2489
2490 RL_LOCK(sc);
2491 re_stop(sc);
2492 RL_UNLOCK(sc);
2493 }
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