FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.46.2.14 2006/03/17 21:30:55 glebius Exp $");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
48 * and the RTL8110S.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124
125 #include <net/if.h>
126 #include <net/if_arp.h>
127 #include <net/ethernet.h>
128 #include <net/if_dl.h>
129 #include <net/if_media.h>
130 #include <net/if_types.h>
131 #include <net/if_vlan_var.h>
132
133 #include <net/bpf.h>
134
135 #include <machine/bus.h>
136 #include <machine/resource.h>
137 #include <sys/bus.h>
138 #include <sys/rman.h>
139
140 #include <dev/mii/mii.h>
141 #include <dev/mii/miivar.h>
142
143 #include <dev/pci/pcireg.h>
144 #include <dev/pci/pcivar.h>
145
146 MODULE_DEPEND(re, pci, 1, 1, 1);
147 MODULE_DEPEND(re, ether, 1, 1, 1);
148 MODULE_DEPEND(re, miibus, 1, 1, 1);
149
150 /* "controller miibus0" required. See GENERIC if you get errors here. */
151 #include "miibus_if.h"
152
153 /*
154 * Default to using PIO access for this driver.
155 */
156 #define RE_USEIOSPACE
157
158 #include <pci/if_rlreg.h>
159
160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161
162 /*
163 * Various supported device vendors/types and their names.
164 */
165 static struct rl_type re_devs[] = {
166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
169 "RealTek 8139C+ 10/100BaseTX" },
170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
171 "RealTek 8169 Gigabit Ethernet" },
172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
173 "RealTek 8169S Single-chip Gigabit Ethernet" },
174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
175 "RealTek 8169SB Single-chip Gigabit Ethernet" },
176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
177 "RealTek 8110S Single-chip Gigabit Ethernet" },
178 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
179 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
180 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
181 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
182 { 0, 0, 0, NULL }
183 };
184
185 static struct rl_hwrev re_hwrevs[] = {
186 { RL_HWREV_8139, RL_8139, "" },
187 { RL_HWREV_8139A, RL_8139, "A" },
188 { RL_HWREV_8139AG, RL_8139, "A-G" },
189 { RL_HWREV_8139B, RL_8139, "B" },
190 { RL_HWREV_8130, RL_8139, "8130" },
191 { RL_HWREV_8139C, RL_8139, "C" },
192 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
193 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
194 { RL_HWREV_8169, RL_8169, "8169"},
195 { RL_HWREV_8169S, RL_8169, "8169S"},
196 { RL_HWREV_8169SB, RL_8169, "8169SB"},
197 { RL_HWREV_8110S, RL_8169, "8110S"},
198 { RL_HWREV_8100, RL_8139, "8100"},
199 { RL_HWREV_8101, RL_8139, "8101"},
200 { 0, 0, NULL }
201 };
202
203 static int re_probe (device_t);
204 static int re_attach (device_t);
205 static int re_detach (device_t);
206
207 static int re_encap (struct rl_softc *, struct mbuf **, int *);
208
209 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
210 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
211 bus_size_t, int);
212 static int re_allocmem (device_t, struct rl_softc *);
213 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
214 static int re_rx_list_init (struct rl_softc *);
215 static int re_tx_list_init (struct rl_softc *);
216 #ifdef RE_FIXUP_RX
217 static __inline void re_fixup_rx
218 (struct mbuf *);
219 #endif
220 static void re_rxeof (struct rl_softc *);
221 static void re_txeof (struct rl_softc *);
222 #ifdef DEVICE_POLLING
223 static void re_poll (struct ifnet *, enum poll_cmd, int);
224 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
225 #endif
226 static void re_intr (void *);
227 static void re_tick (void *);
228 static void re_start (struct ifnet *);
229 static void re_start_locked (struct ifnet *);
230 static int re_ioctl (struct ifnet *, u_long, caddr_t);
231 static void re_init (void *);
232 static void re_init_locked (struct rl_softc *);
233 static void re_stop (struct rl_softc *);
234 static void re_watchdog (struct ifnet *);
235 static int re_suspend (device_t);
236 static int re_resume (device_t);
237 static void re_shutdown (device_t);
238 static int re_ifmedia_upd (struct ifnet *);
239 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
240
241 static void re_eeprom_putbyte (struct rl_softc *, int);
242 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
243 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
244 static int re_gmii_readreg (device_t, int, int);
245 static int re_gmii_writereg (device_t, int, int, int);
246
247 static int re_miibus_readreg (device_t, int, int);
248 static int re_miibus_writereg (device_t, int, int, int);
249 static void re_miibus_statchg (device_t);
250
251 static void re_setmulti (struct rl_softc *);
252 static void re_reset (struct rl_softc *);
253
254 static int re_diag (struct rl_softc *);
255
256 #ifdef RE_USEIOSPACE
257 #define RL_RES SYS_RES_IOPORT
258 #define RL_RID RL_PCI_LOIO
259 #else
260 #define RL_RES SYS_RES_MEMORY
261 #define RL_RID RL_PCI_LOMEM
262 #endif
263
264 static device_method_t re_methods[] = {
265 /* Device interface */
266 DEVMETHOD(device_probe, re_probe),
267 DEVMETHOD(device_attach, re_attach),
268 DEVMETHOD(device_detach, re_detach),
269 DEVMETHOD(device_suspend, re_suspend),
270 DEVMETHOD(device_resume, re_resume),
271 DEVMETHOD(device_shutdown, re_shutdown),
272
273 /* bus interface */
274 DEVMETHOD(bus_print_child, bus_generic_print_child),
275 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276
277 /* MII interface */
278 DEVMETHOD(miibus_readreg, re_miibus_readreg),
279 DEVMETHOD(miibus_writereg, re_miibus_writereg),
280 DEVMETHOD(miibus_statchg, re_miibus_statchg),
281
282 { 0, 0 }
283 };
284
285 static driver_t re_driver = {
286 "re",
287 re_methods,
288 sizeof(struct rl_softc)
289 };
290
291 static devclass_t re_devclass;
292
293 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
294 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
295 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
296
297 #define EE_SET(x) \
298 CSR_WRITE_1(sc, RL_EECMD, \
299 CSR_READ_1(sc, RL_EECMD) | x)
300
301 #define EE_CLR(x) \
302 CSR_WRITE_1(sc, RL_EECMD, \
303 CSR_READ_1(sc, RL_EECMD) & ~x)
304
305 /*
306 * Send a read command and address to the EEPROM, check for ACK.
307 */
308 static void
309 re_eeprom_putbyte(sc, addr)
310 struct rl_softc *sc;
311 int addr;
312 {
313 register int d, i;
314
315 d = addr | sc->rl_eecmd_read;
316
317 /*
318 * Feed in each bit and strobe the clock.
319 */
320 for (i = 0x400; i; i >>= 1) {
321 if (d & i) {
322 EE_SET(RL_EE_DATAIN);
323 } else {
324 EE_CLR(RL_EE_DATAIN);
325 }
326 DELAY(100);
327 EE_SET(RL_EE_CLK);
328 DELAY(150);
329 EE_CLR(RL_EE_CLK);
330 DELAY(100);
331 }
332 }
333
334 /*
335 * Read a word of data stored in the EEPROM at address 'addr.'
336 */
337 static void
338 re_eeprom_getword(sc, addr, dest)
339 struct rl_softc *sc;
340 int addr;
341 u_int16_t *dest;
342 {
343 register int i;
344 u_int16_t word = 0;
345
346 /* Enter EEPROM access mode. */
347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
348
349 /*
350 * Send address of word we want to read.
351 */
352 re_eeprom_putbyte(sc, addr);
353
354 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
355
356 /*
357 * Start reading bits from EEPROM.
358 */
359 for (i = 0x8000; i; i >>= 1) {
360 EE_SET(RL_EE_CLK);
361 DELAY(100);
362 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
363 word |= i;
364 EE_CLR(RL_EE_CLK);
365 DELAY(100);
366 }
367
368 /* Turn off EEPROM access mode. */
369 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
370
371 *dest = word;
372 }
373
374 /*
375 * Read a sequence of words from the EEPROM.
376 */
377 static void
378 re_read_eeprom(sc, dest, off, cnt, swap)
379 struct rl_softc *sc;
380 caddr_t dest;
381 int off;
382 int cnt;
383 int swap;
384 {
385 int i;
386 u_int16_t word = 0, *ptr;
387
388 for (i = 0; i < cnt; i++) {
389 re_eeprom_getword(sc, off + i, &word);
390 ptr = (u_int16_t *)(dest + (i * 2));
391 if (swap)
392 *ptr = ntohs(word);
393 else
394 *ptr = word;
395 }
396 }
397
398 static int
399 re_gmii_readreg(dev, phy, reg)
400 device_t dev;
401 int phy, reg;
402 {
403 struct rl_softc *sc;
404 u_int32_t rval;
405 int i;
406
407 if (phy != 1)
408 return (0);
409
410 sc = device_get_softc(dev);
411
412 /* Let the rgephy driver read the GMEDIASTAT register */
413
414 if (reg == RL_GMEDIASTAT) {
415 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
416 return (rval);
417 }
418
419 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
420 DELAY(1000);
421
422 for (i = 0; i < RL_TIMEOUT; i++) {
423 rval = CSR_READ_4(sc, RL_PHYAR);
424 if (rval & RL_PHYAR_BUSY)
425 break;
426 DELAY(100);
427 }
428
429 if (i == RL_TIMEOUT) {
430 if_printf(sc->rl_ifp, "PHY read failed\n");
431 return (0);
432 }
433
434 return (rval & RL_PHYAR_PHYDATA);
435 }
436
437 static int
438 re_gmii_writereg(dev, phy, reg, data)
439 device_t dev;
440 int phy, reg, data;
441 {
442 struct rl_softc *sc;
443 u_int32_t rval;
444 int i;
445
446 sc = device_get_softc(dev);
447
448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
450 DELAY(1000);
451
452 for (i = 0; i < RL_TIMEOUT; i++) {
453 rval = CSR_READ_4(sc, RL_PHYAR);
454 if (!(rval & RL_PHYAR_BUSY))
455 break;
456 DELAY(100);
457 }
458
459 if (i == RL_TIMEOUT) {
460 if_printf(sc->rl_ifp, "PHY write failed\n");
461 return (0);
462 }
463
464 return (0);
465 }
466
467 static int
468 re_miibus_readreg(dev, phy, reg)
469 device_t dev;
470 int phy, reg;
471 {
472 struct rl_softc *sc;
473 u_int16_t rval = 0;
474 u_int16_t re8139_reg = 0;
475
476 sc = device_get_softc(dev);
477
478 if (sc->rl_type == RL_8169) {
479 rval = re_gmii_readreg(dev, phy, reg);
480 return (rval);
481 }
482
483 /* Pretend the internal PHY is only at address 0 */
484 if (phy) {
485 return (0);
486 }
487 switch (reg) {
488 case MII_BMCR:
489 re8139_reg = RL_BMCR;
490 break;
491 case MII_BMSR:
492 re8139_reg = RL_BMSR;
493 break;
494 case MII_ANAR:
495 re8139_reg = RL_ANAR;
496 break;
497 case MII_ANER:
498 re8139_reg = RL_ANER;
499 break;
500 case MII_ANLPAR:
501 re8139_reg = RL_LPAR;
502 break;
503 case MII_PHYIDR1:
504 case MII_PHYIDR2:
505 return (0);
506 /*
507 * Allow the rlphy driver to read the media status
508 * register. If we have a link partner which does not
509 * support NWAY, this is the register which will tell
510 * us the results of parallel detection.
511 */
512 case RL_MEDIASTAT:
513 rval = CSR_READ_1(sc, RL_MEDIASTAT);
514 return (rval);
515 default:
516 if_printf(sc->rl_ifp, "bad phy register\n");
517 return (0);
518 }
519 rval = CSR_READ_2(sc, re8139_reg);
520 return (rval);
521 }
522
523 static int
524 re_miibus_writereg(dev, phy, reg, data)
525 device_t dev;
526 int phy, reg, data;
527 {
528 struct rl_softc *sc;
529 u_int16_t re8139_reg = 0;
530 int rval = 0;
531
532 sc = device_get_softc(dev);
533
534 if (sc->rl_type == RL_8169) {
535 rval = re_gmii_writereg(dev, phy, reg, data);
536 return (rval);
537 }
538
539 /* Pretend the internal PHY is only at address 0 */
540 if (phy)
541 return (0);
542
543 switch (reg) {
544 case MII_BMCR:
545 re8139_reg = RL_BMCR;
546 break;
547 case MII_BMSR:
548 re8139_reg = RL_BMSR;
549 break;
550 case MII_ANAR:
551 re8139_reg = RL_ANAR;
552 break;
553 case MII_ANER:
554 re8139_reg = RL_ANER;
555 break;
556 case MII_ANLPAR:
557 re8139_reg = RL_LPAR;
558 break;
559 case MII_PHYIDR1:
560 case MII_PHYIDR2:
561 return (0);
562 break;
563 default:
564 if_printf(sc->rl_ifp, "bad phy register\n");
565 return (0);
566 }
567 CSR_WRITE_2(sc, re8139_reg, data);
568 return (0);
569 }
570
571 static void
572 re_miibus_statchg(dev)
573 device_t dev;
574 {
575
576 }
577
578 /*
579 * Program the 64-bit multicast hash filter.
580 */
581 static void
582 re_setmulti(sc)
583 struct rl_softc *sc;
584 {
585 struct ifnet *ifp;
586 int h = 0;
587 u_int32_t hashes[2] = { 0, 0 };
588 struct ifmultiaddr *ifma;
589 u_int32_t rxfilt;
590 int mcnt = 0;
591
592 RL_LOCK_ASSERT(sc);
593
594 ifp = sc->rl_ifp;
595
596 rxfilt = CSR_READ_4(sc, RL_RXCFG);
597
598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
599 rxfilt |= RL_RXCFG_RX_MULTI;
600 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
601 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
602 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
603 return;
604 }
605
606 /* first, zot all the existing hash bits */
607 CSR_WRITE_4(sc, RL_MAR0, 0);
608 CSR_WRITE_4(sc, RL_MAR4, 0);
609
610 /* now program new ones */
611 IF_ADDR_LOCK(ifp);
612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
613 if (ifma->ifma_addr->sa_family != AF_LINK)
614 continue;
615 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
616 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
617 if (h < 32)
618 hashes[0] |= (1 << h);
619 else
620 hashes[1] |= (1 << (h - 32));
621 mcnt++;
622 }
623 IF_ADDR_UNLOCK(ifp);
624
625 if (mcnt)
626 rxfilt |= RL_RXCFG_RX_MULTI;
627 else
628 rxfilt &= ~RL_RXCFG_RX_MULTI;
629
630 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
631 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
632 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
633 }
634
635 static void
636 re_reset(sc)
637 struct rl_softc *sc;
638 {
639 register int i;
640
641 RL_LOCK_ASSERT(sc);
642
643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
644
645 for (i = 0; i < RL_TIMEOUT; i++) {
646 DELAY(10);
647 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
648 break;
649 }
650 if (i == RL_TIMEOUT)
651 if_printf(sc->rl_ifp, "reset never completed!\n");
652
653 CSR_WRITE_1(sc, 0x82, 1);
654 }
655
656 /*
657 * The following routine is designed to test for a defect on some
658 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
659 * lines connected to the bus, however for a 32-bit only card, they
660 * should be pulled high. The result of this defect is that the
661 * NIC will not work right if you plug it into a 64-bit slot: DMA
662 * operations will be done with 64-bit transfers, which will fail
663 * because the 64-bit data lines aren't connected.
664 *
665 * There's no way to work around this (short of talking a soldering
666 * iron to the board), however we can detect it. The method we use
667 * here is to put the NIC into digital loopback mode, set the receiver
668 * to promiscuous mode, and then try to send a frame. We then compare
669 * the frame data we sent to what was received. If the data matches,
670 * then the NIC is working correctly, otherwise we know the user has
671 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
672 * slot. In the latter case, there's no way the NIC can work correctly,
673 * so we print out a message on the console and abort the device attach.
674 */
675
676 static int
677 re_diag(sc)
678 struct rl_softc *sc;
679 {
680 struct ifnet *ifp = sc->rl_ifp;
681 struct mbuf *m0;
682 struct ether_header *eh;
683 struct rl_desc *cur_rx;
684 u_int16_t status;
685 u_int32_t rxstat;
686 int total_len, i, error = 0;
687 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
688 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
689
690 /* Allocate a single mbuf */
691 MGETHDR(m0, M_DONTWAIT, MT_DATA);
692 if (m0 == NULL)
693 return (ENOBUFS);
694
695 RL_LOCK(sc);
696
697 /*
698 * Initialize the NIC in test mode. This sets the chip up
699 * so that it can send and receive frames, but performs the
700 * following special functions:
701 * - Puts receiver in promiscuous mode
702 * - Enables digital loopback mode
703 * - Leaves interrupts turned off
704 */
705
706 ifp->if_flags |= IFF_PROMISC;
707 sc->rl_testmode = 1;
708 re_init_locked(sc);
709 re_stop(sc);
710 DELAY(100000);
711 re_init_locked(sc);
712
713 /* Put some data in the mbuf */
714
715 eh = mtod(m0, struct ether_header *);
716 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
717 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
718 eh->ether_type = htons(ETHERTYPE_IP);
719 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
720
721 /*
722 * Queue the packet, start transmission.
723 * Note: IF_HANDOFF() ultimately calls re_start() for us.
724 */
725
726 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
727 RL_UNLOCK(sc);
728 /* XXX: re_diag must not be called when in ALTQ mode */
729 IF_HANDOFF(&ifp->if_snd, m0, ifp);
730 RL_LOCK(sc);
731 m0 = NULL;
732
733 /* Wait for it to propagate through the chip */
734
735 DELAY(100000);
736 for (i = 0; i < RL_TIMEOUT; i++) {
737 status = CSR_READ_2(sc, RL_ISR);
738 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
739 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
740 break;
741 DELAY(10);
742 }
743
744 if (i == RL_TIMEOUT) {
745 if_printf(ifp, "diagnostic failed, failed to receive packet "
746 "in loopback mode\n");
747 error = EIO;
748 goto done;
749 }
750
751 /*
752 * The packet should have been dumped into the first
753 * entry in the RX DMA ring. Grab it from there.
754 */
755
756 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
757 sc->rl_ldata.rl_rx_list_map,
758 BUS_DMASYNC_POSTREAD);
759 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
760 sc->rl_ldata.rl_rx_dmamap[0],
761 BUS_DMASYNC_POSTWRITE);
762 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
763 sc->rl_ldata.rl_rx_dmamap[0]);
764
765 m0 = sc->rl_ldata.rl_rx_mbuf[0];
766 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
767 eh = mtod(m0, struct ether_header *);
768
769 cur_rx = &sc->rl_ldata.rl_rx_list[0];
770 total_len = RL_RXBYTES(cur_rx);
771 rxstat = le32toh(cur_rx->rl_cmdstat);
772
773 if (total_len != ETHER_MIN_LEN) {
774 if_printf(ifp, "diagnostic failed, received short packet\n");
775 error = EIO;
776 goto done;
777 }
778
779 /* Test that the received packet data matches what we sent. */
780
781 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
782 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
783 ntohs(eh->ether_type) != ETHERTYPE_IP) {
784 if_printf(ifp, "WARNING, DMA FAILURE!\n");
785 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
786 dst, ":", src, ":", ETHERTYPE_IP);
787 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
788 eh->ether_dhost, ":", eh->ether_shost, ":",
789 ntohs(eh->ether_type));
790 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
791 "into a 64-bit PCI slot.\n");
792 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
793 "for proper operation.\n");
794 if_printf(ifp, "Read the re(4) man page for more details.\n");
795 error = EIO;
796 }
797
798 done:
799 /* Turn interface off, release resources */
800
801 sc->rl_testmode = 0;
802 ifp->if_flags &= ~IFF_PROMISC;
803 re_stop(sc);
804 if (m0 != NULL)
805 m_freem(m0);
806
807 RL_UNLOCK(sc);
808
809 return (error);
810 }
811
812 /*
813 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
814 * IDs against our list and return a device name if we find a match.
815 */
816 static int
817 re_probe(dev)
818 device_t dev;
819 {
820 struct rl_type *t;
821 struct rl_softc *sc;
822 int rid;
823 u_int32_t hwrev;
824
825 t = re_devs;
826 sc = device_get_softc(dev);
827
828 while (t->rl_name != NULL) {
829 if ((pci_get_vendor(dev) == t->rl_vid) &&
830 (pci_get_device(dev) == t->rl_did)) {
831 /*
832 * Only attach to rev. 3 of the Linksys EG1032 adapter.
833 * Rev. 2 i supported by sk(4).
834 */
835 if ((t->rl_vid == LINKSYS_VENDORID) &&
836 (t->rl_did == LINKSYS_DEVICEID_EG1032) &&
837 (pci_get_subdevice(dev) !=
838 LINKSYS_SUBDEVICE_EG1032_REV3)) {
839 t++;
840 continue;
841 }
842
843 /*
844 * Temporarily map the I/O space
845 * so we can read the chip ID register.
846 */
847 rid = RL_RID;
848 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
849 RF_ACTIVE);
850 if (sc->rl_res == NULL) {
851 device_printf(dev,
852 "couldn't map ports/memory\n");
853 return (ENXIO);
854 }
855 sc->rl_btag = rman_get_bustag(sc->rl_res);
856 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
857 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
858 bus_release_resource(dev, RL_RES,
859 RL_RID, sc->rl_res);
860 if (t->rl_basetype == hwrev) {
861 device_set_desc(dev, t->rl_name);
862 return (BUS_PROBE_DEFAULT);
863 }
864 }
865 t++;
866 }
867
868 return (ENXIO);
869 }
870
871 /*
872 * This routine takes the segment list provided as the result of
873 * a bus_dma_map_load() operation and assigns the addresses/lengths
874 * to RealTek DMA descriptors. This can be called either by the RX
875 * code or the TX code. In the RX case, we'll probably wind up mapping
876 * at most one segment. For the TX case, there could be any number of
877 * segments since TX packets may span multiple mbufs. In either case,
878 * if the number of segments is larger than the rl_maxsegs limit
879 * specified by the caller, we abort the mapping operation. Sadly,
880 * whoever designed the buffer mapping API did not provide a way to
881 * return an error from here, so we have to fake it a bit.
882 */
883
884 static void
885 re_dma_map_desc(arg, segs, nseg, mapsize, error)
886 void *arg;
887 bus_dma_segment_t *segs;
888 int nseg;
889 bus_size_t mapsize;
890 int error;
891 {
892 struct rl_dmaload_arg *ctx;
893 struct rl_desc *d = NULL;
894 int i = 0, idx;
895
896 if (error)
897 return;
898
899 ctx = arg;
900
901 /* Signal error to caller if there's too many segments */
902 if (nseg > ctx->rl_maxsegs) {
903 ctx->rl_maxsegs = 0;
904 return;
905 }
906
907 /*
908 * Map the segment array into descriptors. Note that we set the
909 * start-of-frame and end-of-frame markers for either TX or RX, but
910 * they really only have meaning in the TX case. (In the RX case,
911 * it's the chip that tells us where packets begin and end.)
912 * We also keep track of the end of the ring and set the
913 * end-of-ring bits as needed, and we set the ownership bits
914 * in all except the very first descriptor. (The caller will
915 * set this descriptor later when it start transmission or
916 * reception.)
917 */
918 idx = ctx->rl_idx;
919 for (;;) {
920 u_int32_t cmdstat;
921 d = &ctx->rl_ring[idx];
922 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
923 ctx->rl_maxsegs = 0;
924 return;
925 }
926 cmdstat = segs[i].ds_len;
927 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
928 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
929 if (i == 0)
930 cmdstat |= RL_TDESC_CMD_SOF;
931 else
932 cmdstat |= RL_TDESC_CMD_OWN;
933 if (idx == (RL_RX_DESC_CNT - 1))
934 cmdstat |= RL_TDESC_CMD_EOR;
935 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
936 i++;
937 if (i == nseg)
938 break;
939 RL_DESC_INC(idx);
940 }
941
942 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
943 ctx->rl_maxsegs = nseg;
944 ctx->rl_idx = idx;
945 }
946
947 /*
948 * Map a single buffer address.
949 */
950
951 static void
952 re_dma_map_addr(arg, segs, nseg, error)
953 void *arg;
954 bus_dma_segment_t *segs;
955 int nseg;
956 int error;
957 {
958 bus_addr_t *addr;
959
960 if (error)
961 return;
962
963 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
964 addr = arg;
965 *addr = segs->ds_addr;
966 }
967
968 static int
969 re_allocmem(dev, sc)
970 device_t dev;
971 struct rl_softc *sc;
972 {
973 int error;
974 int nseg;
975 int i;
976
977 /*
978 * Allocate map for RX mbufs.
979 */
980 nseg = 32;
981 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
982 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
983 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
984 NULL, NULL, &sc->rl_ldata.rl_mtag);
985 if (error) {
986 device_printf(dev, "could not allocate dma tag\n");
987 return (ENOMEM);
988 }
989
990 /*
991 * Allocate map for TX descriptor list.
992 */
993 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
994 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
995 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
996 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
997 if (error) {
998 device_printf(dev, "could not allocate dma tag\n");
999 return (ENOMEM);
1000 }
1001
1002 /* Allocate DMA'able memory for the TX ring */
1003
1004 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1005 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1006 &sc->rl_ldata.rl_tx_list_map);
1007 if (error)
1008 return (ENOMEM);
1009
1010 /* Load the map for the TX ring. */
1011
1012 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1013 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1014 RL_TX_LIST_SZ, re_dma_map_addr,
1015 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1016
1017 /* Create DMA maps for TX buffers */
1018
1019 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1020 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1021 &sc->rl_ldata.rl_tx_dmamap[i]);
1022 if (error) {
1023 device_printf(dev, "can't create DMA map for TX\n");
1024 return (ENOMEM);
1025 }
1026 }
1027
1028 /*
1029 * Allocate map for RX descriptor list.
1030 */
1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1033 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1034 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1035 if (error) {
1036 device_printf(dev, "could not allocate dma tag\n");
1037 return (ENOMEM);
1038 }
1039
1040 /* Allocate DMA'able memory for the RX ring */
1041
1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1043 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1044 &sc->rl_ldata.rl_rx_list_map);
1045 if (error)
1046 return (ENOMEM);
1047
1048 /* Load the map for the RX ring. */
1049
1050 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1051 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1052 RL_RX_LIST_SZ, re_dma_map_addr,
1053 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1054
1055 /* Create DMA maps for RX buffers */
1056
1057 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1058 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1059 &sc->rl_ldata.rl_rx_dmamap[i]);
1060 if (error) {
1061 device_printf(dev, "can't create DMA map for RX\n");
1062 return (ENOMEM);
1063 }
1064 }
1065
1066 return (0);
1067 }
1068
1069 /*
1070 * Attach the interface. Allocate softc structures, do ifmedia
1071 * setup and ethernet/BPF attach.
1072 */
1073 static int
1074 re_attach(dev)
1075 device_t dev;
1076 {
1077 u_char eaddr[ETHER_ADDR_LEN];
1078 u_int16_t as[3];
1079 struct rl_softc *sc;
1080 struct ifnet *ifp;
1081 struct rl_hwrev *hw_rev;
1082 int hwrev;
1083 u_int16_t re_did = 0;
1084 int error = 0, rid, i;
1085
1086 sc = device_get_softc(dev);
1087
1088 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1089 MTX_DEF);
1090 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1091
1092 /*
1093 * Map control/status registers.
1094 */
1095 pci_enable_busmaster(dev);
1096
1097 rid = RL_RID;
1098 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1099 RF_ACTIVE);
1100
1101 if (sc->rl_res == NULL) {
1102 device_printf(dev, "couldn't map ports/memory\n");
1103 error = ENXIO;
1104 goto fail;
1105 }
1106
1107 sc->rl_btag = rman_get_bustag(sc->rl_res);
1108 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1109
1110 /* Allocate interrupt */
1111 rid = 0;
1112 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1113 RF_SHAREABLE | RF_ACTIVE);
1114
1115 if (sc->rl_irq == NULL) {
1116 device_printf(dev, "couldn't map interrupt\n");
1117 error = ENXIO;
1118 goto fail;
1119 }
1120
1121 /* Reset the adapter. */
1122 RL_LOCK(sc);
1123 re_reset(sc);
1124 RL_UNLOCK(sc);
1125
1126 hw_rev = re_hwrevs;
1127 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1128 while (hw_rev->rl_desc != NULL) {
1129 if (hw_rev->rl_rev == hwrev) {
1130 sc->rl_type = hw_rev->rl_type;
1131 break;
1132 }
1133 hw_rev++;
1134 }
1135
1136 if (sc->rl_type == RL_8169) {
1137
1138 /* Set RX length mask */
1139
1140 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1141
1142 /* Force station address autoload from the EEPROM */
1143
1144 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1145 for (i = 0; i < RL_TIMEOUT; i++) {
1146 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1147 break;
1148 DELAY(100);
1149 }
1150 if (i == RL_TIMEOUT)
1151 device_printf(dev, "eeprom autoload timed out\n");
1152
1153 for (i = 0; i < ETHER_ADDR_LEN; i++)
1154 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1155 } else {
1156
1157 /* Set RX length mask */
1158
1159 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1160
1161 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1162 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1163 if (re_did != 0x8129)
1164 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1165
1166 /*
1167 * Get station address from the EEPROM.
1168 */
1169 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1170 for (i = 0; i < 3; i++) {
1171 eaddr[(i * 2) + 0] = as[i] & 0xff;
1172 eaddr[(i * 2) + 1] = as[i] >> 8;
1173 }
1174 }
1175
1176 /*
1177 * Allocate the parent bus DMA tag appropriate for PCI.
1178 */
1179 #define RL_NSEG_NEW 32
1180 error = bus_dma_tag_create(NULL, /* parent */
1181 1, 0, /* alignment, boundary */
1182 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1183 BUS_SPACE_MAXADDR, /* highaddr */
1184 NULL, NULL, /* filter, filterarg */
1185 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1186 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1187 BUS_DMA_ALLOCNOW, /* flags */
1188 NULL, NULL, /* lockfunc, lockarg */
1189 &sc->rl_parent_tag);
1190 if (error)
1191 goto fail;
1192
1193 error = re_allocmem(dev, sc);
1194
1195 if (error)
1196 goto fail;
1197
1198 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1199 if (ifp == NULL) {
1200 device_printf(dev, "can not if_alloc()\n");
1201 error = ENOSPC;
1202 goto fail;
1203 }
1204
1205 /* Do MII setup */
1206 if (mii_phy_probe(dev, &sc->rl_miibus,
1207 re_ifmedia_upd, re_ifmedia_sts)) {
1208 device_printf(dev, "MII without any phy!\n");
1209 error = ENXIO;
1210 goto fail;
1211 }
1212
1213 ifp->if_softc = sc;
1214 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1215 ifp->if_mtu = ETHERMTU;
1216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1217 ifp->if_ioctl = re_ioctl;
1218 ifp->if_capabilities = IFCAP_VLAN_MTU;
1219 ifp->if_start = re_start;
1220 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1221 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1222 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1223 #ifdef DEVICE_POLLING
1224 ifp->if_capabilities |= IFCAP_POLLING;
1225 #endif
1226 ifp->if_watchdog = re_watchdog;
1227 ifp->if_init = re_init;
1228 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1229 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1230 IFQ_SET_READY(&ifp->if_snd);
1231
1232 /*
1233 * Call MI attach routine.
1234 */
1235 ether_ifattach(ifp, eaddr);
1236
1237 /* Perform hardware diagnostic. */
1238 error = re_diag(sc);
1239
1240 if (error) {
1241 device_printf(dev, "attach aborted due to hardware diag failure\n");
1242 ether_ifdetach(ifp);
1243 goto fail;
1244 }
1245
1246 /* Hook interrupt last to avoid having to lock softc */
1247 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1248 re_intr, sc, &sc->rl_intrhand);
1249 if (error) {
1250 device_printf(dev, "couldn't set up irq\n");
1251 ether_ifdetach(ifp);
1252 }
1253
1254 fail:
1255 if (error)
1256 re_detach(dev);
1257
1258 return (error);
1259 }
1260
1261 /*
1262 * Shutdown hardware and free up resources. This can be called any
1263 * time after the mutex has been initialized. It is called in both
1264 * the error case in attach and the normal detach case so it needs
1265 * to be careful about only freeing resources that have actually been
1266 * allocated.
1267 */
1268 static int
1269 re_detach(dev)
1270 device_t dev;
1271 {
1272 struct rl_softc *sc;
1273 struct ifnet *ifp;
1274 int i;
1275
1276 sc = device_get_softc(dev);
1277 ifp = sc->rl_ifp;
1278 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1279
1280 #ifdef DEVICE_POLLING
1281 if (ifp->if_capenable & IFCAP_POLLING)
1282 ether_poll_deregister(ifp);
1283 #endif
1284 /* These should only be active if attach succeeded */
1285 if (device_is_attached(dev)) {
1286 RL_LOCK(sc);
1287 #if 0
1288 sc->suspended = 1;
1289 #endif
1290 re_stop(sc);
1291 RL_UNLOCK(sc);
1292 callout_drain(&sc->rl_stat_callout);
1293 /*
1294 * Force off the IFF_UP flag here, in case someone
1295 * still had a BPF descriptor attached to this
1296 * interface. If they do, ether_ifdetach() will cause
1297 * the BPF code to try and clear the promisc mode
1298 * flag, which will bubble down to re_ioctl(),
1299 * which will try to call re_init() again. This will
1300 * turn the NIC back on and restart the MII ticker,
1301 * which will panic the system when the kernel tries
1302 * to invoke the re_tick() function that isn't there
1303 * anymore.
1304 */
1305 ifp->if_flags &= ~IFF_UP;
1306 ether_ifdetach(ifp);
1307 }
1308 if (sc->rl_miibus)
1309 device_delete_child(dev, sc->rl_miibus);
1310 bus_generic_detach(dev);
1311
1312 /*
1313 * The rest is resource deallocation, so we should already be
1314 * stopped here.
1315 */
1316
1317 if (sc->rl_intrhand)
1318 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1319 if (ifp != NULL)
1320 if_free(ifp);
1321 if (sc->rl_irq)
1322 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1323 if (sc->rl_res)
1324 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1325
1326
1327 /* Unload and free the RX DMA ring memory and map */
1328
1329 if (sc->rl_ldata.rl_rx_list_tag) {
1330 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1331 sc->rl_ldata.rl_rx_list_map);
1332 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1333 sc->rl_ldata.rl_rx_list,
1334 sc->rl_ldata.rl_rx_list_map);
1335 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1336 }
1337
1338 /* Unload and free the TX DMA ring memory and map */
1339
1340 if (sc->rl_ldata.rl_tx_list_tag) {
1341 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1342 sc->rl_ldata.rl_tx_list_map);
1343 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1344 sc->rl_ldata.rl_tx_list,
1345 sc->rl_ldata.rl_tx_list_map);
1346 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1347 }
1348
1349 /* Destroy all the RX and TX buffer maps */
1350
1351 if (sc->rl_ldata.rl_mtag) {
1352 for (i = 0; i < RL_TX_DESC_CNT; i++)
1353 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1354 sc->rl_ldata.rl_tx_dmamap[i]);
1355 for (i = 0; i < RL_RX_DESC_CNT; i++)
1356 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1357 sc->rl_ldata.rl_rx_dmamap[i]);
1358 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1359 }
1360
1361 /* Unload and free the stats buffer and map */
1362
1363 if (sc->rl_ldata.rl_stag) {
1364 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1365 sc->rl_ldata.rl_rx_list_map);
1366 bus_dmamem_free(sc->rl_ldata.rl_stag,
1367 sc->rl_ldata.rl_stats,
1368 sc->rl_ldata.rl_smap);
1369 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1370 }
1371
1372 if (sc->rl_parent_tag)
1373 bus_dma_tag_destroy(sc->rl_parent_tag);
1374
1375 mtx_destroy(&sc->rl_mtx);
1376
1377 return (0);
1378 }
1379
1380 static int
1381 re_newbuf(sc, idx, m)
1382 struct rl_softc *sc;
1383 int idx;
1384 struct mbuf *m;
1385 {
1386 struct rl_dmaload_arg arg;
1387 struct mbuf *n = NULL;
1388 int error;
1389
1390 if (m == NULL) {
1391 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1392 if (n == NULL)
1393 return (ENOBUFS);
1394 m = n;
1395 } else
1396 m->m_data = m->m_ext.ext_buf;
1397
1398 m->m_len = m->m_pkthdr.len = MCLBYTES;
1399 #ifdef RE_FIXUP_RX
1400 /*
1401 * This is part of an evil trick to deal with non-x86 platforms.
1402 * The RealTek chip requires RX buffers to be aligned on 64-bit
1403 * boundaries, but that will hose non-x86 machines. To get around
1404 * this, we leave some empty space at the start of each buffer
1405 * and for non-x86 hosts, we copy the buffer back six bytes
1406 * to achieve word alignment. This is slightly more efficient
1407 * than allocating a new buffer, copying the contents, and
1408 * discarding the old buffer.
1409 */
1410 m_adj(m, RE_ETHER_ALIGN);
1411 #endif
1412 arg.sc = sc;
1413 arg.rl_idx = idx;
1414 arg.rl_maxsegs = 1;
1415 arg.rl_flags = 0;
1416 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1417
1418 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1419 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1420 &arg, BUS_DMA_NOWAIT);
1421 if (error || arg.rl_maxsegs != 1) {
1422 if (n != NULL)
1423 m_freem(n);
1424 return (ENOMEM);
1425 }
1426
1427 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1428 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1429
1430 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1431 sc->rl_ldata.rl_rx_dmamap[idx],
1432 BUS_DMASYNC_PREREAD);
1433
1434 return (0);
1435 }
1436
1437 #ifdef RE_FIXUP_RX
1438 static __inline void
1439 re_fixup_rx(m)
1440 struct mbuf *m;
1441 {
1442 int i;
1443 uint16_t *src, *dst;
1444
1445 src = mtod(m, uint16_t *);
1446 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1447
1448 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1449 *dst++ = *src++;
1450
1451 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1452
1453 return;
1454 }
1455 #endif
1456
1457 static int
1458 re_tx_list_init(sc)
1459 struct rl_softc *sc;
1460 {
1461
1462 RL_LOCK_ASSERT(sc);
1463
1464 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1465 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1466 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1467
1468 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1469 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1470 sc->rl_ldata.rl_tx_prodidx = 0;
1471 sc->rl_ldata.rl_tx_considx = 0;
1472 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1473
1474 return (0);
1475 }
1476
1477 static int
1478 re_rx_list_init(sc)
1479 struct rl_softc *sc;
1480 {
1481 int i;
1482
1483 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1484 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1485 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1486
1487 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1488 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1489 return (ENOBUFS);
1490 }
1491
1492 /* Flush the RX descriptors */
1493
1494 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1495 sc->rl_ldata.rl_rx_list_map,
1496 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1497
1498 sc->rl_ldata.rl_rx_prodidx = 0;
1499 sc->rl_head = sc->rl_tail = NULL;
1500
1501 return (0);
1502 }
1503
1504 /*
1505 * RX handler for C+ and 8169. For the gigE chips, we support
1506 * the reception of jumbo frames that have been fragmented
1507 * across multiple 2K mbuf cluster buffers.
1508 */
1509 static void
1510 re_rxeof(sc)
1511 struct rl_softc *sc;
1512 {
1513 struct mbuf *m;
1514 struct ifnet *ifp;
1515 int i, total_len;
1516 struct rl_desc *cur_rx;
1517 u_int32_t rxstat, rxvlan;
1518
1519 RL_LOCK_ASSERT(sc);
1520
1521 ifp = sc->rl_ifp;
1522 i = sc->rl_ldata.rl_rx_prodidx;
1523
1524 /* Invalidate the descriptor memory */
1525
1526 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1527 sc->rl_ldata.rl_rx_list_map,
1528 BUS_DMASYNC_POSTREAD);
1529
1530 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1531 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1532 m = sc->rl_ldata.rl_rx_mbuf[i];
1533 total_len = RL_RXBYTES(cur_rx);
1534 rxstat = le32toh(cur_rx->rl_cmdstat);
1535 rxvlan = le32toh(cur_rx->rl_vlanctl);
1536
1537 /* Invalidate the RX mbuf and unload its map */
1538
1539 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1540 sc->rl_ldata.rl_rx_dmamap[i],
1541 BUS_DMASYNC_POSTWRITE);
1542 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1543 sc->rl_ldata.rl_rx_dmamap[i]);
1544
1545 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1546 m->m_len = RE_RX_DESC_BUFLEN;
1547 if (sc->rl_head == NULL)
1548 sc->rl_head = sc->rl_tail = m;
1549 else {
1550 m->m_flags &= ~M_PKTHDR;
1551 sc->rl_tail->m_next = m;
1552 sc->rl_tail = m;
1553 }
1554 re_newbuf(sc, i, NULL);
1555 RL_DESC_INC(i);
1556 continue;
1557 }
1558
1559 /*
1560 * NOTE: for the 8139C+, the frame length field
1561 * is always 12 bits in size, but for the gigE chips,
1562 * it is 13 bits (since the max RX frame length is 16K).
1563 * Unfortunately, all 32 bits in the status word
1564 * were already used, so to make room for the extra
1565 * length bit, RealTek took out the 'frame alignment
1566 * error' bit and shifted the other status bits
1567 * over one slot. The OWN, EOR, FS and LS bits are
1568 * still in the same places. We have already extracted
1569 * the frame length and checked the OWN bit, so rather
1570 * than using an alternate bit mapping, we shift the
1571 * status bits one space to the right so we can evaluate
1572 * them using the 8169 status as though it was in the
1573 * same format as that of the 8139C+.
1574 */
1575 if (sc->rl_type == RL_8169)
1576 rxstat >>= 1;
1577
1578 /*
1579 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1580 * set, but if CRC is clear, it will still be a valid frame.
1581 */
1582 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1583 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1584 ifp->if_ierrors++;
1585 /*
1586 * If this is part of a multi-fragment packet,
1587 * discard all the pieces.
1588 */
1589 if (sc->rl_head != NULL) {
1590 m_freem(sc->rl_head);
1591 sc->rl_head = sc->rl_tail = NULL;
1592 }
1593 re_newbuf(sc, i, m);
1594 RL_DESC_INC(i);
1595 continue;
1596 }
1597
1598 /*
1599 * If allocating a replacement mbuf fails,
1600 * reload the current one.
1601 */
1602
1603 if (re_newbuf(sc, i, NULL)) {
1604 ifp->if_ierrors++;
1605 if (sc->rl_head != NULL) {
1606 m_freem(sc->rl_head);
1607 sc->rl_head = sc->rl_tail = NULL;
1608 }
1609 re_newbuf(sc, i, m);
1610 RL_DESC_INC(i);
1611 continue;
1612 }
1613
1614 RL_DESC_INC(i);
1615
1616 if (sc->rl_head != NULL) {
1617 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1618 if (m->m_len == 0)
1619 m->m_len = RE_RX_DESC_BUFLEN;
1620 /*
1621 * Special case: if there's 4 bytes or less
1622 * in this buffer, the mbuf can be discarded:
1623 * the last 4 bytes is the CRC, which we don't
1624 * care about anyway.
1625 */
1626 if (m->m_len <= ETHER_CRC_LEN) {
1627 sc->rl_tail->m_len -=
1628 (ETHER_CRC_LEN - m->m_len);
1629 m_freem(m);
1630 } else {
1631 m->m_len -= ETHER_CRC_LEN;
1632 m->m_flags &= ~M_PKTHDR;
1633 sc->rl_tail->m_next = m;
1634 }
1635 m = sc->rl_head;
1636 sc->rl_head = sc->rl_tail = NULL;
1637 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1638 } else
1639 m->m_pkthdr.len = m->m_len =
1640 (total_len - ETHER_CRC_LEN);
1641
1642 #ifdef RE_FIXUP_RX
1643 re_fixup_rx(m);
1644 #endif
1645 ifp->if_ipackets++;
1646 m->m_pkthdr.rcvif = ifp;
1647
1648 /* Do RX checksumming if enabled */
1649
1650 if (ifp->if_capenable & IFCAP_RXCSUM) {
1651
1652 /* Check IP header checksum */
1653 if (rxstat & RL_RDESC_STAT_PROTOID)
1654 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1655 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1656 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1657
1658 /* Check TCP/UDP checksum */
1659 if ((RL_TCPPKT(rxstat) &&
1660 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1661 (RL_UDPPKT(rxstat) &&
1662 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1663 m->m_pkthdr.csum_flags |=
1664 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1665 m->m_pkthdr.csum_data = 0xffff;
1666 }
1667 }
1668
1669 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1670 VLAN_INPUT_TAG_NEW(ifp, m,
1671 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1672 if (m == NULL)
1673 continue;
1674 }
1675 RL_UNLOCK(sc);
1676 (*ifp->if_input)(ifp, m);
1677 RL_LOCK(sc);
1678 }
1679
1680 /* Flush the RX DMA ring */
1681
1682 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1683 sc->rl_ldata.rl_rx_list_map,
1684 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1685
1686 sc->rl_ldata.rl_rx_prodidx = i;
1687 }
1688
1689 static void
1690 re_txeof(sc)
1691 struct rl_softc *sc;
1692 {
1693 struct ifnet *ifp;
1694 u_int32_t txstat;
1695 int idx;
1696
1697 ifp = sc->rl_ifp;
1698 idx = sc->rl_ldata.rl_tx_considx;
1699
1700 /* Invalidate the TX descriptor list */
1701
1702 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1703 sc->rl_ldata.rl_tx_list_map,
1704 BUS_DMASYNC_POSTREAD);
1705
1706 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1707
1708 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1709 if (txstat & RL_TDESC_CMD_OWN)
1710 break;
1711
1712 /*
1713 * We only stash mbufs in the last descriptor
1714 * in a fragment chain, which also happens to
1715 * be the only place where the TX status bits
1716 * are valid.
1717 */
1718
1719 if (txstat & RL_TDESC_CMD_EOF) {
1720 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1721 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1722 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1723 sc->rl_ldata.rl_tx_dmamap[idx]);
1724 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1725 RL_TDESC_STAT_COLCNT))
1726 ifp->if_collisions++;
1727 if (txstat & RL_TDESC_STAT_TXERRSUM)
1728 ifp->if_oerrors++;
1729 else
1730 ifp->if_opackets++;
1731 }
1732 sc->rl_ldata.rl_tx_free++;
1733 RL_DESC_INC(idx);
1734 }
1735
1736 /* No changes made to the TX ring, so no flush needed */
1737
1738 if (idx != sc->rl_ldata.rl_tx_considx) {
1739 sc->rl_ldata.rl_tx_considx = idx;
1740 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1741 ifp->if_timer = 0;
1742 }
1743
1744 /*
1745 * If not all descriptors have been released reaped yet,
1746 * reload the timer so that we will eventually get another
1747 * interrupt that will cause us to re-enter this routine.
1748 * This is done in case the transmitter has gone idle.
1749 */
1750 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1751 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1752 }
1753
1754 static void
1755 re_tick(xsc)
1756 void *xsc;
1757 {
1758 struct rl_softc *sc;
1759 struct mii_data *mii;
1760
1761 sc = xsc;
1762
1763 RL_LOCK_ASSERT(sc);
1764
1765 mii = device_get_softc(sc->rl_miibus);
1766
1767 mii_tick(mii);
1768
1769 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1770 }
1771
1772 #ifdef DEVICE_POLLING
1773 static void
1774 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1775 {
1776 struct rl_softc *sc = ifp->if_softc;
1777
1778 RL_LOCK(sc);
1779 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1780 re_poll_locked(ifp, cmd, count);
1781 RL_UNLOCK(sc);
1782 }
1783
1784 static void
1785 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1786 {
1787 struct rl_softc *sc = ifp->if_softc;
1788
1789 RL_LOCK_ASSERT(sc);
1790
1791 sc->rxcycles = count;
1792 re_rxeof(sc);
1793 re_txeof(sc);
1794
1795 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1796 re_start_locked(ifp);
1797
1798 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1799 u_int16_t status;
1800
1801 status = CSR_READ_2(sc, RL_ISR);
1802 if (status == 0xffff)
1803 return;
1804 if (status)
1805 CSR_WRITE_2(sc, RL_ISR, status);
1806
1807 /*
1808 * XXX check behaviour on receiver stalls.
1809 */
1810
1811 if (status & RL_ISR_SYSTEM_ERR) {
1812 re_reset(sc);
1813 re_init_locked(sc);
1814 }
1815 }
1816 }
1817 #endif /* DEVICE_POLLING */
1818
1819 static void
1820 re_intr(arg)
1821 void *arg;
1822 {
1823 struct rl_softc *sc;
1824 struct ifnet *ifp;
1825 u_int16_t status;
1826
1827 sc = arg;
1828
1829 RL_LOCK(sc);
1830
1831 ifp = sc->rl_ifp;
1832
1833 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1834 goto done_locked;
1835
1836 #ifdef DEVICE_POLLING
1837 if (ifp->if_capenable & IFCAP_POLLING)
1838 goto done_locked;
1839 #endif
1840
1841 for (;;) {
1842
1843 status = CSR_READ_2(sc, RL_ISR);
1844 /* If the card has gone away the read returns 0xffff. */
1845 if (status == 0xffff)
1846 break;
1847 if (status)
1848 CSR_WRITE_2(sc, RL_ISR, status);
1849
1850 if ((status & RL_INTRS_CPLUS) == 0)
1851 break;
1852
1853 if (((status & RL_ISR_RX_OK) ||
1854 (status & RL_ISR_RX_ERR)) &&
1855 ifp->if_drv_flags & IFF_DRV_RUNNING)
1856 re_rxeof(sc);
1857
1858 if (((status & RL_ISR_TIMEOUT_EXPIRED) ||
1859 (status & RL_ISR_TX_ERR) ||
1860 (status & RL_ISR_TX_DESC_UNAVAIL)) &&
1861 ifp->if_drv_flags & IFF_DRV_RUNNING)
1862 re_txeof(sc);
1863
1864 if (status & RL_ISR_SYSTEM_ERR) {
1865 re_reset(sc);
1866 re_init_locked(sc);
1867 }
1868
1869 if (status & RL_ISR_LINKCHG) {
1870 callout_stop(&sc->rl_stat_callout);
1871 re_tick(sc);
1872 }
1873 }
1874
1875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1876 re_start_locked(ifp);
1877
1878 done_locked:
1879 RL_UNLOCK(sc);
1880 }
1881
1882 static int
1883 re_encap(sc, m_head, idx)
1884 struct rl_softc *sc;
1885 struct mbuf **m_head;
1886 int *idx;
1887 {
1888 struct mbuf *m_new = NULL;
1889 struct rl_dmaload_arg arg;
1890 bus_dmamap_t map;
1891 int error;
1892 struct m_tag *mtag;
1893
1894 RL_LOCK_ASSERT(sc);
1895
1896 if (sc->rl_ldata.rl_tx_free <= 4)
1897 return (EFBIG);
1898
1899 /*
1900 * Set up checksum offload. Note: checksum offload bits must
1901 * appear in all descriptors of a multi-descriptor transmit
1902 * attempt. This is according to testing done with an 8169
1903 * chip. This is a requirement.
1904 */
1905
1906 arg.rl_flags = 0;
1907
1908 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1909 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1910 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1911 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1912 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1913 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1914
1915 arg.sc = sc;
1916 arg.rl_idx = *idx;
1917 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1918 if (arg.rl_maxsegs > 4)
1919 arg.rl_maxsegs -= 4;
1920 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1921
1922 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1923 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1924 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1925
1926 if (error && error != EFBIG) {
1927 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error);
1928 return (ENOBUFS);
1929 }
1930
1931 /* Too many segments to map, coalesce into a single mbuf */
1932
1933 if (error || arg.rl_maxsegs == 0) {
1934 m_new = m_defrag(*m_head, M_DONTWAIT);
1935 if (m_new == NULL)
1936 return (ENOBUFS);
1937 else
1938 *m_head = m_new;
1939
1940 arg.sc = sc;
1941 arg.rl_idx = *idx;
1942 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1943 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1944
1945 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1946 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1947 if (error) {
1948 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n",
1949 error);
1950 return (EFBIG);
1951 }
1952 }
1953
1954 /*
1955 * Insure that the map for this transmission
1956 * is placed at the array index of the last descriptor
1957 * in this chain. (Swap last and first dmamaps.)
1958 */
1959 sc->rl_ldata.rl_tx_dmamap[*idx] =
1960 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1961 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1962
1963 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1964 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1965
1966 /*
1967 * Set up hardware VLAN tagging. Note: vlan tag info must
1968 * appear in the first descriptor of a multi-descriptor
1969 * transmission attempt.
1970 */
1971
1972 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
1973 if (mtag != NULL)
1974 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1975 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1976
1977 /* Transfer ownership of packet to the chip. */
1978
1979 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1980 htole32(RL_TDESC_CMD_OWN);
1981 if (*idx != arg.rl_idx)
1982 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1983 htole32(RL_TDESC_CMD_OWN);
1984
1985 RL_DESC_INC(arg.rl_idx);
1986 *idx = arg.rl_idx;
1987
1988 return (0);
1989 }
1990
1991 static void
1992 re_start(ifp)
1993 struct ifnet *ifp;
1994 {
1995 struct rl_softc *sc;
1996
1997 sc = ifp->if_softc;
1998 RL_LOCK(sc);
1999 re_start_locked(ifp);
2000 RL_UNLOCK(sc);
2001 }
2002
2003 /*
2004 * Main transmit routine for C+ and gigE NICs.
2005 */
2006 static void
2007 re_start_locked(ifp)
2008 struct ifnet *ifp;
2009 {
2010 struct rl_softc *sc;
2011 struct mbuf *m_head = NULL;
2012 int idx, queued = 0;
2013
2014 sc = ifp->if_softc;
2015
2016 RL_LOCK_ASSERT(sc);
2017
2018 idx = sc->rl_ldata.rl_tx_prodidx;
2019
2020 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2021 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2022 if (m_head == NULL)
2023 break;
2024
2025 if (re_encap(sc, &m_head, &idx)) {
2026 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2027 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2028 break;
2029 }
2030
2031 /*
2032 * If there's a BPF listener, bounce a copy of this frame
2033 * to him.
2034 */
2035 BPF_MTAP(ifp, m_head);
2036
2037 queued++;
2038 }
2039
2040 if (queued == 0)
2041 return;
2042
2043 /* Flush the TX descriptors */
2044
2045 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2046 sc->rl_ldata.rl_tx_list_map,
2047 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2048
2049 sc->rl_ldata.rl_tx_prodidx = idx;
2050
2051 /*
2052 * RealTek put the TX poll request register in a different
2053 * location on the 8169 gigE chip. I don't know why.
2054 */
2055
2056 if (sc->rl_type == RL_8169)
2057 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2058 else
2059 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2060
2061 /*
2062 * Use the countdown timer for interrupt moderation.
2063 * 'TX done' interrupts are disabled. Instead, we reset the
2064 * countdown timer, which will begin counting until it hits
2065 * the value in the TIMERINT register, and then trigger an
2066 * interrupt. Each time we write to the TIMERCNT register,
2067 * the timer count is reset to 0.
2068 */
2069 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2070
2071 /*
2072 * Set a timeout in case the chip goes out to lunch.
2073 */
2074 ifp->if_timer = 5;
2075 }
2076
2077 static void
2078 re_init(xsc)
2079 void *xsc;
2080 {
2081 struct rl_softc *sc = xsc;
2082
2083 RL_LOCK(sc);
2084 re_init_locked(sc);
2085 RL_UNLOCK(sc);
2086 }
2087
2088 static void
2089 re_init_locked(sc)
2090 struct rl_softc *sc;
2091 {
2092 struct ifnet *ifp = sc->rl_ifp;
2093 struct mii_data *mii;
2094 u_int32_t rxcfg = 0;
2095
2096 RL_LOCK_ASSERT(sc);
2097
2098 mii = device_get_softc(sc->rl_miibus);
2099
2100 /*
2101 * Cancel pending I/O and free all RX/TX buffers.
2102 */
2103 re_stop(sc);
2104
2105 /*
2106 * Enable C+ RX and TX mode, as well as VLAN stripping and
2107 * RX checksum offload. We must configure the C+ register
2108 * before all others.
2109 */
2110 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2111 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2112 RL_CPLUSCMD_VLANSTRIP|
2113 (ifp->if_capenable & IFCAP_RXCSUM ?
2114 RL_CPLUSCMD_RXCSUM_ENB : 0));
2115
2116 /*
2117 * Init our MAC address. Even though the chipset
2118 * documentation doesn't mention it, we need to enter "Config
2119 * register write enable" mode to modify the ID registers.
2120 */
2121 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2122 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2123 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
2124 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2125 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
2126 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2127
2128 /*
2129 * For C+ mode, initialize the RX descriptors and mbufs.
2130 */
2131 re_rx_list_init(sc);
2132 re_tx_list_init(sc);
2133
2134 /*
2135 * Enable transmit and receive.
2136 */
2137 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2138
2139 /*
2140 * Set the initial TX and RX configuration.
2141 */
2142 if (sc->rl_testmode) {
2143 if (sc->rl_type == RL_8169)
2144 CSR_WRITE_4(sc, RL_TXCFG,
2145 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2146 else
2147 CSR_WRITE_4(sc, RL_TXCFG,
2148 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2149 } else
2150 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2151 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2152
2153 /* Set the individual bit to receive frames for this host only. */
2154 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2155 rxcfg |= RL_RXCFG_RX_INDIV;
2156
2157 /* If we want promiscuous mode, set the allframes bit. */
2158 if (ifp->if_flags & IFF_PROMISC)
2159 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2160 else
2161 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2162 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2163
2164 /*
2165 * Set capture broadcast bit to capture broadcast frames.
2166 */
2167 if (ifp->if_flags & IFF_BROADCAST)
2168 rxcfg |= RL_RXCFG_RX_BROAD;
2169 else
2170 rxcfg &= ~RL_RXCFG_RX_BROAD;
2171 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2172
2173 /*
2174 * Program the multicast filter, if necessary.
2175 */
2176 re_setmulti(sc);
2177
2178 #ifdef DEVICE_POLLING
2179 /*
2180 * Disable interrupts if we are polling.
2181 */
2182 if (ifp->if_capenable & IFCAP_POLLING)
2183 CSR_WRITE_2(sc, RL_IMR, 0);
2184 else /* otherwise ... */
2185 #endif
2186 /*
2187 * Enable interrupts.
2188 */
2189 if (sc->rl_testmode)
2190 CSR_WRITE_2(sc, RL_IMR, 0);
2191 else
2192 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2193
2194 /* Set initial TX threshold */
2195 sc->rl_txthresh = RL_TX_THRESH_INIT;
2196
2197 /* Start RX/TX process. */
2198 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2199 #ifdef notdef
2200 /* Enable receiver and transmitter. */
2201 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2202 #endif
2203 /*
2204 * Load the addresses of the RX and TX lists into the chip.
2205 */
2206
2207 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2208 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2209 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2210 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2211
2212 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2213 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2214 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2215 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2216
2217 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2218
2219 /*
2220 * Initialize the timer interrupt register so that
2221 * a timer interrupt will be generated once the timer
2222 * reaches a certain number of ticks. The timer is
2223 * reloaded on each transmit. This gives us TX interrupt
2224 * moderation, which dramatically improves TX frame rate.
2225 */
2226 if (sc->rl_type == RL_8169)
2227 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2228 else
2229 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2230
2231 /*
2232 * For 8169 gigE NICs, set the max allowed RX packet
2233 * size so we can receive jumbo frames.
2234 */
2235 if (sc->rl_type == RL_8169)
2236 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2237
2238 if (sc->rl_testmode)
2239 return;
2240
2241 mii_mediachg(mii);
2242
2243 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2244
2245 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2247
2248 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2249 }
2250
2251 /*
2252 * Set media options.
2253 */
2254 static int
2255 re_ifmedia_upd(ifp)
2256 struct ifnet *ifp;
2257 {
2258 struct rl_softc *sc;
2259 struct mii_data *mii;
2260
2261 sc = ifp->if_softc;
2262 mii = device_get_softc(sc->rl_miibus);
2263 RL_LOCK(sc);
2264 mii_mediachg(mii);
2265 RL_UNLOCK(sc);
2266
2267 return (0);
2268 }
2269
2270 /*
2271 * Report current media status.
2272 */
2273 static void
2274 re_ifmedia_sts(ifp, ifmr)
2275 struct ifnet *ifp;
2276 struct ifmediareq *ifmr;
2277 {
2278 struct rl_softc *sc;
2279 struct mii_data *mii;
2280
2281 sc = ifp->if_softc;
2282 mii = device_get_softc(sc->rl_miibus);
2283
2284 RL_LOCK(sc);
2285 mii_pollstat(mii);
2286 RL_UNLOCK(sc);
2287 ifmr->ifm_active = mii->mii_media_active;
2288 ifmr->ifm_status = mii->mii_media_status;
2289 }
2290
2291 static int
2292 re_ioctl(ifp, command, data)
2293 struct ifnet *ifp;
2294 u_long command;
2295 caddr_t data;
2296 {
2297 struct rl_softc *sc = ifp->if_softc;
2298 struct ifreq *ifr = (struct ifreq *) data;
2299 struct mii_data *mii;
2300 int error = 0;
2301
2302 switch (command) {
2303 case SIOCSIFMTU:
2304 RL_LOCK(sc);
2305 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2306 error = EINVAL;
2307 ifp->if_mtu = ifr->ifr_mtu;
2308 RL_UNLOCK(sc);
2309 break;
2310 case SIOCSIFFLAGS:
2311 RL_LOCK(sc);
2312 if (ifp->if_flags & IFF_UP)
2313 re_init_locked(sc);
2314 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2315 re_stop(sc);
2316 RL_UNLOCK(sc);
2317 break;
2318 case SIOCADDMULTI:
2319 case SIOCDELMULTI:
2320 RL_LOCK(sc);
2321 re_setmulti(sc);
2322 RL_UNLOCK(sc);
2323 break;
2324 case SIOCGIFMEDIA:
2325 case SIOCSIFMEDIA:
2326 mii = device_get_softc(sc->rl_miibus);
2327 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2328 break;
2329 case SIOCSIFCAP:
2330 {
2331 int mask, reinit;
2332
2333 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2334 reinit = 0;
2335 #ifdef DEVICE_POLLING
2336 if (mask & IFCAP_POLLING) {
2337 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2338 error = ether_poll_register(re_poll, ifp);
2339 if (error)
2340 return(error);
2341 RL_LOCK(sc);
2342 /* Disable interrupts */
2343 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2344 ifp->if_capenable |= IFCAP_POLLING;
2345 RL_UNLOCK(sc);
2346
2347 } else {
2348 error = ether_poll_deregister(ifp);
2349 /* Enable interrupts. */
2350 RL_LOCK(sc);
2351 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2352 ifp->if_capenable &= ~IFCAP_POLLING;
2353 RL_UNLOCK(sc);
2354 }
2355 }
2356 #endif /* DEVICE_POLLING */
2357 if (mask & IFCAP_HWCSUM) {
2358 ifp->if_capenable ^= IFCAP_HWCSUM;
2359 if (ifp->if_capenable & IFCAP_TXCSUM)
2360 ifp->if_hwassist = RE_CSUM_FEATURES;
2361 else
2362 ifp->if_hwassist = 0;
2363 reinit = 1;
2364 }
2365 if (mask & IFCAP_VLAN_HWTAGGING) {
2366 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2367 reinit = 1;
2368 }
2369 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
2370 re_init(sc);
2371 }
2372 break;
2373 default:
2374 error = ether_ioctl(ifp, command, data);
2375 break;
2376 }
2377
2378 return (error);
2379 }
2380
2381 static void
2382 re_watchdog(ifp)
2383 struct ifnet *ifp;
2384 {
2385 struct rl_softc *sc;
2386
2387 sc = ifp->if_softc;
2388 RL_LOCK(sc);
2389 if_printf(ifp, "watchdog timeout\n");
2390 ifp->if_oerrors++;
2391
2392 re_txeof(sc);
2393 re_rxeof(sc);
2394 re_init_locked(sc);
2395
2396 RL_UNLOCK(sc);
2397 }
2398
2399 /*
2400 * Stop the adapter and free any mbufs allocated to the
2401 * RX and TX lists.
2402 */
2403 static void
2404 re_stop(sc)
2405 struct rl_softc *sc;
2406 {
2407 register int i;
2408 struct ifnet *ifp;
2409
2410 RL_LOCK_ASSERT(sc);
2411
2412 ifp = sc->rl_ifp;
2413 ifp->if_timer = 0;
2414
2415 callout_stop(&sc->rl_stat_callout);
2416 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2417
2418 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2419 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2420
2421 if (sc->rl_head != NULL) {
2422 m_freem(sc->rl_head);
2423 sc->rl_head = sc->rl_tail = NULL;
2424 }
2425
2426 /* Free the TX list buffers. */
2427
2428 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2429 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2430 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2431 sc->rl_ldata.rl_tx_dmamap[i]);
2432 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2433 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2434 }
2435 }
2436
2437 /* Free the RX list buffers. */
2438
2439 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2440 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2441 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2442 sc->rl_ldata.rl_rx_dmamap[i]);
2443 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2444 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2445 }
2446 }
2447 }
2448
2449 /*
2450 * Device suspend routine. Stop the interface and save some PCI
2451 * settings in case the BIOS doesn't restore them properly on
2452 * resume.
2453 */
2454 static int
2455 re_suspend(dev)
2456 device_t dev;
2457 {
2458 struct rl_softc *sc;
2459
2460 sc = device_get_softc(dev);
2461
2462 RL_LOCK(sc);
2463 re_stop(sc);
2464 sc->suspended = 1;
2465 RL_UNLOCK(sc);
2466
2467 return (0);
2468 }
2469
2470 /*
2471 * Device resume routine. Restore some PCI settings in case the BIOS
2472 * doesn't, re-enable busmastering, and restart the interface if
2473 * appropriate.
2474 */
2475 static int
2476 re_resume(dev)
2477 device_t dev;
2478 {
2479 struct rl_softc *sc;
2480 struct ifnet *ifp;
2481
2482 sc = device_get_softc(dev);
2483
2484 RL_LOCK(sc);
2485
2486 ifp = sc->rl_ifp;
2487
2488 /* reinitialize interface if necessary */
2489 if (ifp->if_flags & IFF_UP)
2490 re_init_locked(sc);
2491
2492 sc->suspended = 0;
2493 RL_UNLOCK(sc);
2494
2495 return (0);
2496 }
2497
2498 /*
2499 * Stop all chip I/O so that the kernel's probe routines don't
2500 * get confused by errant DMAs when rebooting.
2501 */
2502 static void
2503 re_shutdown(dev)
2504 device_t dev;
2505 {
2506 struct rl_softc *sc;
2507
2508 sc = device_get_softc(dev);
2509
2510 RL_LOCK(sc);
2511 re_stop(sc);
2512 /*
2513 * Mark interface as down since otherwise we will panic if
2514 * interrupt comes in later on, which can happen in some
2515 * cases. Another option is to call re_detach() instead of
2516 * re_stop(), like ve(4) does.
2517 */
2518 sc->rl_ifp->if_flags &= ~IFF_UP;
2519 RL_UNLOCK(sc);
2520 }
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