FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.46.2.20 2006/09/21 11:08:28 yongari Exp $");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/taskqueue.h>
127
128 #include <net/if.h>
129 #include <net/if_arp.h>
130 #include <net/ethernet.h>
131 #include <net/if_dl.h>
132 #include <net/if_media.h>
133 #include <net/if_types.h>
134 #include <net/if_vlan_var.h>
135
136 #include <net/bpf.h>
137
138 #include <machine/bus.h>
139 #include <machine/resource.h>
140 #include <sys/bus.h>
141 #include <sys/rman.h>
142
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
145
146 #include <dev/pci/pcireg.h>
147 #include <dev/pci/pcivar.h>
148
149 MODULE_DEPEND(re, pci, 1, 1, 1);
150 MODULE_DEPEND(re, ether, 1, 1, 1);
151 MODULE_DEPEND(re, miibus, 1, 1, 1);
152
153 /* "device miibus" required. See GENERIC if you get errors here. */
154 #include "miibus_if.h"
155
156 /*
157 * Default to using PIO access for this driver.
158 */
159 #define RE_USEIOSPACE
160
161 #include <pci/if_rlreg.h>
162
163 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
164
165 /*
166 * Various supported device vendors/types and their names.
167 */
168 static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
174 "RealTek 8101E PCIe 10/100baseTX" },
175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1,
176 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2,
178 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
180 "RealTek 8169 Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
182 "RealTek 8169S Single-chip Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC,
186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
188 "RealTek 8110S Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" },
195 { 0, 0, 0, NULL }
196 };
197
198 static struct rl_hwrev re_hwrevs[] = {
199 { RL_HWREV_8139, RL_8139, "" },
200 { RL_HWREV_8139A, RL_8139, "A" },
201 { RL_HWREV_8139AG, RL_8139, "A-G" },
202 { RL_HWREV_8139B, RL_8139, "B" },
203 { RL_HWREV_8130, RL_8139, "8130" },
204 { RL_HWREV_8139C, RL_8139, "C" },
205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
208 { RL_HWREV_8169, RL_8169, "8169"},
209 { RL_HWREV_8169S, RL_8169, "8169S"},
210 { RL_HWREV_8110S, RL_8169, "8110S"},
211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
213 { RL_HWREV_8100, RL_8139, "8100"},
214 { RL_HWREV_8101, RL_8139, "8101"},
215 { RL_HWREV_8100E, RL_8169, "8100E"},
216 { RL_HWREV_8101E, RL_8169, "8101E"},
217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
218 { 0, 0, NULL }
219 };
220
221 static int re_probe (device_t);
222 static int re_attach (device_t);
223 static int re_detach (device_t);
224
225 static int re_encap (struct rl_softc *, struct mbuf **, int *);
226
227 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
228 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
229 bus_size_t, int);
230 static int re_allocmem (device_t, struct rl_softc *);
231 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
232 static int re_rx_list_init (struct rl_softc *);
233 static int re_tx_list_init (struct rl_softc *);
234 #ifdef RE_FIXUP_RX
235 static __inline void re_fixup_rx
236 (struct mbuf *);
237 #endif
238 static int re_rxeof (struct rl_softc *);
239 static void re_txeof (struct rl_softc *);
240 #ifdef DEVICE_POLLING
241 static void re_poll (struct ifnet *, enum poll_cmd, int);
242 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
243 #endif
244 static void re_intr (void *);
245 static void re_tick (void *);
246 static void re_tx_task (void *, int);
247 static void re_int_task (void *, int);
248 static void re_start (struct ifnet *);
249 static int re_ioctl (struct ifnet *, u_long, caddr_t);
250 static void re_init (void *);
251 static void re_init_locked (struct rl_softc *);
252 static void re_stop (struct rl_softc *);
253 static void re_watchdog (struct ifnet *);
254 static int re_suspend (device_t);
255 static int re_resume (device_t);
256 static void re_shutdown (device_t);
257 static int re_ifmedia_upd (struct ifnet *);
258 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
259
260 static void re_eeprom_putbyte (struct rl_softc *, int);
261 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
262 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
263 static int re_gmii_readreg (device_t, int, int);
264 static int re_gmii_writereg (device_t, int, int, int);
265
266 static int re_miibus_readreg (device_t, int, int);
267 static int re_miibus_writereg (device_t, int, int, int);
268 static void re_miibus_statchg (device_t);
269
270 static void re_setmulti (struct rl_softc *);
271 static void re_reset (struct rl_softc *);
272
273 #ifdef RE_DIAG
274 static int re_diag (struct rl_softc *);
275 #endif
276
277 #ifdef RE_USEIOSPACE
278 #define RL_RES SYS_RES_IOPORT
279 #define RL_RID RL_PCI_LOIO
280 #else
281 #define RL_RES SYS_RES_MEMORY
282 #define RL_RID RL_PCI_LOMEM
283 #endif
284
285 static device_method_t re_methods[] = {
286 /* Device interface */
287 DEVMETHOD(device_probe, re_probe),
288 DEVMETHOD(device_attach, re_attach),
289 DEVMETHOD(device_detach, re_detach),
290 DEVMETHOD(device_suspend, re_suspend),
291 DEVMETHOD(device_resume, re_resume),
292 DEVMETHOD(device_shutdown, re_shutdown),
293
294 /* bus interface */
295 DEVMETHOD(bus_print_child, bus_generic_print_child),
296 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
297
298 /* MII interface */
299 DEVMETHOD(miibus_readreg, re_miibus_readreg),
300 DEVMETHOD(miibus_writereg, re_miibus_writereg),
301 DEVMETHOD(miibus_statchg, re_miibus_statchg),
302
303 { 0, 0 }
304 };
305
306 static driver_t re_driver = {
307 "re",
308 re_methods,
309 sizeof(struct rl_softc)
310 };
311
312 static devclass_t re_devclass;
313
314 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
315 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
316 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
317
318 #define EE_SET(x) \
319 CSR_WRITE_1(sc, RL_EECMD, \
320 CSR_READ_1(sc, RL_EECMD) | x)
321
322 #define EE_CLR(x) \
323 CSR_WRITE_1(sc, RL_EECMD, \
324 CSR_READ_1(sc, RL_EECMD) & ~x)
325
326 /*
327 * Send a read command and address to the EEPROM, check for ACK.
328 */
329 static void
330 re_eeprom_putbyte(sc, addr)
331 struct rl_softc *sc;
332 int addr;
333 {
334 register int d, i;
335
336 d = addr | (RL_9346_READ << sc->rl_eewidth);
337
338 /*
339 * Feed in each bit and strobe the clock.
340 */
341
342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
343 if (d & i) {
344 EE_SET(RL_EE_DATAIN);
345 } else {
346 EE_CLR(RL_EE_DATAIN);
347 }
348 DELAY(100);
349 EE_SET(RL_EE_CLK);
350 DELAY(150);
351 EE_CLR(RL_EE_CLK);
352 DELAY(100);
353 }
354
355 return;
356 }
357
358 /*
359 * Read a word of data stored in the EEPROM at address 'addr.'
360 */
361 static void
362 re_eeprom_getword(sc, addr, dest)
363 struct rl_softc *sc;
364 int addr;
365 u_int16_t *dest;
366 {
367 register int i;
368 u_int16_t word = 0;
369
370 /*
371 * Send address of word we want to read.
372 */
373 re_eeprom_putbyte(sc, addr);
374
375 /*
376 * Start reading bits from EEPROM.
377 */
378 for (i = 0x8000; i; i >>= 1) {
379 EE_SET(RL_EE_CLK);
380 DELAY(100);
381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
382 word |= i;
383 EE_CLR(RL_EE_CLK);
384 DELAY(100);
385 }
386
387 *dest = word;
388
389 return;
390 }
391
392 /*
393 * Read a sequence of words from the EEPROM.
394 */
395 static void
396 re_read_eeprom(sc, dest, off, cnt)
397 struct rl_softc *sc;
398 caddr_t dest;
399 int off;
400 int cnt;
401 {
402 int i;
403 u_int16_t word = 0, *ptr;
404
405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
406
407 DELAY(100);
408
409 for (i = 0; i < cnt; i++) {
410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
411 re_eeprom_getword(sc, off + i, &word);
412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
413 ptr = (u_int16_t *)(dest + (i * 2));
414 *ptr = word;
415 }
416
417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
418
419 return;
420 }
421
422 static int
423 re_gmii_readreg(dev, phy, reg)
424 device_t dev;
425 int phy, reg;
426 {
427 struct rl_softc *sc;
428 u_int32_t rval;
429 int i;
430
431 if (phy != 1)
432 return (0);
433
434 sc = device_get_softc(dev);
435
436 /* Let the rgephy driver read the GMEDIASTAT register */
437
438 if (reg == RL_GMEDIASTAT) {
439 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
440 return (rval);
441 }
442
443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
444 DELAY(1000);
445
446 for (i = 0; i < RL_TIMEOUT; i++) {
447 rval = CSR_READ_4(sc, RL_PHYAR);
448 if (rval & RL_PHYAR_BUSY)
449 break;
450 DELAY(100);
451 }
452
453 if (i == RL_TIMEOUT) {
454 if_printf(sc->rl_ifp, "PHY read failed\n");
455 return (0);
456 }
457
458 return (rval & RL_PHYAR_PHYDATA);
459 }
460
461 static int
462 re_gmii_writereg(dev, phy, reg, data)
463 device_t dev;
464 int phy, reg, data;
465 {
466 struct rl_softc *sc;
467 u_int32_t rval;
468 int i;
469
470 sc = device_get_softc(dev);
471
472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
474 DELAY(1000);
475
476 for (i = 0; i < RL_TIMEOUT; i++) {
477 rval = CSR_READ_4(sc, RL_PHYAR);
478 if (!(rval & RL_PHYAR_BUSY))
479 break;
480 DELAY(100);
481 }
482
483 if (i == RL_TIMEOUT) {
484 if_printf(sc->rl_ifp, "PHY write failed\n");
485 return (0);
486 }
487
488 return (0);
489 }
490
491 static int
492 re_miibus_readreg(dev, phy, reg)
493 device_t dev;
494 int phy, reg;
495 {
496 struct rl_softc *sc;
497 u_int16_t rval = 0;
498 u_int16_t re8139_reg = 0;
499
500 sc = device_get_softc(dev);
501
502 if (sc->rl_type == RL_8169) {
503 rval = re_gmii_readreg(dev, phy, reg);
504 return (rval);
505 }
506
507 /* Pretend the internal PHY is only at address 0 */
508 if (phy) {
509 return (0);
510 }
511 switch (reg) {
512 case MII_BMCR:
513 re8139_reg = RL_BMCR;
514 break;
515 case MII_BMSR:
516 re8139_reg = RL_BMSR;
517 break;
518 case MII_ANAR:
519 re8139_reg = RL_ANAR;
520 break;
521 case MII_ANER:
522 re8139_reg = RL_ANER;
523 break;
524 case MII_ANLPAR:
525 re8139_reg = RL_LPAR;
526 break;
527 case MII_PHYIDR1:
528 case MII_PHYIDR2:
529 return (0);
530 /*
531 * Allow the rlphy driver to read the media status
532 * register. If we have a link partner which does not
533 * support NWAY, this is the register which will tell
534 * us the results of parallel detection.
535 */
536 case RL_MEDIASTAT:
537 rval = CSR_READ_1(sc, RL_MEDIASTAT);
538 return (rval);
539 default:
540 if_printf(sc->rl_ifp, "bad phy register\n");
541 return (0);
542 }
543 rval = CSR_READ_2(sc, re8139_reg);
544 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
545 /* 8139C+ has different bit layout. */
546 rval &= ~(BMCR_LOOP | BMCR_ISO);
547 }
548 return (rval);
549 }
550
551 static int
552 re_miibus_writereg(dev, phy, reg, data)
553 device_t dev;
554 int phy, reg, data;
555 {
556 struct rl_softc *sc;
557 u_int16_t re8139_reg = 0;
558 int rval = 0;
559
560 sc = device_get_softc(dev);
561
562 if (sc->rl_type == RL_8169) {
563 rval = re_gmii_writereg(dev, phy, reg, data);
564 return (rval);
565 }
566
567 /* Pretend the internal PHY is only at address 0 */
568 if (phy)
569 return (0);
570
571 switch (reg) {
572 case MII_BMCR:
573 re8139_reg = RL_BMCR;
574 if (sc->rl_type == RL_8139CPLUS) {
575 /* 8139C+ has different bit layout. */
576 data &= ~(BMCR_LOOP | BMCR_ISO);
577 }
578 break;
579 case MII_BMSR:
580 re8139_reg = RL_BMSR;
581 break;
582 case MII_ANAR:
583 re8139_reg = RL_ANAR;
584 break;
585 case MII_ANER:
586 re8139_reg = RL_ANER;
587 break;
588 case MII_ANLPAR:
589 re8139_reg = RL_LPAR;
590 break;
591 case MII_PHYIDR1:
592 case MII_PHYIDR2:
593 return (0);
594 break;
595 default:
596 if_printf(sc->rl_ifp, "bad phy register\n");
597 return (0);
598 }
599 CSR_WRITE_2(sc, re8139_reg, data);
600 return (0);
601 }
602
603 static void
604 re_miibus_statchg(dev)
605 device_t dev;
606 {
607
608 }
609
610 /*
611 * Program the 64-bit multicast hash filter.
612 */
613 static void
614 re_setmulti(sc)
615 struct rl_softc *sc;
616 {
617 struct ifnet *ifp;
618 int h = 0;
619 u_int32_t hashes[2] = { 0, 0 };
620 struct ifmultiaddr *ifma;
621 u_int32_t rxfilt;
622 int mcnt = 0;
623
624 RL_LOCK_ASSERT(sc);
625
626 ifp = sc->rl_ifp;
627
628 rxfilt = CSR_READ_4(sc, RL_RXCFG);
629
630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
631 rxfilt |= RL_RXCFG_RX_MULTI;
632 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
633 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
634 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
635 return;
636 }
637
638 /* first, zot all the existing hash bits */
639 CSR_WRITE_4(sc, RL_MAR0, 0);
640 CSR_WRITE_4(sc, RL_MAR4, 0);
641
642 /* now program new ones */
643 IF_ADDR_LOCK(ifp);
644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
645 if (ifma->ifma_addr->sa_family != AF_LINK)
646 continue;
647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
649 if (h < 32)
650 hashes[0] |= (1 << h);
651 else
652 hashes[1] |= (1 << (h - 32));
653 mcnt++;
654 }
655 IF_ADDR_UNLOCK(ifp);
656
657 if (mcnt)
658 rxfilt |= RL_RXCFG_RX_MULTI;
659 else
660 rxfilt &= ~RL_RXCFG_RX_MULTI;
661
662 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
663 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
664 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
665 }
666
667 static void
668 re_reset(sc)
669 struct rl_softc *sc;
670 {
671 register int i;
672
673 RL_LOCK_ASSERT(sc);
674
675 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
676
677 for (i = 0; i < RL_TIMEOUT; i++) {
678 DELAY(10);
679 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
680 break;
681 }
682 if (i == RL_TIMEOUT)
683 if_printf(sc->rl_ifp, "reset never completed!\n");
684
685 CSR_WRITE_1(sc, 0x82, 1);
686 }
687
688 #ifdef RE_DIAG
689
690 /*
691 * The following routine is designed to test for a defect on some
692 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
693 * lines connected to the bus, however for a 32-bit only card, they
694 * should be pulled high. The result of this defect is that the
695 * NIC will not work right if you plug it into a 64-bit slot: DMA
696 * operations will be done with 64-bit transfers, which will fail
697 * because the 64-bit data lines aren't connected.
698 *
699 * There's no way to work around this (short of talking a soldering
700 * iron to the board), however we can detect it. The method we use
701 * here is to put the NIC into digital loopback mode, set the receiver
702 * to promiscuous mode, and then try to send a frame. We then compare
703 * the frame data we sent to what was received. If the data matches,
704 * then the NIC is working correctly, otherwise we know the user has
705 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
706 * slot. In the latter case, there's no way the NIC can work correctly,
707 * so we print out a message on the console and abort the device attach.
708 */
709
710 static int
711 re_diag(sc)
712 struct rl_softc *sc;
713 {
714 struct ifnet *ifp = sc->rl_ifp;
715 struct mbuf *m0;
716 struct ether_header *eh;
717 struct rl_desc *cur_rx;
718 u_int16_t status;
719 u_int32_t rxstat;
720 int total_len, i, error = 0, phyaddr;
721 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
722 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
723
724 /* Allocate a single mbuf */
725 MGETHDR(m0, M_DONTWAIT, MT_DATA);
726 if (m0 == NULL)
727 return (ENOBUFS);
728
729 RL_LOCK(sc);
730
731 /*
732 * Initialize the NIC in test mode. This sets the chip up
733 * so that it can send and receive frames, but performs the
734 * following special functions:
735 * - Puts receiver in promiscuous mode
736 * - Enables digital loopback mode
737 * - Leaves interrupts turned off
738 */
739
740 ifp->if_flags |= IFF_PROMISC;
741 sc->rl_testmode = 1;
742 re_reset(sc);
743 re_init_locked(sc);
744 sc->rl_link = 1;
745 if (sc->rl_type == RL_8169)
746 phyaddr = 1;
747 else
748 phyaddr = 0;
749
750 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
751 for (i = 0; i < RL_TIMEOUT; i++) {
752 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
753 if (!(status & BMCR_RESET))
754 break;
755 }
756
757 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
758 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
759
760 DELAY(100000);
761
762 /* Put some data in the mbuf */
763
764 eh = mtod(m0, struct ether_header *);
765 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
766 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
767 eh->ether_type = htons(ETHERTYPE_IP);
768 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
769
770 /*
771 * Queue the packet, start transmission.
772 * Note: IF_HANDOFF() ultimately calls re_start() for us.
773 */
774
775 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
776 RL_UNLOCK(sc);
777 /* XXX: re_diag must not be called when in ALTQ mode */
778 IF_HANDOFF(&ifp->if_snd, m0, ifp);
779 RL_LOCK(sc);
780 m0 = NULL;
781
782 /* Wait for it to propagate through the chip */
783
784 DELAY(100000);
785 for (i = 0; i < RL_TIMEOUT; i++) {
786 status = CSR_READ_2(sc, RL_ISR);
787 CSR_WRITE_2(sc, RL_ISR, status);
788 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
789 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
790 break;
791 DELAY(10);
792 }
793
794 if (i == RL_TIMEOUT) {
795 if_printf(ifp, "diagnostic failed, failed to receive packet "
796 "in loopback mode\n");
797 error = EIO;
798 goto done;
799 }
800
801 /*
802 * The packet should have been dumped into the first
803 * entry in the RX DMA ring. Grab it from there.
804 */
805
806 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
807 sc->rl_ldata.rl_rx_list_map,
808 BUS_DMASYNC_POSTREAD);
809 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
810 sc->rl_ldata.rl_rx_dmamap[0],
811 BUS_DMASYNC_POSTWRITE);
812 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
813 sc->rl_ldata.rl_rx_dmamap[0]);
814
815 m0 = sc->rl_ldata.rl_rx_mbuf[0];
816 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
817 eh = mtod(m0, struct ether_header *);
818
819 cur_rx = &sc->rl_ldata.rl_rx_list[0];
820 total_len = RL_RXBYTES(cur_rx);
821 rxstat = le32toh(cur_rx->rl_cmdstat);
822
823 if (total_len != ETHER_MIN_LEN) {
824 if_printf(ifp, "diagnostic failed, received short packet\n");
825 error = EIO;
826 goto done;
827 }
828
829 /* Test that the received packet data matches what we sent. */
830
831 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
832 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
833 ntohs(eh->ether_type) != ETHERTYPE_IP) {
834 if_printf(ifp, "WARNING, DMA FAILURE!\n");
835 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
836 dst, ":", src, ":", ETHERTYPE_IP);
837 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
838 eh->ether_dhost, ":", eh->ether_shost, ":",
839 ntohs(eh->ether_type));
840 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
841 "into a 64-bit PCI slot.\n");
842 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
843 "for proper operation.\n");
844 if_printf(ifp, "Read the re(4) man page for more details.\n");
845 error = EIO;
846 }
847
848 done:
849 /* Turn interface off, release resources */
850
851 sc->rl_testmode = 0;
852 sc->rl_link = 0;
853 ifp->if_flags &= ~IFF_PROMISC;
854 re_stop(sc);
855 if (m0 != NULL)
856 m_freem(m0);
857
858 RL_UNLOCK(sc);
859
860 return (error);
861 }
862
863 #endif
864
865 /*
866 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
867 * IDs against our list and return a device name if we find a match.
868 */
869 static int
870 re_probe(dev)
871 device_t dev;
872 {
873 struct rl_type *t;
874 struct rl_softc *sc;
875 int rid;
876 u_int32_t hwrev;
877
878 t = re_devs;
879 sc = device_get_softc(dev);
880
881 while (t->rl_name != NULL) {
882 if ((pci_get_vendor(dev) == t->rl_vid) &&
883 (pci_get_device(dev) == t->rl_did)) {
884 /*
885 * Only attach to rev. 3 of the Linksys EG1032 adapter.
886 * Rev. 2 i supported by sk(4).
887 */
888 if ((t->rl_vid == LINKSYS_VENDORID) &&
889 (t->rl_did == LINKSYS_DEVICEID_EG1032) &&
890 (pci_get_subdevice(dev) !=
891 LINKSYS_SUBDEVICE_EG1032_REV3)) {
892 t++;
893 continue;
894 }
895
896 /*
897 * Temporarily map the I/O space
898 * so we can read the chip ID register.
899 */
900 rid = RL_RID;
901 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
902 RF_ACTIVE);
903 if (sc->rl_res == NULL) {
904 device_printf(dev,
905 "couldn't map ports/memory\n");
906 return (ENXIO);
907 }
908 sc->rl_btag = rman_get_bustag(sc->rl_res);
909 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
910 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
911 bus_release_resource(dev, RL_RES,
912 RL_RID, sc->rl_res);
913 if (t->rl_basetype == hwrev) {
914 device_set_desc(dev, t->rl_name);
915 return (BUS_PROBE_DEFAULT);
916 }
917 }
918 t++;
919 }
920
921 return (ENXIO);
922 }
923
924 /*
925 * This routine takes the segment list provided as the result of
926 * a bus_dma_map_load() operation and assigns the addresses/lengths
927 * to RealTek DMA descriptors. This can be called either by the RX
928 * code or the TX code. In the RX case, we'll probably wind up mapping
929 * at most one segment. For the TX case, there could be any number of
930 * segments since TX packets may span multiple mbufs. In either case,
931 * if the number of segments is larger than the rl_maxsegs limit
932 * specified by the caller, we abort the mapping operation. Sadly,
933 * whoever designed the buffer mapping API did not provide a way to
934 * return an error from here, so we have to fake it a bit.
935 */
936
937 static void
938 re_dma_map_desc(arg, segs, nseg, mapsize, error)
939 void *arg;
940 bus_dma_segment_t *segs;
941 int nseg;
942 bus_size_t mapsize;
943 int error;
944 {
945 struct rl_dmaload_arg *ctx;
946 struct rl_desc *d = NULL;
947 int i = 0, idx;
948 u_int32_t cmdstat;
949 int totlen = 0;
950
951 if (error)
952 return;
953
954 ctx = arg;
955
956 /* Signal error to caller if there's too many segments */
957 if (nseg > ctx->rl_maxsegs) {
958 ctx->rl_maxsegs = 0;
959 return;
960 }
961
962 /*
963 * Map the segment array into descriptors. Note that we set the
964 * start-of-frame and end-of-frame markers for either TX or RX, but
965 * they really only have meaning in the TX case. (In the RX case,
966 * it's the chip that tells us where packets begin and end.)
967 * We also keep track of the end of the ring and set the
968 * end-of-ring bits as needed, and we set the ownership bits
969 * in all except the very first descriptor. (The caller will
970 * set this descriptor later when it start transmission or
971 * reception.)
972 */
973 idx = ctx->rl_idx;
974 for (;;) {
975 d = &ctx->rl_ring[idx];
976 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
977 ctx->rl_maxsegs = 0;
978 return;
979 }
980 cmdstat = segs[i].ds_len;
981 totlen += segs[i].ds_len;
982 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
983 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
984 if (i == 0)
985 cmdstat |= RL_TDESC_CMD_SOF;
986 else
987 cmdstat |= RL_TDESC_CMD_OWN;
988 if (idx == (RL_RX_DESC_CNT - 1))
989 cmdstat |= RL_TDESC_CMD_EOR;
990 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
991 i++;
992 if (i == nseg)
993 break;
994 RL_DESC_INC(idx);
995 }
996
997 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
998 ctx->rl_maxsegs = nseg;
999 ctx->rl_idx = idx;
1000 }
1001
1002 /*
1003 * Map a single buffer address.
1004 */
1005
1006 static void
1007 re_dma_map_addr(arg, segs, nseg, error)
1008 void *arg;
1009 bus_dma_segment_t *segs;
1010 int nseg;
1011 int error;
1012 {
1013 bus_addr_t *addr;
1014
1015 if (error)
1016 return;
1017
1018 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1019 addr = arg;
1020 *addr = segs->ds_addr;
1021 }
1022
1023 static int
1024 re_allocmem(dev, sc)
1025 device_t dev;
1026 struct rl_softc *sc;
1027 {
1028 int error;
1029 int nseg;
1030 int i;
1031
1032 /*
1033 * Allocate map for RX mbufs.
1034 */
1035 nseg = 32;
1036 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
1037 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1038 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
1039 NULL, NULL, &sc->rl_ldata.rl_mtag);
1040 if (error) {
1041 device_printf(dev, "could not allocate dma tag\n");
1042 return (ENOMEM);
1043 }
1044
1045 /*
1046 * Allocate map for TX descriptor list.
1047 */
1048 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1049 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1050 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
1051 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1052 if (error) {
1053 device_printf(dev, "could not allocate dma tag\n");
1054 return (ENOMEM);
1055 }
1056
1057 /* Allocate DMA'able memory for the TX ring */
1058
1059 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1060 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1061 &sc->rl_ldata.rl_tx_list_map);
1062 if (error)
1063 return (ENOMEM);
1064
1065 /* Load the map for the TX ring. */
1066
1067 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1068 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1069 RL_TX_LIST_SZ, re_dma_map_addr,
1070 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1071
1072 /* Create DMA maps for TX buffers */
1073
1074 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1075 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1076 &sc->rl_ldata.rl_tx_dmamap[i]);
1077 if (error) {
1078 device_printf(dev, "can't create DMA map for TX\n");
1079 return (ENOMEM);
1080 }
1081 }
1082
1083 /*
1084 * Allocate map for RX descriptor list.
1085 */
1086 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1087 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1088 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1089 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1090 if (error) {
1091 device_printf(dev, "could not allocate dma tag\n");
1092 return (ENOMEM);
1093 }
1094
1095 /* Allocate DMA'able memory for the RX ring */
1096
1097 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1098 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1099 &sc->rl_ldata.rl_rx_list_map);
1100 if (error)
1101 return (ENOMEM);
1102
1103 /* Load the map for the RX ring. */
1104
1105 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1106 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1107 RL_RX_LIST_SZ, re_dma_map_addr,
1108 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1109
1110 /* Create DMA maps for RX buffers */
1111
1112 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1113 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1114 &sc->rl_ldata.rl_rx_dmamap[i]);
1115 if (error) {
1116 device_printf(dev, "can't create DMA map for RX\n");
1117 return (ENOMEM);
1118 }
1119 }
1120
1121 return (0);
1122 }
1123
1124 /*
1125 * Attach the interface. Allocate softc structures, do ifmedia
1126 * setup and ethernet/BPF attach.
1127 */
1128 static int
1129 re_attach(dev)
1130 device_t dev;
1131 {
1132 u_char eaddr[ETHER_ADDR_LEN];
1133 u_int16_t as[ETHER_ADDR_LEN / 2];
1134 struct rl_softc *sc;
1135 struct ifnet *ifp;
1136 struct rl_hwrev *hw_rev;
1137 int hwrev;
1138 u_int16_t re_did = 0;
1139 int error = 0, rid, i;
1140
1141 sc = device_get_softc(dev);
1142 sc->rl_dev = dev;
1143
1144 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1145 MTX_DEF);
1146 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1147
1148 /*
1149 * Map control/status registers.
1150 */
1151 pci_enable_busmaster(dev);
1152
1153 rid = RL_RID;
1154 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1155 RF_ACTIVE);
1156
1157 if (sc->rl_res == NULL) {
1158 device_printf(dev, "couldn't map ports/memory\n");
1159 error = ENXIO;
1160 goto fail;
1161 }
1162
1163 sc->rl_btag = rman_get_bustag(sc->rl_res);
1164 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1165
1166 /* Allocate interrupt */
1167 rid = 0;
1168 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1169 RF_SHAREABLE | RF_ACTIVE);
1170
1171 if (sc->rl_irq == NULL) {
1172 device_printf(dev, "couldn't map interrupt\n");
1173 error = ENXIO;
1174 goto fail;
1175 }
1176
1177 /* Reset the adapter. */
1178 RL_LOCK(sc);
1179 re_reset(sc);
1180 RL_UNLOCK(sc);
1181
1182 hw_rev = re_hwrevs;
1183 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1184 while (hw_rev->rl_desc != NULL) {
1185 if (hw_rev->rl_rev == hwrev) {
1186 sc->rl_type = hw_rev->rl_type;
1187 break;
1188 }
1189 hw_rev++;
1190 }
1191
1192 sc->rl_eewidth = 6;
1193 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1194 if (re_did != 0x8129)
1195 sc->rl_eewidth = 8;
1196
1197 /*
1198 * Get station address from the EEPROM.
1199 */
1200 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1201 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1202 as[i] = le16toh(as[i]);
1203 bcopy(as, eaddr, sizeof(eaddr));
1204
1205 if (sc->rl_type == RL_8169) {
1206 /* Set RX length mask */
1207 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1208 sc->rl_txstart = RL_GTXSTART;
1209 } else {
1210 /* Set RX length mask */
1211 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1212 sc->rl_txstart = RL_TXSTART;
1213 }
1214
1215 /*
1216 * Allocate the parent bus DMA tag appropriate for PCI.
1217 */
1218 #define RL_NSEG_NEW 32
1219 error = bus_dma_tag_create(NULL, /* parent */
1220 1, 0, /* alignment, boundary */
1221 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1222 BUS_SPACE_MAXADDR, /* highaddr */
1223 NULL, NULL, /* filter, filterarg */
1224 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1225 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1226 BUS_DMA_ALLOCNOW, /* flags */
1227 NULL, NULL, /* lockfunc, lockarg */
1228 &sc->rl_parent_tag);
1229 if (error)
1230 goto fail;
1231
1232 error = re_allocmem(dev, sc);
1233
1234 if (error)
1235 goto fail;
1236
1237 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1238 if (ifp == NULL) {
1239 device_printf(dev, "can not if_alloc()\n");
1240 error = ENOSPC;
1241 goto fail;
1242 }
1243
1244 /* Do MII setup */
1245 if (mii_phy_probe(dev, &sc->rl_miibus,
1246 re_ifmedia_upd, re_ifmedia_sts)) {
1247 device_printf(dev, "MII without any phy!\n");
1248 error = ENXIO;
1249 goto fail;
1250 }
1251
1252 ifp->if_softc = sc;
1253 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1254 ifp->if_mtu = ETHERMTU;
1255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1256 ifp->if_ioctl = re_ioctl;
1257 ifp->if_capabilities = IFCAP_VLAN_MTU;
1258 ifp->if_start = re_start;
1259 ifp->if_hwassist = RE_CSUM_FEATURES;
1260 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1261 ifp->if_capenable = ifp->if_capabilities;
1262 #ifdef DEVICE_POLLING
1263 ifp->if_capabilities |= IFCAP_POLLING;
1264 #endif
1265 ifp->if_watchdog = re_watchdog;
1266 ifp->if_init = re_init;
1267 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1268 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1269 IFQ_SET_READY(&ifp->if_snd);
1270
1271 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1272 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1273
1274 /*
1275 * Call MI attach routine.
1276 */
1277 ether_ifattach(ifp, eaddr);
1278
1279 #ifdef RE_DIAG
1280 /*
1281 * Perform hardware diagnostic on the original RTL8169.
1282 * Some 32-bit cards were incorrectly wired and would
1283 * malfunction if plugged into a 64-bit slot.
1284 */
1285
1286 if (hwrev == RL_HWREV_8169) {
1287 error = re_diag(sc);
1288 if (error) {
1289 device_printf(dev,
1290 "attach aborted due to hardware diag failure\n");
1291 ether_ifdetach(ifp);
1292 goto fail;
1293 }
1294 }
1295 #endif
1296
1297 /* Hook interrupt last to avoid having to lock softc */
1298 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE |
1299 INTR_FAST, re_intr, sc, &sc->rl_intrhand);
1300 if (error) {
1301 device_printf(dev, "couldn't set up irq\n");
1302 ether_ifdetach(ifp);
1303 }
1304
1305 fail:
1306
1307 if (error)
1308 re_detach(dev);
1309
1310 return (error);
1311 }
1312
1313 /*
1314 * Shutdown hardware and free up resources. This can be called any
1315 * time after the mutex has been initialized. It is called in both
1316 * the error case in attach and the normal detach case so it needs
1317 * to be careful about only freeing resources that have actually been
1318 * allocated.
1319 */
1320 static int
1321 re_detach(dev)
1322 device_t dev;
1323 {
1324 struct rl_softc *sc;
1325 struct ifnet *ifp;
1326 int i;
1327
1328 sc = device_get_softc(dev);
1329 ifp = sc->rl_ifp;
1330 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1331
1332 #ifdef DEVICE_POLLING
1333 if (ifp->if_capenable & IFCAP_POLLING)
1334 ether_poll_deregister(ifp);
1335 #endif
1336 /* These should only be active if attach succeeded */
1337 if (device_is_attached(dev)) {
1338 RL_LOCK(sc);
1339 #if 0
1340 sc->suspended = 1;
1341 #endif
1342 re_stop(sc);
1343 RL_UNLOCK(sc);
1344 callout_drain(&sc->rl_stat_callout);
1345 /*
1346 * Force off the IFF_UP flag here, in case someone
1347 * still had a BPF descriptor attached to this
1348 * interface. If they do, ether_ifdetach() will cause
1349 * the BPF code to try and clear the promisc mode
1350 * flag, which will bubble down to re_ioctl(),
1351 * which will try to call re_init() again. This will
1352 * turn the NIC back on and restart the MII ticker,
1353 * which will panic the system when the kernel tries
1354 * to invoke the re_tick() function that isn't there
1355 * anymore.
1356 */
1357 ifp->if_flags &= ~IFF_UP;
1358 ether_ifdetach(ifp);
1359 }
1360 if (sc->rl_miibus)
1361 device_delete_child(dev, sc->rl_miibus);
1362 bus_generic_detach(dev);
1363
1364 /*
1365 * The rest is resource deallocation, so we should already be
1366 * stopped here.
1367 */
1368
1369 if (sc->rl_intrhand)
1370 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1371 if (ifp != NULL)
1372 if_free(ifp);
1373 if (sc->rl_irq)
1374 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1375 if (sc->rl_res)
1376 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1377
1378 /* Yield the CPU long enough for any tasks to drain */
1379
1380 tsleep(sc, PPAUSE, "rewait", hz);
1381
1382 /* Unload and free the RX DMA ring memory and map */
1383
1384 if (sc->rl_ldata.rl_rx_list_tag) {
1385 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1386 sc->rl_ldata.rl_rx_list_map);
1387 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1388 sc->rl_ldata.rl_rx_list,
1389 sc->rl_ldata.rl_rx_list_map);
1390 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1391 }
1392
1393 /* Unload and free the TX DMA ring memory and map */
1394
1395 if (sc->rl_ldata.rl_tx_list_tag) {
1396 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1397 sc->rl_ldata.rl_tx_list_map);
1398 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1399 sc->rl_ldata.rl_tx_list,
1400 sc->rl_ldata.rl_tx_list_map);
1401 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1402 }
1403
1404 /* Destroy all the RX and TX buffer maps */
1405
1406 if (sc->rl_ldata.rl_mtag) {
1407 for (i = 0; i < RL_TX_DESC_CNT; i++)
1408 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1409 sc->rl_ldata.rl_tx_dmamap[i]);
1410 for (i = 0; i < RL_RX_DESC_CNT; i++)
1411 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1412 sc->rl_ldata.rl_rx_dmamap[i]);
1413 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1414 }
1415
1416 /* Unload and free the stats buffer and map */
1417
1418 if (sc->rl_ldata.rl_stag) {
1419 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1420 sc->rl_ldata.rl_rx_list_map);
1421 bus_dmamem_free(sc->rl_ldata.rl_stag,
1422 sc->rl_ldata.rl_stats,
1423 sc->rl_ldata.rl_smap);
1424 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1425 }
1426
1427 if (sc->rl_parent_tag)
1428 bus_dma_tag_destroy(sc->rl_parent_tag);
1429
1430 mtx_destroy(&sc->rl_mtx);
1431
1432 return (0);
1433 }
1434
1435 static int
1436 re_newbuf(sc, idx, m)
1437 struct rl_softc *sc;
1438 int idx;
1439 struct mbuf *m;
1440 {
1441 struct rl_dmaload_arg arg;
1442 struct mbuf *n = NULL;
1443 int error;
1444
1445 if (m == NULL) {
1446 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1447 if (n == NULL)
1448 return (ENOBUFS);
1449 m = n;
1450 } else
1451 m->m_data = m->m_ext.ext_buf;
1452
1453 m->m_len = m->m_pkthdr.len = MCLBYTES;
1454 #ifdef RE_FIXUP_RX
1455 /*
1456 * This is part of an evil trick to deal with non-x86 platforms.
1457 * The RealTek chip requires RX buffers to be aligned on 64-bit
1458 * boundaries, but that will hose non-x86 machines. To get around
1459 * this, we leave some empty space at the start of each buffer
1460 * and for non-x86 hosts, we copy the buffer back six bytes
1461 * to achieve word alignment. This is slightly more efficient
1462 * than allocating a new buffer, copying the contents, and
1463 * discarding the old buffer.
1464 */
1465 m_adj(m, RE_ETHER_ALIGN);
1466 #endif
1467 arg.sc = sc;
1468 arg.rl_idx = idx;
1469 arg.rl_maxsegs = 1;
1470 arg.rl_flags = 0;
1471 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1472
1473 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1474 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1475 &arg, BUS_DMA_NOWAIT);
1476 if (error || arg.rl_maxsegs != 1) {
1477 if (n != NULL)
1478 m_freem(n);
1479 return (ENOMEM);
1480 }
1481
1482 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1483 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1484
1485 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1486 sc->rl_ldata.rl_rx_dmamap[idx],
1487 BUS_DMASYNC_PREREAD);
1488
1489 return (0);
1490 }
1491
1492 #ifdef RE_FIXUP_RX
1493 static __inline void
1494 re_fixup_rx(m)
1495 struct mbuf *m;
1496 {
1497 int i;
1498 uint16_t *src, *dst;
1499
1500 src = mtod(m, uint16_t *);
1501 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1502
1503 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1504 *dst++ = *src++;
1505
1506 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1507
1508 return;
1509 }
1510 #endif
1511
1512 static int
1513 re_tx_list_init(sc)
1514 struct rl_softc *sc;
1515 {
1516
1517 RL_LOCK_ASSERT(sc);
1518
1519 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1520 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1521 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1522
1523 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1524 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1525 sc->rl_ldata.rl_tx_prodidx = 0;
1526 sc->rl_ldata.rl_tx_considx = 0;
1527 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1528
1529 return (0);
1530 }
1531
1532 static int
1533 re_rx_list_init(sc)
1534 struct rl_softc *sc;
1535 {
1536 int i;
1537
1538 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1539 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1540 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1541
1542 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1543 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1544 return (ENOBUFS);
1545 }
1546
1547 /* Flush the RX descriptors */
1548
1549 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1550 sc->rl_ldata.rl_rx_list_map,
1551 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1552
1553 sc->rl_ldata.rl_rx_prodidx = 0;
1554 sc->rl_head = sc->rl_tail = NULL;
1555
1556 return (0);
1557 }
1558
1559 /*
1560 * RX handler for C+ and 8169. For the gigE chips, we support
1561 * the reception of jumbo frames that have been fragmented
1562 * across multiple 2K mbuf cluster buffers.
1563 */
1564 static int
1565 re_rxeof(sc)
1566 struct rl_softc *sc;
1567 {
1568 struct mbuf *m;
1569 struct ifnet *ifp;
1570 int i, total_len;
1571 struct rl_desc *cur_rx;
1572 u_int32_t rxstat, rxvlan;
1573 int maxpkt = 16;
1574
1575 RL_LOCK_ASSERT(sc);
1576
1577 ifp = sc->rl_ifp;
1578 i = sc->rl_ldata.rl_rx_prodidx;
1579
1580 /* Invalidate the descriptor memory */
1581
1582 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1583 sc->rl_ldata.rl_rx_list_map,
1584 BUS_DMASYNC_POSTREAD);
1585
1586 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) {
1587 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1588 m = sc->rl_ldata.rl_rx_mbuf[i];
1589 total_len = RL_RXBYTES(cur_rx);
1590 rxstat = le32toh(cur_rx->rl_cmdstat);
1591 rxvlan = le32toh(cur_rx->rl_vlanctl);
1592
1593 /* Invalidate the RX mbuf and unload its map */
1594
1595 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1596 sc->rl_ldata.rl_rx_dmamap[i],
1597 BUS_DMASYNC_POSTWRITE);
1598 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1599 sc->rl_ldata.rl_rx_dmamap[i]);
1600
1601 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1602 m->m_len = RE_RX_DESC_BUFLEN;
1603 if (sc->rl_head == NULL)
1604 sc->rl_head = sc->rl_tail = m;
1605 else {
1606 m->m_flags &= ~M_PKTHDR;
1607 sc->rl_tail->m_next = m;
1608 sc->rl_tail = m;
1609 }
1610 re_newbuf(sc, i, NULL);
1611 RL_DESC_INC(i);
1612 continue;
1613 }
1614
1615 /*
1616 * NOTE: for the 8139C+, the frame length field
1617 * is always 12 bits in size, but for the gigE chips,
1618 * it is 13 bits (since the max RX frame length is 16K).
1619 * Unfortunately, all 32 bits in the status word
1620 * were already used, so to make room for the extra
1621 * length bit, RealTek took out the 'frame alignment
1622 * error' bit and shifted the other status bits
1623 * over one slot. The OWN, EOR, FS and LS bits are
1624 * still in the same places. We have already extracted
1625 * the frame length and checked the OWN bit, so rather
1626 * than using an alternate bit mapping, we shift the
1627 * status bits one space to the right so we can evaluate
1628 * them using the 8169 status as though it was in the
1629 * same format as that of the 8139C+.
1630 */
1631 if (sc->rl_type == RL_8169)
1632 rxstat >>= 1;
1633
1634 /*
1635 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1636 * set, but if CRC is clear, it will still be a valid frame.
1637 */
1638 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1639 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1640 ifp->if_ierrors++;
1641 /*
1642 * If this is part of a multi-fragment packet,
1643 * discard all the pieces.
1644 */
1645 if (sc->rl_head != NULL) {
1646 m_freem(sc->rl_head);
1647 sc->rl_head = sc->rl_tail = NULL;
1648 }
1649 re_newbuf(sc, i, m);
1650 RL_DESC_INC(i);
1651 continue;
1652 }
1653
1654 /*
1655 * If allocating a replacement mbuf fails,
1656 * reload the current one.
1657 */
1658
1659 if (re_newbuf(sc, i, NULL)) {
1660 ifp->if_ierrors++;
1661 if (sc->rl_head != NULL) {
1662 m_freem(sc->rl_head);
1663 sc->rl_head = sc->rl_tail = NULL;
1664 }
1665 re_newbuf(sc, i, m);
1666 RL_DESC_INC(i);
1667 continue;
1668 }
1669
1670 RL_DESC_INC(i);
1671
1672 if (sc->rl_head != NULL) {
1673 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1674 if (m->m_len == 0)
1675 m->m_len = RE_RX_DESC_BUFLEN;
1676 /*
1677 * Special case: if there's 4 bytes or less
1678 * in this buffer, the mbuf can be discarded:
1679 * the last 4 bytes is the CRC, which we don't
1680 * care about anyway.
1681 */
1682 if (m->m_len <= ETHER_CRC_LEN) {
1683 sc->rl_tail->m_len -=
1684 (ETHER_CRC_LEN - m->m_len);
1685 m_freem(m);
1686 } else {
1687 m->m_len -= ETHER_CRC_LEN;
1688 m->m_flags &= ~M_PKTHDR;
1689 sc->rl_tail->m_next = m;
1690 }
1691 m = sc->rl_head;
1692 sc->rl_head = sc->rl_tail = NULL;
1693 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1694 } else
1695 m->m_pkthdr.len = m->m_len =
1696 (total_len - ETHER_CRC_LEN);
1697
1698 #ifdef RE_FIXUP_RX
1699 re_fixup_rx(m);
1700 #endif
1701 ifp->if_ipackets++;
1702 m->m_pkthdr.rcvif = ifp;
1703
1704 /* Do RX checksumming if enabled */
1705
1706 if (ifp->if_capenable & IFCAP_RXCSUM) {
1707
1708 /* Check IP header checksum */
1709 if (rxstat & RL_RDESC_STAT_PROTOID)
1710 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1711 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1712 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1713
1714 /* Check TCP/UDP checksum */
1715 if ((RL_TCPPKT(rxstat) &&
1716 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1717 (RL_UDPPKT(rxstat) &&
1718 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1719 m->m_pkthdr.csum_flags |=
1720 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1721 m->m_pkthdr.csum_data = 0xffff;
1722 }
1723 }
1724 maxpkt--;
1725 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1726 VLAN_INPUT_TAG_NEW(ifp, m,
1727 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1728 if (m == NULL)
1729 continue;
1730 }
1731 RL_UNLOCK(sc);
1732 (*ifp->if_input)(ifp, m);
1733 RL_LOCK(sc);
1734 }
1735
1736 /* Flush the RX DMA ring */
1737
1738 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1739 sc->rl_ldata.rl_rx_list_map,
1740 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1741
1742 sc->rl_ldata.rl_rx_prodidx = i;
1743
1744 if (maxpkt)
1745 return(EAGAIN);
1746
1747 return(0);
1748 }
1749
1750 static void
1751 re_txeof(sc)
1752 struct rl_softc *sc;
1753 {
1754 struct ifnet *ifp;
1755 u_int32_t txstat;
1756 int idx;
1757
1758 ifp = sc->rl_ifp;
1759 idx = sc->rl_ldata.rl_tx_considx;
1760
1761 /* Invalidate the TX descriptor list */
1762
1763 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1764 sc->rl_ldata.rl_tx_list_map,
1765 BUS_DMASYNC_POSTREAD);
1766
1767 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1768
1769 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1770 if (txstat & RL_TDESC_CMD_OWN)
1771 break;
1772
1773 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0;
1774
1775 /*
1776 * We only stash mbufs in the last descriptor
1777 * in a fragment chain, which also happens to
1778 * be the only place where the TX status bits
1779 * are valid.
1780 */
1781
1782 if (txstat & RL_TDESC_CMD_EOF) {
1783 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1784 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1785 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1786 sc->rl_ldata.rl_tx_dmamap[idx]);
1787 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1788 RL_TDESC_STAT_COLCNT))
1789 ifp->if_collisions++;
1790 if (txstat & RL_TDESC_STAT_TXERRSUM)
1791 ifp->if_oerrors++;
1792 else
1793 ifp->if_opackets++;
1794 }
1795 sc->rl_ldata.rl_tx_free++;
1796 RL_DESC_INC(idx);
1797 }
1798
1799 /* No changes made to the TX ring, so no flush needed */
1800
1801 if (sc->rl_ldata.rl_tx_free) {
1802 sc->rl_ldata.rl_tx_considx = idx;
1803 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1804 ifp->if_timer = 0;
1805 }
1806
1807 /*
1808 * Some chips will ignore a second TX request issued while an
1809 * existing transmission is in progress. If the transmitter goes
1810 * idle but there are still packets waiting to be sent, we need
1811 * to restart the channel here to flush them out. This only seems
1812 * to be required with the PCIe devices.
1813 */
1814
1815 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT)
1816 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
1817
1818 #ifdef RE_TX_MODERATION
1819 /*
1820 * If not all descriptors have been released reaped yet,
1821 * reload the timer so that we will eventually get another
1822 * interrupt that will cause us to re-enter this routine.
1823 * This is done in case the transmitter has gone idle.
1824 */
1825 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1826 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1827 #endif
1828
1829 }
1830
1831 static void
1832 re_tick(xsc)
1833 void *xsc;
1834 {
1835 struct rl_softc *sc;
1836 struct mii_data *mii;
1837 struct ifnet *ifp;
1838
1839 sc = xsc;
1840 ifp = sc->rl_ifp;
1841
1842 RL_LOCK_ASSERT(sc);
1843
1844 mii = device_get_softc(sc->rl_miibus);
1845
1846 mii_tick(mii);
1847 if (sc->rl_link) {
1848 if (!(mii->mii_media_status & IFM_ACTIVE))
1849 sc->rl_link = 0;
1850 } else {
1851 if (mii->mii_media_status & IFM_ACTIVE &&
1852 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1853 sc->rl_link = 1;
1854 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1855 taskqueue_enqueue_fast(taskqueue_fast,
1856 &sc->rl_txtask);
1857 }
1858 }
1859
1860 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1861 }
1862
1863 #ifdef DEVICE_POLLING
1864 static void
1865 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1866 {
1867 struct rl_softc *sc = ifp->if_softc;
1868
1869 RL_LOCK(sc);
1870 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1871 re_poll_locked(ifp, cmd, count);
1872 RL_UNLOCK(sc);
1873 }
1874
1875 static void
1876 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1877 {
1878 struct rl_softc *sc = ifp->if_softc;
1879
1880 RL_LOCK_ASSERT(sc);
1881
1882 sc->rxcycles = count;
1883 re_rxeof(sc);
1884 re_txeof(sc);
1885
1886 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1887 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1888
1889 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1890 u_int16_t status;
1891
1892 status = CSR_READ_2(sc, RL_ISR);
1893 if (status == 0xffff)
1894 return;
1895 if (status)
1896 CSR_WRITE_2(sc, RL_ISR, status);
1897
1898 /*
1899 * XXX check behaviour on receiver stalls.
1900 */
1901
1902 if (status & RL_ISR_SYSTEM_ERR) {
1903 re_reset(sc);
1904 re_init_locked(sc);
1905 }
1906 }
1907 }
1908 #endif /* DEVICE_POLLING */
1909
1910 static void
1911 re_intr(arg)
1912 void *arg;
1913 {
1914 struct rl_softc *sc;
1915 struct ifnet *ifp;
1916 uint16_t status;
1917
1918 sc = arg;
1919 ifp = sc->rl_ifp;
1920
1921 status = CSR_READ_2(sc, RL_ISR);
1922 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
1923 return;
1924 CSR_WRITE_2(sc, RL_IMR, 0);
1925
1926 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1927
1928 return;
1929 }
1930
1931 static void
1932 re_int_task(arg, npending)
1933 void *arg;
1934 int npending;
1935 {
1936 struct rl_softc *sc;
1937 struct ifnet *ifp;
1938 u_int16_t status;
1939 int rval = 0;
1940
1941 sc = arg;
1942 ifp = sc->rl_ifp;
1943
1944 RL_LOCK(sc);
1945
1946 status = CSR_READ_2(sc, RL_ISR);
1947 CSR_WRITE_2(sc, RL_ISR, status);
1948
1949 if (sc->suspended || !(ifp->if_flags & IFF_UP)) {
1950 RL_UNLOCK(sc);
1951 return;
1952 }
1953
1954 #ifdef DEVICE_POLLING
1955 if (ifp->if_capenable & IFCAP_POLLING) {
1956 RL_UNLOCK(sc);
1957 return;
1958 }
1959 #endif
1960
1961 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
1962 rval = re_rxeof(sc);
1963
1964 #ifdef RE_TX_MODERATION
1965 if (status & (RL_ISR_TIMEOUT_EXPIRED|
1966 #else
1967 if (status & (RL_ISR_TX_OK|
1968 #endif
1969 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
1970 re_txeof(sc);
1971
1972 if (status & RL_ISR_SYSTEM_ERR) {
1973 re_reset(sc);
1974 re_init_locked(sc);
1975 }
1976
1977 if (status & RL_ISR_LINKCHG) {
1978 callout_stop(&sc->rl_stat_callout);
1979 re_tick(sc);
1980 }
1981
1982 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1983 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1984
1985 RL_UNLOCK(sc);
1986
1987 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
1988 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1989 return;
1990 }
1991
1992 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1993
1994 return;
1995 }
1996
1997 static int
1998 re_encap(sc, m_head, idx)
1999 struct rl_softc *sc;
2000 struct mbuf **m_head;
2001 int *idx;
2002 {
2003 struct mbuf *m_new = NULL;
2004 struct rl_dmaload_arg arg;
2005 bus_dmamap_t map;
2006 int error;
2007 struct m_tag *mtag;
2008
2009 RL_LOCK_ASSERT(sc);
2010
2011 if (sc->rl_ldata.rl_tx_free <= 4)
2012 return (EFBIG);
2013
2014 /*
2015 * Set up checksum offload. Note: checksum offload bits must
2016 * appear in all descriptors of a multi-descriptor transmit
2017 * attempt. This is according to testing done with an 8169
2018 * chip. This is a requirement.
2019 */
2020
2021 arg.rl_flags = 0;
2022
2023 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2024 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
2025 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2026 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
2027 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2028 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
2029
2030 arg.sc = sc;
2031 arg.rl_idx = *idx;
2032 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2033 if (arg.rl_maxsegs > 4)
2034 arg.rl_maxsegs -= 4;
2035 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2036
2037 map = sc->rl_ldata.rl_tx_dmamap[*idx];
2038
2039 /*
2040 * With some of the RealTek chips, using the checksum offload
2041 * support in conjunction with the autopadding feature results
2042 * in the transmission of corrupt frames. For example, if we
2043 * need to send a really small IP fragment that's less than 60
2044 * bytes in size, and IP header checksumming is enabled, the
2045 * resulting ethernet frame that appears on the wire will
2046 * have garbled payload. To work around this, if TX checksum
2047 * offload is enabled, we always manually pad short frames out
2048 * to the minimum ethernet frame size. We do this by pretending
2049 * the mbuf chain has too many fragments so the coalescing code
2050 * below can assemble the packet into a single buffer that's
2051 * padded out to the mininum frame size.
2052 */
2053
2054 if (arg.rl_flags && (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN)
2055 error = EFBIG;
2056 else
2057 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2058 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2059
2060 if (error && error != EFBIG) {
2061 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error);
2062 return (ENOBUFS);
2063 }
2064
2065 /* Too many segments to map, coalesce into a single mbuf */
2066
2067 if (error || arg.rl_maxsegs == 0) {
2068 m_new = m_defrag(*m_head, M_DONTWAIT);
2069 if (m_new == NULL)
2070 return (ENOBUFS);
2071 else
2072 *m_head = m_new;
2073
2074 /*
2075 * Manually pad short frames, and zero the pad space
2076 * to avoid leaking data.
2077 */
2078
2079 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) {
2080 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
2081 RL_MIN_FRAMELEN - m_new->m_pkthdr.len);
2082 m_new->m_pkthdr.len += RL_MIN_FRAMELEN -
2083 m_new->m_pkthdr.len;
2084 m_new->m_len = m_new->m_pkthdr.len;
2085 }
2086
2087 arg.sc = sc;
2088 arg.rl_idx = *idx;
2089 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2090 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2091
2092 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2093 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2094 if (error) {
2095 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n",
2096 error);
2097 return (EFBIG);
2098 }
2099 }
2100
2101 /*
2102 * Insure that the map for this transmission
2103 * is placed at the array index of the last descriptor
2104 * in this chain. (Swap last and first dmamaps.)
2105 */
2106 sc->rl_ldata.rl_tx_dmamap[*idx] =
2107 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
2108 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
2109
2110 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
2111 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
2112
2113 /*
2114 * Set up hardware VLAN tagging. Note: vlan tag info must
2115 * appear in the first descriptor of a multi-descriptor
2116 * transmission attempt.
2117 */
2118
2119 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
2120 if (mtag != NULL)
2121 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
2122 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
2123
2124 /* Transfer ownership of packet to the chip. */
2125
2126 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
2127 htole32(RL_TDESC_CMD_OWN);
2128 if (*idx != arg.rl_idx)
2129 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
2130 htole32(RL_TDESC_CMD_OWN);
2131
2132 RL_DESC_INC(arg.rl_idx);
2133 *idx = arg.rl_idx;
2134
2135 return (0);
2136 }
2137
2138 static void
2139 re_tx_task(arg, npending)
2140 void *arg;
2141 int npending;
2142 {
2143 struct ifnet *ifp;
2144
2145 ifp = arg;
2146 re_start(ifp);
2147
2148 return;
2149 }
2150
2151 /*
2152 * Main transmit routine for C+ and gigE NICs.
2153 */
2154 static void
2155 re_start(ifp)
2156 struct ifnet *ifp;
2157 {
2158 struct rl_softc *sc;
2159 struct mbuf *m_head = NULL;
2160 int idx, queued = 0;
2161
2162 sc = ifp->if_softc;
2163
2164 RL_LOCK(sc);
2165
2166 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) {
2167 RL_UNLOCK(sc);
2168 return;
2169 }
2170
2171 idx = sc->rl_ldata.rl_tx_prodidx;
2172
2173 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2174 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2175 if (m_head == NULL)
2176 break;
2177
2178 if (re_encap(sc, &m_head, &idx)) {
2179 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2180 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2181 break;
2182 }
2183
2184 /*
2185 * If there's a BPF listener, bounce a copy of this frame
2186 * to him.
2187 */
2188 BPF_MTAP(ifp, m_head);
2189
2190 queued++;
2191 }
2192
2193 if (queued == 0) {
2194 #ifdef RE_TX_MODERATION
2195 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
2196 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2197 #endif
2198 RL_UNLOCK(sc);
2199 return;
2200 }
2201
2202 /* Flush the TX descriptors */
2203
2204 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2205 sc->rl_ldata.rl_tx_list_map,
2206 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2207
2208 sc->rl_ldata.rl_tx_prodidx = idx;
2209
2210 /*
2211 * RealTek put the TX poll request register in a different
2212 * location on the 8169 gigE chip. I don't know why.
2213 */
2214
2215 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2216
2217 #ifdef RE_TX_MODERATION
2218 /*
2219 * Use the countdown timer for interrupt moderation.
2220 * 'TX done' interrupts are disabled. Instead, we reset the
2221 * countdown timer, which will begin counting until it hits
2222 * the value in the TIMERINT register, and then trigger an
2223 * interrupt. Each time we write to the TIMERCNT register,
2224 * the timer count is reset to 0.
2225 */
2226 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2227 #endif
2228
2229 /*
2230 * Set a timeout in case the chip goes out to lunch.
2231 */
2232
2233 ifp->if_timer = 5;
2234
2235 RL_UNLOCK(sc);
2236
2237 return;
2238 }
2239
2240 static void
2241 re_init(xsc)
2242 void *xsc;
2243 {
2244 struct rl_softc *sc = xsc;
2245
2246 RL_LOCK(sc);
2247 re_init_locked(sc);
2248 RL_UNLOCK(sc);
2249 }
2250
2251 static void
2252 re_init_locked(sc)
2253 struct rl_softc *sc;
2254 {
2255 struct ifnet *ifp = sc->rl_ifp;
2256 struct mii_data *mii;
2257 u_int32_t rxcfg = 0;
2258 union {
2259 uint32_t align_dummy;
2260 u_char eaddr[ETHER_ADDR_LEN];
2261 } eaddr;
2262
2263 RL_LOCK_ASSERT(sc);
2264
2265 mii = device_get_softc(sc->rl_miibus);
2266
2267 /*
2268 * Cancel pending I/O and free all RX/TX buffers.
2269 */
2270 re_stop(sc);
2271
2272 /*
2273 * Enable C+ RX and TX mode, as well as VLAN stripping and
2274 * RX checksum offload. We must configure the C+ register
2275 * before all others.
2276 */
2277 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2278 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2279 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
2280
2281 /*
2282 * Init our MAC address. Even though the chipset
2283 * documentation doesn't mention it, we need to enter "Config
2284 * register write enable" mode to modify the ID registers.
2285 */
2286 /* Copy MAC address on stack to align. */
2287 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2288 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2289 CSR_WRITE_4(sc, RL_IDR0,
2290 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2291 CSR_WRITE_4(sc, RL_IDR4,
2292 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2293 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2294
2295 /*
2296 * For C+ mode, initialize the RX descriptors and mbufs.
2297 */
2298 re_rx_list_init(sc);
2299 re_tx_list_init(sc);
2300
2301 /*
2302 * Enable transmit and receive.
2303 */
2304 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2305
2306 /*
2307 * Set the initial TX and RX configuration.
2308 */
2309 if (sc->rl_testmode) {
2310 if (sc->rl_type == RL_8169)
2311 CSR_WRITE_4(sc, RL_TXCFG,
2312 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2313 else
2314 CSR_WRITE_4(sc, RL_TXCFG,
2315 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2316 } else
2317 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2318 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2319
2320 /* Set the individual bit to receive frames for this host only. */
2321 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2322 rxcfg |= RL_RXCFG_RX_INDIV;
2323
2324 /* If we want promiscuous mode, set the allframes bit. */
2325 if (ifp->if_flags & IFF_PROMISC)
2326 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2327 else
2328 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2329 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2330
2331 /*
2332 * Set capture broadcast bit to capture broadcast frames.
2333 */
2334 if (ifp->if_flags & IFF_BROADCAST)
2335 rxcfg |= RL_RXCFG_RX_BROAD;
2336 else
2337 rxcfg &= ~RL_RXCFG_RX_BROAD;
2338 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2339
2340 /*
2341 * Program the multicast filter, if necessary.
2342 */
2343 re_setmulti(sc);
2344
2345 #ifdef DEVICE_POLLING
2346 /*
2347 * Disable interrupts if we are polling.
2348 */
2349 if (ifp->if_capenable & IFCAP_POLLING)
2350 CSR_WRITE_2(sc, RL_IMR, 0);
2351 else /* otherwise ... */
2352 #endif
2353
2354 /*
2355 * Enable interrupts.
2356 */
2357 if (sc->rl_testmode)
2358 CSR_WRITE_2(sc, RL_IMR, 0);
2359 else
2360 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2361 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2362
2363 /* Set initial TX threshold */
2364 sc->rl_txthresh = RL_TX_THRESH_INIT;
2365
2366 /* Start RX/TX process. */
2367 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2368 #ifdef notdef
2369 /* Enable receiver and transmitter. */
2370 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2371 #endif
2372 /*
2373 * Load the addresses of the RX and TX lists into the chip.
2374 */
2375
2376 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2377 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2378 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2379 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2380
2381 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2382 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2383 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2384 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2385
2386 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2387
2388 #ifdef RE_TX_MODERATION
2389 /*
2390 * Initialize the timer interrupt register so that
2391 * a timer interrupt will be generated once the timer
2392 * reaches a certain number of ticks. The timer is
2393 * reloaded on each transmit. This gives us TX interrupt
2394 * moderation, which dramatically improves TX frame rate.
2395 */
2396 if (sc->rl_type == RL_8169)
2397 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2398 else
2399 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2400 #endif
2401
2402 /*
2403 * For 8169 gigE NICs, set the max allowed RX packet
2404 * size so we can receive jumbo frames.
2405 */
2406 if (sc->rl_type == RL_8169)
2407 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2408
2409 if (sc->rl_testmode)
2410 return;
2411
2412 mii_mediachg(mii);
2413
2414 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2415
2416 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2417 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2418
2419
2420 sc->rl_link = 0;
2421
2422 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2423 }
2424
2425 /*
2426 * Set media options.
2427 */
2428 static int
2429 re_ifmedia_upd(ifp)
2430 struct ifnet *ifp;
2431 {
2432 struct rl_softc *sc;
2433 struct mii_data *mii;
2434
2435 sc = ifp->if_softc;
2436 mii = device_get_softc(sc->rl_miibus);
2437 RL_LOCK(sc);
2438 mii_mediachg(mii);
2439 RL_UNLOCK(sc);
2440
2441 return (0);
2442 }
2443
2444 /*
2445 * Report current media status.
2446 */
2447 static void
2448 re_ifmedia_sts(ifp, ifmr)
2449 struct ifnet *ifp;
2450 struct ifmediareq *ifmr;
2451 {
2452 struct rl_softc *sc;
2453 struct mii_data *mii;
2454
2455 sc = ifp->if_softc;
2456 mii = device_get_softc(sc->rl_miibus);
2457
2458 RL_LOCK(sc);
2459 mii_pollstat(mii);
2460 RL_UNLOCK(sc);
2461 ifmr->ifm_active = mii->mii_media_active;
2462 ifmr->ifm_status = mii->mii_media_status;
2463 }
2464
2465 static int
2466 re_ioctl(ifp, command, data)
2467 struct ifnet *ifp;
2468 u_long command;
2469 caddr_t data;
2470 {
2471 struct rl_softc *sc = ifp->if_softc;
2472 struct ifreq *ifr = (struct ifreq *) data;
2473 struct mii_data *mii;
2474 int error = 0;
2475
2476 switch (command) {
2477 case SIOCSIFMTU:
2478 RL_LOCK(sc);
2479 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2480 error = EINVAL;
2481 ifp->if_mtu = ifr->ifr_mtu;
2482 RL_UNLOCK(sc);
2483 break;
2484 case SIOCSIFFLAGS:
2485 RL_LOCK(sc);
2486 if (ifp->if_flags & IFF_UP)
2487 re_init_locked(sc);
2488 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2489 re_stop(sc);
2490 RL_UNLOCK(sc);
2491 break;
2492 case SIOCADDMULTI:
2493 case SIOCDELMULTI:
2494 RL_LOCK(sc);
2495 re_setmulti(sc);
2496 RL_UNLOCK(sc);
2497 break;
2498 case SIOCGIFMEDIA:
2499 case SIOCSIFMEDIA:
2500 mii = device_get_softc(sc->rl_miibus);
2501 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2502 break;
2503 case SIOCSIFCAP:
2504 {
2505 int mask, reinit;
2506
2507 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2508 reinit = 0;
2509 #ifdef DEVICE_POLLING
2510 if (mask & IFCAP_POLLING) {
2511 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2512 error = ether_poll_register(re_poll, ifp);
2513 if (error)
2514 return(error);
2515 RL_LOCK(sc);
2516 /* Disable interrupts */
2517 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2518 ifp->if_capenable |= IFCAP_POLLING;
2519 RL_UNLOCK(sc);
2520
2521 } else {
2522 error = ether_poll_deregister(ifp);
2523 /* Enable interrupts. */
2524 RL_LOCK(sc);
2525 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2526 ifp->if_capenable &= ~IFCAP_POLLING;
2527 RL_UNLOCK(sc);
2528 }
2529 }
2530 #endif /* DEVICE_POLLING */
2531 if (mask & IFCAP_HWCSUM) {
2532 ifp->if_capenable ^= IFCAP_HWCSUM;
2533 if (ifp->if_capenable & IFCAP_TXCSUM)
2534 ifp->if_hwassist = RE_CSUM_FEATURES;
2535 else
2536 ifp->if_hwassist = 0;
2537 reinit = 1;
2538 }
2539 if (mask & IFCAP_VLAN_HWTAGGING) {
2540 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2541 reinit = 1;
2542 }
2543 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
2544 re_init(sc);
2545 }
2546 break;
2547 default:
2548 error = ether_ioctl(ifp, command, data);
2549 break;
2550 }
2551
2552 return (error);
2553 }
2554
2555 static void
2556 re_watchdog(ifp)
2557 struct ifnet *ifp;
2558 {
2559 struct rl_softc *sc;
2560
2561 sc = ifp->if_softc;
2562 RL_LOCK(sc);
2563 if_printf(ifp, "watchdog timeout\n");
2564 ifp->if_oerrors++;
2565
2566 re_txeof(sc);
2567 re_rxeof(sc);
2568 re_init_locked(sc);
2569
2570 RL_UNLOCK(sc);
2571 }
2572
2573 /*
2574 * Stop the adapter and free any mbufs allocated to the
2575 * RX and TX lists.
2576 */
2577 static void
2578 re_stop(sc)
2579 struct rl_softc *sc;
2580 {
2581 register int i;
2582 struct ifnet *ifp;
2583
2584 RL_LOCK_ASSERT(sc);
2585
2586 ifp = sc->rl_ifp;
2587 ifp->if_timer = 0;
2588
2589 callout_stop(&sc->rl_stat_callout);
2590 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2591
2592 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2593 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2594 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
2595
2596 if (sc->rl_head != NULL) {
2597 m_freem(sc->rl_head);
2598 sc->rl_head = sc->rl_tail = NULL;
2599 }
2600
2601 /* Free the TX list buffers. */
2602
2603 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2604 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2605 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2606 sc->rl_ldata.rl_tx_dmamap[i]);
2607 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2608 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2609 }
2610 }
2611
2612 /* Free the RX list buffers. */
2613
2614 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2615 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2616 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2617 sc->rl_ldata.rl_rx_dmamap[i]);
2618 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2619 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2620 }
2621 }
2622 }
2623
2624 /*
2625 * Device suspend routine. Stop the interface and save some PCI
2626 * settings in case the BIOS doesn't restore them properly on
2627 * resume.
2628 */
2629 static int
2630 re_suspend(dev)
2631 device_t dev;
2632 {
2633 struct rl_softc *sc;
2634
2635 sc = device_get_softc(dev);
2636
2637 RL_LOCK(sc);
2638 re_stop(sc);
2639 sc->suspended = 1;
2640 RL_UNLOCK(sc);
2641
2642 return (0);
2643 }
2644
2645 /*
2646 * Device resume routine. Restore some PCI settings in case the BIOS
2647 * doesn't, re-enable busmastering, and restart the interface if
2648 * appropriate.
2649 */
2650 static int
2651 re_resume(dev)
2652 device_t dev;
2653 {
2654 struct rl_softc *sc;
2655 struct ifnet *ifp;
2656
2657 sc = device_get_softc(dev);
2658
2659 RL_LOCK(sc);
2660
2661 ifp = sc->rl_ifp;
2662
2663 /* reinitialize interface if necessary */
2664 if (ifp->if_flags & IFF_UP)
2665 re_init_locked(sc);
2666
2667 sc->suspended = 0;
2668 RL_UNLOCK(sc);
2669
2670 return (0);
2671 }
2672
2673 /*
2674 * Stop all chip I/O so that the kernel's probe routines don't
2675 * get confused by errant DMAs when rebooting.
2676 */
2677 static void
2678 re_shutdown(dev)
2679 device_t dev;
2680 {
2681 struct rl_softc *sc;
2682
2683 sc = device_get_softc(dev);
2684
2685 RL_LOCK(sc);
2686 re_stop(sc);
2687 /*
2688 * Mark interface as down since otherwise we will panic if
2689 * interrupt comes in later on, which can happen in some
2690 * cases.
2691 */
2692 sc->rl_ifp->if_flags &= ~IFF_UP;
2693 RL_UNLOCK(sc);
2694 }
Cache object: 4d2fdfb93ed2fffccde4c97d7ed100f5
|