FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: src/sys/dev/re/if_re.c,v 1.46.2.35.2.1 2007/12/06 06:02:43 yongari Exp $");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/taskqueue.h>
127
128 #include <net/if.h>
129 #include <net/if_arp.h>
130 #include <net/ethernet.h>
131 #include <net/if_dl.h>
132 #include <net/if_media.h>
133 #include <net/if_types.h>
134 #include <net/if_vlan_var.h>
135
136 #include <net/bpf.h>
137
138 #include <machine/bus.h>
139 #include <machine/resource.h>
140 #include <sys/bus.h>
141 #include <sys/rman.h>
142
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
145
146 #include <dev/pci/pcireg.h>
147 #include <dev/pci/pcivar.h>
148
149 MODULE_DEPEND(re, pci, 1, 1, 1);
150 MODULE_DEPEND(re, ether, 1, 1, 1);
151 MODULE_DEPEND(re, miibus, 1, 1, 1);
152
153 /* "device miibus" required. See GENERIC if you get errors here. */
154 #include "miibus_if.h"
155
156 /*
157 * Default to using PIO access for this driver.
158 */
159 #define RE_USEIOSPACE
160
161 #include <pci/if_rlreg.h>
162
163 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
164
165 /*
166 * Various supported device vendors/types and their names.
167 */
168 static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB,
172 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" },
173 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
174 "RealTek 8139C+ 10/100BaseTX" },
175 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
176 "RealTek 8101E PCIe 10/100baseTX" },
177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1,
178 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2,
180 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
182 "RealTek 8169 Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
184 "RealTek 8169S Single-chip Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
186 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC,
190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
192 "RealTek 8110S Single-chip Gigabit Ethernet" },
193 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
194 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
195 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
196 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
197 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S,
198 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" },
199 { 0, 0, 0, NULL }
200 };
201
202 static struct rl_hwrev re_hwrevs[] = {
203 { RL_HWREV_8139, RL_8139, "" },
204 { RL_HWREV_8139A, RL_8139, "A" },
205 { RL_HWREV_8139AG, RL_8139, "A-G" },
206 { RL_HWREV_8139B, RL_8139, "B" },
207 { RL_HWREV_8130, RL_8139, "8130" },
208 { RL_HWREV_8139C, RL_8139, "C" },
209 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
210 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
211 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
212 { RL_HWREV_8169, RL_8169, "8169"},
213 { RL_HWREV_8169S, RL_8169, "8169S"},
214 { RL_HWREV_8110S, RL_8169, "8110S"},
215 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
216 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
217 { RL_HWREV_8100, RL_8139, "8100"},
218 { RL_HWREV_8101, RL_8139, "8101"},
219 { RL_HWREV_8100E, RL_8169, "8100E"},
220 { RL_HWREV_8101E, RL_8169, "8101E"},
221 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
222 { 0, 0, NULL }
223 };
224
225 static int re_probe (device_t);
226 static int re_attach (device_t);
227 static int re_detach (device_t);
228
229 static int re_encap (struct rl_softc *, struct mbuf **, int *);
230
231 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
232 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
233 bus_size_t, int);
234 static int re_allocmem (device_t, struct rl_softc *);
235 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
236 static int re_rx_list_init (struct rl_softc *);
237 static int re_tx_list_init (struct rl_softc *);
238 #ifdef RE_FIXUP_RX
239 static __inline void re_fixup_rx
240 (struct mbuf *);
241 #endif
242 static int re_rxeof (struct rl_softc *);
243 static void re_txeof (struct rl_softc *);
244 #ifdef DEVICE_POLLING
245 static void re_poll (struct ifnet *, enum poll_cmd, int);
246 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
247 #endif
248 static void re_intr (void *);
249 static void re_tick (void *);
250 static void re_tx_task (void *, int);
251 static void re_int_task (void *, int);
252 static void re_start (struct ifnet *);
253 static int re_ioctl (struct ifnet *, u_long, caddr_t);
254 static void re_init (void *);
255 static void re_init_locked (struct rl_softc *);
256 static void re_stop (struct rl_softc *);
257 static void re_watchdog (struct rl_softc *);
258 static int re_suspend (device_t);
259 static int re_resume (device_t);
260 static void re_shutdown (device_t);
261 static int re_ifmedia_upd (struct ifnet *);
262 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
263
264 static void re_eeprom_putbyte (struct rl_softc *, int);
265 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
266 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
267 static int re_gmii_readreg (device_t, int, int);
268 static int re_gmii_writereg (device_t, int, int, int);
269
270 static int re_miibus_readreg (device_t, int, int);
271 static int re_miibus_writereg (device_t, int, int, int);
272 static void re_miibus_statchg (device_t);
273
274 static void re_setmulti (struct rl_softc *);
275 static void re_reset (struct rl_softc *);
276
277 #ifdef RE_DIAG
278 static int re_diag (struct rl_softc *);
279 #endif
280
281 #ifdef RE_USEIOSPACE
282 #define RL_RES SYS_RES_IOPORT
283 #define RL_RID RL_PCI_LOIO
284 #else
285 #define RL_RES SYS_RES_MEMORY
286 #define RL_RID RL_PCI_LOMEM
287 #endif
288
289 static device_method_t re_methods[] = {
290 /* Device interface */
291 DEVMETHOD(device_probe, re_probe),
292 DEVMETHOD(device_attach, re_attach),
293 DEVMETHOD(device_detach, re_detach),
294 DEVMETHOD(device_suspend, re_suspend),
295 DEVMETHOD(device_resume, re_resume),
296 DEVMETHOD(device_shutdown, re_shutdown),
297
298 /* bus interface */
299 DEVMETHOD(bus_print_child, bus_generic_print_child),
300 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
301
302 /* MII interface */
303 DEVMETHOD(miibus_readreg, re_miibus_readreg),
304 DEVMETHOD(miibus_writereg, re_miibus_writereg),
305 DEVMETHOD(miibus_statchg, re_miibus_statchg),
306
307 { 0, 0 }
308 };
309
310 static driver_t re_driver = {
311 "re",
312 re_methods,
313 sizeof(struct rl_softc)
314 };
315
316 static devclass_t re_devclass;
317
318 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
319 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
320 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
321
322 #define EE_SET(x) \
323 CSR_WRITE_1(sc, RL_EECMD, \
324 CSR_READ_1(sc, RL_EECMD) | x)
325
326 #define EE_CLR(x) \
327 CSR_WRITE_1(sc, RL_EECMD, \
328 CSR_READ_1(sc, RL_EECMD) & ~x)
329
330 /*
331 * Send a read command and address to the EEPROM, check for ACK.
332 */
333 static void
334 re_eeprom_putbyte(sc, addr)
335 struct rl_softc *sc;
336 int addr;
337 {
338 register int d, i;
339
340 d = addr | (RL_9346_READ << sc->rl_eewidth);
341
342 /*
343 * Feed in each bit and strobe the clock.
344 */
345
346 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
347 if (d & i) {
348 EE_SET(RL_EE_DATAIN);
349 } else {
350 EE_CLR(RL_EE_DATAIN);
351 }
352 DELAY(100);
353 EE_SET(RL_EE_CLK);
354 DELAY(150);
355 EE_CLR(RL_EE_CLK);
356 DELAY(100);
357 }
358
359 return;
360 }
361
362 /*
363 * Read a word of data stored in the EEPROM at address 'addr.'
364 */
365 static void
366 re_eeprom_getword(sc, addr, dest)
367 struct rl_softc *sc;
368 int addr;
369 u_int16_t *dest;
370 {
371 register int i;
372 u_int16_t word = 0;
373
374 /*
375 * Send address of word we want to read.
376 */
377 re_eeprom_putbyte(sc, addr);
378
379 /*
380 * Start reading bits from EEPROM.
381 */
382 for (i = 0x8000; i; i >>= 1) {
383 EE_SET(RL_EE_CLK);
384 DELAY(100);
385 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
386 word |= i;
387 EE_CLR(RL_EE_CLK);
388 DELAY(100);
389 }
390
391 *dest = word;
392
393 return;
394 }
395
396 /*
397 * Read a sequence of words from the EEPROM.
398 */
399 static void
400 re_read_eeprom(sc, dest, off, cnt)
401 struct rl_softc *sc;
402 caddr_t dest;
403 int off;
404 int cnt;
405 {
406 int i;
407 u_int16_t word = 0, *ptr;
408
409 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
410
411 DELAY(100);
412
413 for (i = 0; i < cnt; i++) {
414 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
415 re_eeprom_getword(sc, off + i, &word);
416 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
417 ptr = (u_int16_t *)(dest + (i * 2));
418 *ptr = word;
419 }
420
421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
422
423 return;
424 }
425
426 static int
427 re_gmii_readreg(dev, phy, reg)
428 device_t dev;
429 int phy, reg;
430 {
431 struct rl_softc *sc;
432 u_int32_t rval;
433 int i;
434
435 if (phy != 1)
436 return (0);
437
438 sc = device_get_softc(dev);
439
440 /* Let the rgephy driver read the GMEDIASTAT register */
441
442 if (reg == RL_GMEDIASTAT) {
443 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
444 return (rval);
445 }
446
447 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
448 DELAY(1000);
449
450 for (i = 0; i < RL_TIMEOUT; i++) {
451 rval = CSR_READ_4(sc, RL_PHYAR);
452 if (rval & RL_PHYAR_BUSY)
453 break;
454 DELAY(100);
455 }
456
457 if (i == RL_TIMEOUT) {
458 device_printf(sc->rl_dev, "PHY read failed\n");
459 return (0);
460 }
461
462 return (rval & RL_PHYAR_PHYDATA);
463 }
464
465 static int
466 re_gmii_writereg(dev, phy, reg, data)
467 device_t dev;
468 int phy, reg, data;
469 {
470 struct rl_softc *sc;
471 u_int32_t rval;
472 int i;
473
474 sc = device_get_softc(dev);
475
476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
478 DELAY(1000);
479
480 for (i = 0; i < RL_TIMEOUT; i++) {
481 rval = CSR_READ_4(sc, RL_PHYAR);
482 if (!(rval & RL_PHYAR_BUSY))
483 break;
484 DELAY(100);
485 }
486
487 if (i == RL_TIMEOUT) {
488 device_printf(sc->rl_dev, "PHY write failed\n");
489 return (0);
490 }
491
492 return (0);
493 }
494
495 static int
496 re_miibus_readreg(dev, phy, reg)
497 device_t dev;
498 int phy, reg;
499 {
500 struct rl_softc *sc;
501 u_int16_t rval = 0;
502 u_int16_t re8139_reg = 0;
503
504 sc = device_get_softc(dev);
505
506 if (sc->rl_type == RL_8169) {
507 rval = re_gmii_readreg(dev, phy, reg);
508 return (rval);
509 }
510
511 /* Pretend the internal PHY is only at address 0 */
512 if (phy) {
513 return (0);
514 }
515 switch (reg) {
516 case MII_BMCR:
517 re8139_reg = RL_BMCR;
518 break;
519 case MII_BMSR:
520 re8139_reg = RL_BMSR;
521 break;
522 case MII_ANAR:
523 re8139_reg = RL_ANAR;
524 break;
525 case MII_ANER:
526 re8139_reg = RL_ANER;
527 break;
528 case MII_ANLPAR:
529 re8139_reg = RL_LPAR;
530 break;
531 case MII_PHYIDR1:
532 case MII_PHYIDR2:
533 return (0);
534 /*
535 * Allow the rlphy driver to read the media status
536 * register. If we have a link partner which does not
537 * support NWAY, this is the register which will tell
538 * us the results of parallel detection.
539 */
540 case RL_MEDIASTAT:
541 rval = CSR_READ_1(sc, RL_MEDIASTAT);
542 return (rval);
543 default:
544 device_printf(sc->rl_dev, "bad phy register\n");
545 return (0);
546 }
547 rval = CSR_READ_2(sc, re8139_reg);
548 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
549 /* 8139C+ has different bit layout. */
550 rval &= ~(BMCR_LOOP | BMCR_ISO);
551 }
552 return (rval);
553 }
554
555 static int
556 re_miibus_writereg(dev, phy, reg, data)
557 device_t dev;
558 int phy, reg, data;
559 {
560 struct rl_softc *sc;
561 u_int16_t re8139_reg = 0;
562 int rval = 0;
563
564 sc = device_get_softc(dev);
565
566 if (sc->rl_type == RL_8169) {
567 rval = re_gmii_writereg(dev, phy, reg, data);
568 return (rval);
569 }
570
571 /* Pretend the internal PHY is only at address 0 */
572 if (phy)
573 return (0);
574
575 switch (reg) {
576 case MII_BMCR:
577 re8139_reg = RL_BMCR;
578 if (sc->rl_type == RL_8139CPLUS) {
579 /* 8139C+ has different bit layout. */
580 data &= ~(BMCR_LOOP | BMCR_ISO);
581 }
582 break;
583 case MII_BMSR:
584 re8139_reg = RL_BMSR;
585 break;
586 case MII_ANAR:
587 re8139_reg = RL_ANAR;
588 break;
589 case MII_ANER:
590 re8139_reg = RL_ANER;
591 break;
592 case MII_ANLPAR:
593 re8139_reg = RL_LPAR;
594 break;
595 case MII_PHYIDR1:
596 case MII_PHYIDR2:
597 return (0);
598 break;
599 default:
600 device_printf(sc->rl_dev, "bad phy register\n");
601 return (0);
602 }
603 CSR_WRITE_2(sc, re8139_reg, data);
604 return (0);
605 }
606
607 static void
608 re_miibus_statchg(dev)
609 device_t dev;
610 {
611
612 }
613
614 /*
615 * Program the 64-bit multicast hash filter.
616 */
617 static void
618 re_setmulti(sc)
619 struct rl_softc *sc;
620 {
621 struct ifnet *ifp;
622 int h = 0;
623 u_int32_t hashes[2] = { 0, 0 };
624 struct ifmultiaddr *ifma;
625 u_int32_t rxfilt;
626 int mcnt = 0;
627 u_int32_t hwrev;
628
629 RL_LOCK_ASSERT(sc);
630
631 ifp = sc->rl_ifp;
632
633
634 rxfilt = CSR_READ_4(sc, RL_RXCFG);
635 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI);
636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
637 if (ifp->if_flags & IFF_PROMISC)
638 rxfilt |= RL_RXCFG_RX_ALLPHYS;
639 if (ifp->if_flags & IFF_ALLMULTI)
640 rxfilt |= RL_RXCFG_RX_MULTI;
641 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
642 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
643 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
644 return;
645 }
646
647 /* first, zot all the existing hash bits */
648 CSR_WRITE_4(sc, RL_MAR0, 0);
649 CSR_WRITE_4(sc, RL_MAR4, 0);
650
651 /* now program new ones */
652 IF_ADDR_LOCK(ifp);
653 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
654 if (ifma->ifma_addr->sa_family != AF_LINK)
655 continue;
656 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
657 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
658 if (h < 32)
659 hashes[0] |= (1 << h);
660 else
661 hashes[1] |= (1 << (h - 32));
662 mcnt++;
663 }
664 IF_ADDR_UNLOCK(ifp);
665
666 if (mcnt)
667 rxfilt |= RL_RXCFG_RX_MULTI;
668 else
669 rxfilt &= ~RL_RXCFG_RX_MULTI;
670
671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
672
673 /*
674 * For some unfathomable reason, RealTek decided to reverse
675 * the order of the multicast hash registers in the PCI Express
676 * parts. This means we have to write the hash pattern in reverse
677 * order for those devices.
678 */
679
680 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
681
682 if (hwrev == RL_HWREV_8100E || hwrev == RL_HWREV_8101E ||
683 hwrev == RL_HWREV_8168_SPIN1 || hwrev == RL_HWREV_8168_SPIN2) {
684 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1]));
685 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0]));
686 } else {
687 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
688 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
689 }
690 }
691
692 static void
693 re_reset(sc)
694 struct rl_softc *sc;
695 {
696 register int i;
697
698 RL_LOCK_ASSERT(sc);
699
700 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
701
702 for (i = 0; i < RL_TIMEOUT; i++) {
703 DELAY(10);
704 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
705 break;
706 }
707 if (i == RL_TIMEOUT)
708 device_printf(sc->rl_dev, "reset never completed!\n");
709
710 CSR_WRITE_1(sc, 0x82, 1);
711 }
712
713 #ifdef RE_DIAG
714
715 /*
716 * The following routine is designed to test for a defect on some
717 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
718 * lines connected to the bus, however for a 32-bit only card, they
719 * should be pulled high. The result of this defect is that the
720 * NIC will not work right if you plug it into a 64-bit slot: DMA
721 * operations will be done with 64-bit transfers, which will fail
722 * because the 64-bit data lines aren't connected.
723 *
724 * There's no way to work around this (short of talking a soldering
725 * iron to the board), however we can detect it. The method we use
726 * here is to put the NIC into digital loopback mode, set the receiver
727 * to promiscuous mode, and then try to send a frame. We then compare
728 * the frame data we sent to what was received. If the data matches,
729 * then the NIC is working correctly, otherwise we know the user has
730 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
731 * slot. In the latter case, there's no way the NIC can work correctly,
732 * so we print out a message on the console and abort the device attach.
733 */
734
735 static int
736 re_diag(sc)
737 struct rl_softc *sc;
738 {
739 struct ifnet *ifp = sc->rl_ifp;
740 struct mbuf *m0;
741 struct ether_header *eh;
742 struct rl_desc *cur_rx;
743 u_int16_t status;
744 u_int32_t rxstat;
745 int total_len, i, error = 0, phyaddr;
746 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
747 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
748
749 /* Allocate a single mbuf */
750 MGETHDR(m0, M_DONTWAIT, MT_DATA);
751 if (m0 == NULL)
752 return (ENOBUFS);
753
754 RL_LOCK(sc);
755
756 /*
757 * Initialize the NIC in test mode. This sets the chip up
758 * so that it can send and receive frames, but performs the
759 * following special functions:
760 * - Puts receiver in promiscuous mode
761 * - Enables digital loopback mode
762 * - Leaves interrupts turned off
763 */
764
765 ifp->if_flags |= IFF_PROMISC;
766 sc->rl_testmode = 1;
767 re_reset(sc);
768 re_init_locked(sc);
769 sc->rl_link = 1;
770 if (sc->rl_type == RL_8169)
771 phyaddr = 1;
772 else
773 phyaddr = 0;
774
775 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
776 for (i = 0; i < RL_TIMEOUT; i++) {
777 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
778 if (!(status & BMCR_RESET))
779 break;
780 }
781
782 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
783 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
784
785 DELAY(100000);
786
787 /* Put some data in the mbuf */
788
789 eh = mtod(m0, struct ether_header *);
790 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
791 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
792 eh->ether_type = htons(ETHERTYPE_IP);
793 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
794
795 /*
796 * Queue the packet, start transmission.
797 * Note: IF_HANDOFF() ultimately calls re_start() for us.
798 */
799
800 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
801 RL_UNLOCK(sc);
802 /* XXX: re_diag must not be called when in ALTQ mode */
803 IF_HANDOFF(&ifp->if_snd, m0, ifp);
804 RL_LOCK(sc);
805 m0 = NULL;
806
807 /* Wait for it to propagate through the chip */
808
809 DELAY(100000);
810 for (i = 0; i < RL_TIMEOUT; i++) {
811 status = CSR_READ_2(sc, RL_ISR);
812 CSR_WRITE_2(sc, RL_ISR, status);
813 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
814 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
815 break;
816 DELAY(10);
817 }
818
819 if (i == RL_TIMEOUT) {
820 device_printf(sc->rl_dev,
821 "diagnostic failed, failed to receive packet in"
822 " loopback mode\n");
823 error = EIO;
824 goto done;
825 }
826
827 /*
828 * The packet should have been dumped into the first
829 * entry in the RX DMA ring. Grab it from there.
830 */
831
832 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
833 sc->rl_ldata.rl_rx_list_map,
834 BUS_DMASYNC_POSTREAD);
835 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
836 sc->rl_ldata.rl_rx_dmamap[0],
837 BUS_DMASYNC_POSTWRITE);
838 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
839 sc->rl_ldata.rl_rx_dmamap[0]);
840
841 m0 = sc->rl_ldata.rl_rx_mbuf[0];
842 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
843 eh = mtod(m0, struct ether_header *);
844
845 cur_rx = &sc->rl_ldata.rl_rx_list[0];
846 total_len = RL_RXBYTES(cur_rx);
847 rxstat = le32toh(cur_rx->rl_cmdstat);
848
849 if (total_len != ETHER_MIN_LEN) {
850 device_printf(sc->rl_dev,
851 "diagnostic failed, received short packet\n");
852 error = EIO;
853 goto done;
854 }
855
856 /* Test that the received packet data matches what we sent. */
857
858 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
859 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
860 ntohs(eh->ether_type) != ETHERTYPE_IP) {
861 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
862 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
863 dst, ":", src, ":", ETHERTYPE_IP);
864 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
865 eh->ether_dhost, ":", eh->ether_shost, ":",
866 ntohs(eh->ether_type));
867 device_printf(sc->rl_dev, "You may have a defective 32-bit "
868 "NIC plugged into a 64-bit PCI slot.\n");
869 device_printf(sc->rl_dev, "Please re-install the NIC in a "
870 "32-bit slot for proper operation.\n");
871 device_printf(sc->rl_dev, "Read the re(4) man page for more "
872 "details.\n");
873 error = EIO;
874 }
875
876 done:
877 /* Turn interface off, release resources */
878
879 sc->rl_testmode = 0;
880 sc->rl_link = 0;
881 ifp->if_flags &= ~IFF_PROMISC;
882 re_stop(sc);
883 if (m0 != NULL)
884 m_freem(m0);
885
886 RL_UNLOCK(sc);
887
888 return (error);
889 }
890
891 #endif
892
893 /*
894 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
895 * IDs against our list and return a device name if we find a match.
896 */
897 static int
898 re_probe(dev)
899 device_t dev;
900 {
901 struct rl_type *t;
902 struct rl_softc *sc;
903 int rid;
904 u_int32_t hwrev;
905
906 t = re_devs;
907 sc = device_get_softc(dev);
908
909 while (t->rl_name != NULL) {
910 if ((pci_get_vendor(dev) == t->rl_vid) &&
911 (pci_get_device(dev) == t->rl_did)) {
912 /*
913 * Only attach to rev. 3 of the Linksys EG1032 adapter.
914 * Rev. 2 i supported by sk(4).
915 */
916 if ((t->rl_vid == LINKSYS_VENDORID) &&
917 (t->rl_did == LINKSYS_DEVICEID_EG1032) &&
918 (pci_get_subdevice(dev) !=
919 LINKSYS_SUBDEVICE_EG1032_REV3)) {
920 t++;
921 continue;
922 }
923
924 /*
925 * Temporarily map the I/O space
926 * so we can read the chip ID register.
927 */
928 rid = RL_RID;
929 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
930 RF_ACTIVE);
931 if (sc->rl_res == NULL) {
932 device_printf(dev,
933 "couldn't map ports/memory\n");
934 return (ENXIO);
935 }
936 sc->rl_btag = rman_get_bustag(sc->rl_res);
937 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
938 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
939 bus_release_resource(dev, RL_RES,
940 RL_RID, sc->rl_res);
941 if (t->rl_basetype == hwrev) {
942 device_set_desc(dev, t->rl_name);
943 return (BUS_PROBE_DEFAULT);
944 }
945 }
946 t++;
947 }
948
949 return (ENXIO);
950 }
951
952 /*
953 * This routine takes the segment list provided as the result of
954 * a bus_dma_map_load() operation and assigns the addresses/lengths
955 * to RealTek DMA descriptors. This can be called either by the RX
956 * code or the TX code. In the RX case, we'll probably wind up mapping
957 * at most one segment. For the TX case, there could be any number of
958 * segments since TX packets may span multiple mbufs. In either case,
959 * if the number of segments is larger than the rl_maxsegs limit
960 * specified by the caller, we abort the mapping operation. Sadly,
961 * whoever designed the buffer mapping API did not provide a way to
962 * return an error from here, so we have to fake it a bit.
963 */
964
965 static void
966 re_dma_map_desc(arg, segs, nseg, mapsize, error)
967 void *arg;
968 bus_dma_segment_t *segs;
969 int nseg;
970 bus_size_t mapsize;
971 int error;
972 {
973 struct rl_dmaload_arg *ctx;
974 struct rl_desc *d = NULL;
975 int i = 0, idx;
976 u_int32_t cmdstat;
977 int totlen = 0;
978
979 if (error)
980 return;
981
982 ctx = arg;
983
984 /* Signal error to caller if there's too many segments */
985 if (nseg > ctx->rl_maxsegs) {
986 ctx->rl_maxsegs = 0;
987 return;
988 }
989
990 /*
991 * Map the segment array into descriptors. Note that we set the
992 * start-of-frame and end-of-frame markers for either TX or RX, but
993 * they really only have meaning in the TX case. (In the RX case,
994 * it's the chip that tells us where packets begin and end.)
995 * We also keep track of the end of the ring and set the
996 * end-of-ring bits as needed, and we set the ownership bits
997 * in all except the very first descriptor. (The caller will
998 * set this descriptor later when it start transmission or
999 * reception.)
1000 */
1001 idx = ctx->rl_idx;
1002 for (;;) {
1003 d = &ctx->rl_ring[idx];
1004 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
1005 ctx->rl_maxsegs = 0;
1006 return;
1007 }
1008 cmdstat = segs[i].ds_len;
1009 totlen += segs[i].ds_len;
1010 d->rl_vlanctl = 0;
1011 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
1012 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
1013 if (i == 0)
1014 cmdstat |= RL_TDESC_CMD_SOF;
1015 else
1016 cmdstat |= RL_TDESC_CMD_OWN;
1017 if (idx == (RL_RX_DESC_CNT - 1))
1018 cmdstat |= RL_TDESC_CMD_EOR;
1019 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
1020 i++;
1021 if (i == nseg)
1022 break;
1023 RL_DESC_INC(idx);
1024 }
1025
1026 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1027 ctx->rl_maxsegs = nseg;
1028 ctx->rl_idx = idx;
1029 }
1030
1031 /*
1032 * Map a single buffer address.
1033 */
1034
1035 static void
1036 re_dma_map_addr(arg, segs, nseg, error)
1037 void *arg;
1038 bus_dma_segment_t *segs;
1039 int nseg;
1040 int error;
1041 {
1042 bus_addr_t *addr;
1043
1044 if (error)
1045 return;
1046
1047 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1048 addr = arg;
1049 *addr = segs->ds_addr;
1050 }
1051
1052 static int
1053 re_allocmem(dev, sc)
1054 device_t dev;
1055 struct rl_softc *sc;
1056 {
1057 int error;
1058 int nseg;
1059 int i;
1060
1061 /*
1062 * Allocate map for RX mbufs.
1063 */
1064 nseg = 32;
1065 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
1066 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1067 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
1068 NULL, NULL, &sc->rl_ldata.rl_mtag);
1069 if (error) {
1070 device_printf(dev, "could not allocate dma tag\n");
1071 return (ENOMEM);
1072 }
1073
1074 /*
1075 * Allocate map for TX descriptor list.
1076 */
1077 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1078 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1079 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0,
1080 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1081 if (error) {
1082 device_printf(dev, "could not allocate dma tag\n");
1083 return (ENOMEM);
1084 }
1085
1086 /* Allocate DMA'able memory for the TX ring */
1087
1088 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1089 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1090 &sc->rl_ldata.rl_tx_list_map);
1091 if (error)
1092 return (ENOMEM);
1093
1094 /* Load the map for the TX ring. */
1095
1096 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1097 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1098 RL_TX_LIST_SZ, re_dma_map_addr,
1099 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1100
1101 /* Create DMA maps for TX buffers */
1102
1103 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1104 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1105 &sc->rl_ldata.rl_tx_dmamap[i]);
1106 if (error) {
1107 device_printf(dev, "can't create DMA map for TX\n");
1108 return (ENOMEM);
1109 }
1110 }
1111
1112 /*
1113 * Allocate map for RX descriptor list.
1114 */
1115 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1116 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1117 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0,
1118 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1119 if (error) {
1120 device_printf(dev, "could not allocate dma tag\n");
1121 return (ENOMEM);
1122 }
1123
1124 /* Allocate DMA'able memory for the RX ring */
1125
1126 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1127 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1128 &sc->rl_ldata.rl_rx_list_map);
1129 if (error)
1130 return (ENOMEM);
1131
1132 /* Load the map for the RX ring. */
1133
1134 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1135 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1136 RL_RX_LIST_SZ, re_dma_map_addr,
1137 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1138
1139 /* Create DMA maps for RX buffers */
1140
1141 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1142 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1143 &sc->rl_ldata.rl_rx_dmamap[i]);
1144 if (error) {
1145 device_printf(dev, "can't create DMA map for RX\n");
1146 return (ENOMEM);
1147 }
1148 }
1149
1150 return (0);
1151 }
1152
1153 /*
1154 * Attach the interface. Allocate softc structures, do ifmedia
1155 * setup and ethernet/BPF attach.
1156 */
1157 static int
1158 re_attach(dev)
1159 device_t dev;
1160 {
1161 u_char eaddr[ETHER_ADDR_LEN];
1162 u_int16_t as[ETHER_ADDR_LEN / 2];
1163 struct rl_softc *sc;
1164 struct ifnet *ifp;
1165 struct rl_hwrev *hw_rev;
1166 int hwrev;
1167 u_int16_t re_did = 0;
1168 int error = 0, rid, i;
1169
1170 sc = device_get_softc(dev);
1171 sc->rl_dev = dev;
1172
1173 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1174 MTX_DEF);
1175 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1176
1177 /*
1178 * Map control/status registers.
1179 */
1180 pci_enable_busmaster(dev);
1181
1182 rid = RL_RID;
1183 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1184 RF_ACTIVE);
1185
1186 if (sc->rl_res == NULL) {
1187 device_printf(dev, "couldn't map ports/memory\n");
1188 error = ENXIO;
1189 goto fail;
1190 }
1191
1192 sc->rl_btag = rman_get_bustag(sc->rl_res);
1193 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1194
1195 /* Allocate interrupt */
1196 rid = 0;
1197 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1198 RF_SHAREABLE | RF_ACTIVE);
1199
1200 if (sc->rl_irq == NULL) {
1201 device_printf(dev, "couldn't map interrupt\n");
1202 error = ENXIO;
1203 goto fail;
1204 }
1205
1206 /* Reset the adapter. */
1207 RL_LOCK(sc);
1208 re_reset(sc);
1209 RL_UNLOCK(sc);
1210
1211 hw_rev = re_hwrevs;
1212 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1213 while (hw_rev->rl_desc != NULL) {
1214 if (hw_rev->rl_rev == hwrev) {
1215 sc->rl_type = hw_rev->rl_type;
1216 break;
1217 }
1218 hw_rev++;
1219 }
1220
1221 sc->rl_eewidth = RL_9356_ADDR_LEN;
1222 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1223 if (re_did != 0x8129)
1224 sc->rl_eewidth = RL_9346_ADDR_LEN;
1225
1226 /*
1227 * Get station address from the EEPROM.
1228 */
1229 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1230 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1231 as[i] = le16toh(as[i]);
1232 bcopy(as, eaddr, sizeof(eaddr));
1233
1234 if (sc->rl_type == RL_8169) {
1235 /* Set RX length mask */
1236 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1237 sc->rl_txstart = RL_GTXSTART;
1238 } else {
1239 /* Set RX length mask */
1240 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1241 sc->rl_txstart = RL_TXSTART;
1242 }
1243
1244 /*
1245 * Allocate the parent bus DMA tag appropriate for PCI.
1246 */
1247 #define RL_NSEG_NEW 32
1248 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1249 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1250 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0,
1251 NULL, NULL, &sc->rl_parent_tag);
1252 if (error)
1253 goto fail;
1254
1255 error = re_allocmem(dev, sc);
1256
1257 if (error)
1258 goto fail;
1259
1260 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1261 if (ifp == NULL) {
1262 device_printf(dev, "can not if_alloc()\n");
1263 error = ENOSPC;
1264 goto fail;
1265 }
1266
1267 /* Do MII setup */
1268 if (mii_phy_probe(dev, &sc->rl_miibus,
1269 re_ifmedia_upd, re_ifmedia_sts)) {
1270 device_printf(dev, "MII without any phy!\n");
1271 error = ENXIO;
1272 goto fail;
1273 }
1274
1275 /* Take PHY out of power down mode. */
1276 if (sc->rl_type == RL_8169) {
1277 uint32_t rev;
1278
1279 rev = CSR_READ_4(sc, RL_TXCFG);
1280 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */
1281 rev &= 0x7c800000;
1282 if (rev != 0) {
1283 /* RTL8169S single chip */
1284 switch (rev) {
1285 case RL_HWREV_8169_8110SB:
1286 case RL_HWREV_8169_8110SC:
1287 case RL_HWREV_8168_SPIN2:
1288 re_gmii_writereg(dev, 1, 0x1f, 0);
1289 re_gmii_writereg(dev, 1, 0x0e, 0);
1290 break;
1291 default:
1292 break;
1293 }
1294 }
1295 }
1296
1297 ifp->if_softc = sc;
1298 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1299 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1300 ifp->if_ioctl = re_ioctl;
1301 ifp->if_start = re_start;
1302 ifp->if_hwassist = RE_CSUM_FEATURES;
1303 ifp->if_capabilities = IFCAP_HWCSUM;
1304 ifp->if_capenable = ifp->if_capabilities;
1305 ifp->if_init = re_init;
1306 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1307 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1308 IFQ_SET_READY(&ifp->if_snd);
1309
1310 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1311 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1312
1313 /*
1314 * Call MI attach routine.
1315 */
1316 ether_ifattach(ifp, eaddr);
1317
1318 /* VLAN capability setup */
1319 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1320 #ifdef IFCAP_VLAN_HWCSUM
1321 if (ifp->if_capabilities & IFCAP_HWCSUM)
1322 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1323 #endif
1324 ifp->if_capenable = ifp->if_capabilities;
1325 #ifdef DEVICE_POLLING
1326 ifp->if_capabilities |= IFCAP_POLLING;
1327 #endif
1328 /*
1329 * Tell the upper layer(s) we support long frames.
1330 * Must appear after the call to ether_ifattach() because
1331 * ether_ifattach() sets ifi_hdrlen to the default value.
1332 */
1333 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1334
1335 #ifdef RE_DIAG
1336 /*
1337 * Perform hardware diagnostic on the original RTL8169.
1338 * Some 32-bit cards were incorrectly wired and would
1339 * malfunction if plugged into a 64-bit slot.
1340 */
1341
1342 if (hwrev == RL_HWREV_8169) {
1343 error = re_diag(sc);
1344 if (error) {
1345 device_printf(dev,
1346 "attach aborted due to hardware diag failure\n");
1347 ether_ifdetach(ifp);
1348 goto fail;
1349 }
1350 }
1351 #endif
1352
1353 /* Hook interrupt last to avoid having to lock softc */
1354 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE |
1355 INTR_FAST, re_intr, sc, &sc->rl_intrhand);
1356 if (error) {
1357 device_printf(dev, "couldn't set up irq\n");
1358 ether_ifdetach(ifp);
1359 }
1360
1361 fail:
1362
1363 if (error)
1364 re_detach(dev);
1365
1366 return (error);
1367 }
1368
1369 /*
1370 * Shutdown hardware and free up resources. This can be called any
1371 * time after the mutex has been initialized. It is called in both
1372 * the error case in attach and the normal detach case so it needs
1373 * to be careful about only freeing resources that have actually been
1374 * allocated.
1375 */
1376 static int
1377 re_detach(dev)
1378 device_t dev;
1379 {
1380 struct rl_softc *sc;
1381 struct ifnet *ifp;
1382 int i;
1383
1384 sc = device_get_softc(dev);
1385 ifp = sc->rl_ifp;
1386 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1387
1388 #ifdef DEVICE_POLLING
1389 if (ifp->if_capenable & IFCAP_POLLING)
1390 ether_poll_deregister(ifp);
1391 #endif
1392 /* These should only be active if attach succeeded */
1393 if (device_is_attached(dev)) {
1394 RL_LOCK(sc);
1395 #if 0
1396 sc->suspended = 1;
1397 #endif
1398 re_stop(sc);
1399 RL_UNLOCK(sc);
1400 callout_drain(&sc->rl_stat_callout);
1401 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1402 taskqueue_drain(taskqueue_fast, &sc->rl_txtask);
1403 /*
1404 * Force off the IFF_UP flag here, in case someone
1405 * still had a BPF descriptor attached to this
1406 * interface. If they do, ether_ifdetach() will cause
1407 * the BPF code to try and clear the promisc mode
1408 * flag, which will bubble down to re_ioctl(),
1409 * which will try to call re_init() again. This will
1410 * turn the NIC back on and restart the MII ticker,
1411 * which will panic the system when the kernel tries
1412 * to invoke the re_tick() function that isn't there
1413 * anymore.
1414 */
1415 ifp->if_flags &= ~IFF_UP;
1416 ether_ifdetach(ifp);
1417 }
1418 if (sc->rl_miibus)
1419 device_delete_child(dev, sc->rl_miibus);
1420 bus_generic_detach(dev);
1421
1422 /*
1423 * The rest is resource deallocation, so we should already be
1424 * stopped here.
1425 */
1426
1427 if (sc->rl_intrhand)
1428 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1429 if (ifp != NULL)
1430 if_free(ifp);
1431 if (sc->rl_irq)
1432 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1433 if (sc->rl_res)
1434 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1435
1436 /* Unload and free the RX DMA ring memory and map */
1437
1438 if (sc->rl_ldata.rl_rx_list_tag) {
1439 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1440 sc->rl_ldata.rl_rx_list_map);
1441 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1442 sc->rl_ldata.rl_rx_list,
1443 sc->rl_ldata.rl_rx_list_map);
1444 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1445 }
1446
1447 /* Unload and free the TX DMA ring memory and map */
1448
1449 if (sc->rl_ldata.rl_tx_list_tag) {
1450 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1451 sc->rl_ldata.rl_tx_list_map);
1452 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1453 sc->rl_ldata.rl_tx_list,
1454 sc->rl_ldata.rl_tx_list_map);
1455 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1456 }
1457
1458 /* Destroy all the RX and TX buffer maps */
1459
1460 if (sc->rl_ldata.rl_mtag) {
1461 for (i = 0; i < RL_TX_DESC_CNT; i++)
1462 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1463 sc->rl_ldata.rl_tx_dmamap[i]);
1464 for (i = 0; i < RL_RX_DESC_CNT; i++)
1465 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1466 sc->rl_ldata.rl_rx_dmamap[i]);
1467 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1468 }
1469
1470 /* Unload and free the stats buffer and map */
1471
1472 if (sc->rl_ldata.rl_stag) {
1473 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1474 sc->rl_ldata.rl_rx_list_map);
1475 bus_dmamem_free(sc->rl_ldata.rl_stag,
1476 sc->rl_ldata.rl_stats,
1477 sc->rl_ldata.rl_smap);
1478 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1479 }
1480
1481 if (sc->rl_parent_tag)
1482 bus_dma_tag_destroy(sc->rl_parent_tag);
1483
1484 mtx_destroy(&sc->rl_mtx);
1485
1486 return (0);
1487 }
1488
1489 static int
1490 re_newbuf(sc, idx, m)
1491 struct rl_softc *sc;
1492 int idx;
1493 struct mbuf *m;
1494 {
1495 struct rl_dmaload_arg arg;
1496 struct mbuf *n = NULL;
1497 int error;
1498
1499 if (m == NULL) {
1500 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1501 if (n == NULL)
1502 return (ENOBUFS);
1503 m = n;
1504 } else
1505 m->m_data = m->m_ext.ext_buf;
1506
1507 m->m_len = m->m_pkthdr.len = MCLBYTES;
1508 #ifdef RE_FIXUP_RX
1509 /*
1510 * This is part of an evil trick to deal with non-x86 platforms.
1511 * The RealTek chip requires RX buffers to be aligned on 64-bit
1512 * boundaries, but that will hose non-x86 machines. To get around
1513 * this, we leave some empty space at the start of each buffer
1514 * and for non-x86 hosts, we copy the buffer back six bytes
1515 * to achieve word alignment. This is slightly more efficient
1516 * than allocating a new buffer, copying the contents, and
1517 * discarding the old buffer.
1518 */
1519 m_adj(m, RE_ETHER_ALIGN);
1520 #endif
1521 arg.rl_idx = idx;
1522 arg.rl_maxsegs = 1;
1523 arg.rl_flags = 0;
1524 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1525
1526 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1527 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1528 &arg, BUS_DMA_NOWAIT);
1529 if (error || arg.rl_maxsegs != 1) {
1530 if (n != NULL)
1531 m_freem(n);
1532 if (arg.rl_maxsegs == 0)
1533 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1534 sc->rl_ldata.rl_rx_dmamap[idx]);
1535 return (ENOMEM);
1536 }
1537
1538 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1539 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1540
1541 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1542 sc->rl_ldata.rl_rx_dmamap[idx],
1543 BUS_DMASYNC_PREREAD);
1544
1545 return (0);
1546 }
1547
1548 #ifdef RE_FIXUP_RX
1549 static __inline void
1550 re_fixup_rx(m)
1551 struct mbuf *m;
1552 {
1553 int i;
1554 uint16_t *src, *dst;
1555
1556 src = mtod(m, uint16_t *);
1557 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1558
1559 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1560 *dst++ = *src++;
1561
1562 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1563
1564 return;
1565 }
1566 #endif
1567
1568 static int
1569 re_tx_list_init(sc)
1570 struct rl_softc *sc;
1571 {
1572
1573 RL_LOCK_ASSERT(sc);
1574
1575 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1576 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1577 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1578
1579 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1580 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1581 sc->rl_ldata.rl_tx_prodidx = 0;
1582 sc->rl_ldata.rl_tx_considx = 0;
1583 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1584
1585 return (0);
1586 }
1587
1588 static int
1589 re_rx_list_init(sc)
1590 struct rl_softc *sc;
1591 {
1592 int i;
1593
1594 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1595 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1596 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1597
1598 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1599 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1600 return (ENOBUFS);
1601 }
1602
1603 /* Flush the RX descriptors */
1604
1605 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1606 sc->rl_ldata.rl_rx_list_map,
1607 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1608
1609 sc->rl_ldata.rl_rx_prodidx = 0;
1610 sc->rl_head = sc->rl_tail = NULL;
1611
1612 return (0);
1613 }
1614
1615 /*
1616 * RX handler for C+ and 8169. For the gigE chips, we support
1617 * the reception of jumbo frames that have been fragmented
1618 * across multiple 2K mbuf cluster buffers.
1619 */
1620 static int
1621 re_rxeof(sc)
1622 struct rl_softc *sc;
1623 {
1624 struct mbuf *m;
1625 struct ifnet *ifp;
1626 int i, total_len;
1627 struct rl_desc *cur_rx;
1628 u_int32_t rxstat, rxvlan;
1629 int maxpkt = 16;
1630
1631 RL_LOCK_ASSERT(sc);
1632
1633 ifp = sc->rl_ifp;
1634 i = sc->rl_ldata.rl_rx_prodidx;
1635
1636 /* Invalidate the descriptor memory */
1637
1638 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1639 sc->rl_ldata.rl_rx_list_map,
1640 BUS_DMASYNC_POSTREAD);
1641
1642 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) {
1643 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1644 m = sc->rl_ldata.rl_rx_mbuf[i];
1645 total_len = RL_RXBYTES(cur_rx);
1646 rxstat = le32toh(cur_rx->rl_cmdstat);
1647 rxvlan = le32toh(cur_rx->rl_vlanctl);
1648
1649 /* Invalidate the RX mbuf and unload its map */
1650
1651 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1652 sc->rl_ldata.rl_rx_dmamap[i],
1653 BUS_DMASYNC_POSTWRITE);
1654 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1655 sc->rl_ldata.rl_rx_dmamap[i]);
1656
1657 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1658 m->m_len = RE_RX_DESC_BUFLEN;
1659 if (sc->rl_head == NULL)
1660 sc->rl_head = sc->rl_tail = m;
1661 else {
1662 m->m_flags &= ~M_PKTHDR;
1663 sc->rl_tail->m_next = m;
1664 sc->rl_tail = m;
1665 }
1666 re_newbuf(sc, i, NULL);
1667 RL_DESC_INC(i);
1668 continue;
1669 }
1670
1671 /*
1672 * NOTE: for the 8139C+, the frame length field
1673 * is always 12 bits in size, but for the gigE chips,
1674 * it is 13 bits (since the max RX frame length is 16K).
1675 * Unfortunately, all 32 bits in the status word
1676 * were already used, so to make room for the extra
1677 * length bit, RealTek took out the 'frame alignment
1678 * error' bit and shifted the other status bits
1679 * over one slot. The OWN, EOR, FS and LS bits are
1680 * still in the same places. We have already extracted
1681 * the frame length and checked the OWN bit, so rather
1682 * than using an alternate bit mapping, we shift the
1683 * status bits one space to the right so we can evaluate
1684 * them using the 8169 status as though it was in the
1685 * same format as that of the 8139C+.
1686 */
1687 if (sc->rl_type == RL_8169)
1688 rxstat >>= 1;
1689
1690 /*
1691 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1692 * set, but if CRC is clear, it will still be a valid frame.
1693 */
1694 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1695 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1696 ifp->if_ierrors++;
1697 /*
1698 * If this is part of a multi-fragment packet,
1699 * discard all the pieces.
1700 */
1701 if (sc->rl_head != NULL) {
1702 m_freem(sc->rl_head);
1703 sc->rl_head = sc->rl_tail = NULL;
1704 }
1705 re_newbuf(sc, i, m);
1706 RL_DESC_INC(i);
1707 continue;
1708 }
1709
1710 /*
1711 * If allocating a replacement mbuf fails,
1712 * reload the current one.
1713 */
1714
1715 if (re_newbuf(sc, i, NULL)) {
1716 ifp->if_ierrors++;
1717 if (sc->rl_head != NULL) {
1718 m_freem(sc->rl_head);
1719 sc->rl_head = sc->rl_tail = NULL;
1720 }
1721 re_newbuf(sc, i, m);
1722 RL_DESC_INC(i);
1723 continue;
1724 }
1725
1726 RL_DESC_INC(i);
1727
1728 if (sc->rl_head != NULL) {
1729 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1730 if (m->m_len == 0)
1731 m->m_len = RE_RX_DESC_BUFLEN;
1732 /*
1733 * Special case: if there's 4 bytes or less
1734 * in this buffer, the mbuf can be discarded:
1735 * the last 4 bytes is the CRC, which we don't
1736 * care about anyway.
1737 */
1738 if (m->m_len <= ETHER_CRC_LEN) {
1739 sc->rl_tail->m_len -=
1740 (ETHER_CRC_LEN - m->m_len);
1741 m_freem(m);
1742 } else {
1743 m->m_len -= ETHER_CRC_LEN;
1744 m->m_flags &= ~M_PKTHDR;
1745 sc->rl_tail->m_next = m;
1746 }
1747 m = sc->rl_head;
1748 sc->rl_head = sc->rl_tail = NULL;
1749 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1750 } else
1751 m->m_pkthdr.len = m->m_len =
1752 (total_len - ETHER_CRC_LEN);
1753
1754 #ifdef RE_FIXUP_RX
1755 re_fixup_rx(m);
1756 #endif
1757 ifp->if_ipackets++;
1758 m->m_pkthdr.rcvif = ifp;
1759
1760 /* Do RX checksumming if enabled */
1761
1762 if (ifp->if_capenable & IFCAP_RXCSUM) {
1763
1764 /* Check IP header checksum */
1765 if (rxstat & RL_RDESC_STAT_PROTOID)
1766 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1767 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1768 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1769
1770 /* Check TCP/UDP checksum */
1771 if ((RL_TCPPKT(rxstat) &&
1772 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1773 (RL_UDPPKT(rxstat) &&
1774 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1775 m->m_pkthdr.csum_flags |=
1776 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1777 m->m_pkthdr.csum_data = 0xffff;
1778 }
1779 }
1780 maxpkt--;
1781 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1782 VLAN_INPUT_TAG_NEW(ifp, m,
1783 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1784 if (m == NULL)
1785 continue;
1786 }
1787 RL_UNLOCK(sc);
1788 (*ifp->if_input)(ifp, m);
1789 RL_LOCK(sc);
1790 }
1791
1792 /* Flush the RX DMA ring */
1793
1794 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1795 sc->rl_ldata.rl_rx_list_map,
1796 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1797
1798 sc->rl_ldata.rl_rx_prodidx = i;
1799
1800 if (maxpkt)
1801 return(EAGAIN);
1802
1803 return(0);
1804 }
1805
1806 static void
1807 re_txeof(sc)
1808 struct rl_softc *sc;
1809 {
1810 struct ifnet *ifp;
1811 u_int32_t txstat;
1812 int idx;
1813
1814 ifp = sc->rl_ifp;
1815 idx = sc->rl_ldata.rl_tx_considx;
1816
1817 /* Invalidate the TX descriptor list */
1818 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1819 sc->rl_ldata.rl_tx_list_map,
1820 BUS_DMASYNC_POSTREAD);
1821
1822 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1823 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1824 if (txstat & RL_TDESC_CMD_OWN)
1825 break;
1826
1827 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0;
1828
1829 /*
1830 * We only stash mbufs in the last descriptor
1831 * in a fragment chain, which also happens to
1832 * be the only place where the TX status bits
1833 * are valid.
1834 */
1835 if (txstat & RL_TDESC_CMD_EOF) {
1836 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1837 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1838 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1839 sc->rl_ldata.rl_tx_dmamap[idx]);
1840 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1841 RL_TDESC_STAT_COLCNT))
1842 ifp->if_collisions++;
1843 if (txstat & RL_TDESC_STAT_TXERRSUM)
1844 ifp->if_oerrors++;
1845 else
1846 ifp->if_opackets++;
1847 }
1848 sc->rl_ldata.rl_tx_free++;
1849 RL_DESC_INC(idx);
1850 }
1851 sc->rl_ldata.rl_tx_considx = idx;
1852
1853 /* No changes made to the TX ring, so no flush needed */
1854
1855 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD)
1856 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1857
1858 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1859 /*
1860 * Some chips will ignore a second TX request issued
1861 * while an existing transmission is in progress. If
1862 * the transmitter goes idle but there are still
1863 * packets waiting to be sent, we need to restart the
1864 * channel here to flush them out. This only seems to
1865 * be required with the PCIe devices.
1866 */
1867 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
1868
1869 #ifdef RE_TX_MODERATION
1870 /*
1871 * If not all descriptors have been reaped yet, reload
1872 * the timer so that we will eventually get another
1873 * interrupt that will cause us to re-enter this routine.
1874 * This is done in case the transmitter has gone idle.
1875 */
1876 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1877 #endif
1878 } else
1879 sc->rl_watchdog_timer = 0;
1880 }
1881
1882 static void
1883 re_tick(xsc)
1884 void *xsc;
1885 {
1886 struct rl_softc *sc;
1887 struct mii_data *mii;
1888 struct ifnet *ifp;
1889
1890 sc = xsc;
1891 ifp = sc->rl_ifp;
1892
1893 RL_LOCK_ASSERT(sc);
1894
1895 re_watchdog(sc);
1896
1897 mii = device_get_softc(sc->rl_miibus);
1898 mii_tick(mii);
1899 if (sc->rl_link) {
1900 if (!(mii->mii_media_status & IFM_ACTIVE))
1901 sc->rl_link = 0;
1902 } else {
1903 if (mii->mii_media_status & IFM_ACTIVE &&
1904 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1905 sc->rl_link = 1;
1906 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1907 taskqueue_enqueue_fast(taskqueue_fast,
1908 &sc->rl_txtask);
1909 }
1910 }
1911
1912 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1913 }
1914
1915 #ifdef DEVICE_POLLING
1916 static void
1917 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1918 {
1919 struct rl_softc *sc = ifp->if_softc;
1920
1921 RL_LOCK(sc);
1922 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1923 re_poll_locked(ifp, cmd, count);
1924 RL_UNLOCK(sc);
1925 }
1926
1927 static void
1928 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1929 {
1930 struct rl_softc *sc = ifp->if_softc;
1931
1932 RL_LOCK_ASSERT(sc);
1933
1934 sc->rxcycles = count;
1935 re_rxeof(sc);
1936 re_txeof(sc);
1937
1938 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1939 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1940
1941 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1942 u_int16_t status;
1943
1944 status = CSR_READ_2(sc, RL_ISR);
1945 if (status == 0xffff)
1946 return;
1947 if (status)
1948 CSR_WRITE_2(sc, RL_ISR, status);
1949
1950 /*
1951 * XXX check behaviour on receiver stalls.
1952 */
1953
1954 if (status & RL_ISR_SYSTEM_ERR) {
1955 re_reset(sc);
1956 re_init_locked(sc);
1957 }
1958 }
1959 }
1960 #endif /* DEVICE_POLLING */
1961
1962 static void
1963 re_intr(arg)
1964 void *arg;
1965 {
1966 struct rl_softc *sc;
1967 uint16_t status;
1968
1969 sc = arg;
1970
1971 status = CSR_READ_2(sc, RL_ISR);
1972 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
1973 return;
1974 CSR_WRITE_2(sc, RL_IMR, 0);
1975
1976 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1977
1978 return;
1979 }
1980
1981 static void
1982 re_int_task(arg, npending)
1983 void *arg;
1984 int npending;
1985 {
1986 struct rl_softc *sc;
1987 struct ifnet *ifp;
1988 u_int16_t status;
1989 int rval = 0;
1990
1991 sc = arg;
1992 ifp = sc->rl_ifp;
1993
1994 RL_LOCK(sc);
1995
1996 status = CSR_READ_2(sc, RL_ISR);
1997 CSR_WRITE_2(sc, RL_ISR, status);
1998
1999 if (sc->suspended || !(ifp->if_flags & IFF_UP)) {
2000 RL_UNLOCK(sc);
2001 return;
2002 }
2003
2004 #ifdef DEVICE_POLLING
2005 if (ifp->if_capenable & IFCAP_POLLING) {
2006 RL_UNLOCK(sc);
2007 return;
2008 }
2009 #endif
2010
2011 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2012 rval = re_rxeof(sc);
2013
2014 #ifdef RE_TX_MODERATION
2015 if (status & (RL_ISR_TIMEOUT_EXPIRED|
2016 #else
2017 if (status & (RL_ISR_TX_OK|
2018 #endif
2019 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2020 re_txeof(sc);
2021
2022 if (status & RL_ISR_SYSTEM_ERR) {
2023 re_reset(sc);
2024 re_init_locked(sc);
2025 }
2026
2027 if (status & RL_ISR_LINKCHG) {
2028 callout_stop(&sc->rl_stat_callout);
2029 re_tick(sc);
2030 }
2031
2032 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2033 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2034
2035 RL_UNLOCK(sc);
2036
2037 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2038 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2039 return;
2040 }
2041
2042 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2043
2044 return;
2045 }
2046
2047 static int
2048 re_encap(sc, m_head, idx)
2049 struct rl_softc *sc;
2050 struct mbuf **m_head;
2051 int *idx;
2052 {
2053 struct mbuf *m_new = NULL;
2054 struct rl_dmaload_arg arg;
2055 bus_dmamap_t map;
2056 int error;
2057 struct m_tag *mtag;
2058
2059 RL_LOCK_ASSERT(sc);
2060
2061 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD)
2062 return (EFBIG);
2063
2064 /*
2065 * Set up checksum offload. Note: checksum offload bits must
2066 * appear in all descriptors of a multi-descriptor transmit
2067 * attempt. This is according to testing done with an 8169
2068 * chip. This is a requirement.
2069 */
2070
2071 arg.rl_flags = 0;
2072
2073 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2074 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
2075 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2076 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
2077 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2078 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
2079
2080 arg.rl_idx = *idx;
2081 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2082 if (arg.rl_maxsegs > RL_TX_DESC_THLD)
2083 arg.rl_maxsegs -= RL_TX_DESC_THLD;
2084 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2085
2086 map = sc->rl_ldata.rl_tx_dmamap[*idx];
2087
2088 /*
2089 * With some of the RealTek chips, using the checksum offload
2090 * support in conjunction with the autopadding feature results
2091 * in the transmission of corrupt frames. For example, if we
2092 * need to send a really small IP fragment that's less than 60
2093 * bytes in size, and IP header checksumming is enabled, the
2094 * resulting ethernet frame that appears on the wire will
2095 * have garbled payload. To work around this, if TX checksum
2096 * offload is enabled, we always manually pad short frames out
2097 * to the minimum ethernet frame size. We do this by pretending
2098 * the mbuf chain has too many fragments so the coalescing code
2099 * below can assemble the packet into a single buffer that's
2100 * padded out to the mininum frame size.
2101 *
2102 * Note: this appears unnecessary for TCP, and doing it for TCP
2103 * with PCIe adapters seems to result in bad checksums.
2104 */
2105
2106 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) &&
2107 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN)
2108 error = EFBIG;
2109 else
2110 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2111 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2112
2113 if (error && error != EFBIG) {
2114 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error);
2115 return (ENOBUFS);
2116 }
2117
2118 /* Too many segments to map, coalesce into a single mbuf */
2119
2120 if (error || arg.rl_maxsegs == 0) {
2121 if (arg.rl_maxsegs == 0)
2122 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map);
2123 m_new = m_defrag(*m_head, M_DONTWAIT);
2124 if (m_new == NULL) {
2125 m_freem(*m_head);
2126 *m_head = NULL;
2127 return (ENOBUFS);
2128 }
2129 *m_head = m_new;
2130
2131 /*
2132 * Manually pad short frames, and zero the pad space
2133 * to avoid leaking data.
2134 */
2135 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) {
2136 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
2137 RL_MIN_FRAMELEN - m_new->m_pkthdr.len);
2138 m_new->m_pkthdr.len += RL_MIN_FRAMELEN -
2139 m_new->m_pkthdr.len;
2140 m_new->m_len = m_new->m_pkthdr.len;
2141 }
2142
2143 /* Note that we'll run over RL_TX_DESC_THLD here. */
2144 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2145 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2146 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2147 if (error || arg.rl_maxsegs == 0) {
2148 device_printf(sc->rl_dev,
2149 "can't map defragmented mbuf (error %d)\n", error);
2150 m_freem(m_new);
2151 *m_head = NULL;
2152 if (arg.rl_maxsegs == 0)
2153 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map);
2154 return (EFBIG);
2155 }
2156 }
2157
2158 /*
2159 * Insure that the map for this transmission
2160 * is placed at the array index of the last descriptor
2161 * in this chain. (Swap last and first dmamaps.)
2162 */
2163 sc->rl_ldata.rl_tx_dmamap[*idx] =
2164 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
2165 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
2166
2167 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
2168 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
2169
2170 /*
2171 * Set up hardware VLAN tagging. Note: vlan tag info must
2172 * appear in the first descriptor of a multi-descriptor
2173 * transmission attempt.
2174 */
2175
2176 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
2177 if (mtag != NULL)
2178 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
2179 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
2180
2181 /* Transfer ownership of packet to the chip. */
2182
2183 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
2184 htole32(RL_TDESC_CMD_OWN);
2185 if (*idx != arg.rl_idx)
2186 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
2187 htole32(RL_TDESC_CMD_OWN);
2188
2189 RL_DESC_INC(arg.rl_idx);
2190 *idx = arg.rl_idx;
2191
2192 return (0);
2193 }
2194
2195 static void
2196 re_tx_task(arg, npending)
2197 void *arg;
2198 int npending;
2199 {
2200 struct ifnet *ifp;
2201
2202 ifp = arg;
2203 re_start(ifp);
2204
2205 return;
2206 }
2207
2208 /*
2209 * Main transmit routine for C+ and gigE NICs.
2210 */
2211 static void
2212 re_start(ifp)
2213 struct ifnet *ifp;
2214 {
2215 struct rl_softc *sc;
2216 struct mbuf *m_head = NULL;
2217 int idx, queued = 0;
2218
2219 sc = ifp->if_softc;
2220
2221 RL_LOCK(sc);
2222
2223 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) {
2224 RL_UNLOCK(sc);
2225 return;
2226 }
2227
2228 idx = sc->rl_ldata.rl_tx_prodidx;
2229
2230 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2231 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2232 if (m_head == NULL)
2233 break;
2234
2235 if (re_encap(sc, &m_head, &idx)) {
2236 if (m_head == NULL)
2237 break;
2238 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2239 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2240 break;
2241 }
2242
2243 /*
2244 * If there's a BPF listener, bounce a copy of this frame
2245 * to him.
2246 */
2247 ETHER_BPF_MTAP(ifp, m_head);
2248
2249 queued++;
2250 }
2251
2252 if (queued == 0) {
2253 #ifdef RE_TX_MODERATION
2254 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
2255 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2256 #endif
2257 RL_UNLOCK(sc);
2258 return;
2259 }
2260
2261 /* Flush the TX descriptors */
2262
2263 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2264 sc->rl_ldata.rl_tx_list_map,
2265 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2266
2267 sc->rl_ldata.rl_tx_prodidx = idx;
2268
2269 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2270
2271 #ifdef RE_TX_MODERATION
2272 /*
2273 * Use the countdown timer for interrupt moderation.
2274 * 'TX done' interrupts are disabled. Instead, we reset the
2275 * countdown timer, which will begin counting until it hits
2276 * the value in the TIMERINT register, and then trigger an
2277 * interrupt. Each time we write to the TIMERCNT register,
2278 * the timer count is reset to 0.
2279 */
2280 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2281 #endif
2282
2283 /*
2284 * Set a timeout in case the chip goes out to lunch.
2285 */
2286 sc->rl_watchdog_timer = 5;
2287
2288 RL_UNLOCK(sc);
2289
2290 return;
2291 }
2292
2293 static void
2294 re_init(xsc)
2295 void *xsc;
2296 {
2297 struct rl_softc *sc = xsc;
2298
2299 RL_LOCK(sc);
2300 re_init_locked(sc);
2301 RL_UNLOCK(sc);
2302 }
2303
2304 static void
2305 re_init_locked(sc)
2306 struct rl_softc *sc;
2307 {
2308 struct ifnet *ifp = sc->rl_ifp;
2309 struct mii_data *mii;
2310 u_int32_t rxcfg = 0;
2311 union {
2312 uint32_t align_dummy;
2313 u_char eaddr[ETHER_ADDR_LEN];
2314 } eaddr;
2315
2316 RL_LOCK_ASSERT(sc);
2317
2318 mii = device_get_softc(sc->rl_miibus);
2319
2320 /*
2321 * Cancel pending I/O and free all RX/TX buffers.
2322 */
2323 re_stop(sc);
2324
2325 /*
2326 * Enable C+ RX and TX mode, as well as VLAN stripping and
2327 * RX checksum offload. We must configure the C+ register
2328 * before all others.
2329 */
2330 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2331 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2332 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
2333
2334 /*
2335 * Init our MAC address. Even though the chipset
2336 * documentation doesn't mention it, we need to enter "Config
2337 * register write enable" mode to modify the ID registers.
2338 */
2339 /* Copy MAC address on stack to align. */
2340 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2342 CSR_WRITE_4(sc, RL_IDR0,
2343 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2344 CSR_WRITE_4(sc, RL_IDR4,
2345 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2347
2348 /*
2349 * For C+ mode, initialize the RX descriptors and mbufs.
2350 */
2351 re_rx_list_init(sc);
2352 re_tx_list_init(sc);
2353
2354 /*
2355 * Load the addresses of the RX and TX lists into the chip.
2356 */
2357
2358 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2359 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2360 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2361 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2362
2363 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2364 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2365 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2366 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2367
2368 /*
2369 * Enable transmit and receive.
2370 */
2371 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2372
2373 /*
2374 * Set the initial TX and RX configuration.
2375 */
2376 if (sc->rl_testmode) {
2377 if (sc->rl_type == RL_8169)
2378 CSR_WRITE_4(sc, RL_TXCFG,
2379 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2380 else
2381 CSR_WRITE_4(sc, RL_TXCFG,
2382 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2383 } else
2384 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2385
2386 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2387
2388 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2389
2390 /* Set the individual bit to receive frames for this host only. */
2391 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2392 rxcfg |= RL_RXCFG_RX_INDIV;
2393
2394 /* If we want promiscuous mode, set the allframes bit. */
2395 if (ifp->if_flags & IFF_PROMISC)
2396 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2397 else
2398 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2399 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2400
2401 /*
2402 * Set capture broadcast bit to capture broadcast frames.
2403 */
2404 if (ifp->if_flags & IFF_BROADCAST)
2405 rxcfg |= RL_RXCFG_RX_BROAD;
2406 else
2407 rxcfg &= ~RL_RXCFG_RX_BROAD;
2408 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2409
2410 /*
2411 * Program the multicast filter, if necessary.
2412 */
2413 re_setmulti(sc);
2414
2415 #ifdef DEVICE_POLLING
2416 /*
2417 * Disable interrupts if we are polling.
2418 */
2419 if (ifp->if_capenable & IFCAP_POLLING)
2420 CSR_WRITE_2(sc, RL_IMR, 0);
2421 else /* otherwise ... */
2422 #endif
2423
2424 /*
2425 * Enable interrupts.
2426 */
2427 if (sc->rl_testmode)
2428 CSR_WRITE_2(sc, RL_IMR, 0);
2429 else
2430 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2431 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2432
2433 /* Set initial TX threshold */
2434 sc->rl_txthresh = RL_TX_THRESH_INIT;
2435
2436 /* Start RX/TX process. */
2437 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2438 #ifdef notdef
2439 /* Enable receiver and transmitter. */
2440 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2441 #endif
2442
2443 #ifdef RE_TX_MODERATION
2444 /*
2445 * Initialize the timer interrupt register so that
2446 * a timer interrupt will be generated once the timer
2447 * reaches a certain number of ticks. The timer is
2448 * reloaded on each transmit. This gives us TX interrupt
2449 * moderation, which dramatically improves TX frame rate.
2450 */
2451 if (sc->rl_type == RL_8169)
2452 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2453 else
2454 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2455 #endif
2456
2457 /*
2458 * For 8169 gigE NICs, set the max allowed RX packet
2459 * size so we can receive jumbo frames.
2460 */
2461 if (sc->rl_type == RL_8169)
2462 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2463
2464 if (sc->rl_testmode)
2465 return;
2466
2467 mii_mediachg(mii);
2468
2469 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
2470
2471 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2472 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2473
2474 sc->rl_link = 0;
2475 sc->rl_watchdog_timer = 0;
2476 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2477 }
2478
2479 /*
2480 * Set media options.
2481 */
2482 static int
2483 re_ifmedia_upd(ifp)
2484 struct ifnet *ifp;
2485 {
2486 struct rl_softc *sc;
2487 struct mii_data *mii;
2488
2489 sc = ifp->if_softc;
2490 mii = device_get_softc(sc->rl_miibus);
2491 RL_LOCK(sc);
2492 mii_mediachg(mii);
2493 RL_UNLOCK(sc);
2494
2495 return (0);
2496 }
2497
2498 /*
2499 * Report current media status.
2500 */
2501 static void
2502 re_ifmedia_sts(ifp, ifmr)
2503 struct ifnet *ifp;
2504 struct ifmediareq *ifmr;
2505 {
2506 struct rl_softc *sc;
2507 struct mii_data *mii;
2508
2509 sc = ifp->if_softc;
2510 mii = device_get_softc(sc->rl_miibus);
2511
2512 RL_LOCK(sc);
2513 mii_pollstat(mii);
2514 RL_UNLOCK(sc);
2515 ifmr->ifm_active = mii->mii_media_active;
2516 ifmr->ifm_status = mii->mii_media_status;
2517 }
2518
2519 static int
2520 re_ioctl(ifp, command, data)
2521 struct ifnet *ifp;
2522 u_long command;
2523 caddr_t data;
2524 {
2525 struct rl_softc *sc = ifp->if_softc;
2526 struct ifreq *ifr = (struct ifreq *) data;
2527 struct mii_data *mii;
2528 int error = 0;
2529
2530 switch (command) {
2531 case SIOCSIFMTU:
2532 RL_LOCK(sc);
2533 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2534 error = EINVAL;
2535 ifp->if_mtu = ifr->ifr_mtu;
2536 RL_UNLOCK(sc);
2537 break;
2538 case SIOCSIFFLAGS:
2539 RL_LOCK(sc);
2540 if ((ifp->if_flags & IFF_UP) != 0) {
2541 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2542 if (((ifp->if_flags ^ sc->rl_if_flags)
2543 & IFF_PROMISC) != 0)
2544 re_setmulti(sc);
2545 } else
2546 re_init_locked(sc);
2547 } else {
2548 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2549 re_stop(sc);
2550 }
2551 sc->rl_if_flags = ifp->if_flags;
2552 RL_UNLOCK(sc);
2553 break;
2554 case SIOCADDMULTI:
2555 case SIOCDELMULTI:
2556 RL_LOCK(sc);
2557 re_setmulti(sc);
2558 RL_UNLOCK(sc);
2559 break;
2560 case SIOCGIFMEDIA:
2561 case SIOCSIFMEDIA:
2562 mii = device_get_softc(sc->rl_miibus);
2563 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2564 break;
2565 case SIOCSIFCAP:
2566 {
2567 int mask, reinit;
2568
2569 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2570 reinit = 0;
2571 #ifdef DEVICE_POLLING
2572 if (mask & IFCAP_POLLING) {
2573 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2574 error = ether_poll_register(re_poll, ifp);
2575 if (error)
2576 return(error);
2577 RL_LOCK(sc);
2578 /* Disable interrupts */
2579 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2580 ifp->if_capenable |= IFCAP_POLLING;
2581 RL_UNLOCK(sc);
2582 } else {
2583 error = ether_poll_deregister(ifp);
2584 /* Enable interrupts. */
2585 RL_LOCK(sc);
2586 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2587 ifp->if_capenable &= ~IFCAP_POLLING;
2588 RL_UNLOCK(sc);
2589 }
2590 }
2591 #endif /* DEVICE_POLLING */
2592 if (mask & IFCAP_HWCSUM) {
2593 ifp->if_capenable ^= IFCAP_HWCSUM;
2594 if (ifp->if_capenable & IFCAP_TXCSUM)
2595 ifp->if_hwassist = RE_CSUM_FEATURES;
2596 else
2597 ifp->if_hwassist = 0;
2598 reinit = 1;
2599 }
2600 if (mask & IFCAP_VLAN_HWTAGGING) {
2601 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2602 reinit = 1;
2603 }
2604 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
2605 re_init(sc);
2606 #ifdef VLAN_CAPABILITIES
2607 VLAN_CAPABILITIES(ifp);
2608 #endif
2609 }
2610 break;
2611 default:
2612 error = ether_ioctl(ifp, command, data);
2613 break;
2614 }
2615
2616 return (error);
2617 }
2618
2619 static void
2620 re_watchdog(sc)
2621 struct rl_softc *sc;
2622 {
2623
2624 RL_LOCK_ASSERT(sc);
2625
2626 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
2627 return;
2628
2629 device_printf(sc->rl_dev, "watchdog timeout\n");
2630 sc->rl_ifp->if_oerrors++;
2631
2632 re_txeof(sc);
2633 re_rxeof(sc);
2634 re_init_locked(sc);
2635 }
2636
2637 /*
2638 * Stop the adapter and free any mbufs allocated to the
2639 * RX and TX lists.
2640 */
2641 static void
2642 re_stop(sc)
2643 struct rl_softc *sc;
2644 {
2645 register int i;
2646 struct ifnet *ifp;
2647
2648 RL_LOCK_ASSERT(sc);
2649
2650 ifp = sc->rl_ifp;
2651
2652 sc->rl_watchdog_timer = 0;
2653 callout_stop(&sc->rl_stat_callout);
2654 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2655
2656 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2657 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2658 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
2659
2660 if (sc->rl_head != NULL) {
2661 m_freem(sc->rl_head);
2662 sc->rl_head = sc->rl_tail = NULL;
2663 }
2664
2665 /* Free the TX list buffers. */
2666
2667 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2668 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2669 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2670 sc->rl_ldata.rl_tx_dmamap[i]);
2671 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2672 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2673 }
2674 }
2675
2676 /* Free the RX list buffers. */
2677
2678 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2679 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2680 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2681 sc->rl_ldata.rl_rx_dmamap[i]);
2682 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2683 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2684 }
2685 }
2686 }
2687
2688 /*
2689 * Device suspend routine. Stop the interface and save some PCI
2690 * settings in case the BIOS doesn't restore them properly on
2691 * resume.
2692 */
2693 static int
2694 re_suspend(dev)
2695 device_t dev;
2696 {
2697 struct rl_softc *sc;
2698
2699 sc = device_get_softc(dev);
2700
2701 RL_LOCK(sc);
2702 re_stop(sc);
2703 sc->suspended = 1;
2704 RL_UNLOCK(sc);
2705
2706 return (0);
2707 }
2708
2709 /*
2710 * Device resume routine. Restore some PCI settings in case the BIOS
2711 * doesn't, re-enable busmastering, and restart the interface if
2712 * appropriate.
2713 */
2714 static int
2715 re_resume(dev)
2716 device_t dev;
2717 {
2718 struct rl_softc *sc;
2719 struct ifnet *ifp;
2720
2721 sc = device_get_softc(dev);
2722
2723 RL_LOCK(sc);
2724
2725 ifp = sc->rl_ifp;
2726
2727 /* reinitialize interface if necessary */
2728 if (ifp->if_flags & IFF_UP)
2729 re_init_locked(sc);
2730
2731 sc->suspended = 0;
2732 RL_UNLOCK(sc);
2733
2734 return (0);
2735 }
2736
2737 /*
2738 * Stop all chip I/O so that the kernel's probe routines don't
2739 * get confused by errant DMAs when rebooting.
2740 */
2741 static void
2742 re_shutdown(dev)
2743 device_t dev;
2744 {
2745 struct rl_softc *sc;
2746
2747 sc = device_get_softc(dev);
2748
2749 RL_LOCK(sc);
2750 re_stop(sc);
2751 /*
2752 * Mark interface as down since otherwise we will panic if
2753 * interrupt comes in later on, which can happen in some
2754 * cases.
2755 */
2756 sc->rl_ifp->if_flags &= ~IFF_UP;
2757 RL_UNLOCK(sc);
2758 }
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