FreeBSD/Linux Kernel Cross Reference
sys/dev/re/if_re.c
1 /*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
57 * any byte boundary.
58 *
59 * o 64-bit DMA
60 *
61 * o TCP/IP checksum offload for both RX and TX
62 *
63 * o High and normal priority transmit DMA rings
64 *
65 * o VLAN tag insertion and extraction
66 *
67 * o TCP large send (segmentation offload)
68 *
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
72 * chips.
73 *
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
77 *
78 * o 1000Mbps mode
79 *
80 * o Jumbo frames
81 *
82 * o GMII and TBI ports/registers for interfacing with copper
83 * or fiber PHYs
84 *
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
87 *
88 * o Slight differences in register layout from the 8139C+
89 *
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94 * copper gigE PHY.
95 *
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101 *
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
109 */
110
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/taskqueue.h>
127
128 #include <net/if.h>
129 #include <net/if_arp.h>
130 #include <net/ethernet.h>
131 #include <net/if_dl.h>
132 #include <net/if_media.h>
133 #include <net/if_types.h>
134 #include <net/if_vlan_var.h>
135
136 #include <net/bpf.h>
137
138 #include <machine/bus.h>
139 #include <machine/resource.h>
140 #include <sys/bus.h>
141 #include <sys/rman.h>
142
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
145
146 #include <dev/pci/pcireg.h>
147 #include <dev/pci/pcivar.h>
148
149 #include <pci/if_rlreg.h>
150
151 MODULE_DEPEND(re, pci, 1, 1, 1);
152 MODULE_DEPEND(re, ether, 1, 1, 1);
153 MODULE_DEPEND(re, miibus, 1, 1, 1);
154
155 /* "device miibus" required. See GENERIC if you get errors here. */
156 #include "miibus_if.h"
157
158 /* Tunables. */
159 static int msi_disable = 0;
160 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
161 static int prefer_iomap = 0;
162 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
163
164 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
165
166 /*
167 * Various supported device vendors/types and their names.
168 */
169 static struct rl_type re_devs[] = {
170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
172 { RT_VENDORID, RT_DEVICEID_8139, 0,
173 "RealTek 8139C+ 10/100BaseTX" },
174 { RT_VENDORID, RT_DEVICEID_8101E, 0,
175 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" },
176 { RT_VENDORID, RT_DEVICEID_8168, 0,
177 "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/"
178 "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, 0,
180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
187 { USR_VENDORID, USR_DEVICEID_997902, 0,
188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
189 };
190
191 static struct rl_hwrev re_hwrevs[] = {
192 { RL_HWREV_8139, RL_8139, "" },
193 { RL_HWREV_8139A, RL_8139, "A" },
194 { RL_HWREV_8139AG, RL_8139, "A-G" },
195 { RL_HWREV_8139B, RL_8139, "B" },
196 { RL_HWREV_8130, RL_8139, "8130" },
197 { RL_HWREV_8139C, RL_8139, "C" },
198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
201 { RL_HWREV_8169, RL_8169, "8169"},
202 { RL_HWREV_8169S, RL_8169, "8169S"},
203 { RL_HWREV_8110S, RL_8169, "8110S"},
204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"},
205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"},
206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"},
207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"},
208 { RL_HWREV_8100, RL_8139, "8100"},
209 { RL_HWREV_8101, RL_8139, "8101"},
210 { RL_HWREV_8100E, RL_8169, "8100E"},
211 { RL_HWREV_8101E, RL_8169, "8101E"},
212 { RL_HWREV_8102E, RL_8169, "8102E"},
213 { RL_HWREV_8102EL, RL_8169, "8102EL"},
214 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
215 { RL_HWREV_8168_SPIN3, RL_8169, "8168"},
216 { RL_HWREV_8168C, RL_8169, "8168C/8111C"},
217 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
218 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
219 { RL_HWREV_8168D, RL_8169, "8168D/8111D"},
220 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"},
221 { 0, 0, NULL }
222 };
223
224 static int re_probe (device_t);
225 static int re_attach (device_t);
226 static int re_detach (device_t);
227
228 static int re_encap (struct rl_softc *, struct mbuf **);
229
230 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
231 static int re_allocmem (device_t, struct rl_softc *);
232 static __inline void re_discard_rxbuf
233 (struct rl_softc *, int);
234 static int re_newbuf (struct rl_softc *, int);
235 static int re_rx_list_init (struct rl_softc *);
236 static int re_tx_list_init (struct rl_softc *);
237 #ifdef RE_FIXUP_RX
238 static __inline void re_fixup_rx
239 (struct mbuf *);
240 #endif
241 static int re_rxeof (struct rl_softc *);
242 static void re_txeof (struct rl_softc *);
243 #ifdef DEVICE_POLLING
244 static void re_poll (struct ifnet *, enum poll_cmd, int);
245 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
246 #endif
247 static int re_intr (void *);
248 static void re_tick (void *);
249 static void re_tx_task (void *, int);
250 static void re_int_task (void *, int);
251 static void re_start (struct ifnet *);
252 static int re_ioctl (struct ifnet *, u_long, caddr_t);
253 static void re_init (void *);
254 static void re_init_locked (struct rl_softc *);
255 static void re_stop (struct rl_softc *);
256 static void re_watchdog (struct rl_softc *);
257 static int re_suspend (device_t);
258 static int re_resume (device_t);
259 static int re_shutdown (device_t);
260 static int re_ifmedia_upd (struct ifnet *);
261 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
262
263 static void re_eeprom_putbyte (struct rl_softc *, int);
264 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
265 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
266 static int re_gmii_readreg (device_t, int, int);
267 static int re_gmii_writereg (device_t, int, int, int);
268
269 static int re_miibus_readreg (device_t, int, int);
270 static int re_miibus_writereg (device_t, int, int, int);
271 static void re_miibus_statchg (device_t);
272
273 static void re_set_rxmode (struct rl_softc *);
274 static void re_reset (struct rl_softc *);
275 static void re_setwol (struct rl_softc *);
276 static void re_clrwol (struct rl_softc *);
277
278 #ifdef RE_DIAG
279 static int re_diag (struct rl_softc *);
280 #endif
281
282 static device_method_t re_methods[] = {
283 /* Device interface */
284 DEVMETHOD(device_probe, re_probe),
285 DEVMETHOD(device_attach, re_attach),
286 DEVMETHOD(device_detach, re_detach),
287 DEVMETHOD(device_suspend, re_suspend),
288 DEVMETHOD(device_resume, re_resume),
289 DEVMETHOD(device_shutdown, re_shutdown),
290
291 /* bus interface */
292 DEVMETHOD(bus_print_child, bus_generic_print_child),
293 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
294
295 /* MII interface */
296 DEVMETHOD(miibus_readreg, re_miibus_readreg),
297 DEVMETHOD(miibus_writereg, re_miibus_writereg),
298 DEVMETHOD(miibus_statchg, re_miibus_statchg),
299
300 { 0, 0 }
301 };
302
303 static driver_t re_driver = {
304 "re",
305 re_methods,
306 sizeof(struct rl_softc)
307 };
308
309 static devclass_t re_devclass;
310
311 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
312 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
313 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
314
315 #define EE_SET(x) \
316 CSR_WRITE_1(sc, RL_EECMD, \
317 CSR_READ_1(sc, RL_EECMD) | x)
318
319 #define EE_CLR(x) \
320 CSR_WRITE_1(sc, RL_EECMD, \
321 CSR_READ_1(sc, RL_EECMD) & ~x)
322
323 /*
324 * Send a read command and address to the EEPROM, check for ACK.
325 */
326 static void
327 re_eeprom_putbyte(struct rl_softc *sc, int addr)
328 {
329 int d, i;
330
331 d = addr | (RL_9346_READ << sc->rl_eewidth);
332
333 /*
334 * Feed in each bit and strobe the clock.
335 */
336
337 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
338 if (d & i) {
339 EE_SET(RL_EE_DATAIN);
340 } else {
341 EE_CLR(RL_EE_DATAIN);
342 }
343 DELAY(100);
344 EE_SET(RL_EE_CLK);
345 DELAY(150);
346 EE_CLR(RL_EE_CLK);
347 DELAY(100);
348 }
349 }
350
351 /*
352 * Read a word of data stored in the EEPROM at address 'addr.'
353 */
354 static void
355 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
356 {
357 int i;
358 u_int16_t word = 0;
359
360 /*
361 * Send address of word we want to read.
362 */
363 re_eeprom_putbyte(sc, addr);
364
365 /*
366 * Start reading bits from EEPROM.
367 */
368 for (i = 0x8000; i; i >>= 1) {
369 EE_SET(RL_EE_CLK);
370 DELAY(100);
371 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
372 word |= i;
373 EE_CLR(RL_EE_CLK);
374 DELAY(100);
375 }
376
377 *dest = word;
378 }
379
380 /*
381 * Read a sequence of words from the EEPROM.
382 */
383 static void
384 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
385 {
386 int i;
387 u_int16_t word = 0, *ptr;
388
389 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
390
391 DELAY(100);
392
393 for (i = 0; i < cnt; i++) {
394 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
395 re_eeprom_getword(sc, off + i, &word);
396 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
397 ptr = (u_int16_t *)(dest + (i * 2));
398 *ptr = word;
399 }
400
401 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
402 }
403
404 static int
405 re_gmii_readreg(device_t dev, int phy, int reg)
406 {
407 struct rl_softc *sc;
408 u_int32_t rval;
409 int i;
410
411 if (phy != 1)
412 return (0);
413
414 sc = device_get_softc(dev);
415
416 /* Let the rgephy driver read the GMEDIASTAT register */
417
418 if (reg == RL_GMEDIASTAT) {
419 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
420 return (rval);
421 }
422
423 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
424 DELAY(1000);
425
426 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
427 rval = CSR_READ_4(sc, RL_PHYAR);
428 if (rval & RL_PHYAR_BUSY)
429 break;
430 DELAY(100);
431 }
432
433 if (i == RL_PHY_TIMEOUT) {
434 device_printf(sc->rl_dev, "PHY read failed\n");
435 return (0);
436 }
437
438 return (rval & RL_PHYAR_PHYDATA);
439 }
440
441 static int
442 re_gmii_writereg(device_t dev, int phy, int reg, int data)
443 {
444 struct rl_softc *sc;
445 u_int32_t rval;
446 int i;
447
448 sc = device_get_softc(dev);
449
450 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
451 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
452 DELAY(1000);
453
454 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
455 rval = CSR_READ_4(sc, RL_PHYAR);
456 if (!(rval & RL_PHYAR_BUSY))
457 break;
458 DELAY(100);
459 }
460
461 if (i == RL_PHY_TIMEOUT) {
462 device_printf(sc->rl_dev, "PHY write failed\n");
463 return (0);
464 }
465
466 return (0);
467 }
468
469 static int
470 re_miibus_readreg(device_t dev, int phy, int reg)
471 {
472 struct rl_softc *sc;
473 u_int16_t rval = 0;
474 u_int16_t re8139_reg = 0;
475
476 sc = device_get_softc(dev);
477
478 if (sc->rl_type == RL_8169) {
479 rval = re_gmii_readreg(dev, phy, reg);
480 return (rval);
481 }
482
483 /* Pretend the internal PHY is only at address 0 */
484 if (phy) {
485 return (0);
486 }
487 switch (reg) {
488 case MII_BMCR:
489 re8139_reg = RL_BMCR;
490 break;
491 case MII_BMSR:
492 re8139_reg = RL_BMSR;
493 break;
494 case MII_ANAR:
495 re8139_reg = RL_ANAR;
496 break;
497 case MII_ANER:
498 re8139_reg = RL_ANER;
499 break;
500 case MII_ANLPAR:
501 re8139_reg = RL_LPAR;
502 break;
503 case MII_PHYIDR1:
504 case MII_PHYIDR2:
505 return (0);
506 /*
507 * Allow the rlphy driver to read the media status
508 * register. If we have a link partner which does not
509 * support NWAY, this is the register which will tell
510 * us the results of parallel detection.
511 */
512 case RL_MEDIASTAT:
513 rval = CSR_READ_1(sc, RL_MEDIASTAT);
514 return (rval);
515 default:
516 device_printf(sc->rl_dev, "bad phy register\n");
517 return (0);
518 }
519 rval = CSR_READ_2(sc, re8139_reg);
520 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
521 /* 8139C+ has different bit layout. */
522 rval &= ~(BMCR_LOOP | BMCR_ISO);
523 }
524 return (rval);
525 }
526
527 static int
528 re_miibus_writereg(device_t dev, int phy, int reg, int data)
529 {
530 struct rl_softc *sc;
531 u_int16_t re8139_reg = 0;
532 int rval = 0;
533
534 sc = device_get_softc(dev);
535
536 if (sc->rl_type == RL_8169) {
537 rval = re_gmii_writereg(dev, phy, reg, data);
538 return (rval);
539 }
540
541 /* Pretend the internal PHY is only at address 0 */
542 if (phy)
543 return (0);
544
545 switch (reg) {
546 case MII_BMCR:
547 re8139_reg = RL_BMCR;
548 if (sc->rl_type == RL_8139CPLUS) {
549 /* 8139C+ has different bit layout. */
550 data &= ~(BMCR_LOOP | BMCR_ISO);
551 }
552 break;
553 case MII_BMSR:
554 re8139_reg = RL_BMSR;
555 break;
556 case MII_ANAR:
557 re8139_reg = RL_ANAR;
558 break;
559 case MII_ANER:
560 re8139_reg = RL_ANER;
561 break;
562 case MII_ANLPAR:
563 re8139_reg = RL_LPAR;
564 break;
565 case MII_PHYIDR1:
566 case MII_PHYIDR2:
567 return (0);
568 break;
569 default:
570 device_printf(sc->rl_dev, "bad phy register\n");
571 return (0);
572 }
573 CSR_WRITE_2(sc, re8139_reg, data);
574 return (0);
575 }
576
577 static void
578 re_miibus_statchg(device_t dev)
579 {
580 struct rl_softc *sc;
581 struct ifnet *ifp;
582 struct mii_data *mii;
583
584 sc = device_get_softc(dev);
585 mii = device_get_softc(sc->rl_miibus);
586 ifp = sc->rl_ifp;
587 if (mii == NULL || ifp == NULL ||
588 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
589 return;
590
591 sc->rl_flags &= ~RL_FLAG_LINK;
592 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
593 (IFM_ACTIVE | IFM_AVALID)) {
594 switch (IFM_SUBTYPE(mii->mii_media_active)) {
595 case IFM_10_T:
596 case IFM_100_TX:
597 sc->rl_flags |= RL_FLAG_LINK;
598 break;
599 case IFM_1000_T:
600 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
601 break;
602 sc->rl_flags |= RL_FLAG_LINK;
603 break;
604 default:
605 break;
606 }
607 }
608 /*
609 * RealTek controllers does not provide any interface to
610 * Tx/Rx MACs for resolved speed, duplex and flow-control
611 * parameters.
612 */
613 }
614
615 /*
616 * Set the RX configuration and 64-bit multicast hash filter.
617 */
618 static void
619 re_set_rxmode(struct rl_softc *sc)
620 {
621 struct ifnet *ifp;
622 struct ifmultiaddr *ifma;
623 uint32_t hashes[2] = { 0, 0 };
624 uint32_t h, rxfilt;
625
626 RL_LOCK_ASSERT(sc);
627
628 ifp = sc->rl_ifp;
629
630 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
631
632 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
633 if (ifp->if_flags & IFF_PROMISC)
634 rxfilt |= RL_RXCFG_RX_ALLPHYS;
635 /*
636 * Unlike other hardwares, we have to explicitly set
637 * RL_RXCFG_RX_MULTI to receive multicast frames in
638 * promiscuous mode.
639 */
640 rxfilt |= RL_RXCFG_RX_MULTI;
641 hashes[0] = hashes[1] = 0xffffffff;
642 goto done;
643 }
644
645 IF_ADDR_LOCK(ifp);
646 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
647 if (ifma->ifma_addr->sa_family != AF_LINK)
648 continue;
649 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
650 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
651 if (h < 32)
652 hashes[0] |= (1 << h);
653 else
654 hashes[1] |= (1 << (h - 32));
655 }
656 IF_ADDR_UNLOCK(ifp);
657
658 if (hashes[0] != 0 || hashes[1] != 0) {
659 /*
660 * For some unfathomable reason, RealTek decided to
661 * reverse the order of the multicast hash registers
662 * in the PCI Express parts. This means we have to
663 * write the hash pattern in reverse order for those
664 * devices.
665 */
666 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
667 h = bswap32(hashes[0]);
668 hashes[0] = bswap32(hashes[1]);
669 hashes[1] = h;
670 }
671 rxfilt |= RL_RXCFG_RX_MULTI;
672 }
673
674 done:
675 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
676 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
678 }
679
680 static void
681 re_reset(struct rl_softc *sc)
682 {
683 int i;
684
685 RL_LOCK_ASSERT(sc);
686
687 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
688
689 for (i = 0; i < RL_TIMEOUT; i++) {
690 DELAY(10);
691 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
692 break;
693 }
694 if (i == RL_TIMEOUT)
695 device_printf(sc->rl_dev, "reset never completed!\n");
696
697 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
698 CSR_WRITE_1(sc, 0x82, 1);
699 if (sc->rl_hwrev == RL_HWREV_8169S)
700 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
701 }
702
703 #ifdef RE_DIAG
704
705 /*
706 * The following routine is designed to test for a defect on some
707 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
708 * lines connected to the bus, however for a 32-bit only card, they
709 * should be pulled high. The result of this defect is that the
710 * NIC will not work right if you plug it into a 64-bit slot: DMA
711 * operations will be done with 64-bit transfers, which will fail
712 * because the 64-bit data lines aren't connected.
713 *
714 * There's no way to work around this (short of talking a soldering
715 * iron to the board), however we can detect it. The method we use
716 * here is to put the NIC into digital loopback mode, set the receiver
717 * to promiscuous mode, and then try to send a frame. We then compare
718 * the frame data we sent to what was received. If the data matches,
719 * then the NIC is working correctly, otherwise we know the user has
720 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
721 * slot. In the latter case, there's no way the NIC can work correctly,
722 * so we print out a message on the console and abort the device attach.
723 */
724
725 static int
726 re_diag(struct rl_softc *sc)
727 {
728 struct ifnet *ifp = sc->rl_ifp;
729 struct mbuf *m0;
730 struct ether_header *eh;
731 struct rl_desc *cur_rx;
732 u_int16_t status;
733 u_int32_t rxstat;
734 int total_len, i, error = 0, phyaddr;
735 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
736 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
737
738 /* Allocate a single mbuf */
739 MGETHDR(m0, M_DONTWAIT, MT_DATA);
740 if (m0 == NULL)
741 return (ENOBUFS);
742
743 RL_LOCK(sc);
744
745 /*
746 * Initialize the NIC in test mode. This sets the chip up
747 * so that it can send and receive frames, but performs the
748 * following special functions:
749 * - Puts receiver in promiscuous mode
750 * - Enables digital loopback mode
751 * - Leaves interrupts turned off
752 */
753
754 ifp->if_flags |= IFF_PROMISC;
755 sc->rl_testmode = 1;
756 re_init_locked(sc);
757 sc->rl_flags |= RL_FLAG_LINK;
758 if (sc->rl_type == RL_8169)
759 phyaddr = 1;
760 else
761 phyaddr = 0;
762
763 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
764 for (i = 0; i < RL_TIMEOUT; i++) {
765 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
766 if (!(status & BMCR_RESET))
767 break;
768 }
769
770 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
771 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
772
773 DELAY(100000);
774
775 /* Put some data in the mbuf */
776
777 eh = mtod(m0, struct ether_header *);
778 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
779 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
780 eh->ether_type = htons(ETHERTYPE_IP);
781 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
782
783 /*
784 * Queue the packet, start transmission.
785 * Note: IF_HANDOFF() ultimately calls re_start() for us.
786 */
787
788 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
789 RL_UNLOCK(sc);
790 /* XXX: re_diag must not be called when in ALTQ mode */
791 IF_HANDOFF(&ifp->if_snd, m0, ifp);
792 RL_LOCK(sc);
793 m0 = NULL;
794
795 /* Wait for it to propagate through the chip */
796
797 DELAY(100000);
798 for (i = 0; i < RL_TIMEOUT; i++) {
799 status = CSR_READ_2(sc, RL_ISR);
800 CSR_WRITE_2(sc, RL_ISR, status);
801 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
802 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
803 break;
804 DELAY(10);
805 }
806
807 if (i == RL_TIMEOUT) {
808 device_printf(sc->rl_dev,
809 "diagnostic failed, failed to receive packet in"
810 " loopback mode\n");
811 error = EIO;
812 goto done;
813 }
814
815 /*
816 * The packet should have been dumped into the first
817 * entry in the RX DMA ring. Grab it from there.
818 */
819
820 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
821 sc->rl_ldata.rl_rx_list_map,
822 BUS_DMASYNC_POSTREAD);
823 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
824 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
825 BUS_DMASYNC_POSTREAD);
826 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
827 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
828
829 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
830 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
831 eh = mtod(m0, struct ether_header *);
832
833 cur_rx = &sc->rl_ldata.rl_rx_list[0];
834 total_len = RL_RXBYTES(cur_rx);
835 rxstat = le32toh(cur_rx->rl_cmdstat);
836
837 if (total_len != ETHER_MIN_LEN) {
838 device_printf(sc->rl_dev,
839 "diagnostic failed, received short packet\n");
840 error = EIO;
841 goto done;
842 }
843
844 /* Test that the received packet data matches what we sent. */
845
846 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
847 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
848 ntohs(eh->ether_type) != ETHERTYPE_IP) {
849 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
850 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
851 dst, ":", src, ":", ETHERTYPE_IP);
852 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
853 eh->ether_dhost, ":", eh->ether_shost, ":",
854 ntohs(eh->ether_type));
855 device_printf(sc->rl_dev, "You may have a defective 32-bit "
856 "NIC plugged into a 64-bit PCI slot.\n");
857 device_printf(sc->rl_dev, "Please re-install the NIC in a "
858 "32-bit slot for proper operation.\n");
859 device_printf(sc->rl_dev, "Read the re(4) man page for more "
860 "details.\n");
861 error = EIO;
862 }
863
864 done:
865 /* Turn interface off, release resources */
866
867 sc->rl_testmode = 0;
868 sc->rl_flags &= ~RL_FLAG_LINK;
869 ifp->if_flags &= ~IFF_PROMISC;
870 re_stop(sc);
871 if (m0 != NULL)
872 m_freem(m0);
873
874 RL_UNLOCK(sc);
875
876 return (error);
877 }
878
879 #endif
880
881 /*
882 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
883 * IDs against our list and return a device name if we find a match.
884 */
885 static int
886 re_probe(device_t dev)
887 {
888 struct rl_type *t;
889 uint16_t devid, vendor;
890 uint16_t revid, sdevid;
891 int i;
892
893 vendor = pci_get_vendor(dev);
894 devid = pci_get_device(dev);
895 revid = pci_get_revid(dev);
896 sdevid = pci_get_subdevice(dev);
897
898 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
899 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
900 /*
901 * Only attach to rev. 3 of the Linksys EG1032 adapter.
902 * Rev. 2 is supported by sk(4).
903 */
904 return (ENXIO);
905 }
906 }
907
908 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
909 if (revid != 0x20) {
910 /* 8139, let rl(4) take care of this device. */
911 return (ENXIO);
912 }
913 }
914
915 t = re_devs;
916 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
917 if (vendor == t->rl_vid && devid == t->rl_did) {
918 device_set_desc(dev, t->rl_name);
919 return (BUS_PROBE_DEFAULT);
920 }
921 }
922
923 return (ENXIO);
924 }
925
926 /*
927 * Map a single buffer address.
928 */
929
930 static void
931 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
932 {
933 bus_addr_t *addr;
934
935 if (error)
936 return;
937
938 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
939 addr = arg;
940 *addr = segs->ds_addr;
941 }
942
943 static int
944 re_allocmem(device_t dev, struct rl_softc *sc)
945 {
946 bus_size_t rx_list_size, tx_list_size;
947 int error;
948 int i;
949
950 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
951 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
952
953 /*
954 * Allocate the parent bus DMA tag appropriate for PCI.
955 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
956 * register should be set. However some RealTek chips are known
957 * to be buggy on DAC handling, therefore disable DAC by limiting
958 * DMA address space to 32bit. PCIe variants of RealTek chips
959 * may not have the limitation but I took safer path.
960 */
961 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
962 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
963 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
964 NULL, NULL, &sc->rl_parent_tag);
965 if (error) {
966 device_printf(dev, "could not allocate parent DMA tag\n");
967 return (error);
968 }
969
970 /*
971 * Allocate map for TX mbufs.
972 */
973 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
974 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
975 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
976 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
977 if (error) {
978 device_printf(dev, "could not allocate TX DMA tag\n");
979 return (error);
980 }
981
982 /*
983 * Allocate map for RX mbufs.
984 */
985
986 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
988 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
989 if (error) {
990 device_printf(dev, "could not allocate RX DMA tag\n");
991 return (error);
992 }
993
994 /*
995 * Allocate map for TX descriptor list.
996 */
997 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
998 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
999 NULL, tx_list_size, 1, tx_list_size, 0,
1000 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1001 if (error) {
1002 device_printf(dev, "could not allocate TX DMA ring tag\n");
1003 return (error);
1004 }
1005
1006 /* Allocate DMA'able memory for the TX ring */
1007
1008 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1009 (void **)&sc->rl_ldata.rl_tx_list,
1010 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1011 &sc->rl_ldata.rl_tx_list_map);
1012 if (error) {
1013 device_printf(dev, "could not allocate TX DMA ring\n");
1014 return (error);
1015 }
1016
1017 /* Load the map for the TX ring. */
1018
1019 sc->rl_ldata.rl_tx_list_addr = 0;
1020 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1021 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1022 tx_list_size, re_dma_map_addr,
1023 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1024 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1025 device_printf(dev, "could not load TX DMA ring\n");
1026 return (ENOMEM);
1027 }
1028
1029 /* Create DMA maps for TX buffers */
1030
1031 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1032 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1033 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1034 if (error) {
1035 device_printf(dev, "could not create DMA map for TX\n");
1036 return (error);
1037 }
1038 }
1039
1040 /*
1041 * Allocate map for RX descriptor list.
1042 */
1043 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1044 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1045 NULL, rx_list_size, 1, rx_list_size, 0,
1046 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1047 if (error) {
1048 device_printf(dev, "could not create RX DMA ring tag\n");
1049 return (error);
1050 }
1051
1052 /* Allocate DMA'able memory for the RX ring */
1053
1054 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1055 (void **)&sc->rl_ldata.rl_rx_list,
1056 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1057 &sc->rl_ldata.rl_rx_list_map);
1058 if (error) {
1059 device_printf(dev, "could not allocate RX DMA ring\n");
1060 return (error);
1061 }
1062
1063 /* Load the map for the RX ring. */
1064
1065 sc->rl_ldata.rl_rx_list_addr = 0;
1066 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1067 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1068 rx_list_size, re_dma_map_addr,
1069 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1070 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1071 device_printf(dev, "could not load RX DMA ring\n");
1072 return (ENOMEM);
1073 }
1074
1075 /* Create DMA maps for RX buffers */
1076
1077 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1078 &sc->rl_ldata.rl_rx_sparemap);
1079 if (error) {
1080 device_printf(dev, "could not create spare DMA map for RX\n");
1081 return (error);
1082 }
1083 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1085 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1086 if (error) {
1087 device_printf(dev, "could not create DMA map for RX\n");
1088 return (error);
1089 }
1090 }
1091
1092 return (0);
1093 }
1094
1095 /*
1096 * Attach the interface. Allocate softc structures, do ifmedia
1097 * setup and ethernet/BPF attach.
1098 */
1099 static int
1100 re_attach(device_t dev)
1101 {
1102 u_char eaddr[ETHER_ADDR_LEN];
1103 u_int16_t as[ETHER_ADDR_LEN / 2];
1104 struct rl_softc *sc;
1105 struct ifnet *ifp;
1106 struct rl_hwrev *hw_rev;
1107 int hwrev;
1108 u_int16_t devid, re_did = 0;
1109 int error = 0, rid, i;
1110 int msic, reg;
1111 uint8_t cfg;
1112
1113 sc = device_get_softc(dev);
1114 sc->rl_dev = dev;
1115
1116 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1117 MTX_DEF);
1118 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1119
1120 /*
1121 * Map control/status registers.
1122 */
1123 pci_enable_busmaster(dev);
1124
1125 devid = pci_get_device(dev);
1126 /*
1127 * Prefer memory space register mapping over IO space.
1128 * Because RTL8169SC does not seem to work when memory mapping
1129 * is used always activate io mapping.
1130 */
1131 if (devid == RT_DEVICEID_8169SC)
1132 prefer_iomap = 1;
1133 if (prefer_iomap == 0) {
1134 sc->rl_res_id = PCIR_BAR(1);
1135 sc->rl_res_type = SYS_RES_MEMORY;
1136 /* RTL8168/8101E seems to use different BARs. */
1137 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1138 sc->rl_res_id = PCIR_BAR(2);
1139 } else {
1140 sc->rl_res_id = PCIR_BAR(0);
1141 sc->rl_res_type = SYS_RES_IOPORT;
1142 }
1143 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1144 &sc->rl_res_id, RF_ACTIVE);
1145 if (sc->rl_res == NULL && prefer_iomap == 0) {
1146 sc->rl_res_id = PCIR_BAR(0);
1147 sc->rl_res_type = SYS_RES_IOPORT;
1148 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1149 &sc->rl_res_id, RF_ACTIVE);
1150 }
1151 if (sc->rl_res == NULL) {
1152 device_printf(dev, "couldn't map ports/memory\n");
1153 error = ENXIO;
1154 goto fail;
1155 }
1156
1157 sc->rl_btag = rman_get_bustag(sc->rl_res);
1158 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1159
1160 msic = 0;
1161 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
1162 sc->rl_flags |= RL_FLAG_PCIE;
1163 msic = pci_msi_count(dev);
1164 if (bootverbose)
1165 device_printf(dev, "MSI count : %d\n", msic);
1166 }
1167 if (msic > 0 && msi_disable == 0) {
1168 msic = 1;
1169 if (pci_alloc_msi(dev, &msic) == 0) {
1170 if (msic == RL_MSI_MESSAGES) {
1171 device_printf(dev, "Using %d MSI messages\n",
1172 msic);
1173 sc->rl_flags |= RL_FLAG_MSI;
1174 /* Explicitly set MSI enable bit. */
1175 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1176 cfg = CSR_READ_1(sc, RL_CFG2);
1177 cfg |= RL_CFG2_MSI;
1178 CSR_WRITE_1(sc, RL_CFG2, cfg);
1179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1180 } else
1181 pci_release_msi(dev);
1182 }
1183 }
1184
1185 /* Allocate interrupt */
1186 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1187 rid = 0;
1188 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1189 RF_SHAREABLE | RF_ACTIVE);
1190 if (sc->rl_irq[0] == NULL) {
1191 device_printf(dev, "couldn't allocate IRQ resources\n");
1192 error = ENXIO;
1193 goto fail;
1194 }
1195 } else {
1196 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1197 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1198 SYS_RES_IRQ, &rid, RF_ACTIVE);
1199 if (sc->rl_irq[i] == NULL) {
1200 device_printf(dev,
1201 "couldn't llocate IRQ resources for "
1202 "message %d\n", rid);
1203 error = ENXIO;
1204 goto fail;
1205 }
1206 }
1207 }
1208
1209 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1210 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1211 cfg = CSR_READ_1(sc, RL_CFG2);
1212 if ((cfg & RL_CFG2_MSI) != 0) {
1213 device_printf(dev, "turning off MSI enable bit.\n");
1214 cfg &= ~RL_CFG2_MSI;
1215 CSR_WRITE_1(sc, RL_CFG2, cfg);
1216 }
1217 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1218 }
1219
1220 /* Reset the adapter. */
1221 RL_LOCK(sc);
1222 re_reset(sc);
1223 RL_UNLOCK(sc);
1224
1225 hw_rev = re_hwrevs;
1226 hwrev = CSR_READ_4(sc, RL_TXCFG);
1227 switch (hwrev & 0x70000000) {
1228 case 0x00000000:
1229 case 0x10000000:
1230 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1231 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1232 break;
1233 default:
1234 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1235 hwrev &= RL_TXCFG_HWREV;
1236 break;
1237 }
1238 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1239 while (hw_rev->rl_desc != NULL) {
1240 if (hw_rev->rl_rev == hwrev) {
1241 sc->rl_type = hw_rev->rl_type;
1242 sc->rl_hwrev = hw_rev->rl_rev;
1243 break;
1244 }
1245 hw_rev++;
1246 }
1247 if (hw_rev->rl_desc == NULL) {
1248 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1249 error = ENXIO;
1250 goto fail;
1251 }
1252
1253 switch (hw_rev->rl_rev) {
1254 case RL_HWREV_8139CPLUS:
1255 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER;
1256 break;
1257 case RL_HWREV_8100E:
1258 case RL_HWREV_8101E:
1259 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
1260 RL_FLAG_FASTETHER;
1261 break;
1262 case RL_HWREV_8102E:
1263 case RL_HWREV_8102EL:
1264 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
1265 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1266 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP;
1267 break;
1268 case RL_HWREV_8168_SPIN1:
1269 case RL_HWREV_8168_SPIN2:
1270 sc->rl_flags |= RL_FLAG_WOLRXENB;
1271 /* FALLTHROUGH */
1272 case RL_HWREV_8168_SPIN3:
1273 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1274 break;
1275 case RL_HWREV_8168C_SPIN2:
1276 sc->rl_flags |= RL_FLAG_MACSLEEP;
1277 /* FALLTHROUGH */
1278 case RL_HWREV_8168C:
1279 if ((hwrev & 0x00700000) == 0x00200000)
1280 sc->rl_flags |= RL_FLAG_MACSLEEP;
1281 /* FALLTHROUGH */
1282 case RL_HWREV_8168CP:
1283 case RL_HWREV_8168D:
1284 case RL_HWREV_8168DP:
1285 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1286 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP;
1287 /*
1288 * These controllers support jumbo frame but it seems
1289 * that enabling it requires touching additional magic
1290 * registers. Depending on MAC revisions some
1291 * controllers need to disable checksum offload. So
1292 * disable jumbo frame until I have better idea what
1293 * it really requires to make it support.
1294 * RTL8168C/CP : supports up to 6KB jumbo frame.
1295 * RTL8111C/CP : supports up to 9KB jumbo frame.
1296 */
1297 sc->rl_flags |= RL_FLAG_NOJUMBO;
1298 break;
1299 case RL_HWREV_8169_8110SB:
1300 case RL_HWREV_8169_8110SBL:
1301 case RL_HWREV_8169_8110SC:
1302 case RL_HWREV_8169_8110SCE:
1303 sc->rl_flags |= RL_FLAG_PHYWAKE;
1304 /* FALLTHROUGH */
1305 case RL_HWREV_8169:
1306 case RL_HWREV_8169S:
1307 case RL_HWREV_8110S:
1308 sc->rl_flags |= RL_FLAG_MACRESET;
1309 break;
1310 default:
1311 break;
1312 }
1313
1314 /* Enable PME. */
1315 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1316 cfg = CSR_READ_1(sc, RL_CFG1);
1317 cfg |= RL_CFG1_PME;
1318 CSR_WRITE_1(sc, RL_CFG1, cfg);
1319 cfg = CSR_READ_1(sc, RL_CFG5);
1320 cfg &= RL_CFG5_PME_STS;
1321 CSR_WRITE_1(sc, RL_CFG5, cfg);
1322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1323
1324 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1325 /*
1326 * XXX Should have a better way to extract station
1327 * address from EEPROM.
1328 */
1329 for (i = 0; i < ETHER_ADDR_LEN; i++)
1330 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1331 } else {
1332 sc->rl_eewidth = RL_9356_ADDR_LEN;
1333 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1334 if (re_did != 0x8129)
1335 sc->rl_eewidth = RL_9346_ADDR_LEN;
1336
1337 /*
1338 * Get station address from the EEPROM.
1339 */
1340 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1341 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1342 as[i] = le16toh(as[i]);
1343 bcopy(as, eaddr, sizeof(eaddr));
1344 }
1345
1346 if (sc->rl_type == RL_8169) {
1347 /* Set RX length mask and number of descriptors. */
1348 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1349 sc->rl_txstart = RL_GTXSTART;
1350 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1351 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1352 } else {
1353 /* Set RX length mask and number of descriptors. */
1354 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1355 sc->rl_txstart = RL_TXSTART;
1356 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1357 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1358 }
1359
1360 error = re_allocmem(dev, sc);
1361 if (error)
1362 goto fail;
1363
1364 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1365 if (ifp == NULL) {
1366 device_printf(dev, "can not if_alloc()\n");
1367 error = ENOSPC;
1368 goto fail;
1369 }
1370
1371 /* Take controller out of deep sleep mode. */
1372 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1373 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1374 CSR_WRITE_1(sc, RL_GPIO,
1375 CSR_READ_1(sc, RL_GPIO) | 0x01);
1376 else
1377 CSR_WRITE_1(sc, RL_GPIO,
1378 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1379 }
1380
1381 /* Take PHY out of power down mode. */
1382 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1383 re_gmii_writereg(dev, 1, 0x1f, 0);
1384 re_gmii_writereg(dev, 1, 0x0e, 0);
1385 }
1386
1387 /* Do MII setup */
1388 if (mii_phy_probe(dev, &sc->rl_miibus,
1389 re_ifmedia_upd, re_ifmedia_sts)) {
1390 device_printf(dev, "MII without any phy!\n");
1391 error = ENXIO;
1392 goto fail;
1393 }
1394
1395 ifp->if_softc = sc;
1396 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1398 ifp->if_ioctl = re_ioctl;
1399 ifp->if_start = re_start;
1400 ifp->if_hwassist = RE_CSUM_FEATURES;
1401 ifp->if_capabilities = IFCAP_HWCSUM;
1402 ifp->if_capenable = ifp->if_capabilities;
1403 ifp->if_init = re_init;
1404 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1405 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1406 IFQ_SET_READY(&ifp->if_snd);
1407
1408 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1409 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1410
1411 /*
1412 * XXX
1413 * Still have no idea how to make TSO work on 8168C, 8168CP,
1414 * 8111C and 8111CP.
1415 */
1416 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
1417 ifp->if_hwassist |= CSUM_TSO;
1418 ifp->if_capabilities |= IFCAP_TSO4;
1419 }
1420
1421 /*
1422 * Call MI attach routine.
1423 */
1424 ether_ifattach(ifp, eaddr);
1425
1426 /* VLAN capability setup */
1427 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1428 if (ifp->if_capabilities & IFCAP_HWCSUM)
1429 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1430 /* Enable WOL if PM is supported. */
1431 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0)
1432 ifp->if_capabilities |= IFCAP_WOL;
1433 ifp->if_capenable = ifp->if_capabilities;
1434 /*
1435 * Don't enable TSO by default. Under certain
1436 * circumtances the controller generated corrupted
1437 * packets in TSO size.
1438 */
1439 ifp->if_hwassist &= ~CSUM_TSO;
1440 ifp->if_capenable &= ~IFCAP_TSO4;
1441 #ifdef DEVICE_POLLING
1442 ifp->if_capabilities |= IFCAP_POLLING;
1443 #endif
1444 /*
1445 * Tell the upper layer(s) we support long frames.
1446 * Must appear after the call to ether_ifattach() because
1447 * ether_ifattach() sets ifi_hdrlen to the default value.
1448 */
1449 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1450
1451 #ifdef RE_DIAG
1452 /*
1453 * Perform hardware diagnostic on the original RTL8169.
1454 * Some 32-bit cards were incorrectly wired and would
1455 * malfunction if plugged into a 64-bit slot.
1456 */
1457
1458 if (hwrev == RL_HWREV_8169) {
1459 error = re_diag(sc);
1460 if (error) {
1461 device_printf(dev,
1462 "attach aborted due to hardware diag failure\n");
1463 ether_ifdetach(ifp);
1464 goto fail;
1465 }
1466 }
1467 #endif
1468
1469 /* Hook interrupt last to avoid having to lock softc */
1470 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1471 error = bus_setup_intr(dev, sc->rl_irq[0],
1472 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1473 &sc->rl_intrhand[0]);
1474 else {
1475 for (i = 0; i < RL_MSI_MESSAGES; i++) {
1476 error = bus_setup_intr(dev, sc->rl_irq[i],
1477 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1478 &sc->rl_intrhand[i]);
1479 if (error != 0)
1480 break;
1481 }
1482 }
1483 if (error) {
1484 device_printf(dev, "couldn't set up irq\n");
1485 ether_ifdetach(ifp);
1486 }
1487
1488 fail:
1489
1490 if (error)
1491 re_detach(dev);
1492
1493 return (error);
1494 }
1495
1496 /*
1497 * Shutdown hardware and free up resources. This can be called any
1498 * time after the mutex has been initialized. It is called in both
1499 * the error case in attach and the normal detach case so it needs
1500 * to be careful about only freeing resources that have actually been
1501 * allocated.
1502 */
1503 static int
1504 re_detach(device_t dev)
1505 {
1506 struct rl_softc *sc;
1507 struct ifnet *ifp;
1508 int i, rid;
1509
1510 sc = device_get_softc(dev);
1511 ifp = sc->rl_ifp;
1512 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1513
1514 /* These should only be active if attach succeeded */
1515 if (device_is_attached(dev)) {
1516 #ifdef DEVICE_POLLING
1517 if (ifp->if_capenable & IFCAP_POLLING)
1518 ether_poll_deregister(ifp);
1519 #endif
1520 RL_LOCK(sc);
1521 #if 0
1522 sc->suspended = 1;
1523 #endif
1524 re_stop(sc);
1525 RL_UNLOCK(sc);
1526 callout_drain(&sc->rl_stat_callout);
1527 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1528 taskqueue_drain(taskqueue_fast, &sc->rl_txtask);
1529 /*
1530 * Force off the IFF_UP flag here, in case someone
1531 * still had a BPF descriptor attached to this
1532 * interface. If they do, ether_ifdetach() will cause
1533 * the BPF code to try and clear the promisc mode
1534 * flag, which will bubble down to re_ioctl(),
1535 * which will try to call re_init() again. This will
1536 * turn the NIC back on and restart the MII ticker,
1537 * which will panic the system when the kernel tries
1538 * to invoke the re_tick() function that isn't there
1539 * anymore.
1540 */
1541 ifp->if_flags &= ~IFF_UP;
1542 ether_ifdetach(ifp);
1543 }
1544 if (sc->rl_miibus)
1545 device_delete_child(dev, sc->rl_miibus);
1546 bus_generic_detach(dev);
1547
1548 /*
1549 * The rest is resource deallocation, so we should already be
1550 * stopped here.
1551 */
1552
1553 for (i = 0; i < RL_MSI_MESSAGES; i++) {
1554 if (sc->rl_intrhand[i] != NULL) {
1555 bus_teardown_intr(dev, sc->rl_irq[i],
1556 sc->rl_intrhand[i]);
1557 sc->rl_intrhand[i] = NULL;
1558 }
1559 }
1560 if (ifp != NULL)
1561 if_free(ifp);
1562 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1563 if (sc->rl_irq[0] != NULL) {
1564 bus_release_resource(dev, SYS_RES_IRQ, 0,
1565 sc->rl_irq[0]);
1566 sc->rl_irq[0] = NULL;
1567 }
1568 } else {
1569 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1570 if (sc->rl_irq[i] != NULL) {
1571 bus_release_resource(dev, SYS_RES_IRQ, rid,
1572 sc->rl_irq[i]);
1573 sc->rl_irq[i] = NULL;
1574 }
1575 }
1576 pci_release_msi(dev);
1577 }
1578 if (sc->rl_res)
1579 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1580 sc->rl_res);
1581
1582 /* Unload and free the RX DMA ring memory and map */
1583
1584 if (sc->rl_ldata.rl_rx_list_tag) {
1585 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1586 sc->rl_ldata.rl_rx_list_map);
1587 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1588 sc->rl_ldata.rl_rx_list,
1589 sc->rl_ldata.rl_rx_list_map);
1590 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1591 }
1592
1593 /* Unload and free the TX DMA ring memory and map */
1594
1595 if (sc->rl_ldata.rl_tx_list_tag) {
1596 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1597 sc->rl_ldata.rl_tx_list_map);
1598 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1599 sc->rl_ldata.rl_tx_list,
1600 sc->rl_ldata.rl_tx_list_map);
1601 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1602 }
1603
1604 /* Destroy all the RX and TX buffer maps */
1605
1606 if (sc->rl_ldata.rl_tx_mtag) {
1607 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1608 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1609 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1610 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1611 }
1612 if (sc->rl_ldata.rl_rx_mtag) {
1613 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++)
1614 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1615 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1616 if (sc->rl_ldata.rl_rx_sparemap)
1617 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1618 sc->rl_ldata.rl_rx_sparemap);
1619 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1620 }
1621
1622 /* Unload and free the stats buffer and map */
1623
1624 if (sc->rl_ldata.rl_stag) {
1625 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1626 sc->rl_ldata.rl_rx_list_map);
1627 bus_dmamem_free(sc->rl_ldata.rl_stag,
1628 sc->rl_ldata.rl_stats,
1629 sc->rl_ldata.rl_smap);
1630 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1631 }
1632
1633 if (sc->rl_parent_tag)
1634 bus_dma_tag_destroy(sc->rl_parent_tag);
1635
1636 mtx_destroy(&sc->rl_mtx);
1637
1638 return (0);
1639 }
1640
1641 static __inline void
1642 re_discard_rxbuf(struct rl_softc *sc, int idx)
1643 {
1644 struct rl_desc *desc;
1645 struct rl_rxdesc *rxd;
1646 uint32_t cmdstat;
1647
1648 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1649 desc = &sc->rl_ldata.rl_rx_list[idx];
1650 desc->rl_vlanctl = 0;
1651 cmdstat = rxd->rx_size;
1652 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1653 cmdstat |= RL_RDESC_CMD_EOR;
1654 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1655 }
1656
1657 static int
1658 re_newbuf(struct rl_softc *sc, int idx)
1659 {
1660 struct mbuf *m;
1661 struct rl_rxdesc *rxd;
1662 bus_dma_segment_t segs[1];
1663 bus_dmamap_t map;
1664 struct rl_desc *desc;
1665 uint32_t cmdstat;
1666 int error, nsegs;
1667
1668 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1669 if (m == NULL)
1670 return (ENOBUFS);
1671
1672 m->m_len = m->m_pkthdr.len = MCLBYTES;
1673 #ifdef RE_FIXUP_RX
1674 /*
1675 * This is part of an evil trick to deal with non-x86 platforms.
1676 * The RealTek chip requires RX buffers to be aligned on 64-bit
1677 * boundaries, but that will hose non-x86 machines. To get around
1678 * this, we leave some empty space at the start of each buffer
1679 * and for non-x86 hosts, we copy the buffer back six bytes
1680 * to achieve word alignment. This is slightly more efficient
1681 * than allocating a new buffer, copying the contents, and
1682 * discarding the old buffer.
1683 */
1684 m_adj(m, RE_ETHER_ALIGN);
1685 #endif
1686 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1687 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1688 if (error != 0) {
1689 m_freem(m);
1690 return (ENOBUFS);
1691 }
1692 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1693
1694 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1695 if (rxd->rx_m != NULL) {
1696 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1697 BUS_DMASYNC_POSTREAD);
1698 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1699 }
1700
1701 rxd->rx_m = m;
1702 map = rxd->rx_dmamap;
1703 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1704 rxd->rx_size = segs[0].ds_len;
1705 sc->rl_ldata.rl_rx_sparemap = map;
1706 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1707 BUS_DMASYNC_PREREAD);
1708
1709 desc = &sc->rl_ldata.rl_rx_list[idx];
1710 desc->rl_vlanctl = 0;
1711 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1712 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1713 cmdstat = segs[0].ds_len;
1714 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1715 cmdstat |= RL_RDESC_CMD_EOR;
1716 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1717
1718 return (0);
1719 }
1720
1721 #ifdef RE_FIXUP_RX
1722 static __inline void
1723 re_fixup_rx(struct mbuf *m)
1724 {
1725 int i;
1726 uint16_t *src, *dst;
1727
1728 src = mtod(m, uint16_t *);
1729 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1730
1731 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1732 *dst++ = *src++;
1733
1734 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1735 }
1736 #endif
1737
1738 static int
1739 re_tx_list_init(struct rl_softc *sc)
1740 {
1741 struct rl_desc *desc;
1742 int i;
1743
1744 RL_LOCK_ASSERT(sc);
1745
1746 bzero(sc->rl_ldata.rl_tx_list,
1747 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
1748 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1749 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
1750 /* Set EOR. */
1751 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
1752 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
1753
1754 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1755 sc->rl_ldata.rl_tx_list_map,
1756 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1757
1758 sc->rl_ldata.rl_tx_prodidx = 0;
1759 sc->rl_ldata.rl_tx_considx = 0;
1760 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
1761
1762 return (0);
1763 }
1764
1765 static int
1766 re_rx_list_init(struct rl_softc *sc)
1767 {
1768 int error, i;
1769
1770 bzero(sc->rl_ldata.rl_rx_list,
1771 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
1772 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1773 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
1774 if ((error = re_newbuf(sc, i)) != 0)
1775 return (error);
1776 }
1777
1778 /* Flush the RX descriptors */
1779
1780 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1781 sc->rl_ldata.rl_rx_list_map,
1782 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1783
1784 sc->rl_ldata.rl_rx_prodidx = 0;
1785 sc->rl_head = sc->rl_tail = NULL;
1786
1787 return (0);
1788 }
1789
1790 /*
1791 * RX handler for C+ and 8169. For the gigE chips, we support
1792 * the reception of jumbo frames that have been fragmented
1793 * across multiple 2K mbuf cluster buffers.
1794 */
1795 static int
1796 re_rxeof(struct rl_softc *sc)
1797 {
1798 struct mbuf *m;
1799 struct ifnet *ifp;
1800 int i, total_len;
1801 struct rl_desc *cur_rx;
1802 u_int32_t rxstat, rxvlan;
1803 int maxpkt = 16;
1804
1805 RL_LOCK_ASSERT(sc);
1806
1807 ifp = sc->rl_ifp;
1808
1809 /* Invalidate the descriptor memory */
1810
1811 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1812 sc->rl_ldata.rl_rx_list_map,
1813 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1814
1815 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
1816 i = RL_RX_DESC_NXT(sc, i)) {
1817 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1818 rxstat = le32toh(cur_rx->rl_cmdstat);
1819 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
1820 break;
1821 total_len = rxstat & sc->rl_rxlenmask;
1822 rxvlan = le32toh(cur_rx->rl_vlanctl);
1823 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
1824
1825 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1826 if (re_newbuf(sc, i) != 0) {
1827 /*
1828 * If this is part of a multi-fragment packet,
1829 * discard all the pieces.
1830 */
1831 if (sc->rl_head != NULL) {
1832 m_freem(sc->rl_head);
1833 sc->rl_head = sc->rl_tail = NULL;
1834 }
1835 re_discard_rxbuf(sc, i);
1836 continue;
1837 }
1838 m->m_len = RE_RX_DESC_BUFLEN;
1839 if (sc->rl_head == NULL)
1840 sc->rl_head = sc->rl_tail = m;
1841 else {
1842 m->m_flags &= ~M_PKTHDR;
1843 sc->rl_tail->m_next = m;
1844 sc->rl_tail = m;
1845 }
1846 continue;
1847 }
1848
1849 /*
1850 * NOTE: for the 8139C+, the frame length field
1851 * is always 12 bits in size, but for the gigE chips,
1852 * it is 13 bits (since the max RX frame length is 16K).
1853 * Unfortunately, all 32 bits in the status word
1854 * were already used, so to make room for the extra
1855 * length bit, RealTek took out the 'frame alignment
1856 * error' bit and shifted the other status bits
1857 * over one slot. The OWN, EOR, FS and LS bits are
1858 * still in the same places. We have already extracted
1859 * the frame length and checked the OWN bit, so rather
1860 * than using an alternate bit mapping, we shift the
1861 * status bits one space to the right so we can evaluate
1862 * them using the 8169 status as though it was in the
1863 * same format as that of the 8139C+.
1864 */
1865 if (sc->rl_type == RL_8169)
1866 rxstat >>= 1;
1867
1868 /*
1869 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1870 * set, but if CRC is clear, it will still be a valid frame.
1871 */
1872 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1873 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1874 ifp->if_ierrors++;
1875 /*
1876 * If this is part of a multi-fragment packet,
1877 * discard all the pieces.
1878 */
1879 if (sc->rl_head != NULL) {
1880 m_freem(sc->rl_head);
1881 sc->rl_head = sc->rl_tail = NULL;
1882 }
1883 re_discard_rxbuf(sc, i);
1884 continue;
1885 }
1886
1887 /*
1888 * If allocating a replacement mbuf fails,
1889 * reload the current one.
1890 */
1891
1892 if (re_newbuf(sc, i) != 0) {
1893 ifp->if_iqdrops++;
1894 if (sc->rl_head != NULL) {
1895 m_freem(sc->rl_head);
1896 sc->rl_head = sc->rl_tail = NULL;
1897 }
1898 re_discard_rxbuf(sc, i);
1899 continue;
1900 }
1901
1902 if (sc->rl_head != NULL) {
1903 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1904 if (m->m_len == 0)
1905 m->m_len = RE_RX_DESC_BUFLEN;
1906 /*
1907 * Special case: if there's 4 bytes or less
1908 * in this buffer, the mbuf can be discarded:
1909 * the last 4 bytes is the CRC, which we don't
1910 * care about anyway.
1911 */
1912 if (m->m_len <= ETHER_CRC_LEN) {
1913 sc->rl_tail->m_len -=
1914 (ETHER_CRC_LEN - m->m_len);
1915 m_freem(m);
1916 } else {
1917 m->m_len -= ETHER_CRC_LEN;
1918 m->m_flags &= ~M_PKTHDR;
1919 sc->rl_tail->m_next = m;
1920 }
1921 m = sc->rl_head;
1922 sc->rl_head = sc->rl_tail = NULL;
1923 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1924 } else
1925 m->m_pkthdr.len = m->m_len =
1926 (total_len - ETHER_CRC_LEN);
1927
1928 #ifdef RE_FIXUP_RX
1929 re_fixup_rx(m);
1930 #endif
1931 ifp->if_ipackets++;
1932 m->m_pkthdr.rcvif = ifp;
1933
1934 /* Do RX checksumming if enabled */
1935
1936 if (ifp->if_capenable & IFCAP_RXCSUM) {
1937 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
1938 /* Check IP header checksum */
1939 if (rxstat & RL_RDESC_STAT_PROTOID)
1940 m->m_pkthdr.csum_flags |=
1941 CSUM_IP_CHECKED;
1942 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1943 m->m_pkthdr.csum_flags |=
1944 CSUM_IP_VALID;
1945
1946 /* Check TCP/UDP checksum */
1947 if ((RL_TCPPKT(rxstat) &&
1948 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1949 (RL_UDPPKT(rxstat) &&
1950 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1951 m->m_pkthdr.csum_flags |=
1952 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1953 m->m_pkthdr.csum_data = 0xffff;
1954 }
1955 } else {
1956 /*
1957 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
1958 */
1959 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
1960 (rxvlan & RL_RDESC_IPV4))
1961 m->m_pkthdr.csum_flags |=
1962 CSUM_IP_CHECKED;
1963 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
1964 (rxvlan & RL_RDESC_IPV4))
1965 m->m_pkthdr.csum_flags |=
1966 CSUM_IP_VALID;
1967 if (((rxstat & RL_RDESC_STAT_TCP) &&
1968 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1969 ((rxstat & RL_RDESC_STAT_UDP) &&
1970 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1971 m->m_pkthdr.csum_flags |=
1972 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1973 m->m_pkthdr.csum_data = 0xffff;
1974 }
1975 }
1976 }
1977 maxpkt--;
1978 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1979 m->m_pkthdr.ether_vtag =
1980 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
1981 m->m_flags |= M_VLANTAG;
1982 }
1983 RL_UNLOCK(sc);
1984 (*ifp->if_input)(ifp, m);
1985 RL_LOCK(sc);
1986 }
1987
1988 /* Flush the RX DMA ring */
1989
1990 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1991 sc->rl_ldata.rl_rx_list_map,
1992 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1993
1994 sc->rl_ldata.rl_rx_prodidx = i;
1995
1996 if (maxpkt)
1997 return(EAGAIN);
1998
1999 return(0);
2000 }
2001
2002 static void
2003 re_txeof(struct rl_softc *sc)
2004 {
2005 struct ifnet *ifp;
2006 struct rl_txdesc *txd;
2007 u_int32_t txstat;
2008 int cons;
2009
2010 cons = sc->rl_ldata.rl_tx_considx;
2011 if (cons == sc->rl_ldata.rl_tx_prodidx)
2012 return;
2013
2014 ifp = sc->rl_ifp;
2015 /* Invalidate the TX descriptor list */
2016 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2017 sc->rl_ldata.rl_tx_list_map,
2018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2019
2020 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2021 cons = RL_TX_DESC_NXT(sc, cons)) {
2022 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2023 if (txstat & RL_TDESC_STAT_OWN)
2024 break;
2025 /*
2026 * We only stash mbufs in the last descriptor
2027 * in a fragment chain, which also happens to
2028 * be the only place where the TX status bits
2029 * are valid.
2030 */
2031 if (txstat & RL_TDESC_CMD_EOF) {
2032 txd = &sc->rl_ldata.rl_tx_desc[cons];
2033 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2034 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2035 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2036 txd->tx_dmamap);
2037 KASSERT(txd->tx_m != NULL,
2038 ("%s: freeing NULL mbufs!", __func__));
2039 m_freem(txd->tx_m);
2040 txd->tx_m = NULL;
2041 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2042 RL_TDESC_STAT_COLCNT))
2043 ifp->if_collisions++;
2044 if (txstat & RL_TDESC_STAT_TXERRSUM)
2045 ifp->if_oerrors++;
2046 else
2047 ifp->if_opackets++;
2048 }
2049 sc->rl_ldata.rl_tx_free++;
2050 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2051 }
2052 sc->rl_ldata.rl_tx_considx = cons;
2053
2054 /* No changes made to the TX ring, so no flush needed */
2055
2056 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2057 #ifdef RE_TX_MODERATION
2058 /*
2059 * If not all descriptors have been reaped yet, reload
2060 * the timer so that we will eventually get another
2061 * interrupt that will cause us to re-enter this routine.
2062 * This is done in case the transmitter has gone idle.
2063 */
2064 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2065 #endif
2066 } else
2067 sc->rl_watchdog_timer = 0;
2068 }
2069
2070 static void
2071 re_tick(void *xsc)
2072 {
2073 struct rl_softc *sc;
2074 struct mii_data *mii;
2075
2076 sc = xsc;
2077
2078 RL_LOCK_ASSERT(sc);
2079
2080 mii = device_get_softc(sc->rl_miibus);
2081 mii_tick(mii);
2082 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2083 re_miibus_statchg(sc->rl_dev);
2084 /*
2085 * Reclaim transmitted frames here. Technically it is not
2086 * necessary to do here but it ensures periodic reclamation
2087 * regardless of Tx completion interrupt which seems to be
2088 * lost on PCIe based controllers under certain situations.
2089 */
2090 re_txeof(sc);
2091 re_watchdog(sc);
2092 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2093 }
2094
2095 #ifdef DEVICE_POLLING
2096 static void
2097 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2098 {
2099 struct rl_softc *sc = ifp->if_softc;
2100
2101 RL_LOCK(sc);
2102 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2103 re_poll_locked(ifp, cmd, count);
2104 RL_UNLOCK(sc);
2105 }
2106
2107 static void
2108 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2109 {
2110 struct rl_softc *sc = ifp->if_softc;
2111
2112 RL_LOCK_ASSERT(sc);
2113
2114 sc->rxcycles = count;
2115 re_rxeof(sc);
2116 re_txeof(sc);
2117
2118 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2119 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2120
2121 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2122 u_int16_t status;
2123
2124 status = CSR_READ_2(sc, RL_ISR);
2125 if (status == 0xffff)
2126 return;
2127 if (status)
2128 CSR_WRITE_2(sc, RL_ISR, status);
2129 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2130 (sc->rl_flags & RL_FLAG_PCIE))
2131 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2132
2133 /*
2134 * XXX check behaviour on receiver stalls.
2135 */
2136
2137 if (status & RL_ISR_SYSTEM_ERR)
2138 re_init_locked(sc);
2139 }
2140 }
2141 #endif /* DEVICE_POLLING */
2142
2143 static int
2144 re_intr(void *arg)
2145 {
2146 struct rl_softc *sc;
2147 uint16_t status;
2148
2149 sc = arg;
2150
2151 status = CSR_READ_2(sc, RL_ISR);
2152 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2153 return (FILTER_STRAY);
2154 CSR_WRITE_2(sc, RL_IMR, 0);
2155
2156 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2157
2158 return (FILTER_HANDLED);
2159 }
2160
2161 static void
2162 re_int_task(void *arg, int npending)
2163 {
2164 struct rl_softc *sc;
2165 struct ifnet *ifp;
2166 u_int16_t status;
2167 int rval = 0;
2168
2169 sc = arg;
2170 ifp = sc->rl_ifp;
2171
2172 RL_LOCK(sc);
2173
2174 status = CSR_READ_2(sc, RL_ISR);
2175 CSR_WRITE_2(sc, RL_ISR, status);
2176
2177 if (sc->suspended ||
2178 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2179 RL_UNLOCK(sc);
2180 return;
2181 }
2182
2183 #ifdef DEVICE_POLLING
2184 if (ifp->if_capenable & IFCAP_POLLING) {
2185 RL_UNLOCK(sc);
2186 return;
2187 }
2188 #endif
2189
2190 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2191 rval = re_rxeof(sc);
2192
2193 /*
2194 * Some chips will ignore a second TX request issued
2195 * while an existing transmission is in progress. If
2196 * the transmitter goes idle but there are still
2197 * packets waiting to be sent, we need to restart the
2198 * channel here to flush them out. This only seems to
2199 * be required with the PCIe devices.
2200 */
2201 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2202 (sc->rl_flags & RL_FLAG_PCIE))
2203 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2204 if (status & (
2205 #ifdef RE_TX_MODERATION
2206 RL_ISR_TIMEOUT_EXPIRED|
2207 #else
2208 RL_ISR_TX_OK|
2209 #endif
2210 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2211 re_txeof(sc);
2212
2213 if (status & RL_ISR_SYSTEM_ERR)
2214 re_init_locked(sc);
2215
2216 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2217 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2218
2219 RL_UNLOCK(sc);
2220
2221 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2222 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2223 return;
2224 }
2225
2226 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2227 }
2228
2229 static int
2230 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2231 {
2232 struct rl_txdesc *txd, *txd_last;
2233 bus_dma_segment_t segs[RL_NTXSEGS];
2234 bus_dmamap_t map;
2235 struct mbuf *m_new;
2236 struct rl_desc *desc;
2237 int nsegs, prod;
2238 int i, error, ei, si;
2239 int padlen;
2240 uint32_t cmdstat, csum_flags, vlanctl;
2241
2242 RL_LOCK_ASSERT(sc);
2243 M_ASSERTPKTHDR((*m_head));
2244
2245 /*
2246 * With some of the RealTek chips, using the checksum offload
2247 * support in conjunction with the autopadding feature results
2248 * in the transmission of corrupt frames. For example, if we
2249 * need to send a really small IP fragment that's less than 60
2250 * bytes in size, and IP header checksumming is enabled, the
2251 * resulting ethernet frame that appears on the wire will
2252 * have garbled payload. To work around this, if TX IP checksum
2253 * offload is enabled, we always manually pad short frames out
2254 * to the minimum ethernet frame size.
2255 */
2256 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 &&
2257 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2258 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2259 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2260 if (M_WRITABLE(*m_head) == 0) {
2261 /* Get a writable copy. */
2262 m_new = m_dup(*m_head, M_DONTWAIT);
2263 m_freem(*m_head);
2264 if (m_new == NULL) {
2265 *m_head = NULL;
2266 return (ENOBUFS);
2267 }
2268 *m_head = m_new;
2269 }
2270 if ((*m_head)->m_next != NULL ||
2271 M_TRAILINGSPACE(*m_head) < padlen) {
2272 m_new = m_defrag(*m_head, M_DONTWAIT);
2273 if (m_new == NULL) {
2274 m_freem(*m_head);
2275 *m_head = NULL;
2276 return (ENOBUFS);
2277 }
2278 } else
2279 m_new = *m_head;
2280
2281 /*
2282 * Manually pad short frames, and zero the pad space
2283 * to avoid leaking data.
2284 */
2285 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2286 m_new->m_pkthdr.len += padlen;
2287 m_new->m_len = m_new->m_pkthdr.len;
2288 *m_head = m_new;
2289 }
2290
2291 prod = sc->rl_ldata.rl_tx_prodidx;
2292 txd = &sc->rl_ldata.rl_tx_desc[prod];
2293 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2294 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2295 if (error == EFBIG) {
2296 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
2297 if (m_new == NULL) {
2298 m_freem(*m_head);
2299 *m_head = NULL;
2300 return (ENOBUFS);
2301 }
2302 *m_head = m_new;
2303 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2304 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2305 if (error != 0) {
2306 m_freem(*m_head);
2307 *m_head = NULL;
2308 return (error);
2309 }
2310 } else if (error != 0)
2311 return (error);
2312 if (nsegs == 0) {
2313 m_freem(*m_head);
2314 *m_head = NULL;
2315 return (EIO);
2316 }
2317
2318 /* Check for number of available descriptors. */
2319 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2320 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2321 return (ENOBUFS);
2322 }
2323
2324 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2325 BUS_DMASYNC_PREWRITE);
2326
2327 /*
2328 * Set up checksum offload. Note: checksum offload bits must
2329 * appear in all descriptors of a multi-descriptor transmit
2330 * attempt. This is according to testing done with an 8169
2331 * chip. This is a requirement.
2332 */
2333 vlanctl = 0;
2334 csum_flags = 0;
2335 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0)
2336 csum_flags = RL_TDESC_CMD_LGSEND |
2337 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2338 RL_TDESC_CMD_MSSVAL_SHIFT);
2339 else {
2340 /*
2341 * Unconditionally enable IP checksum if TCP or UDP
2342 * checksum is required. Otherwise, TCP/UDP checksum
2343 * does't make effects.
2344 */
2345 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2346 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2347 csum_flags |= RL_TDESC_CMD_IPCSUM;
2348 if (((*m_head)->m_pkthdr.csum_flags &
2349 CSUM_TCP) != 0)
2350 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2351 if (((*m_head)->m_pkthdr.csum_flags &
2352 CSUM_UDP) != 0)
2353 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2354 } else {
2355 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2356 if (((*m_head)->m_pkthdr.csum_flags &
2357 CSUM_TCP) != 0)
2358 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2359 if (((*m_head)->m_pkthdr.csum_flags &
2360 CSUM_UDP) != 0)
2361 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2362 }
2363 }
2364 }
2365
2366 /*
2367 * Set up hardware VLAN tagging. Note: vlan tag info must
2368 * appear in all descriptors of a multi-descriptor
2369 * transmission attempt.
2370 */
2371 if ((*m_head)->m_flags & M_VLANTAG)
2372 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2373 RL_TDESC_VLANCTL_TAG;
2374
2375 si = prod;
2376 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2377 desc = &sc->rl_ldata.rl_tx_list[prod];
2378 desc->rl_vlanctl = htole32(vlanctl);
2379 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2380 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2381 cmdstat = segs[i].ds_len;
2382 if (i != 0)
2383 cmdstat |= RL_TDESC_CMD_OWN;
2384 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2385 cmdstat |= RL_TDESC_CMD_EOR;
2386 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2387 sc->rl_ldata.rl_tx_free--;
2388 }
2389 /* Update producer index. */
2390 sc->rl_ldata.rl_tx_prodidx = prod;
2391
2392 /* Set EOF on the last descriptor. */
2393 ei = RL_TX_DESC_PRV(sc, prod);
2394 desc = &sc->rl_ldata.rl_tx_list[ei];
2395 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2396
2397 desc = &sc->rl_ldata.rl_tx_list[si];
2398 /* Set SOF and transfer ownership of packet to the chip. */
2399 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2400
2401 /*
2402 * Insure that the map for this transmission
2403 * is placed at the array index of the last descriptor
2404 * in this chain. (Swap last and first dmamaps.)
2405 */
2406 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2407 map = txd->tx_dmamap;
2408 txd->tx_dmamap = txd_last->tx_dmamap;
2409 txd_last->tx_dmamap = map;
2410 txd_last->tx_m = *m_head;
2411
2412 return (0);
2413 }
2414
2415 static void
2416 re_tx_task(void *arg, int npending)
2417 {
2418 struct ifnet *ifp;
2419
2420 ifp = arg;
2421 re_start(ifp);
2422 }
2423
2424 /*
2425 * Main transmit routine for C+ and gigE NICs.
2426 */
2427 static void
2428 re_start(struct ifnet *ifp)
2429 {
2430 struct rl_softc *sc;
2431 struct mbuf *m_head;
2432 int queued;
2433
2434 sc = ifp->if_softc;
2435
2436 RL_LOCK(sc);
2437
2438 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2439 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) {
2440 RL_UNLOCK(sc);
2441 return;
2442 }
2443
2444 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2445 sc->rl_ldata.rl_tx_free > 1;) {
2446 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2447 if (m_head == NULL)
2448 break;
2449
2450 if (re_encap(sc, &m_head) != 0) {
2451 if (m_head == NULL)
2452 break;
2453 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2454 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2455 break;
2456 }
2457
2458 /*
2459 * If there's a BPF listener, bounce a copy of this frame
2460 * to him.
2461 */
2462 ETHER_BPF_MTAP(ifp, m_head);
2463
2464 queued++;
2465 }
2466
2467 if (queued == 0) {
2468 #ifdef RE_TX_MODERATION
2469 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2470 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2471 #endif
2472 RL_UNLOCK(sc);
2473 return;
2474 }
2475
2476 /* Flush the TX descriptors */
2477
2478 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2479 sc->rl_ldata.rl_tx_list_map,
2480 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2481
2482 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2483
2484 #ifdef RE_TX_MODERATION
2485 /*
2486 * Use the countdown timer for interrupt moderation.
2487 * 'TX done' interrupts are disabled. Instead, we reset the
2488 * countdown timer, which will begin counting until it hits
2489 * the value in the TIMERINT register, and then trigger an
2490 * interrupt. Each time we write to the TIMERCNT register,
2491 * the timer count is reset to 0.
2492 */
2493 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2494 #endif
2495
2496 /*
2497 * Set a timeout in case the chip goes out to lunch.
2498 */
2499 sc->rl_watchdog_timer = 5;
2500
2501 RL_UNLOCK(sc);
2502 }
2503
2504 static void
2505 re_init(void *xsc)
2506 {
2507 struct rl_softc *sc = xsc;
2508
2509 RL_LOCK(sc);
2510 re_init_locked(sc);
2511 RL_UNLOCK(sc);
2512 }
2513
2514 static void
2515 re_init_locked(struct rl_softc *sc)
2516 {
2517 struct ifnet *ifp = sc->rl_ifp;
2518 struct mii_data *mii;
2519 uint32_t reg;
2520 uint16_t cfg;
2521 union {
2522 uint32_t align_dummy;
2523 u_char eaddr[ETHER_ADDR_LEN];
2524 } eaddr;
2525
2526 RL_LOCK_ASSERT(sc);
2527
2528 mii = device_get_softc(sc->rl_miibus);
2529
2530 /*
2531 * Cancel pending I/O and free all RX/TX buffers.
2532 */
2533 re_stop(sc);
2534
2535 /* Put controller into known state. */
2536 re_reset(sc);
2537
2538 /*
2539 * Enable C+ RX and TX mode, as well as VLAN stripping and
2540 * RX checksum offload. We must configure the C+ register
2541 * before all others.
2542 */
2543 cfg = RL_CPLUSCMD_PCI_MRW;
2544 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2545 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
2546 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2547 cfg |= RL_CPLUSCMD_VLANSTRIP;
2548 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
2549 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
2550 /* XXX magic. */
2551 cfg |= 0x0001;
2552 } else
2553 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
2554 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
2555 if (sc->rl_hwrev == RL_HWREV_8169_8110SC ||
2556 sc->rl_hwrev == RL_HWREV_8169_8110SCE) {
2557 reg = 0x000fff00;
2558 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
2559 reg |= 0x000000ff;
2560 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE)
2561 reg |= 0x00f00000;
2562 CSR_WRITE_4(sc, 0x7c, reg);
2563 /* Disable interrupt mitigation. */
2564 CSR_WRITE_2(sc, 0xe2, 0);
2565 }
2566 /*
2567 * Disable TSO if interface MTU size is greater than MSS
2568 * allowed in controller.
2569 */
2570 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
2571 ifp->if_capenable &= ~IFCAP_TSO4;
2572 ifp->if_hwassist &= ~CSUM_TSO;
2573 }
2574
2575 /*
2576 * Init our MAC address. Even though the chipset
2577 * documentation doesn't mention it, we need to enter "Config
2578 * register write enable" mode to modify the ID registers.
2579 */
2580 /* Copy MAC address on stack to align. */
2581 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2582 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2583 CSR_WRITE_4(sc, RL_IDR0,
2584 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2585 CSR_WRITE_4(sc, RL_IDR4,
2586 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2587 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2588
2589 /*
2590 * For C+ mode, initialize the RX descriptors and mbufs.
2591 */
2592 re_rx_list_init(sc);
2593 re_tx_list_init(sc);
2594
2595 /*
2596 * Load the addresses of the RX and TX lists into the chip.
2597 */
2598
2599 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2600 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2601 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2602 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2603
2604 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2605 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2606 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2607 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2608
2609 /*
2610 * Enable transmit and receive.
2611 */
2612 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2613
2614 /*
2615 * Set the initial TX configuration.
2616 */
2617 if (sc->rl_testmode) {
2618 if (sc->rl_type == RL_8169)
2619 CSR_WRITE_4(sc, RL_TXCFG,
2620 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2621 else
2622 CSR_WRITE_4(sc, RL_TXCFG,
2623 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2624 } else
2625 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2626
2627 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2628
2629 /*
2630 * Set the initial RX configuration.
2631 */
2632 re_set_rxmode(sc);
2633
2634 #ifdef DEVICE_POLLING
2635 /*
2636 * Disable interrupts if we are polling.
2637 */
2638 if (ifp->if_capenable & IFCAP_POLLING)
2639 CSR_WRITE_2(sc, RL_IMR, 0);
2640 else /* otherwise ... */
2641 #endif
2642
2643 /*
2644 * Enable interrupts.
2645 */
2646 if (sc->rl_testmode)
2647 CSR_WRITE_2(sc, RL_IMR, 0);
2648 else
2649 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2650 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2651
2652 /* Set initial TX threshold */
2653 sc->rl_txthresh = RL_TX_THRESH_INIT;
2654
2655 /* Start RX/TX process. */
2656 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2657 #ifdef notdef
2658 /* Enable receiver and transmitter. */
2659 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2660 #endif
2661
2662 #ifdef RE_TX_MODERATION
2663 /*
2664 * Initialize the timer interrupt register so that
2665 * a timer interrupt will be generated once the timer
2666 * reaches a certain number of ticks. The timer is
2667 * reloaded on each transmit. This gives us TX interrupt
2668 * moderation, which dramatically improves TX frame rate.
2669 */
2670 if (sc->rl_type == RL_8169)
2671 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2672 else
2673 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2674 #endif
2675
2676 /*
2677 * For 8169 gigE NICs, set the max allowed RX packet
2678 * size so we can receive jumbo frames.
2679 */
2680 if (sc->rl_type == RL_8169)
2681 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2682
2683 if (sc->rl_testmode)
2684 return;
2685
2686 mii_mediachg(mii);
2687
2688 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
2689
2690 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2691 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2692
2693 sc->rl_flags &= ~RL_FLAG_LINK;
2694 sc->rl_watchdog_timer = 0;
2695 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2696 }
2697
2698 /*
2699 * Set media options.
2700 */
2701 static int
2702 re_ifmedia_upd(struct ifnet *ifp)
2703 {
2704 struct rl_softc *sc;
2705 struct mii_data *mii;
2706 int error;
2707
2708 sc = ifp->if_softc;
2709 mii = device_get_softc(sc->rl_miibus);
2710 RL_LOCK(sc);
2711 error = mii_mediachg(mii);
2712 RL_UNLOCK(sc);
2713
2714 return (error);
2715 }
2716
2717 /*
2718 * Report current media status.
2719 */
2720 static void
2721 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2722 {
2723 struct rl_softc *sc;
2724 struct mii_data *mii;
2725
2726 sc = ifp->if_softc;
2727 mii = device_get_softc(sc->rl_miibus);
2728
2729 RL_LOCK(sc);
2730 mii_pollstat(mii);
2731 RL_UNLOCK(sc);
2732 ifmr->ifm_active = mii->mii_media_active;
2733 ifmr->ifm_status = mii->mii_media_status;
2734 }
2735
2736 static int
2737 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2738 {
2739 struct rl_softc *sc = ifp->if_softc;
2740 struct ifreq *ifr = (struct ifreq *) data;
2741 struct mii_data *mii;
2742 int error = 0;
2743
2744 switch (command) {
2745 case SIOCSIFMTU:
2746 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) {
2747 error = EINVAL;
2748 break;
2749 }
2750 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 &&
2751 ifr->ifr_mtu > RL_MAX_FRAMELEN) {
2752 error = EINVAL;
2753 break;
2754 }
2755 RL_LOCK(sc);
2756 if (ifp->if_mtu != ifr->ifr_mtu)
2757 ifp->if_mtu = ifr->ifr_mtu;
2758 if (ifp->if_mtu > RL_TSO_MTU &&
2759 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2760 ifp->if_capenable &= ~IFCAP_TSO4;
2761 ifp->if_hwassist &= ~CSUM_TSO;
2762 }
2763 RL_UNLOCK(sc);
2764 break;
2765 case SIOCSIFFLAGS:
2766 RL_LOCK(sc);
2767 if ((ifp->if_flags & IFF_UP) != 0) {
2768 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2769 if (((ifp->if_flags ^ sc->rl_if_flags)
2770 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2771 re_set_rxmode(sc);
2772 } else
2773 re_init_locked(sc);
2774 } else {
2775 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2776 re_stop(sc);
2777 }
2778 sc->rl_if_flags = ifp->if_flags;
2779 RL_UNLOCK(sc);
2780 break;
2781 case SIOCADDMULTI:
2782 case SIOCDELMULTI:
2783 RL_LOCK(sc);
2784 re_set_rxmode(sc);
2785 RL_UNLOCK(sc);
2786 break;
2787 case SIOCGIFMEDIA:
2788 case SIOCSIFMEDIA:
2789 mii = device_get_softc(sc->rl_miibus);
2790 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2791 break;
2792 case SIOCSIFCAP:
2793 {
2794 int mask, reinit;
2795
2796 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2797 reinit = 0;
2798 #ifdef DEVICE_POLLING
2799 if (mask & IFCAP_POLLING) {
2800 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2801 error = ether_poll_register(re_poll, ifp);
2802 if (error)
2803 return(error);
2804 RL_LOCK(sc);
2805 /* Disable interrupts */
2806 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2807 ifp->if_capenable |= IFCAP_POLLING;
2808 RL_UNLOCK(sc);
2809 } else {
2810 error = ether_poll_deregister(ifp);
2811 /* Enable interrupts. */
2812 RL_LOCK(sc);
2813 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2814 ifp->if_capenable &= ~IFCAP_POLLING;
2815 RL_UNLOCK(sc);
2816 }
2817 }
2818 #endif /* DEVICE_POLLING */
2819 if (mask & IFCAP_HWCSUM) {
2820 ifp->if_capenable ^= IFCAP_HWCSUM;
2821 if (ifp->if_capenable & IFCAP_TXCSUM)
2822 ifp->if_hwassist |= RE_CSUM_FEATURES;
2823 else
2824 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
2825 reinit = 1;
2826 }
2827 if (mask & IFCAP_VLAN_HWTAGGING) {
2828 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2829 reinit = 1;
2830 }
2831 if (mask & IFCAP_TSO4) {
2832 ifp->if_capenable ^= IFCAP_TSO4;
2833 if ((IFCAP_TSO4 & ifp->if_capenable) &&
2834 (IFCAP_TSO4 & ifp->if_capabilities))
2835 ifp->if_hwassist |= CSUM_TSO;
2836 else
2837 ifp->if_hwassist &= ~CSUM_TSO;
2838 if (ifp->if_mtu > RL_TSO_MTU &&
2839 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2840 ifp->if_capenable &= ~IFCAP_TSO4;
2841 ifp->if_hwassist &= ~CSUM_TSO;
2842 }
2843 }
2844 if ((mask & IFCAP_WOL) != 0 &&
2845 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2846 if ((mask & IFCAP_WOL_UCAST) != 0)
2847 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2848 if ((mask & IFCAP_WOL_MCAST) != 0)
2849 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2850 if ((mask & IFCAP_WOL_MAGIC) != 0)
2851 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2852 }
2853 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
2854 re_init(sc);
2855 VLAN_CAPABILITIES(ifp);
2856 }
2857 break;
2858 default:
2859 error = ether_ioctl(ifp, command, data);
2860 break;
2861 }
2862
2863 return (error);
2864 }
2865
2866 static void
2867 re_watchdog(struct rl_softc *sc)
2868 {
2869 struct ifnet *ifp;
2870
2871 RL_LOCK_ASSERT(sc);
2872
2873 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
2874 return;
2875
2876 ifp = sc->rl_ifp;
2877 re_txeof(sc);
2878 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
2879 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2880 "-- recovering\n");
2881 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2882 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2883 return;
2884 }
2885
2886 if_printf(ifp, "watchdog timeout\n");
2887 ifp->if_oerrors++;
2888
2889 re_rxeof(sc);
2890 re_init_locked(sc);
2891 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2892 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2893 }
2894
2895 /*
2896 * Stop the adapter and free any mbufs allocated to the
2897 * RX and TX lists.
2898 */
2899 static void
2900 re_stop(struct rl_softc *sc)
2901 {
2902 int i;
2903 struct ifnet *ifp;
2904 struct rl_txdesc *txd;
2905 struct rl_rxdesc *rxd;
2906
2907 RL_LOCK_ASSERT(sc);
2908
2909 ifp = sc->rl_ifp;
2910
2911 sc->rl_watchdog_timer = 0;
2912 callout_stop(&sc->rl_stat_callout);
2913 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2914
2915 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0)
2916 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
2917 RL_CMD_RX_ENB);
2918 else
2919 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2920 DELAY(1000);
2921 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2922 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
2923
2924 if (sc->rl_head != NULL) {
2925 m_freem(sc->rl_head);
2926 sc->rl_head = sc->rl_tail = NULL;
2927 }
2928
2929 /* Free the TX list buffers. */
2930
2931 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
2932 txd = &sc->rl_ldata.rl_tx_desc[i];
2933 if (txd->tx_m != NULL) {
2934 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2935 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2936 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2937 txd->tx_dmamap);
2938 m_freem(txd->tx_m);
2939 txd->tx_m = NULL;
2940 }
2941 }
2942
2943 /* Free the RX list buffers. */
2944
2945 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2946 rxd = &sc->rl_ldata.rl_rx_desc[i];
2947 if (rxd->rx_m != NULL) {
2948 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2949 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2950 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
2951 rxd->rx_dmamap);
2952 m_freem(rxd->rx_m);
2953 rxd->rx_m = NULL;
2954 }
2955 }
2956 }
2957
2958 /*
2959 * Device suspend routine. Stop the interface and save some PCI
2960 * settings in case the BIOS doesn't restore them properly on
2961 * resume.
2962 */
2963 static int
2964 re_suspend(device_t dev)
2965 {
2966 struct rl_softc *sc;
2967
2968 sc = device_get_softc(dev);
2969
2970 RL_LOCK(sc);
2971 re_stop(sc);
2972 re_setwol(sc);
2973 sc->suspended = 1;
2974 RL_UNLOCK(sc);
2975
2976 return (0);
2977 }
2978
2979 /*
2980 * Device resume routine. Restore some PCI settings in case the BIOS
2981 * doesn't, re-enable busmastering, and restart the interface if
2982 * appropriate.
2983 */
2984 static int
2985 re_resume(device_t dev)
2986 {
2987 struct rl_softc *sc;
2988 struct ifnet *ifp;
2989
2990 sc = device_get_softc(dev);
2991
2992 RL_LOCK(sc);
2993
2994 ifp = sc->rl_ifp;
2995 /* Take controller out of sleep mode. */
2996 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
2997 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
2998 CSR_WRITE_1(sc, RL_GPIO,
2999 CSR_READ_1(sc, RL_GPIO) | 0x01);
3000 }
3001
3002 /* reinitialize interface if necessary */
3003 if (ifp->if_flags & IFF_UP)
3004 re_init_locked(sc);
3005
3006 /*
3007 * Clear WOL matching such that normal Rx filtering
3008 * wouldn't interfere with WOL patterns.
3009 */
3010 re_clrwol(sc);
3011 sc->suspended = 0;
3012 RL_UNLOCK(sc);
3013
3014 return (0);
3015 }
3016
3017 /*
3018 * Stop all chip I/O so that the kernel's probe routines don't
3019 * get confused by errant DMAs when rebooting.
3020 */
3021 static int
3022 re_shutdown(device_t dev)
3023 {
3024 struct rl_softc *sc;
3025
3026 sc = device_get_softc(dev);
3027
3028 RL_LOCK(sc);
3029 re_stop(sc);
3030 /*
3031 * Mark interface as down since otherwise we will panic if
3032 * interrupt comes in later on, which can happen in some
3033 * cases.
3034 */
3035 sc->rl_ifp->if_flags &= ~IFF_UP;
3036 re_setwol(sc);
3037 RL_UNLOCK(sc);
3038
3039 return (0);
3040 }
3041
3042 static void
3043 re_setwol(struct rl_softc *sc)
3044 {
3045 struct ifnet *ifp;
3046 int pmc;
3047 uint16_t pmstat;
3048 uint8_t v;
3049
3050 RL_LOCK_ASSERT(sc);
3051
3052 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3053 return;
3054
3055 ifp = sc->rl_ifp;
3056 /* Put controller into sleep mode. */
3057 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3058 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3059 CSR_WRITE_1(sc, RL_GPIO,
3060 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3061 }
3062 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3063 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3064 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3065 /* Enable config register write. */
3066 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3067
3068 /* Enable PME. */
3069 v = CSR_READ_1(sc, RL_CFG1);
3070 v &= ~RL_CFG1_PME;
3071 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3072 v |= RL_CFG1_PME;
3073 CSR_WRITE_1(sc, RL_CFG1, v);
3074
3075 v = CSR_READ_1(sc, RL_CFG3);
3076 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3077 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3078 v |= RL_CFG3_WOL_MAGIC;
3079 CSR_WRITE_1(sc, RL_CFG3, v);
3080
3081 /* Config register write done. */
3082 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3083
3084 v = CSR_READ_1(sc, RL_CFG5);
3085 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3086 v &= ~RL_CFG5_WOL_LANWAKE;
3087 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3088 v |= RL_CFG5_WOL_UCAST;
3089 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3090 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3091 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3092 v |= RL_CFG5_WOL_LANWAKE;
3093 CSR_WRITE_1(sc, RL_CFG5, v);
3094
3095 /*
3096 * It seems that hardware resets its link speed to 100Mbps in
3097 * power down mode so switching to 100Mbps in driver is not
3098 * needed.
3099 */
3100
3101 /* Request PME if WOL is requested. */
3102 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3103 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3104 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3105 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3106 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3107 }
3108
3109 static void
3110 re_clrwol(struct rl_softc *sc)
3111 {
3112 int pmc;
3113 uint8_t v;
3114
3115 RL_LOCK_ASSERT(sc);
3116
3117 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3118 return;
3119
3120 /* Enable config register write. */
3121 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3122
3123 v = CSR_READ_1(sc, RL_CFG3);
3124 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3125 CSR_WRITE_1(sc, RL_CFG3, v);
3126
3127 /* Config register write done. */
3128 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3129
3130 v = CSR_READ_1(sc, RL_CFG5);
3131 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3132 v &= ~RL_CFG5_WOL_LANWAKE;
3133 CSR_WRITE_1(sc, RL_CFG5, v);
3134 }
Cache object: f52894317efa1314e3465f735f9ee695
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