FreeBSD/Linux Kernel Cross Reference
sys/dev/rl/if_rl.c
1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47 /*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
88 #endif
89
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
100
101 #include <net/if.h>
102 #include <net/if_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108
109 #include <net/bpf.h>
110
111 #include <machine/bus.h>
112 #include <machine/resource.h>
113 #include <sys/bus.h>
114 #include <sys/rman.h>
115
116 #include <dev/mii/mii.h>
117 #include <dev/mii/mii_bitbang.h>
118 #include <dev/mii/miivar.h>
119
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
122
123 MODULE_DEPEND(rl, pci, 1, 1, 1);
124 MODULE_DEPEND(rl, ether, 1, 1, 1);
125 MODULE_DEPEND(rl, miibus, 1, 1, 1);
126
127 /* "device miibus" required. See GENERIC if you get errors here. */
128 #include "miibus_if.h"
129
130 #include <dev/rl/if_rlreg.h>
131
132 /*
133 * Various supported device vendors/types and their names.
134 */
135 static const struct rl_type rl_devs[] = {
136 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
137 "RealTek 8129 10/100BaseTX" },
138 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
139 "RealTek 8139 10/100BaseTX" },
140 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
141 "RealTek 8139 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
143 "RealTek 8139 10/100BaseTX CardBus" },
144 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
145 "RealTek 8100 10/100BaseTX" },
146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
147 "Accton MPX 5030/5038 10/100BaseTX" },
148 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
149 "Delta Electronics 8139 10/100BaseTX" },
150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
151 "Addtron Technology 8139 10/100BaseTX" },
152 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
153 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
167 "Planex FNW-3603-TX" },
168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
169 "Planex FNW-3800-TX" },
170 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
171 "Compaq HNE-300" },
172 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
173 "LevelOne FPC-0106TX" },
174 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
175 "Edimax EP-4103DL CardBus" }
176 };
177
178 static int rl_attach(device_t);
179 static int rl_detach(device_t);
180 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int rl_dma_alloc(struct rl_softc *);
182 static void rl_dma_free(struct rl_softc *);
183 static void rl_eeprom_putbyte(struct rl_softc *, int);
184 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
185 static int rl_encap(struct rl_softc *, struct mbuf **);
186 static int rl_list_tx_init(struct rl_softc *);
187 static int rl_list_rx_init(struct rl_softc *);
188 static int rl_ifmedia_upd(struct ifnet *);
189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
191 static void rl_intr(void *);
192 static void rl_init(void *);
193 static void rl_init_locked(struct rl_softc *sc);
194 static int rl_miibus_readreg(device_t, int, int);
195 static void rl_miibus_statchg(device_t);
196 static int rl_miibus_writereg(device_t, int, int, int);
197 #ifdef DEVICE_POLLING
198 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
199 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
200 #endif
201 static int rl_probe(device_t);
202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
203 static void rl_reset(struct rl_softc *);
204 static int rl_resume(device_t);
205 static int rl_rxeof(struct rl_softc *);
206 static void rl_rxfilter(struct rl_softc *);
207 static int rl_shutdown(device_t);
208 static void rl_start(struct ifnet *);
209 static void rl_start_locked(struct ifnet *);
210 static void rl_stop(struct rl_softc *);
211 static int rl_suspend(device_t);
212 static void rl_tick(void *);
213 static void rl_txeof(struct rl_softc *);
214 static void rl_watchdog(struct rl_softc *);
215 static void rl_setwol(struct rl_softc *);
216 static void rl_clrwol(struct rl_softc *);
217
218 /*
219 * MII bit-bang glue
220 */
221 static uint32_t rl_mii_bitbang_read(device_t);
222 static void rl_mii_bitbang_write(device_t, uint32_t);
223
224 static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
225 rl_mii_bitbang_read,
226 rl_mii_bitbang_write,
227 {
228 RL_MII_DATAOUT, /* MII_BIT_MDO */
229 RL_MII_DATAIN, /* MII_BIT_MDI */
230 RL_MII_CLK, /* MII_BIT_MDC */
231 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
232 0, /* MII_BIT_DIR_PHY_HOST */
233 }
234 };
235
236 static device_method_t rl_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, rl_probe),
239 DEVMETHOD(device_attach, rl_attach),
240 DEVMETHOD(device_detach, rl_detach),
241 DEVMETHOD(device_suspend, rl_suspend),
242 DEVMETHOD(device_resume, rl_resume),
243 DEVMETHOD(device_shutdown, rl_shutdown),
244
245 /* MII interface */
246 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
247 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
248 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
249
250 DEVMETHOD_END
251 };
252
253 static driver_t rl_driver = {
254 "rl",
255 rl_methods,
256 sizeof(struct rl_softc)
257 };
258
259 static devclass_t rl_devclass;
260
261 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
262 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs,
263 nitems(rl_devs) - 1);
264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
266
267 #define EE_SET(x) \
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
270
271 #define EE_CLR(x) \
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
274
275 /*
276 * Send a read command and address to the EEPROM, check for ACK.
277 */
278 static void
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
280 {
281 int d, i;
282
283 d = addr | sc->rl_eecmd_read;
284
285 /*
286 * Feed in each bit and strobe the clock.
287 */
288 for (i = 0x400; i; i >>= 1) {
289 if (d & i) {
290 EE_SET(RL_EE_DATAIN);
291 } else {
292 EE_CLR(RL_EE_DATAIN);
293 }
294 DELAY(100);
295 EE_SET(RL_EE_CLK);
296 DELAY(150);
297 EE_CLR(RL_EE_CLK);
298 DELAY(100);
299 }
300 }
301
302 /*
303 * Read a word of data stored in the EEPROM at address 'addr.'
304 */
305 static void
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
307 {
308 int i;
309 uint16_t word = 0;
310
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
313
314 /*
315 * Send address of word we want to read.
316 */
317 rl_eeprom_putbyte(sc, addr);
318
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
320
321 /*
322 * Start reading bits from EEPROM.
323 */
324 for (i = 0x8000; i; i >>= 1) {
325 EE_SET(RL_EE_CLK);
326 DELAY(100);
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
328 word |= i;
329 EE_CLR(RL_EE_CLK);
330 DELAY(100);
331 }
332
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
335
336 *dest = word;
337 }
338
339 /*
340 * Read a sequence of words from the EEPROM.
341 */
342 static void
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
344 {
345 int i;
346 uint16_t word = 0, *ptr;
347
348 for (i = 0; i < cnt; i++) {
349 rl_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)(dest + (i * 2));
351 if (swap)
352 *ptr = ntohs(word);
353 else
354 *ptr = word;
355 }
356 }
357
358 /*
359 * Read the MII serial port for the MII bit-bang module.
360 */
361 static uint32_t
362 rl_mii_bitbang_read(device_t dev)
363 {
364 struct rl_softc *sc;
365 uint32_t val;
366
367 sc = device_get_softc(dev);
368
369 val = CSR_READ_1(sc, RL_MII);
370 CSR_BARRIER(sc, RL_MII, 1,
371 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
372
373 return (val);
374 }
375
376 /*
377 * Write the MII serial port for the MII bit-bang module.
378 */
379 static void
380 rl_mii_bitbang_write(device_t dev, uint32_t val)
381 {
382 struct rl_softc *sc;
383
384 sc = device_get_softc(dev);
385
386 CSR_WRITE_1(sc, RL_MII, val);
387 CSR_BARRIER(sc, RL_MII, 1,
388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
389 }
390
391 static int
392 rl_miibus_readreg(device_t dev, int phy, int reg)
393 {
394 struct rl_softc *sc;
395 uint16_t rl8139_reg;
396
397 sc = device_get_softc(dev);
398
399 if (sc->rl_type == RL_8139) {
400 switch (reg) {
401 case MII_BMCR:
402 rl8139_reg = RL_BMCR;
403 break;
404 case MII_BMSR:
405 rl8139_reg = RL_BMSR;
406 break;
407 case MII_ANAR:
408 rl8139_reg = RL_ANAR;
409 break;
410 case MII_ANER:
411 rl8139_reg = RL_ANER;
412 break;
413 case MII_ANLPAR:
414 rl8139_reg = RL_LPAR;
415 break;
416 case MII_PHYIDR1:
417 case MII_PHYIDR2:
418 return (0);
419 /*
420 * Allow the rlphy driver to read the media status
421 * register. If we have a link partner which does not
422 * support NWAY, this is the register which will tell
423 * us the results of parallel detection.
424 */
425 case RL_MEDIASTAT:
426 return (CSR_READ_1(sc, RL_MEDIASTAT));
427 default:
428 device_printf(sc->rl_dev, "bad phy register\n");
429 return (0);
430 }
431 return (CSR_READ_2(sc, rl8139_reg));
432 }
433
434 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
435 }
436
437 static int
438 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
439 {
440 struct rl_softc *sc;
441 uint16_t rl8139_reg;
442
443 sc = device_get_softc(dev);
444
445 if (sc->rl_type == RL_8139) {
446 switch (reg) {
447 case MII_BMCR:
448 rl8139_reg = RL_BMCR;
449 break;
450 case MII_BMSR:
451 rl8139_reg = RL_BMSR;
452 break;
453 case MII_ANAR:
454 rl8139_reg = RL_ANAR;
455 break;
456 case MII_ANER:
457 rl8139_reg = RL_ANER;
458 break;
459 case MII_ANLPAR:
460 rl8139_reg = RL_LPAR;
461 break;
462 case MII_PHYIDR1:
463 case MII_PHYIDR2:
464 return (0);
465 break;
466 default:
467 device_printf(sc->rl_dev, "bad phy register\n");
468 return (0);
469 }
470 CSR_WRITE_2(sc, rl8139_reg, data);
471 return (0);
472 }
473
474 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
475
476 return (0);
477 }
478
479 static void
480 rl_miibus_statchg(device_t dev)
481 {
482 struct rl_softc *sc;
483 struct ifnet *ifp;
484 struct mii_data *mii;
485
486 sc = device_get_softc(dev);
487 mii = device_get_softc(sc->rl_miibus);
488 ifp = sc->rl_ifp;
489 if (mii == NULL || ifp == NULL ||
490 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
491 return;
492
493 sc->rl_flags &= ~RL_FLAG_LINK;
494 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
495 (IFM_ACTIVE | IFM_AVALID)) {
496 switch (IFM_SUBTYPE(mii->mii_media_active)) {
497 case IFM_10_T:
498 case IFM_100_TX:
499 sc->rl_flags |= RL_FLAG_LINK;
500 break;
501 default:
502 break;
503 }
504 }
505 /*
506 * RealTek controllers do not provide any interface to
507 * Tx/Rx MACs for resolved speed, duplex and flow-control
508 * parameters.
509 */
510 }
511
512 static u_int
513 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
514 {
515 uint32_t *hashes = arg;
516 int h;
517
518 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
519 if (h < 32)
520 hashes[0] |= (1 << h);
521 else
522 hashes[1] |= (1 << (h - 32));
523
524 return (1);
525 }
526
527 /*
528 * Program the 64-bit multicast hash filter.
529 */
530 static void
531 rl_rxfilter(struct rl_softc *sc)
532 {
533 struct ifnet *ifp = sc->rl_ifp;
534 uint32_t hashes[2] = { 0, 0 };
535 uint32_t rxfilt;
536
537 RL_LOCK_ASSERT(sc);
538
539 rxfilt = CSR_READ_4(sc, RL_RXCFG);
540 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
541 RL_RXCFG_RX_MULTI);
542 /* Always accept frames destined for this host. */
543 rxfilt |= RL_RXCFG_RX_INDIV;
544 /* Set capture broadcast bit to capture broadcast frames. */
545 if (ifp->if_flags & IFF_BROADCAST)
546 rxfilt |= RL_RXCFG_RX_BROAD;
547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
548 rxfilt |= RL_RXCFG_RX_MULTI;
549 if (ifp->if_flags & IFF_PROMISC)
550 rxfilt |= RL_RXCFG_RX_ALLPHYS;
551 hashes[0] = 0xFFFFFFFF;
552 hashes[1] = 0xFFFFFFFF;
553 } else {
554 /* Now program new ones. */
555 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes);
556 if (hashes[0] != 0 || hashes[1] != 0)
557 rxfilt |= RL_RXCFG_RX_MULTI;
558 }
559
560 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
561 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
562 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
563 }
564
565 static void
566 rl_reset(struct rl_softc *sc)
567 {
568 int i;
569
570 RL_LOCK_ASSERT(sc);
571
572 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
573
574 for (i = 0; i < RL_TIMEOUT; i++) {
575 DELAY(10);
576 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
577 break;
578 }
579 if (i == RL_TIMEOUT)
580 device_printf(sc->rl_dev, "reset never completed!\n");
581 }
582
583 /*
584 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
585 * IDs against our list and return a device name if we find a match.
586 */
587 static int
588 rl_probe(device_t dev)
589 {
590 const struct rl_type *t;
591 uint16_t devid, revid, vendor;
592 int i;
593
594 vendor = pci_get_vendor(dev);
595 devid = pci_get_device(dev);
596 revid = pci_get_revid(dev);
597
598 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
599 if (revid == 0x20) {
600 /* 8139C+, let re(4) take care of this device. */
601 return (ENXIO);
602 }
603 }
604 t = rl_devs;
605 for (i = 0; i < nitems(rl_devs); i++, t++) {
606 if (vendor == t->rl_vid && devid == t->rl_did) {
607 device_set_desc(dev, t->rl_name);
608 return (BUS_PROBE_DEFAULT);
609 }
610 }
611
612 return (ENXIO);
613 }
614
615 struct rl_dmamap_arg {
616 bus_addr_t rl_busaddr;
617 };
618
619 static void
620 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
621 {
622 struct rl_dmamap_arg *ctx;
623
624 if (error != 0)
625 return;
626
627 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
628
629 ctx = (struct rl_dmamap_arg *)arg;
630 ctx->rl_busaddr = segs[0].ds_addr;
631 }
632
633 /*
634 * Attach the interface. Allocate softc structures, do ifmedia
635 * setup and ethernet/BPF attach.
636 */
637 static int
638 rl_attach(device_t dev)
639 {
640 uint8_t eaddr[ETHER_ADDR_LEN];
641 uint16_t as[3];
642 struct ifnet *ifp;
643 struct rl_softc *sc;
644 const struct rl_type *t;
645 struct sysctl_ctx_list *ctx;
646 struct sysctl_oid_list *children;
647 int error = 0, hwrev, i, phy, pmc, rid;
648 int prefer_iomap, unit;
649 uint16_t rl_did = 0;
650 char tn[32];
651
652 sc = device_get_softc(dev);
653 unit = device_get_unit(dev);
654 sc->rl_dev = dev;
655
656 sc->rl_twister_enable = 0;
657 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
658 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
659 ctx = device_get_sysctl_ctx(sc->rl_dev);
660 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
661 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
662 &sc->rl_twister_enable, 0, "");
663
664 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
665 MTX_DEF);
666 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
667
668 pci_enable_busmaster(dev);
669
670 /*
671 * Map control/status registers.
672 * Default to using PIO access for this driver. On SMP systems,
673 * there appear to be problems with memory mapped mode: it looks
674 * like doing too many memory mapped access back to back in rapid
675 * succession can hang the bus. I'm inclined to blame this on
676 * crummy design/construction on the part of RealTek. Memory
677 * mapped mode does appear to work on uniprocessor systems though.
678 */
679 prefer_iomap = 1;
680 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
681 TUNABLE_INT_FETCH(tn, &prefer_iomap);
682 if (prefer_iomap) {
683 sc->rl_res_id = PCIR_BAR(0);
684 sc->rl_res_type = SYS_RES_IOPORT;
685 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
686 &sc->rl_res_id, RF_ACTIVE);
687 }
688 if (prefer_iomap == 0 || sc->rl_res == NULL) {
689 sc->rl_res_id = PCIR_BAR(1);
690 sc->rl_res_type = SYS_RES_MEMORY;
691 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
692 &sc->rl_res_id, RF_ACTIVE);
693 }
694 if (sc->rl_res == NULL) {
695 device_printf(dev, "couldn't map ports/memory\n");
696 error = ENXIO;
697 goto fail;
698 }
699
700 #ifdef notdef
701 /*
702 * Detect the Realtek 8139B. For some reason, this chip is very
703 * unstable when left to autoselect the media
704 * The best workaround is to set the device to the required
705 * media type or to set it to the 10 Meg speed.
706 */
707 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
708 device_printf(dev,
709 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
710 #endif
711
712 sc->rl_btag = rman_get_bustag(sc->rl_res);
713 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
714
715 /* Allocate interrupt */
716 rid = 0;
717 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
718 RF_SHAREABLE | RF_ACTIVE);
719
720 if (sc->rl_irq[0] == NULL) {
721 device_printf(dev, "couldn't map interrupt\n");
722 error = ENXIO;
723 goto fail;
724 }
725
726 sc->rl_cfg0 = RL_8139_CFG0;
727 sc->rl_cfg1 = RL_8139_CFG1;
728 sc->rl_cfg2 = 0;
729 sc->rl_cfg3 = RL_8139_CFG3;
730 sc->rl_cfg4 = RL_8139_CFG4;
731 sc->rl_cfg5 = RL_8139_CFG5;
732
733 /*
734 * Reset the adapter. Only take the lock here as it's needed in
735 * order to call rl_reset().
736 */
737 RL_LOCK(sc);
738 rl_reset(sc);
739 RL_UNLOCK(sc);
740
741 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
742 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
743 if (rl_did != 0x8129)
744 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
745
746 /*
747 * Get station address from the EEPROM.
748 */
749 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
750 for (i = 0; i < 3; i++) {
751 eaddr[(i * 2) + 0] = as[i] & 0xff;
752 eaddr[(i * 2) + 1] = as[i] >> 8;
753 }
754
755 /*
756 * Now read the exact device type from the EEPROM to find
757 * out if it's an 8129 or 8139.
758 */
759 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
760
761 t = rl_devs;
762 sc->rl_type = 0;
763 while(t->rl_name != NULL) {
764 if (rl_did == t->rl_did) {
765 sc->rl_type = t->rl_basetype;
766 break;
767 }
768 t++;
769 }
770
771 if (sc->rl_type == 0) {
772 device_printf(dev, "unknown device ID: %x assuming 8139\n",
773 rl_did);
774 sc->rl_type = RL_8139;
775 /*
776 * Read RL_IDR register to get ethernet address as accessing
777 * EEPROM may not extract correct address.
778 */
779 for (i = 0; i < ETHER_ADDR_LEN; i++)
780 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
781 }
782
783 if ((error = rl_dma_alloc(sc)) != 0)
784 goto fail;
785
786 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
787 if (ifp == NULL) {
788 device_printf(dev, "can not if_alloc()\n");
789 error = ENOSPC;
790 goto fail;
791 }
792
793 #define RL_PHYAD_INTERNAL 0
794
795 /* Do MII setup */
796 phy = MII_PHY_ANY;
797 if (sc->rl_type == RL_8139)
798 phy = RL_PHYAD_INTERNAL;
799 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
800 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
801 if (error != 0) {
802 device_printf(dev, "attaching PHYs failed\n");
803 goto fail;
804 }
805
806 ifp->if_softc = sc;
807 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
808 ifp->if_mtu = ETHERMTU;
809 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
810 ifp->if_ioctl = rl_ioctl;
811 ifp->if_start = rl_start;
812 ifp->if_init = rl_init;
813 ifp->if_capabilities = IFCAP_VLAN_MTU;
814 /* Check WOL for RTL8139B or newer controllers. */
815 if (sc->rl_type == RL_8139 &&
816 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
817 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
818 switch (hwrev) {
819 case RL_HWREV_8139B:
820 case RL_HWREV_8130:
821 case RL_HWREV_8139C:
822 case RL_HWREV_8139D:
823 case RL_HWREV_8101:
824 case RL_HWREV_8100:
825 ifp->if_capabilities |= IFCAP_WOL;
826 /* Disable WOL. */
827 rl_clrwol(sc);
828 break;
829 default:
830 break;
831 }
832 }
833 ifp->if_capenable = ifp->if_capabilities;
834 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
835 #ifdef DEVICE_POLLING
836 ifp->if_capabilities |= IFCAP_POLLING;
837 #endif
838 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
839 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
840 IFQ_SET_READY(&ifp->if_snd);
841
842 /*
843 * Call MI attach routine.
844 */
845 ether_ifattach(ifp, eaddr);
846
847 /* Hook interrupt last to avoid having to lock softc */
848 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
849 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
850 if (error) {
851 device_printf(sc->rl_dev, "couldn't set up irq\n");
852 ether_ifdetach(ifp);
853 }
854
855 fail:
856 if (error)
857 rl_detach(dev);
858
859 return (error);
860 }
861
862 /*
863 * Shutdown hardware and free up resources. This can be called any
864 * time after the mutex has been initialized. It is called in both
865 * the error case in attach and the normal detach case so it needs
866 * to be careful about only freeing resources that have actually been
867 * allocated.
868 */
869 static int
870 rl_detach(device_t dev)
871 {
872 struct rl_softc *sc;
873 struct ifnet *ifp;
874
875 sc = device_get_softc(dev);
876 ifp = sc->rl_ifp;
877
878 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
879
880 #ifdef DEVICE_POLLING
881 if (ifp->if_capenable & IFCAP_POLLING)
882 ether_poll_deregister(ifp);
883 #endif
884 /* These should only be active if attach succeeded */
885 if (device_is_attached(dev)) {
886 RL_LOCK(sc);
887 rl_stop(sc);
888 RL_UNLOCK(sc);
889 callout_drain(&sc->rl_stat_callout);
890 ether_ifdetach(ifp);
891 }
892 #if 0
893 sc->suspended = 1;
894 #endif
895 if (sc->rl_miibus)
896 device_delete_child(dev, sc->rl_miibus);
897 bus_generic_detach(dev);
898
899 if (sc->rl_intrhand[0])
900 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
901 if (sc->rl_irq[0])
902 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
903 if (sc->rl_res)
904 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
905 sc->rl_res);
906
907 if (ifp)
908 if_free(ifp);
909
910 rl_dma_free(sc);
911
912 mtx_destroy(&sc->rl_mtx);
913
914 return (0);
915 }
916
917 static int
918 rl_dma_alloc(struct rl_softc *sc)
919 {
920 struct rl_dmamap_arg ctx;
921 int error, i;
922
923 /*
924 * Allocate the parent bus DMA tag appropriate for PCI.
925 */
926 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
927 1, 0, /* alignment, boundary */
928 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
929 BUS_SPACE_MAXADDR, /* highaddr */
930 NULL, NULL, /* filter, filterarg */
931 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
932 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
933 0, /* flags */
934 NULL, NULL, /* lockfunc, lockarg */
935 &sc->rl_parent_tag);
936 if (error) {
937 device_printf(sc->rl_dev,
938 "failed to create parent DMA tag.\n");
939 goto fail;
940 }
941 /* Create DMA tag for Rx memory block. */
942 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
943 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
944 BUS_SPACE_MAXADDR, /* lowaddr */
945 BUS_SPACE_MAXADDR, /* highaddr */
946 NULL, NULL, /* filter, filterarg */
947 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
948 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
949 0, /* flags */
950 NULL, NULL, /* lockfunc, lockarg */
951 &sc->rl_cdata.rl_rx_tag);
952 if (error) {
953 device_printf(sc->rl_dev,
954 "failed to create Rx memory block DMA tag.\n");
955 goto fail;
956 }
957 /* Create DMA tag for Tx buffer. */
958 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
959 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
960 BUS_SPACE_MAXADDR, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 MCLBYTES, 1, /* maxsize, nsegments */
964 MCLBYTES, /* maxsegsize */
965 0, /* flags */
966 NULL, NULL, /* lockfunc, lockarg */
967 &sc->rl_cdata.rl_tx_tag);
968 if (error) {
969 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
970 goto fail;
971 }
972
973 /*
974 * Allocate DMA'able memory and load DMA map for Rx memory block.
975 */
976 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
977 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
978 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
979 if (error != 0) {
980 device_printf(sc->rl_dev,
981 "failed to allocate Rx DMA memory block.\n");
982 goto fail;
983 }
984 ctx.rl_busaddr = 0;
985 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
986 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
987 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
988 BUS_DMA_NOWAIT);
989 if (error != 0 || ctx.rl_busaddr == 0) {
990 device_printf(sc->rl_dev,
991 "could not load Rx DMA memory block.\n");
992 goto fail;
993 }
994 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
995
996 /* Create DMA maps for Tx buffers. */
997 for (i = 0; i < RL_TX_LIST_CNT; i++) {
998 sc->rl_cdata.rl_tx_chain[i] = NULL;
999 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1000 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1001 &sc->rl_cdata.rl_tx_dmamap[i]);
1002 if (error != 0) {
1003 device_printf(sc->rl_dev,
1004 "could not create Tx dmamap.\n");
1005 goto fail;
1006 }
1007 }
1008
1009 /* Leave a few bytes before the start of the RX ring buffer. */
1010 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1011 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1012
1013 fail:
1014 return (error);
1015 }
1016
1017 static void
1018 rl_dma_free(struct rl_softc *sc)
1019 {
1020 int i;
1021
1022 /* Rx memory block. */
1023 if (sc->rl_cdata.rl_rx_tag != NULL) {
1024 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1025 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1026 sc->rl_cdata.rl_rx_dmamap);
1027 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1028 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1029 sc->rl_cdata.rl_rx_buf_ptr,
1030 sc->rl_cdata.rl_rx_dmamap);
1031 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1032 sc->rl_cdata.rl_rx_buf = NULL;
1033 sc->rl_cdata.rl_rx_buf_paddr = 0;
1034 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1035 sc->rl_cdata.rl_tx_tag = NULL;
1036 }
1037
1038 /* Tx buffers. */
1039 if (sc->rl_cdata.rl_tx_tag != NULL) {
1040 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1041 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1042 bus_dmamap_destroy(
1043 sc->rl_cdata.rl_tx_tag,
1044 sc->rl_cdata.rl_tx_dmamap[i]);
1045 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1046 }
1047 }
1048 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1049 sc->rl_cdata.rl_tx_tag = NULL;
1050 }
1051
1052 if (sc->rl_parent_tag != NULL) {
1053 bus_dma_tag_destroy(sc->rl_parent_tag);
1054 sc->rl_parent_tag = NULL;
1055 }
1056 }
1057
1058 /*
1059 * Initialize the transmit descriptors.
1060 */
1061 static int
1062 rl_list_tx_init(struct rl_softc *sc)
1063 {
1064 struct rl_chain_data *cd;
1065 int i;
1066
1067 RL_LOCK_ASSERT(sc);
1068
1069 cd = &sc->rl_cdata;
1070 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1071 cd->rl_tx_chain[i] = NULL;
1072 CSR_WRITE_4(sc,
1073 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1074 }
1075
1076 sc->rl_cdata.cur_tx = 0;
1077 sc->rl_cdata.last_tx = 0;
1078
1079 return (0);
1080 }
1081
1082 static int
1083 rl_list_rx_init(struct rl_softc *sc)
1084 {
1085
1086 RL_LOCK_ASSERT(sc);
1087
1088 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1089 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1090 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1092
1093 return (0);
1094 }
1095
1096 /*
1097 * A frame has been uploaded: pass the resulting mbuf chain up to
1098 * the higher level protocols.
1099 *
1100 * You know there's something wrong with a PCI bus-master chip design
1101 * when you have to use m_devget().
1102 *
1103 * The receive operation is badly documented in the datasheet, so I'll
1104 * attempt to document it here. The driver provides a buffer area and
1105 * places its base address in the RX buffer start address register.
1106 * The chip then begins copying frames into the RX buffer. Each frame
1107 * is preceded by a 32-bit RX status word which specifies the length
1108 * of the frame and certain other status bits. Each frame (starting with
1109 * the status word) is also 32-bit aligned. The frame length is in the
1110 * first 16 bits of the status word; the lower 15 bits correspond with
1111 * the 'rx status register' mentioned in the datasheet.
1112 *
1113 * Note: to make the Alpha happy, the frame payload needs to be aligned
1114 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1115 * as the offset argument to m_devget().
1116 */
1117 static int
1118 rl_rxeof(struct rl_softc *sc)
1119 {
1120 struct mbuf *m;
1121 struct ifnet *ifp = sc->rl_ifp;
1122 uint8_t *rxbufpos;
1123 int total_len = 0;
1124 int wrap = 0;
1125 int rx_npkts = 0;
1126 uint32_t rxstat;
1127 uint16_t cur_rx;
1128 uint16_t limit;
1129 uint16_t max_bytes, rx_bytes = 0;
1130
1131 RL_LOCK_ASSERT(sc);
1132
1133 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1134 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1135
1136 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1137
1138 /* Do not try to read past this point. */
1139 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1140
1141 if (limit < cur_rx)
1142 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1143 else
1144 max_bytes = limit - cur_rx;
1145
1146 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1147 #ifdef DEVICE_POLLING
1148 if (ifp->if_capenable & IFCAP_POLLING) {
1149 if (sc->rxcycles <= 0)
1150 break;
1151 sc->rxcycles--;
1152 }
1153 #endif
1154 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1155 rxstat = le32toh(*(uint32_t *)rxbufpos);
1156
1157 /*
1158 * Here's a totally undocumented fact for you. When the
1159 * RealTek chip is in the process of copying a packet into
1160 * RAM for you, the length will be 0xfff0. If you spot a
1161 * packet header with this value, you need to stop. The
1162 * datasheet makes absolutely no mention of this and
1163 * RealTek should be shot for this.
1164 */
1165 total_len = rxstat >> 16;
1166 if (total_len == RL_RXSTAT_UNFINISHED)
1167 break;
1168
1169 if (!(rxstat & RL_RXSTAT_RXOK) ||
1170 total_len < ETHER_MIN_LEN ||
1171 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1172 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1173 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1174 rl_init_locked(sc);
1175 return (rx_npkts);
1176 }
1177
1178 /* No errors; receive the packet. */
1179 rx_bytes += total_len + 4;
1180
1181 /*
1182 * XXX The RealTek chip includes the CRC with every
1183 * received frame, and there's no way to turn this
1184 * behavior off (at least, I can't find anything in
1185 * the manual that explains how to do it) so we have
1186 * to trim off the CRC manually.
1187 */
1188 total_len -= ETHER_CRC_LEN;
1189
1190 /*
1191 * Avoid trying to read more bytes than we know
1192 * the chip has prepared for us.
1193 */
1194 if (rx_bytes > max_bytes)
1195 break;
1196
1197 rxbufpos = sc->rl_cdata.rl_rx_buf +
1198 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1199 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1200 rxbufpos = sc->rl_cdata.rl_rx_buf;
1201
1202 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1203 if (total_len > wrap) {
1204 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1205 NULL);
1206 if (m != NULL)
1207 m_copyback(m, wrap, total_len - wrap,
1208 sc->rl_cdata.rl_rx_buf);
1209 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1210 } else {
1211 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1212 NULL);
1213 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1214 }
1215
1216 /* Round up to 32-bit boundary. */
1217 cur_rx = (cur_rx + 3) & ~3;
1218 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1219
1220 if (m == NULL) {
1221 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1222 continue;
1223 }
1224
1225 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1226 RL_UNLOCK(sc);
1227 (*ifp->if_input)(ifp, m);
1228 RL_LOCK(sc);
1229 rx_npkts++;
1230 }
1231
1232 /* No need to sync Rx memory block as we didn't modify it. */
1233 return (rx_npkts);
1234 }
1235
1236 /*
1237 * A frame was downloaded to the chip. It's safe for us to clean up
1238 * the list buffers.
1239 */
1240 static void
1241 rl_txeof(struct rl_softc *sc)
1242 {
1243 struct ifnet *ifp = sc->rl_ifp;
1244 uint32_t txstat;
1245
1246 RL_LOCK_ASSERT(sc);
1247
1248 /*
1249 * Go through our tx list and free mbufs for those
1250 * frames that have been uploaded.
1251 */
1252 do {
1253 if (RL_LAST_TXMBUF(sc) == NULL)
1254 break;
1255 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1256 if (!(txstat & (RL_TXSTAT_TX_OK|
1257 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1258 break;
1259
1260 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24);
1261
1262 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1263 BUS_DMASYNC_POSTWRITE);
1264 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1265 m_freem(RL_LAST_TXMBUF(sc));
1266 RL_LAST_TXMBUF(sc) = NULL;
1267 /*
1268 * If there was a transmit underrun, bump the TX threshold.
1269 * Make sure not to overflow the 63 * 32byte we can address
1270 * with the 6 available bit.
1271 */
1272 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1273 (sc->rl_txthresh < 2016))
1274 sc->rl_txthresh += 32;
1275 if (txstat & RL_TXSTAT_TX_OK)
1276 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1277 else {
1278 int oldthresh;
1279 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1280 if ((txstat & RL_TXSTAT_TXABRT) ||
1281 (txstat & RL_TXSTAT_OUTOFWIN))
1282 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1283 oldthresh = sc->rl_txthresh;
1284 /* error recovery */
1285 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1286 rl_init_locked(sc);
1287 /* restore original threshold */
1288 sc->rl_txthresh = oldthresh;
1289 return;
1290 }
1291 RL_INC(sc->rl_cdata.last_tx);
1292 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1293 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1294
1295 if (RL_LAST_TXMBUF(sc) == NULL)
1296 sc->rl_watchdog_timer = 0;
1297 }
1298
1299 static void
1300 rl_twister_update(struct rl_softc *sc)
1301 {
1302 uint16_t linktest;
1303 /*
1304 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1305 * Linux driver. Values undocumented otherwise.
1306 */
1307 static const uint32_t param[4][4] = {
1308 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1309 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1310 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1311 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1312 };
1313
1314 /*
1315 * Tune the so-called twister registers of the RTL8139. These
1316 * are used to compensate for impedance mismatches. The
1317 * method for tuning these registers is undocumented and the
1318 * following procedure is collected from public sources.
1319 */
1320 switch (sc->rl_twister)
1321 {
1322 case CHK_LINK:
1323 /*
1324 * If we have a sufficient link, then we can proceed in
1325 * the state machine to the next stage. If not, then
1326 * disable further tuning after writing sane defaults.
1327 */
1328 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1329 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1330 sc->rl_twister = FIND_ROW;
1331 } else {
1332 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1333 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1334 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1335 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1336 sc->rl_twister = DONE;
1337 }
1338 break;
1339 case FIND_ROW:
1340 /*
1341 * Read how long it took to see the echo to find the tuning
1342 * row to use.
1343 */
1344 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1345 if (linktest == RL_CSCFG_ROW3)
1346 sc->rl_twist_row = 3;
1347 else if (linktest == RL_CSCFG_ROW2)
1348 sc->rl_twist_row = 2;
1349 else if (linktest == RL_CSCFG_ROW1)
1350 sc->rl_twist_row = 1;
1351 else
1352 sc->rl_twist_row = 0;
1353 sc->rl_twist_col = 0;
1354 sc->rl_twister = SET_PARAM;
1355 break;
1356 case SET_PARAM:
1357 if (sc->rl_twist_col == 0)
1358 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1359 CSR_WRITE_4(sc, RL_PARA7C,
1360 param[sc->rl_twist_row][sc->rl_twist_col]);
1361 if (++sc->rl_twist_col == 4) {
1362 if (sc->rl_twist_row == 3)
1363 sc->rl_twister = RECHK_LONG;
1364 else
1365 sc->rl_twister = DONE;
1366 }
1367 break;
1368 case RECHK_LONG:
1369 /*
1370 * For long cables, we have to double check to make sure we
1371 * don't mistune.
1372 */
1373 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1374 if (linktest == RL_CSCFG_ROW3)
1375 sc->rl_twister = DONE;
1376 else {
1377 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1378 sc->rl_twister = RETUNE;
1379 }
1380 break;
1381 case RETUNE:
1382 /* Retune for a shorter cable (try column 2) */
1383 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1384 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1385 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1386 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1387 sc->rl_twist_row--;
1388 sc->rl_twist_col = 0;
1389 sc->rl_twister = SET_PARAM;
1390 break;
1391
1392 case DONE:
1393 break;
1394 }
1395
1396 }
1397
1398 static void
1399 rl_tick(void *xsc)
1400 {
1401 struct rl_softc *sc = xsc;
1402 struct mii_data *mii;
1403 int ticks;
1404
1405 RL_LOCK_ASSERT(sc);
1406 /*
1407 * If we're doing the twister cable calibration, then we need to defer
1408 * watchdog timeouts. This is a no-op in normal operations, but
1409 * can falsely trigger when the cable calibration takes a while and
1410 * there was traffic ready to go when rl was started.
1411 *
1412 * We don't defer mii_tick since that updates the mii status, which
1413 * helps the twister process, at least according to similar patches
1414 * for the Linux driver I found online while doing the fixes. Worst
1415 * case is a few extra mii reads during calibration.
1416 */
1417 mii = device_get_softc(sc->rl_miibus);
1418 mii_tick(mii);
1419 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1420 rl_miibus_statchg(sc->rl_dev);
1421 if (sc->rl_twister_enable) {
1422 if (sc->rl_twister == DONE)
1423 rl_watchdog(sc);
1424 else
1425 rl_twister_update(sc);
1426 if (sc->rl_twister == DONE)
1427 ticks = hz;
1428 else
1429 ticks = hz / 10;
1430 } else {
1431 rl_watchdog(sc);
1432 ticks = hz;
1433 }
1434
1435 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1436 }
1437
1438 #ifdef DEVICE_POLLING
1439 static int
1440 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1441 {
1442 struct rl_softc *sc = ifp->if_softc;
1443 int rx_npkts = 0;
1444
1445 RL_LOCK(sc);
1446 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1447 rx_npkts = rl_poll_locked(ifp, cmd, count);
1448 RL_UNLOCK(sc);
1449 return (rx_npkts);
1450 }
1451
1452 static int
1453 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1454 {
1455 struct rl_softc *sc = ifp->if_softc;
1456 int rx_npkts;
1457
1458 RL_LOCK_ASSERT(sc);
1459
1460 sc->rxcycles = count;
1461 rx_npkts = rl_rxeof(sc);
1462 rl_txeof(sc);
1463
1464 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1465 rl_start_locked(ifp);
1466
1467 if (cmd == POLL_AND_CHECK_STATUS) {
1468 uint16_t status;
1469
1470 /* We should also check the status register. */
1471 status = CSR_READ_2(sc, RL_ISR);
1472 if (status == 0xffff)
1473 return (rx_npkts);
1474 if (status != 0)
1475 CSR_WRITE_2(sc, RL_ISR, status);
1476
1477 /* XXX We should check behaviour on receiver stalls. */
1478
1479 if (status & RL_ISR_SYSTEM_ERR) {
1480 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1481 rl_init_locked(sc);
1482 }
1483 }
1484 return (rx_npkts);
1485 }
1486 #endif /* DEVICE_POLLING */
1487
1488 static void
1489 rl_intr(void *arg)
1490 {
1491 struct rl_softc *sc = arg;
1492 struct ifnet *ifp = sc->rl_ifp;
1493 uint16_t status;
1494 int count;
1495
1496 RL_LOCK(sc);
1497
1498 if (sc->suspended)
1499 goto done_locked;
1500
1501 #ifdef DEVICE_POLLING
1502 if (ifp->if_capenable & IFCAP_POLLING)
1503 goto done_locked;
1504 #endif
1505
1506 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1507 goto done_locked2;
1508 status = CSR_READ_2(sc, RL_ISR);
1509 if (status == 0xffff || (status & RL_INTRS) == 0)
1510 goto done_locked;
1511 /*
1512 * Ours, disable further interrupts.
1513 */
1514 CSR_WRITE_2(sc, RL_IMR, 0);
1515 for (count = 16; count > 0; count--) {
1516 CSR_WRITE_2(sc, RL_ISR, status);
1517 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1518 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1519 rl_rxeof(sc);
1520 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1521 rl_txeof(sc);
1522 if (status & RL_ISR_SYSTEM_ERR) {
1523 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1524 rl_init_locked(sc);
1525 RL_UNLOCK(sc);
1526 return;
1527 }
1528 }
1529 status = CSR_READ_2(sc, RL_ISR);
1530 /* If the card has gone away, the read returns 0xffff. */
1531 if (status == 0xffff || (status & RL_INTRS) == 0)
1532 break;
1533 }
1534
1535 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1536 rl_start_locked(ifp);
1537
1538 done_locked2:
1539 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1540 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1541 done_locked:
1542 RL_UNLOCK(sc);
1543 }
1544
1545 /*
1546 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1547 * pointers to the fragment pointers.
1548 */
1549 static int
1550 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1551 {
1552 struct mbuf *m;
1553 bus_dma_segment_t txsegs[1];
1554 int error, nsegs, padlen;
1555
1556 RL_LOCK_ASSERT(sc);
1557
1558 m = *m_head;
1559 padlen = 0;
1560 /*
1561 * Hardware doesn't auto-pad, so we have to make sure
1562 * pad short frames out to the minimum frame length.
1563 */
1564 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1565 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1566 /*
1567 * The RealTek is brain damaged and wants longword-aligned
1568 * TX buffers, plus we can only have one fragment buffer
1569 * per packet. We have to copy pretty much all the time.
1570 */
1571 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1572 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1573 m = m_defrag(*m_head, M_NOWAIT);
1574 if (m == NULL) {
1575 m_freem(*m_head);
1576 *m_head = NULL;
1577 return (ENOMEM);
1578 }
1579 }
1580 *m_head = m;
1581
1582 if (padlen > 0) {
1583 /*
1584 * Make security-conscious people happy: zero out the
1585 * bytes in the pad area, since we don't know what
1586 * this mbuf cluster buffer's previous user might
1587 * have left in it.
1588 */
1589 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1590 m->m_pkthdr.len += padlen;
1591 m->m_len = m->m_pkthdr.len;
1592 }
1593
1594 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1595 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1596 if (error != 0)
1597 return (error);
1598 if (nsegs == 0) {
1599 m_freem(*m_head);
1600 *m_head = NULL;
1601 return (EIO);
1602 }
1603
1604 RL_CUR_TXMBUF(sc) = m;
1605 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1606 BUS_DMASYNC_PREWRITE);
1607 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1608
1609 return (0);
1610 }
1611
1612 /*
1613 * Main transmit routine.
1614 */
1615 static void
1616 rl_start(struct ifnet *ifp)
1617 {
1618 struct rl_softc *sc = ifp->if_softc;
1619
1620 RL_LOCK(sc);
1621 rl_start_locked(ifp);
1622 RL_UNLOCK(sc);
1623 }
1624
1625 static void
1626 rl_start_locked(struct ifnet *ifp)
1627 {
1628 struct rl_softc *sc = ifp->if_softc;
1629 struct mbuf *m_head = NULL;
1630
1631 RL_LOCK_ASSERT(sc);
1632
1633 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1634 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1635 return;
1636
1637 while (RL_CUR_TXMBUF(sc) == NULL) {
1638 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1639
1640 if (m_head == NULL)
1641 break;
1642
1643 if (rl_encap(sc, &m_head)) {
1644 if (m_head == NULL)
1645 break;
1646 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1647 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1648 break;
1649 }
1650
1651 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1652 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1653
1654 /* Transmit the frame. */
1655 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1656 RL_TXTHRESH(sc->rl_txthresh) |
1657 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1658
1659 RL_INC(sc->rl_cdata.cur_tx);
1660
1661 /* Set a timeout in case the chip goes out to lunch. */
1662 sc->rl_watchdog_timer = 5;
1663 }
1664
1665 /*
1666 * We broke out of the loop because all our TX slots are
1667 * full. Mark the NIC as busy until it drains some of the
1668 * packets from the queue.
1669 */
1670 if (RL_CUR_TXMBUF(sc) != NULL)
1671 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1672 }
1673
1674 static void
1675 rl_init(void *xsc)
1676 {
1677 struct rl_softc *sc = xsc;
1678
1679 RL_LOCK(sc);
1680 rl_init_locked(sc);
1681 RL_UNLOCK(sc);
1682 }
1683
1684 static void
1685 rl_init_locked(struct rl_softc *sc)
1686 {
1687 struct ifnet *ifp = sc->rl_ifp;
1688 struct mii_data *mii;
1689 uint32_t eaddr[2];
1690
1691 RL_LOCK_ASSERT(sc);
1692
1693 mii = device_get_softc(sc->rl_miibus);
1694
1695 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1696 return;
1697
1698 /*
1699 * Cancel pending I/O and free all RX/TX buffers.
1700 */
1701 rl_stop(sc);
1702
1703 rl_reset(sc);
1704 if (sc->rl_twister_enable) {
1705 /*
1706 * Reset twister register tuning state. The twister
1707 * registers and their tuning are undocumented, but
1708 * are necessary to cope with bad links. rl_twister =
1709 * DONE here will disable this entirely.
1710 */
1711 sc->rl_twister = CHK_LINK;
1712 }
1713
1714 /*
1715 * Init our MAC address. Even though the chipset
1716 * documentation doesn't mention it, we need to enter "Config
1717 * register write enable" mode to modify the ID registers.
1718 */
1719 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1720 bzero(eaddr, sizeof(eaddr));
1721 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1722 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1723 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1724 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1725
1726 /* Init the RX memory block pointer register. */
1727 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1728 RL_RX_8139_BUF_RESERVE);
1729 /* Init TX descriptors. */
1730 rl_list_tx_init(sc);
1731 /* Init Rx memory block. */
1732 rl_list_rx_init(sc);
1733
1734 /*
1735 * Enable transmit and receive.
1736 */
1737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1738
1739 /*
1740 * Set the initial TX and RX configuration.
1741 */
1742 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1743 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1744
1745 /* Set RX filter. */
1746 rl_rxfilter(sc);
1747
1748 #ifdef DEVICE_POLLING
1749 /* Disable interrupts if we are polling. */
1750 if (ifp->if_capenable & IFCAP_POLLING)
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1752 else
1753 #endif
1754 /* Enable interrupts. */
1755 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1756
1757 /* Set initial TX threshold */
1758 sc->rl_txthresh = RL_TX_THRESH_INIT;
1759
1760 /* Start RX/TX process. */
1761 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1762
1763 /* Enable receiver and transmitter. */
1764 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1765
1766 sc->rl_flags &= ~RL_FLAG_LINK;
1767 mii_mediachg(mii);
1768
1769 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1770
1771 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1772 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1773
1774 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1775 }
1776
1777 /*
1778 * Set media options.
1779 */
1780 static int
1781 rl_ifmedia_upd(struct ifnet *ifp)
1782 {
1783 struct rl_softc *sc = ifp->if_softc;
1784 struct mii_data *mii;
1785
1786 mii = device_get_softc(sc->rl_miibus);
1787
1788 RL_LOCK(sc);
1789 mii_mediachg(mii);
1790 RL_UNLOCK(sc);
1791
1792 return (0);
1793 }
1794
1795 /*
1796 * Report current media status.
1797 */
1798 static void
1799 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1800 {
1801 struct rl_softc *sc = ifp->if_softc;
1802 struct mii_data *mii;
1803
1804 mii = device_get_softc(sc->rl_miibus);
1805
1806 RL_LOCK(sc);
1807 mii_pollstat(mii);
1808 ifmr->ifm_active = mii->mii_media_active;
1809 ifmr->ifm_status = mii->mii_media_status;
1810 RL_UNLOCK(sc);
1811 }
1812
1813 static int
1814 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1815 {
1816 struct ifreq *ifr = (struct ifreq *)data;
1817 struct mii_data *mii;
1818 struct rl_softc *sc = ifp->if_softc;
1819 int error = 0, mask;
1820
1821 switch (command) {
1822 case SIOCSIFFLAGS:
1823 RL_LOCK(sc);
1824 if (ifp->if_flags & IFF_UP) {
1825 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1826 ((ifp->if_flags ^ sc->rl_if_flags) &
1827 (IFF_PROMISC | IFF_ALLMULTI)))
1828 rl_rxfilter(sc);
1829 else
1830 rl_init_locked(sc);
1831 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1832 rl_stop(sc);
1833 sc->rl_if_flags = ifp->if_flags;
1834 RL_UNLOCK(sc);
1835 break;
1836 case SIOCADDMULTI:
1837 case SIOCDELMULTI:
1838 RL_LOCK(sc);
1839 rl_rxfilter(sc);
1840 RL_UNLOCK(sc);
1841 break;
1842 case SIOCGIFMEDIA:
1843 case SIOCSIFMEDIA:
1844 mii = device_get_softc(sc->rl_miibus);
1845 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1846 break;
1847 case SIOCSIFCAP:
1848 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1849 #ifdef DEVICE_POLLING
1850 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1851 !(ifp->if_capenable & IFCAP_POLLING)) {
1852 error = ether_poll_register(rl_poll, ifp);
1853 if (error)
1854 return(error);
1855 RL_LOCK(sc);
1856 /* Disable interrupts */
1857 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1858 ifp->if_capenable |= IFCAP_POLLING;
1859 RL_UNLOCK(sc);
1860 return (error);
1861
1862 }
1863 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1864 ifp->if_capenable & IFCAP_POLLING) {
1865 error = ether_poll_deregister(ifp);
1866 /* Enable interrupts. */
1867 RL_LOCK(sc);
1868 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1869 ifp->if_capenable &= ~IFCAP_POLLING;
1870 RL_UNLOCK(sc);
1871 return (error);
1872 }
1873 #endif /* DEVICE_POLLING */
1874 if ((mask & IFCAP_WOL) != 0 &&
1875 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1876 if ((mask & IFCAP_WOL_UCAST) != 0)
1877 ifp->if_capenable ^= IFCAP_WOL_UCAST;
1878 if ((mask & IFCAP_WOL_MCAST) != 0)
1879 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1880 if ((mask & IFCAP_WOL_MAGIC) != 0)
1881 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1882 }
1883 break;
1884 default:
1885 error = ether_ioctl(ifp, command, data);
1886 break;
1887 }
1888
1889 return (error);
1890 }
1891
1892 static void
1893 rl_watchdog(struct rl_softc *sc)
1894 {
1895
1896 RL_LOCK_ASSERT(sc);
1897
1898 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1899 return;
1900
1901 device_printf(sc->rl_dev, "watchdog timeout\n");
1902 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1903
1904 rl_txeof(sc);
1905 rl_rxeof(sc);
1906 sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1907 rl_init_locked(sc);
1908 }
1909
1910 /*
1911 * Stop the adapter and free any mbufs allocated to the
1912 * RX and TX lists.
1913 */
1914 static void
1915 rl_stop(struct rl_softc *sc)
1916 {
1917 int i;
1918 struct ifnet *ifp = sc->rl_ifp;
1919
1920 RL_LOCK_ASSERT(sc);
1921
1922 sc->rl_watchdog_timer = 0;
1923 callout_stop(&sc->rl_stat_callout);
1924 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1925 sc->rl_flags &= ~RL_FLAG_LINK;
1926
1927 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1928 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1929 for (i = 0; i < RL_TIMEOUT; i++) {
1930 DELAY(10);
1931 if ((CSR_READ_1(sc, RL_COMMAND) &
1932 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1933 break;
1934 }
1935 if (i == RL_TIMEOUT)
1936 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1937
1938 /*
1939 * Free the TX list buffers.
1940 */
1941 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1942 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1943 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1944 sc->rl_cdata.rl_tx_dmamap[i],
1945 BUS_DMASYNC_POSTWRITE);
1946 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1947 sc->rl_cdata.rl_tx_dmamap[i]);
1948 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1949 sc->rl_cdata.rl_tx_chain[i] = NULL;
1950 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1951 0x0000000);
1952 }
1953 }
1954 }
1955
1956 /*
1957 * Device suspend routine. Stop the interface and save some PCI
1958 * settings in case the BIOS doesn't restore them properly on
1959 * resume.
1960 */
1961 static int
1962 rl_suspend(device_t dev)
1963 {
1964 struct rl_softc *sc;
1965
1966 sc = device_get_softc(dev);
1967
1968 RL_LOCK(sc);
1969 rl_stop(sc);
1970 rl_setwol(sc);
1971 sc->suspended = 1;
1972 RL_UNLOCK(sc);
1973
1974 return (0);
1975 }
1976
1977 /*
1978 * Device resume routine. Restore some PCI settings in case the BIOS
1979 * doesn't, re-enable busmastering, and restart the interface if
1980 * appropriate.
1981 */
1982 static int
1983 rl_resume(device_t dev)
1984 {
1985 struct rl_softc *sc;
1986 struct ifnet *ifp;
1987 int pmc;
1988 uint16_t pmstat;
1989
1990 sc = device_get_softc(dev);
1991 ifp = sc->rl_ifp;
1992
1993 RL_LOCK(sc);
1994
1995 if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
1996 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1997 /* Disable PME and clear PME status. */
1998 pmstat = pci_read_config(sc->rl_dev,
1999 pmc + PCIR_POWER_STATUS, 2);
2000 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2001 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2002 pci_write_config(sc->rl_dev,
2003 pmc + PCIR_POWER_STATUS, pmstat, 2);
2004 }
2005 /*
2006 * Clear WOL matching such that normal Rx filtering
2007 * wouldn't interfere with WOL patterns.
2008 */
2009 rl_clrwol(sc);
2010 }
2011
2012 /* reinitialize interface if necessary */
2013 if (ifp->if_flags & IFF_UP)
2014 rl_init_locked(sc);
2015
2016 sc->suspended = 0;
2017
2018 RL_UNLOCK(sc);
2019
2020 return (0);
2021 }
2022
2023 /*
2024 * Stop all chip I/O so that the kernel's probe routines don't
2025 * get confused by errant DMAs when rebooting.
2026 */
2027 static int
2028 rl_shutdown(device_t dev)
2029 {
2030 struct rl_softc *sc;
2031
2032 sc = device_get_softc(dev);
2033
2034 RL_LOCK(sc);
2035 rl_stop(sc);
2036 /*
2037 * Mark interface as down since otherwise we will panic if
2038 * interrupt comes in later on, which can happen in some
2039 * cases.
2040 */
2041 sc->rl_ifp->if_flags &= ~IFF_UP;
2042 rl_setwol(sc);
2043 RL_UNLOCK(sc);
2044
2045 return (0);
2046 }
2047
2048 static void
2049 rl_setwol(struct rl_softc *sc)
2050 {
2051 struct ifnet *ifp;
2052 int pmc;
2053 uint16_t pmstat;
2054 uint8_t v;
2055
2056 RL_LOCK_ASSERT(sc);
2057
2058 ifp = sc->rl_ifp;
2059 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2060 return;
2061 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2062 return;
2063
2064 /* Enable config register write. */
2065 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2066
2067 /* Enable PME. */
2068 v = CSR_READ_1(sc, sc->rl_cfg1);
2069 v &= ~RL_CFG1_PME;
2070 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2071 v |= RL_CFG1_PME;
2072 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2073
2074 v = CSR_READ_1(sc, sc->rl_cfg3);
2075 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2076 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2077 v |= RL_CFG3_WOL_MAGIC;
2078 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2079
2080 v = CSR_READ_1(sc, sc->rl_cfg5);
2081 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2082 v &= ~RL_CFG5_WOL_LANWAKE;
2083 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2084 v |= RL_CFG5_WOL_UCAST;
2085 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2086 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2087 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2088 v |= RL_CFG5_WOL_LANWAKE;
2089 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2090
2091 /* Config register write done. */
2092 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2093
2094 /* Request PME if WOL is requested. */
2095 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2096 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2097 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2098 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2099 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2100 }
2101
2102 static void
2103 rl_clrwol(struct rl_softc *sc)
2104 {
2105 struct ifnet *ifp;
2106 uint8_t v;
2107
2108 ifp = sc->rl_ifp;
2109 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2110 return;
2111
2112 /* Enable config register write. */
2113 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2114
2115 v = CSR_READ_1(sc, sc->rl_cfg3);
2116 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2117 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2118
2119 /* Config register write done. */
2120 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2121
2122 v = CSR_READ_1(sc, sc->rl_cfg5);
2123 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2124 v &= ~RL_CFG5_WOL_LANWAKE;
2125 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2126 }
Cache object: be2f13b4048734b0c216a5e585c67d75
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