rp_pci.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-4-Clause
    3  *
    4  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    5  * All rights reserved.
    6  *
    7  * PCI-specific part separated from:
    8  * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted prodived that the follwoing conditions
   12  * are met.
   13  * 1. Redistributions of source code must retain the above copyright 
   14  *    notive, this list of conditions and the following disclainer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials prodided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *       This product includes software developed by Comtrol Corporation.
   21  * 4. The name of Comtrol Corporation may not be used to endorse or 
   22  *    promote products derived from this software without specific 
   23  *    prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   26  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   28  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   29  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   31  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   35  * SUCH DAMAGE.
   36  */
   37 
   38 #include <sys/cdefs.h>
   39 __FBSDID("$FreeBSD$");
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/fcntl.h>
   44 #include <sys/malloc.h>
   45 #include <sys/conf.h>
   46 #include <sys/kernel.h>
   47 #include <sys/lock.h>
   48 #include <sys/module.h>
   49 #include <sys/mutex.h>
   50 #include <machine/resource.h>
   51 #include <machine/bus.h>
   52 #include <sys/bus.h>
   53 #include <sys/rman.h>
   54 
   55 #define ROCKET_C
   56 #include <dev/rp/rpreg.h>
   57 #include <dev/rp/rpvar.h>
   58 
   59 #include <dev/pci/pcireg.h>
   60 #include <dev/pci/pcivar.h>
   61 
   62 /* PCI IDs  */
   63 #define RP_VENDOR_ID            0x11FE
   64 #define RP_DEVICE_ID_32I        0x0001
   65 #define RP_DEVICE_ID_8I         0x0002
   66 #define RP_DEVICE_ID_16I        0x0003
   67 #define RP_DEVICE_ID_4Q         0x0004
   68 #define RP_DEVICE_ID_8O         0x0005
   69 #define RP_DEVICE_ID_8J         0x0006
   70 #define RP_DEVICE_ID_4J         0x0007
   71 #define RP_DEVICE_ID_6M         0x000C
   72 #define RP_DEVICE_ID_4M         0x000D
   73 #define RP_DEVICE_ID_UPCI_32    0x0801
   74 #define RP_DEVICE_ID_UPCI_16    0x0803
   75 #define RP_DEVICE_ID_UPCI_8O    0x0805
   76 
   77 /**************************************************************************
   78   MUDBAC remapped for PCI
   79 **************************************************************************/
   80 
   81 #define _CFG_INT_PCI    0x40
   82 #define _PCI_INT_FUNC   0x3A
   83 
   84 #define PCI_STROB       0x2000
   85 #define INTR_EN_PCI     0x0010
   86 
   87 /***************************************************************************
   88 Function: sPCIControllerEOI
   89 Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
   90 Call:     sPCIControllerEOI(CtlP)
   91           CONTROLLER_T *CtlP; Ptr to controller structure
   92 */
   93 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
   94 
   95 /***************************************************************************
   96 Function: sPCIGetControllerIntStatus
   97 Purpose:  Get the controller interrupt status
   98 Call:     sPCIGetControllerIntStatus(CtlP)
   99           CONTROLLER_T *CtlP; Ptr to controller structure
  100 Return:   Byte_t: The controller interrupt status in the lower 4
  101                          bits.  Bits 0 through 3 represent AIOP's 0
  102                          through 3 respectively.  If a bit is set that
  103                          AIOP is interrupting.  Bits 4 through 7 will
  104                          always be cleared.
  105 */
  106 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
  107 
  108 static devclass_t rp_devclass;
  109 
  110 static int rp_pciprobe(device_t dev);
  111 static int rp_pciattach(device_t dev);
  112 #ifdef notdef
  113 static int rp_pcidetach(device_t dev);
  114 static int rp_pcishutdown(device_t dev);
  115 #endif /* notdef */
  116 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
  117 static int sPCIInitController( CONTROLLER_t *CtlP,
  118                                int AiopNum,
  119                                int IRQNum,
  120                                Byte_t Frequency,
  121                                int PeriodicOnly,
  122                                int VendorDevice);
  123 static rp_aiop2rid_t rp_pci_aiop2rid;
  124 static rp_aiop2off_t rp_pci_aiop2off;
  125 static rp_ctlmask_t rp_pci_ctlmask;
  126 
  127 /*
  128  * The following functions are the pci-specific part
  129  * of rp driver.
  130  */
  131 
  132 static int
  133 rp_pciprobe(device_t dev)
  134 {
  135         char *s;
  136 
  137         s = NULL;
  138         if (pci_get_vendor(dev) == RP_VENDOR_ID)
  139                 s = "RocketPort PCI";
  140 
  141         if (s != NULL) {
  142                 device_set_desc(dev, s);
  143                 return (BUS_PROBE_DEFAULT);
  144         }
  145 
  146         return (ENXIO);
  147 }
  148 
  149 static int
  150 rp_pciattach(device_t dev)
  151 {
  152         int     num_ports, num_aiops;
  153         int     aiop;
  154         CONTROLLER_t    *ctlp;
  155         int     unit;
  156         int     retval;
  157 
  158         ctlp = device_get_softc(dev);
  159         bzero(ctlp, sizeof(*ctlp));
  160         ctlp->dev = dev;
  161         unit = device_get_unit(dev);
  162         ctlp->aiop2rid = rp_pci_aiop2rid;
  163         ctlp->aiop2off = rp_pci_aiop2off;
  164         ctlp->ctlmask = rp_pci_ctlmask;
  165 
  166         /* The IO ports of AIOPs for a PCI controller are continuous. */
  167         ctlp->io_num = 1;
  168         ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  169         ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  170         if (ctlp->io_rid == NULL || ctlp->io == NULL) {
  171                 device_printf(dev, "rp_pciattach: Out of memory.\n");
  172                 retval = ENOMEM;
  173                 goto nogo;
  174         }
  175 
  176         ctlp->bus_ctlp = NULL;
  177 
  178         switch (pci_get_device(dev)) {
  179         case RP_DEVICE_ID_UPCI_16:
  180         case RP_DEVICE_ID_UPCI_32:
  181         case RP_DEVICE_ID_UPCI_8O:
  182                 ctlp->io_rid[0] = PCIR_BAR(2);
  183                 break;
  184         default:
  185                 ctlp->io_rid[0] = PCIR_BAR(0);
  186                 break;
  187         }
  188         ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  189                 &ctlp->io_rid[0], RF_ACTIVE);
  190         if(ctlp->io[0] == NULL) {
  191                 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
  192                 retval = ENXIO;
  193                 goto nogo;
  194         }
  195 
  196         num_aiops = sPCIInitController(ctlp,
  197                                        MAX_AIOPS_PER_BOARD, 0,
  198                                        FREQ_DIS, 0, pci_get_device(dev));
  199 
  200         num_ports = 0;
  201         for(aiop=0; aiop < num_aiops; aiop++) {
  202                 sResetAiopByNum(ctlp, aiop);
  203                 num_ports += sGetAiopNumChan(ctlp, aiop);
  204         }
  205 
  206         retval = rp_attachcommon(ctlp, num_aiops, num_ports);
  207         if (retval != 0)
  208                 goto nogo;
  209 
  210         return (0);
  211 
  212 nogo:
  213         rp_pcireleaseresource(ctlp);
  214 
  215         return (retval);
  216 }
  217 
  218 static int
  219 rp_pcidetach(device_t dev)
  220 {
  221         CONTROLLER_t    *ctlp;
  222 
  223         ctlp = device_get_softc(dev);
  224         rp_pcireleaseresource(ctlp);
  225 
  226         return (0);
  227 }
  228 
  229 static int
  230 rp_pcishutdown(device_t dev)
  231 {
  232         CONTROLLER_t    *ctlp;
  233 
  234         ctlp = device_get_softc(dev);
  235         rp_pcireleaseresource(ctlp);
  236 
  237         return (0);
  238 }
  239 
  240 static void
  241 rp_pcireleaseresource(CONTROLLER_t *ctlp)
  242 {
  243         rp_releaseresource(ctlp);
  244         if (ctlp->io != NULL) {
  245                 if (ctlp->io[0] != NULL)
  246                         bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
  247                 free(ctlp->io, M_DEVBUF);
  248                 ctlp->io = NULL;
  249         }
  250         if (ctlp->io_rid != NULL) {
  251                 free(ctlp->io_rid, M_DEVBUF);
  252                 ctlp->io = NULL;
  253         }
  254 }
  255 
  256 static int
  257 sPCIInitController( CONTROLLER_t *CtlP,
  258                     int AiopNum,
  259                     int IRQNum,
  260                     Byte_t Frequency,
  261                     int PeriodicOnly,
  262                     int VendorDevice)
  263 {
  264         int             i;
  265 
  266         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
  267 
  268         sPCIControllerEOI(CtlP);
  269 
  270         /* Init AIOPs */
  271         CtlP->NumAiop = 0;
  272         for(i=0; i < AiopNum; i++)
  273         {
  274                 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
  275                 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
  276                 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
  277                 if(CtlP->AiopID[i] == AIOPID_NULL)      /* if AIOP does not exist */
  278                 {
  279                         break;                          /* done looking for AIOPs */
  280                 }
  281 
  282                 switch( VendorDevice ) {
  283                 case RP_DEVICE_ID_4Q:
  284                 case RP_DEVICE_ID_4J:
  285                 case RP_DEVICE_ID_4M:
  286                         CtlP->AiopNumChan[i] = 4;
  287                         break;
  288                 case RP_DEVICE_ID_6M:
  289                         CtlP->AiopNumChan[i] = 6;
  290                         break;
  291                 case RP_DEVICE_ID_8O:
  292                 case RP_DEVICE_ID_8J:
  293                 case RP_DEVICE_ID_8I:
  294                 case RP_DEVICE_ID_16I:
  295                 case RP_DEVICE_ID_32I:
  296                         CtlP->AiopNumChan[i] = 8;
  297                         break;
  298                 default:
  299 #ifdef notdef
  300                         CtlP->AiopNumChan[i] = 8;
  301 #else
  302                         CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
  303 #endif /* notdef */
  304                         break;
  305                 }
  306                 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
  307                 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);    /* clock prescaler */
  308                 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
  309                 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
  310                 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
  311                 CtlP->NumAiop++;                                /* bump count of AIOPs */
  312         }
  313 
  314         if(CtlP->NumAiop == 0)
  315                 return(-1);
  316         else
  317                 return(CtlP->NumAiop);
  318 }
  319 
  320 /*
  321  * ARGSUSED
  322  * Maps (aiop, offset) to rid.
  323  */
  324 static int
  325 rp_pci_aiop2rid(int aiop, int offset)
  326 {
  327         /* Always return zero for a PCI controller. */
  328         return 0;
  329 }
  330 
  331 /*
  332  * ARGSUSED
  333  * Maps (aiop, offset) to the offset of resource.
  334  */
  335 static int
  336 rp_pci_aiop2off(int aiop, int offset)
  337 {
  338         /* Each AIOP reserves 0x40 bytes. */
  339         return aiop * 0x40 + offset;
  340 }
  341 
  342 /* Read the int status for a PCI controller. */
  343 static unsigned char
  344 rp_pci_ctlmask(CONTROLLER_t *ctlp)
  345 {
  346         return sPCIGetControllerIntStatus(ctlp);
  347 }
  348 
  349 static device_method_t rp_pcimethods[] = {
  350         /* Device interface */
  351         DEVMETHOD(device_probe,         rp_pciprobe),
  352         DEVMETHOD(device_attach,        rp_pciattach),
  353         DEVMETHOD(device_detach,        rp_pcidetach),
  354         DEVMETHOD(device_shutdown,      rp_pcishutdown),
  355 
  356         { 0, 0 }
  357 };
  358 
  359 static driver_t rp_pcidriver = {
  360         "rp",
  361         rp_pcimethods,
  362         sizeof(CONTROLLER_t),
  363 };
  364 
  365 /*
  366  * rp can be attached to a pci bus.
  367  */
  368 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
Cache object: f5d88b3bb0648f4bec44ffe020a303eb
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FreeBSD/Linux Kernel Cross Reference sys/dev/rp/rp_pci.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/rp/rp_pci.c
