rp_pci.c

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    1 /* 
    2  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    3  * All rights reserved.
    4  *
    5  * PCI-specific part separated from:
    6  * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted prodived that the follwoing conditions
   10  * are met.
   11  * 1. Redistributions of source code must retain the above copyright 
   12  *    notive, this list of conditions and the following disclainer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials prodided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *       This product includes software developed by Comtrol Corporation.
   19  * 4. The name of Comtrol Corporation may not be used to endorse or 
   20  *    promote products derived from this software without specific 
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD$");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/fcntl.h>
   42 #include <sys/malloc.h>
   43 #include <sys/tty.h>
   44 #include <sys/conf.h>
   45 #include <sys/kernel.h>
   46 #include <machine/resource.h>
   47 #include <machine/bus.h>
   48 #include <sys/bus.h>
   49 #include <sys/rman.h>
   50 
   51 #define ROCKET_C
   52 #include <dev/rp/rpreg.h>
   53 #include <dev/rp/rpvar.h>
   54 
   55 #include <pci/pcireg.h>
   56 #include <pci/pcivar.h>
   57 
   58 /* PCI IDs  */
   59 #define RP_VENDOR_ID            0x11FE
   60 #define RP_DEVICE_ID_32I        0x0001
   61 #define RP_DEVICE_ID_8I         0x0002
   62 #define RP_DEVICE_ID_16I        0x0003
   63 #define RP_DEVICE_ID_4Q         0x0004
   64 #define RP_DEVICE_ID_8O         0x0005
   65 #define RP_DEVICE_ID_8J         0x0006
   66 #define RP_DEVICE_ID_4J         0x0007
   67 #define RP_DEVICE_ID_6M         0x000C
   68 #define RP_DEVICE_ID_4M         0x000D
   69 
   70 /**************************************************************************
   71   MUDBAC remapped for PCI
   72 **************************************************************************/
   73 
   74 #define _CFG_INT_PCI    0x40
   75 #define _PCI_INT_FUNC   0x3A
   76 
   77 #define PCI_STROB       0x2000
   78 #define INTR_EN_PCI     0x0010
   79 
   80 /***************************************************************************
   81 Function: sPCIControllerEOI
   82 Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
   83 Call:     sPCIControllerEOI(CtlP)
   84           CONTROLLER_T *CtlP; Ptr to controller structure
   85 */
   86 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
   87 
   88 /***************************************************************************
   89 Function: sPCIGetControllerIntStatus
   90 Purpose:  Get the controller interrupt status
   91 Call:     sPCIGetControllerIntStatus(CtlP)
   92           CONTROLLER_T *CtlP; Ptr to controller structure
   93 Return:   Byte_t: The controller interrupt status in the lower 4
   94                          bits.  Bits 0 through 3 represent AIOP's 0
   95                          through 3 respectively.  If a bit is set that
   96                          AIOP is interrupting.  Bits 4 through 7 will
   97                          always be cleared.
   98 */
   99 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
  100 
  101 static devclass_t rp_devclass;
  102 
  103 static int rp_pciprobe(device_t dev);
  104 static int rp_pciattach(device_t dev);
  105 #if notdef
  106 static int rp_pcidetach(device_t dev);
  107 static int rp_pcishutdown(device_t dev);
  108 #endif /* notdef */
  109 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
  110 static int sPCIInitController( CONTROLLER_t *CtlP,
  111                                int AiopNum,
  112                                int IRQNum,
  113                                Byte_t Frequency,
  114                                int PeriodicOnly,
  115                                int VendorDevice);
  116 static rp_aiop2rid_t rp_pci_aiop2rid;
  117 static rp_aiop2off_t rp_pci_aiop2off;
  118 static rp_ctlmask_t rp_pci_ctlmask;
  119 
  120 /*
  121  * The following functions are the pci-specific part
  122  * of rp driver.
  123  */
  124 
  125 static int
  126 rp_pciprobe(device_t dev)
  127 {
  128         char *s;
  129 
  130         s = NULL;
  131         if ((pci_get_devid(dev) & 0xffff) == RP_VENDOR_ID)
  132                 s = "RocketPort PCI";
  133 
  134         if (s != NULL) {
  135                 device_set_desc(dev, s);
  136                 return (0);
  137         }
  138 
  139         return (ENXIO);
  140 }
  141 
  142 static int
  143 rp_pciattach(device_t dev)
  144 {
  145         int     num_ports, num_aiops;
  146         int     aiop;
  147         CONTROLLER_t    *ctlp;
  148         int     unit;
  149         int     retval;
  150         u_int32_t       stcmd;
  151 
  152         ctlp = device_get_softc(dev);
  153         bzero(ctlp, sizeof(*ctlp));
  154         ctlp->dev = dev;
  155         unit = device_get_unit(dev);
  156         ctlp->aiop2rid = rp_pci_aiop2rid;
  157         ctlp->aiop2off = rp_pci_aiop2off;
  158         ctlp->ctlmask = rp_pci_ctlmask;
  159 
  160         /* Wake up the device. */
  161         stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
  162         if ((stcmd & PCIM_CMD_PORTEN) == 0) {
  163                 stcmd |= (PCIM_CMD_PORTEN);
  164                 pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
  165         }
  166 
  167         /* The IO ports of AIOPs for a PCI controller are continuous. */
  168         ctlp->io_num = 1;
  169         ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  170         ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  171         if (ctlp->io_rid == NULL || ctlp->io == NULL) {
  172                 device_printf(dev, "rp_pciattach: Out of memory.\n");
  173                 retval = ENOMEM;
  174                 goto nogo;
  175         }
  176 
  177         ctlp->bus_ctlp = NULL;
  178 
  179         ctlp->io_rid[0] = 0x10;
  180         ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 1, RF_ACTIVE);
  181         if(ctlp->io[0] == NULL) {
  182                 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
  183                 retval = ENXIO;
  184                 goto nogo;
  185         }
  186 
  187         num_aiops = sPCIInitController(ctlp,
  188                                        MAX_AIOPS_PER_BOARD, 0,
  189                                        FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff);
  190 
  191         num_ports = 0;
  192         for(aiop=0; aiop < num_aiops; aiop++) {
  193                 sResetAiopByNum(ctlp, aiop);
  194                 num_ports += sGetAiopNumChan(ctlp, aiop);
  195         }
  196 
  197         retval = rp_attachcommon(ctlp, num_aiops, num_ports);
  198         if (retval != 0)
  199                 goto nogo;
  200 
  201         return (0);
  202 
  203 nogo:
  204         rp_pcireleaseresource(ctlp);
  205 
  206         return (retval);
  207 }
  208 
  209 #if notdef
  210 static int
  211 rp_pcidetach(device_t dev)
  212 {
  213         CONTROLLER_t    *ctlp;
  214 
  215         if (device_get_state(dev) == DS_BUSY)
  216                 return (EBUSY);
  217 
  218         ctlp = device_get_softc(dev);
  219 
  220         rp_pcireleaseresource(ctlp);
  221 
  222         return (0);
  223 }
  224 
  225 static int
  226 rp_pcishutdown(device_t dev)
  227 {
  228         CONTROLLER_t    *ctlp;
  229 
  230         if (device_get_state(dev) == DS_BUSY)
  231                 return (EBUSY);
  232 
  233         ctlp = device_get_softc(dev);
  234 
  235         rp_pcireleaseresource(ctlp);
  236 
  237         return (0);
  238 }
  239 #endif /* notdef */
  240 
  241 static void
  242 rp_pcireleaseresource(CONTROLLER_t *ctlp)
  243 {
  244         rp_releaseresource(ctlp);
  245 
  246         if (ctlp->io != NULL) {
  247                 if (ctlp->io[0] != NULL)
  248                         bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
  249                 free(ctlp->io, M_DEVBUF);
  250         }
  251         if (ctlp->io_rid != NULL)
  252                 free(ctlp->io_rid, M_DEVBUF);
  253 }
  254 
  255 static int
  256 sPCIInitController( CONTROLLER_t *CtlP,
  257                     int AiopNum,
  258                     int IRQNum,
  259                     Byte_t Frequency,
  260                     int PeriodicOnly,
  261                     int VendorDevice)
  262 {
  263         int             i;
  264 
  265         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
  266 
  267         sPCIControllerEOI(CtlP);
  268 
  269         /* Init AIOPs */
  270         CtlP->NumAiop = 0;
  271         for(i=0; i < AiopNum; i++)
  272         {
  273                 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
  274                 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
  275                 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
  276                 if(CtlP->AiopID[i] == AIOPID_NULL)      /* if AIOP does not exist */
  277                 {
  278                         break;                          /* done looking for AIOPs */
  279                 }
  280 
  281                 switch( VendorDevice ) {
  282                 case RP_DEVICE_ID_4Q:
  283                 case RP_DEVICE_ID_4J:
  284                 case RP_DEVICE_ID_4M:
  285                         CtlP->AiopNumChan[i] = 4;
  286                         break;
  287                 case RP_DEVICE_ID_6M:
  288                         CtlP->AiopNumChan[i] = 6;
  289                         break;
  290                 case RP_DEVICE_ID_8O:
  291                 case RP_DEVICE_ID_8J:
  292                 case RP_DEVICE_ID_8I:
  293                 case RP_DEVICE_ID_16I:
  294                 case RP_DEVICE_ID_32I:
  295                         CtlP->AiopNumChan[i] = 8;
  296                         break;
  297                 default:
  298 #if notdef
  299                         CtlP->AiopNumChan[i] = 8;
  300 #else
  301                         CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
  302 #endif /* notdef */
  303                         break;
  304                 }
  305                 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
  306                 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);    /* clock prescaler */
  307                 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
  308                 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
  309                 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
  310                 CtlP->NumAiop++;                                /* bump count of AIOPs */
  311         }
  312 
  313         if(CtlP->NumAiop == 0)
  314                 return(-1);
  315         else
  316                 return(CtlP->NumAiop);
  317 }
  318 
  319 /*
  320  * ARGSUSED
  321  * Maps (aiop, offset) to rid.
  322  */
  323 static int
  324 rp_pci_aiop2rid(int aiop, int offset)
  325 {
  326         /* Always return zero for a PCI controller. */
  327         return 0;
  328 }
  329 
  330 /*
  331  * ARGSUSED
  332  * Maps (aiop, offset) to the offset of resource.
  333  */
  334 static int
  335 rp_pci_aiop2off(int aiop, int offset)
  336 {
  337         /* Each AIOP reserves 0x40 bytes. */
  338         return aiop * 0x40 + offset;
  339 }
  340 
  341 /* Read the int status for a PCI controller. */
  342 unsigned char
  343 rp_pci_ctlmask(CONTROLLER_t *ctlp)
  344 {
  345         return sPCIGetControllerIntStatus(ctlp);
  346 }
  347 
  348 static device_method_t rp_pcimethods[] = {
  349         /* Device interface */
  350         DEVMETHOD(device_probe,         rp_pciprobe),
  351         DEVMETHOD(device_attach,        rp_pciattach),
  352 #if notdef
  353         DEVMETHOD(device_detach,        rp_pcidetach),
  354         DEVMETHOD(device_shutdown,      rp_pcishutdown),
  355 #endif /* notdef */
  356 
  357         { 0, 0 }
  358 };
  359 
  360 static driver_t rp_pcidriver = {
  361         "rp",
  362         rp_pcimethods,
  363         sizeof(CONTROLLER_t),
  364 };
  365 
  366 /*
  367  * rp can be attached to a pci bus.
  368  */
  369 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
Cache object: 039090cc91c047e8ef0f595f00ca7b4c
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FreeBSD/Linux Kernel Cross Reference sys/dev/rp/rp_pci.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/rp/rp_pci.c
