The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/rp/rp_pci.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    3  * All rights reserved.
    4  *
    5  * PCI-specific part separated from:
    6  * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted prodived that the follwoing conditions
   10  * are met.
   11  * 1. Redistributions of source code must retain the above copyright 
   12  *    notive, this list of conditions and the following disclainer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials prodided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *       This product includes software developed by Comtrol Corporation.
   19  * 4. The name of Comtrol Corporation may not be used to endorse or 
   20  *    promote products derived from this software without specific 
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD: releng/6.4/sys/dev/rp/rp_pci.c 164873 2006-12-04 12:26:52Z marius $");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/fcntl.h>
   42 #include <sys/malloc.h>
   43 #include <sys/tty.h>
   44 #include <sys/conf.h>
   45 #include <sys/kernel.h>
   46 #include <sys/module.h>
   47 #include <machine/resource.h>
   48 #include <machine/bus.h>
   49 #include <sys/bus.h>
   50 #include <sys/rman.h>
   51 
   52 #define ROCKET_C
   53 #include <dev/rp/rpreg.h>
   54 #include <dev/rp/rpvar.h>
   55 
   56 #include <dev/pci/pcireg.h>
   57 #include <dev/pci/pcivar.h>
   58 
   59 /* PCI IDs  */
   60 #define RP_VENDOR_ID            0x11FE
   61 #define RP_DEVICE_ID_32I        0x0001
   62 #define RP_DEVICE_ID_8I         0x0002
   63 #define RP_DEVICE_ID_16I        0x0003
   64 #define RP_DEVICE_ID_4Q         0x0004
   65 #define RP_DEVICE_ID_8O         0x0005
   66 #define RP_DEVICE_ID_8J         0x0006
   67 #define RP_DEVICE_ID_4J         0x0007
   68 #define RP_DEVICE_ID_6M         0x000C
   69 #define RP_DEVICE_ID_4M         0x000D
   70 #define RP_DEVICE_ID_UPCI_32    0x0801
   71 #define RP_DEVICE_ID_UPCI_8O    0x0805
   72 
   73 /**************************************************************************
   74   MUDBAC remapped for PCI
   75 **************************************************************************/
   76 
   77 #define _CFG_INT_PCI    0x40
   78 #define _PCI_INT_FUNC   0x3A
   79 
   80 #define PCI_STROB       0x2000
   81 #define INTR_EN_PCI     0x0010
   82 
   83 /***************************************************************************
   84 Function: sPCIControllerEOI
   85 Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
   86 Call:     sPCIControllerEOI(CtlP)
   87           CONTROLLER_T *CtlP; Ptr to controller structure
   88 */
   89 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
   90 
   91 /***************************************************************************
   92 Function: sPCIGetControllerIntStatus
   93 Purpose:  Get the controller interrupt status
   94 Call:     sPCIGetControllerIntStatus(CtlP)
   95           CONTROLLER_T *CtlP; Ptr to controller structure
   96 Return:   Byte_t: The controller interrupt status in the lower 4
   97                          bits.  Bits 0 through 3 represent AIOP's 0
   98                          through 3 respectively.  If a bit is set that
   99                          AIOP is interrupting.  Bits 4 through 7 will
  100                          always be cleared.
  101 */
  102 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
  103 
  104 static devclass_t rp_devclass;
  105 
  106 static int rp_pciprobe(device_t dev);
  107 static int rp_pciattach(device_t dev);
  108 #ifdef notdef
  109 static int rp_pcidetach(device_t dev);
  110 static int rp_pcishutdown(device_t dev);
  111 #endif /* notdef */
  112 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
  113 static int sPCIInitController( CONTROLLER_t *CtlP,
  114                                int AiopNum,
  115                                int IRQNum,
  116                                Byte_t Frequency,
  117                                int PeriodicOnly,
  118                                int VendorDevice);
  119 static rp_aiop2rid_t rp_pci_aiop2rid;
  120 static rp_aiop2off_t rp_pci_aiop2off;
  121 static rp_ctlmask_t rp_pci_ctlmask;
  122 
  123 /*
  124  * The following functions are the pci-specific part
  125  * of rp driver.
  126  */
  127 
  128 static int
  129 rp_pciprobe(device_t dev)
  130 {
  131         char *s;
  132 
  133         s = NULL;
  134         if (pci_get_vendor(dev) == RP_VENDOR_ID)
  135                 s = "RocketPort PCI";
  136 
  137         if (s != NULL) {
  138                 device_set_desc(dev, s);
  139                 return (BUS_PROBE_DEFAULT);
  140         }
  141 
  142         return (ENXIO);
  143 }
  144 
  145 static int
  146 rp_pciattach(device_t dev)
  147 {
  148         int     num_ports, num_aiops;
  149         int     aiop;
  150         CONTROLLER_t    *ctlp;
  151         int     unit;
  152         int     retval;
  153         u_int32_t       stcmd;
  154 
  155         ctlp = device_get_softc(dev);
  156         bzero(ctlp, sizeof(*ctlp));
  157         ctlp->dev = dev;
  158         unit = device_get_unit(dev);
  159         ctlp->aiop2rid = rp_pci_aiop2rid;
  160         ctlp->aiop2off = rp_pci_aiop2off;
  161         ctlp->ctlmask = rp_pci_ctlmask;
  162 
  163         /* Wake up the device. */
  164         stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
  165         if ((stcmd & PCIM_CMD_PORTEN) == 0) {
  166                 stcmd |= (PCIM_CMD_PORTEN);
  167                 pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
  168         }
  169 
  170         /* The IO ports of AIOPs for a PCI controller are continuous. */
  171         ctlp->io_num = 1;
  172         ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  173         ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  174         if (ctlp->io_rid == NULL || ctlp->io == NULL) {
  175                 device_printf(dev, "rp_pciattach: Out of memory.\n");
  176                 retval = ENOMEM;
  177                 goto nogo;
  178         }
  179 
  180         ctlp->bus_ctlp = NULL;
  181 
  182         switch (pci_get_device(dev)) {
  183         case RP_DEVICE_ID_UPCI_32:
  184         case RP_DEVICE_ID_UPCI_8O:
  185                 ctlp->io_rid[0] = PCIR_BAR(2);
  186                 break;
  187         default:
  188                 ctlp->io_rid[0] = PCIR_BAR(0);
  189                 break;
  190         }
  191         ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  192                 &ctlp->io_rid[0], RF_ACTIVE);
  193         if(ctlp->io[0] == NULL) {
  194                 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
  195                 retval = ENXIO;
  196                 goto nogo;
  197         }
  198 
  199         num_aiops = sPCIInitController(ctlp,
  200                                        MAX_AIOPS_PER_BOARD, 0,
  201                                        FREQ_DIS, 0, pci_get_device(dev));
  202 
  203         num_ports = 0;
  204         for(aiop=0; aiop < num_aiops; aiop++) {
  205                 sResetAiopByNum(ctlp, aiop);
  206                 num_ports += sGetAiopNumChan(ctlp, aiop);
  207         }
  208 
  209         retval = rp_attachcommon(ctlp, num_aiops, num_ports);
  210         if (retval != 0)
  211                 goto nogo;
  212 
  213         return (0);
  214 
  215 nogo:
  216         rp_pcireleaseresource(ctlp);
  217 
  218         return (retval);
  219 }
  220 
  221 static int
  222 rp_pcidetach(device_t dev)
  223 {
  224         CONTROLLER_t    *ctlp;
  225 
  226         if (device_get_state(dev) == DS_BUSY)
  227                 return (EBUSY);
  228 
  229         ctlp = device_get_softc(dev);
  230 
  231         rp_pcireleaseresource(ctlp);
  232 
  233         return (0);
  234 }
  235 
  236 static int
  237 rp_pcishutdown(device_t dev)
  238 {
  239         CONTROLLER_t    *ctlp;
  240 
  241         if (device_get_state(dev) == DS_BUSY)
  242                 return (EBUSY);
  243 
  244         ctlp = device_get_softc(dev);
  245 
  246         rp_pcireleaseresource(ctlp);
  247 
  248         return (0);
  249 }
  250 
  251 static void
  252 rp_pcireleaseresource(CONTROLLER_t *ctlp)
  253 {
  254         rp_untimeout();
  255         if (ctlp->io != NULL) {
  256                 if (ctlp->io[0] != NULL)
  257                         bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
  258                 free(ctlp->io, M_DEVBUF);
  259                 ctlp->io = NULL;
  260         }
  261         if (ctlp->io_rid != NULL) {
  262                 free(ctlp->io_rid, M_DEVBUF);
  263                 ctlp->io = NULL;
  264         }
  265         rp_releaseresource(ctlp);
  266 }
  267 
  268 static int
  269 sPCIInitController( CONTROLLER_t *CtlP,
  270                     int AiopNum,
  271                     int IRQNum,
  272                     Byte_t Frequency,
  273                     int PeriodicOnly,
  274                     int VendorDevice)
  275 {
  276         int             i;
  277 
  278         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
  279 
  280         sPCIControllerEOI(CtlP);
  281 
  282         /* Init AIOPs */
  283         CtlP->NumAiop = 0;
  284         for(i=0; i < AiopNum; i++)
  285         {
  286                 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
  287                 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
  288                 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
  289                 if(CtlP->AiopID[i] == AIOPID_NULL)      /* if AIOP does not exist */
  290                 {
  291                         break;                          /* done looking for AIOPs */
  292                 }
  293 
  294                 switch( VendorDevice ) {
  295                 case RP_DEVICE_ID_4Q:
  296                 case RP_DEVICE_ID_4J:
  297                 case RP_DEVICE_ID_4M:
  298                         CtlP->AiopNumChan[i] = 4;
  299                         break;
  300                 case RP_DEVICE_ID_6M:
  301                         CtlP->AiopNumChan[i] = 6;
  302                         break;
  303                 case RP_DEVICE_ID_8O:
  304                 case RP_DEVICE_ID_8J:
  305                 case RP_DEVICE_ID_8I:
  306                 case RP_DEVICE_ID_16I:
  307                 case RP_DEVICE_ID_32I:
  308                         CtlP->AiopNumChan[i] = 8;
  309                         break;
  310                 default:
  311 #ifdef notdef
  312                         CtlP->AiopNumChan[i] = 8;
  313 #else
  314                         CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
  315 #endif /* notdef */
  316                         break;
  317                 }
  318                 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
  319                 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);    /* clock prescaler */
  320                 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
  321                 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
  322                 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
  323                 CtlP->NumAiop++;                                /* bump count of AIOPs */
  324         }
  325 
  326         if(CtlP->NumAiop == 0)
  327                 return(-1);
  328         else
  329                 return(CtlP->NumAiop);
  330 }
  331 
  332 /*
  333  * ARGSUSED
  334  * Maps (aiop, offset) to rid.
  335  */
  336 static int
  337 rp_pci_aiop2rid(int aiop, int offset)
  338 {
  339         /* Always return zero for a PCI controller. */
  340         return 0;
  341 }
  342 
  343 /*
  344  * ARGSUSED
  345  * Maps (aiop, offset) to the offset of resource.
  346  */
  347 static int
  348 rp_pci_aiop2off(int aiop, int offset)
  349 {
  350         /* Each AIOP reserves 0x40 bytes. */
  351         return aiop * 0x40 + offset;
  352 }
  353 
  354 /* Read the int status for a PCI controller. */
  355 static unsigned char
  356 rp_pci_ctlmask(CONTROLLER_t *ctlp)
  357 {
  358         return sPCIGetControllerIntStatus(ctlp);
  359 }
  360 
  361 static device_method_t rp_pcimethods[] = {
  362         /* Device interface */
  363         DEVMETHOD(device_probe,         rp_pciprobe),
  364         DEVMETHOD(device_attach,        rp_pciattach),
  365         DEVMETHOD(device_detach,        rp_pcidetach),
  366         DEVMETHOD(device_shutdown,      rp_pcishutdown),
  367 
  368         { 0, 0 }
  369 };
  370 
  371 static driver_t rp_pcidriver = {
  372         "rp",
  373         rp_pcimethods,
  374         sizeof(CONTROLLER_t),
  375 };
  376 
  377 /*
  378  * rp can be attached to a pci bus.
  379  */
  380 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);

Cache object: ef0784028efa033312648623062bdd3f


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.