rp_pci.c

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    1 /*-
    2  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    3  * All rights reserved.
    4  *
    5  * PCI-specific part separated from:
    6  * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted prodived that the follwoing conditions
   10  * are met.
   11  * 1. Redistributions of source code must retain the above copyright 
   12  *    notive, this list of conditions and the following disclainer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials prodided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *       This product includes software developed by Comtrol Corporation.
   19  * 4. The name of Comtrol Corporation may not be used to endorse or 
   20  *    promote products derived from this software without specific 
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD: releng/8.1/sys/dev/rp/rp_pci.c 191563 2009-04-27 15:58:38Z ambrisko $");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/fcntl.h>
   42 #include <sys/malloc.h>
   43 #include <sys/tty.h>
   44 #include <sys/conf.h>
   45 #include <sys/kernel.h>
   46 #include <sys/module.h>
   47 #include <machine/resource.h>
   48 #include <machine/bus.h>
   49 #include <sys/bus.h>
   50 #include <sys/rman.h>
   51 
   52 #define ROCKET_C
   53 #include <dev/rp/rpreg.h>
   54 #include <dev/rp/rpvar.h>
   55 
   56 #include <dev/pci/pcireg.h>
   57 #include <dev/pci/pcivar.h>
   58 
   59 /* PCI IDs  */
   60 #define RP_VENDOR_ID            0x11FE
   61 #define RP_DEVICE_ID_32I        0x0001
   62 #define RP_DEVICE_ID_8I         0x0002
   63 #define RP_DEVICE_ID_16I        0x0003
   64 #define RP_DEVICE_ID_4Q         0x0004
   65 #define RP_DEVICE_ID_8O         0x0005
   66 #define RP_DEVICE_ID_8J         0x0006
   67 #define RP_DEVICE_ID_4J         0x0007
   68 #define RP_DEVICE_ID_6M         0x000C
   69 #define RP_DEVICE_ID_4M         0x000D
   70 #define RP_DEVICE_ID_UPCI_32    0x0801
   71 #define RP_DEVICE_ID_UPCI_16    0x0803
   72 #define RP_DEVICE_ID_UPCI_8O    0x0805
   73 
   74 /**************************************************************************
   75   MUDBAC remapped for PCI
   76 **************************************************************************/
   77 
   78 #define _CFG_INT_PCI    0x40
   79 #define _PCI_INT_FUNC   0x3A
   80 
   81 #define PCI_STROB       0x2000
   82 #define INTR_EN_PCI     0x0010
   83 
   84 /***************************************************************************
   85 Function: sPCIControllerEOI
   86 Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
   87 Call:     sPCIControllerEOI(CtlP)
   88           CONTROLLER_T *CtlP; Ptr to controller structure
   89 */
   90 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
   91 
   92 /***************************************************************************
   93 Function: sPCIGetControllerIntStatus
   94 Purpose:  Get the controller interrupt status
   95 Call:     sPCIGetControllerIntStatus(CtlP)
   96           CONTROLLER_T *CtlP; Ptr to controller structure
   97 Return:   Byte_t: The controller interrupt status in the lower 4
   98                          bits.  Bits 0 through 3 represent AIOP's 0
   99                          through 3 respectively.  If a bit is set that
  100                          AIOP is interrupting.  Bits 4 through 7 will
  101                          always be cleared.
  102 */
  103 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
  104 
  105 static devclass_t rp_devclass;
  106 
  107 static int rp_pciprobe(device_t dev);
  108 static int rp_pciattach(device_t dev);
  109 #ifdef notdef
  110 static int rp_pcidetach(device_t dev);
  111 static int rp_pcishutdown(device_t dev);
  112 #endif /* notdef */
  113 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
  114 static int sPCIInitController( CONTROLLER_t *CtlP,
  115                                int AiopNum,
  116                                int IRQNum,
  117                                Byte_t Frequency,
  118                                int PeriodicOnly,
  119                                int VendorDevice);
  120 static rp_aiop2rid_t rp_pci_aiop2rid;
  121 static rp_aiop2off_t rp_pci_aiop2off;
  122 static rp_ctlmask_t rp_pci_ctlmask;
  123 
  124 /*
  125  * The following functions are the pci-specific part
  126  * of rp driver.
  127  */
  128 
  129 static int
  130 rp_pciprobe(device_t dev)
  131 {
  132         char *s;
  133 
  134         s = NULL;
  135         if (pci_get_vendor(dev) == RP_VENDOR_ID)
  136                 s = "RocketPort PCI";
  137 
  138         if (s != NULL) {
  139                 device_set_desc(dev, s);
  140                 return (BUS_PROBE_DEFAULT);
  141         }
  142 
  143         return (ENXIO);
  144 }
  145 
  146 static int
  147 rp_pciattach(device_t dev)
  148 {
  149         int     num_ports, num_aiops;
  150         int     aiop;
  151         CONTROLLER_t    *ctlp;
  152         int     unit;
  153         int     retval;
  154         u_int32_t       stcmd;
  155 
  156         ctlp = device_get_softc(dev);
  157         bzero(ctlp, sizeof(*ctlp));
  158         ctlp->dev = dev;
  159         unit = device_get_unit(dev);
  160         ctlp->aiop2rid = rp_pci_aiop2rid;
  161         ctlp->aiop2off = rp_pci_aiop2off;
  162         ctlp->ctlmask = rp_pci_ctlmask;
  163 
  164         /* Wake up the device. */
  165         stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
  166         if ((stcmd & PCIM_CMD_PORTEN) == 0) {
  167                 stcmd |= (PCIM_CMD_PORTEN);
  168                 pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
  169         }
  170 
  171         /* The IO ports of AIOPs for a PCI controller are continuous. */
  172         ctlp->io_num = 1;
  173         ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  174         ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
  175         if (ctlp->io_rid == NULL || ctlp->io == NULL) {
  176                 device_printf(dev, "rp_pciattach: Out of memory.\n");
  177                 retval = ENOMEM;
  178                 goto nogo;
  179         }
  180 
  181         ctlp->bus_ctlp = NULL;
  182 
  183         switch (pci_get_device(dev)) {
  184         case RP_DEVICE_ID_UPCI_16:
  185         case RP_DEVICE_ID_UPCI_32:
  186         case RP_DEVICE_ID_UPCI_8O:
  187                 ctlp->io_rid[0] = PCIR_BAR(2);
  188                 break;
  189         default:
  190                 ctlp->io_rid[0] = PCIR_BAR(0);
  191                 break;
  192         }
  193         ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  194                 &ctlp->io_rid[0], RF_ACTIVE);
  195         if(ctlp->io[0] == NULL) {
  196                 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
  197                 retval = ENXIO;
  198                 goto nogo;
  199         }
  200 
  201         num_aiops = sPCIInitController(ctlp,
  202                                        MAX_AIOPS_PER_BOARD, 0,
  203                                        FREQ_DIS, 0, pci_get_device(dev));
  204 
  205         num_ports = 0;
  206         for(aiop=0; aiop < num_aiops; aiop++) {
  207                 sResetAiopByNum(ctlp, aiop);
  208                 num_ports += sGetAiopNumChan(ctlp, aiop);
  209         }
  210 
  211         retval = rp_attachcommon(ctlp, num_aiops, num_ports);
  212         if (retval != 0)
  213                 goto nogo;
  214 
  215         return (0);
  216 
  217 nogo:
  218         rp_pcireleaseresource(ctlp);
  219 
  220         return (retval);
  221 }
  222 
  223 static int
  224 rp_pcidetach(device_t dev)
  225 {
  226         CONTROLLER_t    *ctlp;
  227 
  228         if (device_get_state(dev) == DS_BUSY)
  229                 return (EBUSY);
  230 
  231         ctlp = device_get_softc(dev);
  232 
  233         rp_pcireleaseresource(ctlp);
  234 
  235         return (0);
  236 }
  237 
  238 static int
  239 rp_pcishutdown(device_t dev)
  240 {
  241         CONTROLLER_t    *ctlp;
  242 
  243         if (device_get_state(dev) == DS_BUSY)
  244                 return (EBUSY);
  245 
  246         ctlp = device_get_softc(dev);
  247 
  248         rp_pcireleaseresource(ctlp);
  249 
  250         return (0);
  251 }
  252 
  253 static void
  254 rp_pcireleaseresource(CONTROLLER_t *ctlp)
  255 {
  256         rp_untimeout();
  257         if (ctlp->io != NULL) {
  258                 if (ctlp->io[0] != NULL)
  259                         bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
  260                 free(ctlp->io, M_DEVBUF);
  261                 ctlp->io = NULL;
  262         }
  263         if (ctlp->io_rid != NULL) {
  264                 free(ctlp->io_rid, M_DEVBUF);
  265                 ctlp->io = NULL;
  266         }
  267         rp_releaseresource(ctlp);
  268 }
  269 
  270 static int
  271 sPCIInitController( CONTROLLER_t *CtlP,
  272                     int AiopNum,
  273                     int IRQNum,
  274                     Byte_t Frequency,
  275                     int PeriodicOnly,
  276                     int VendorDevice)
  277 {
  278         int             i;
  279 
  280         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
  281 
  282         sPCIControllerEOI(CtlP);
  283 
  284         /* Init AIOPs */
  285         CtlP->NumAiop = 0;
  286         for(i=0; i < AiopNum; i++)
  287         {
  288                 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
  289                 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
  290                 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
  291                 if(CtlP->AiopID[i] == AIOPID_NULL)      /* if AIOP does not exist */
  292                 {
  293                         break;                          /* done looking for AIOPs */
  294                 }
  295 
  296                 switch( VendorDevice ) {
  297                 case RP_DEVICE_ID_4Q:
  298                 case RP_DEVICE_ID_4J:
  299                 case RP_DEVICE_ID_4M:
  300                         CtlP->AiopNumChan[i] = 4;
  301                         break;
  302                 case RP_DEVICE_ID_6M:
  303                         CtlP->AiopNumChan[i] = 6;
  304                         break;
  305                 case RP_DEVICE_ID_8O:
  306                 case RP_DEVICE_ID_8J:
  307                 case RP_DEVICE_ID_8I:
  308                 case RP_DEVICE_ID_16I:
  309                 case RP_DEVICE_ID_32I:
  310                         CtlP->AiopNumChan[i] = 8;
  311                         break;
  312                 default:
  313 #ifdef notdef
  314                         CtlP->AiopNumChan[i] = 8;
  315 #else
  316                         CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
  317 #endif /* notdef */
  318                         break;
  319                 }
  320                 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
  321                 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);    /* clock prescaler */
  322                 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
  323                 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
  324                 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
  325                 CtlP->NumAiop++;                                /* bump count of AIOPs */
  326         }
  327 
  328         if(CtlP->NumAiop == 0)
  329                 return(-1);
  330         else
  331                 return(CtlP->NumAiop);
  332 }
  333 
  334 /*
  335  * ARGSUSED
  336  * Maps (aiop, offset) to rid.
  337  */
  338 static int
  339 rp_pci_aiop2rid(int aiop, int offset)
  340 {
  341         /* Always return zero for a PCI controller. */
  342         return 0;
  343 }
  344 
  345 /*
  346  * ARGSUSED
  347  * Maps (aiop, offset) to the offset of resource.
  348  */
  349 static int
  350 rp_pci_aiop2off(int aiop, int offset)
  351 {
  352         /* Each AIOP reserves 0x40 bytes. */
  353         return aiop * 0x40 + offset;
  354 }
  355 
  356 /* Read the int status for a PCI controller. */
  357 static unsigned char
  358 rp_pci_ctlmask(CONTROLLER_t *ctlp)
  359 {
  360         return sPCIGetControllerIntStatus(ctlp);
  361 }
  362 
  363 static device_method_t rp_pcimethods[] = {
  364         /* Device interface */
  365         DEVMETHOD(device_probe,         rp_pciprobe),
  366         DEVMETHOD(device_attach,        rp_pciattach),
  367         DEVMETHOD(device_detach,        rp_pcidetach),
  368         DEVMETHOD(device_shutdown,      rp_pcishutdown),
  369 
  370         { 0, 0 }
  371 };
  372 
  373 static driver_t rp_pcidriver = {
  374         "rp",
  375         rp_pcimethods,
  376         sizeof(CONTROLLER_t),
  377 };
  378 
  379 /*
  380  * rp can be attached to a pci bus.
  381  */
  382 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
Cache object: f05933f4e30b9258167bb2933a9d6ed5
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FreeBSD/Linux Kernel Cross Reference sys/dev/rp/rp_pci.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/rp/rp_pci.c
