The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/rp/rpreg.h

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    1 /*-
    2  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted prodived that the follwoing conditions
    7  * are met.
    8  * 1. Redistributions of source code must retain the above copyright 
    9  *    notive, this list of conditions and the following disclainer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials prodided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *       This product includes software developed by Comtrol Corporation.
   16  * 4. The name of Comtrol Corporation may not be used to endorse or 
   17  *    promote products derived from this software without specific 
   18  *    prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/11.2/sys/dev/rp/rpreg.h 331722 2018-03-29 02:50:57Z eadler $
   33  */
   34 
   35 /*
   36  * Begin OS-specific defines -  rpreg.h - for RocketPort FreeBSD
   37  */
   38 
   39 typedef uint8_t Byte_t;
   40 typedef uint8_t ByteIO_t;
   41 
   42 typedef uint16_t Word_t;
   43 typedef uint16_t WordIO_t;
   44 
   45 typedef uint32_t DWord_t;
   46 typedef uint32_t DWordIO_t;
   47 
   48 #define rp_readio(size, ctlp, rid, offset) \
   49         (bus_read_##size(ctlp->io[rid], offset))
   50 #define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
   51         (bus_read_multi_##size(ctlp->io[rid], offset, addr, count))
   52 #define rp_writeio(size, ctlp, rid, offset, data) \
   53         (bus_write_##size(ctlp->io[rid], offset, data))
   54 #define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
   55         (bus_write_multi_##size(ctlp->io[rid], offset, addr, count))
   56 
   57 #define rp_readio1(ctlp, rid, offset)                           rp_readio(1, ctlp, rid, offset)
   58 #define rp_readio2(ctlp, rid, offset)                           rp_readio(2, ctlp, rid, offset)
   59 #define rp_readio4(ctlp, rid, offset)                           rp_readio(4, ctlp, rid, offset)
   60 #define rp_writeio1(ctlp, rid, offset, data)                    rp_writeio(1, ctlp, rid, offset, data)
   61 #define rp_writeio2(ctlp, rid, offset, data)                    rp_writeio(2, ctlp, rid, offset, data)
   62 #define rp_writeio4(ctlp, rid, offset, data)                    rp_writeio(4, ctlp, rid, offset, data)
   63 #define rp_readmultiio1(ctlp, rid, offset, addr, count)         rp_readmultiio(1, ctlp, rid, offset, addr, count) 
   64 #define rp_readmultiio2(ctlp, rid, offset, addr, count)         rp_readmultiio(2, ctlp, rid, offset, addr, count) 
   65 #define rp_readmultiio4(ctlp, rid, offset, addr, count)         rp_readmultiio(4, ctlp, rid, offset, addr, count) 
   66 #define rp_writemultiio1(ctlp, rid, offset, addr, count)        rp_writemultiio(1, ctlp, rid, offset, addr, count) 
   67 #define rp_writemultiio2(ctlp, rid, offset, addr, count)        rp_writemultiio(2, ctlp, rid, offset, addr, count) 
   68 #define rp_writemultiio4(ctlp, rid, offset, addr, count)        rp_writemultiio(4, ctlp, rid, offset, addr, count) 
   69 
   70 #define rp_readaiop1(ctlp, aiop, offset) \
   71         (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
   72 #define rp_readaiop2(ctlp, aiop, offset) \
   73         (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
   74 #define rp_readaiop4(ctlp, aiop, offset) \
   75         (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
   76 #define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
   77         (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   78 #define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
   79         (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   80 #define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
   81         (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   82 #define rp_writeaiop1(ctlp, aiop, offset, data) \
   83         (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
   84 #define rp_writeaiop2(ctlp, aiop, offset, data) \
   85         (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
   86 #define rp_writeaiop4(ctlp, aiop, offset, data) \
   87         (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
   88 #define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
   89         (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   90 #define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
   91         (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   92 #define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
   93         (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
   94 
   95 #define rp_readch1(chp, offset) \
   96         (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
   97 #define rp_readch2(chp, offset) \
   98         (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
   99 #define rp_readch4(chp, offset) \
  100         (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
  101 #define rp_readmultich1(chp, offset, addr, count) \
  102         (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  103 #define rp_readmultich2(chp, offset, addr, count) \
  104         (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  105 #define rp_readmultich4(chp, offset, addr, count) \
  106         (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  107 #define rp_writech1(chp, offset, data) \
  108         (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
  109 #define rp_writech2(chp, offset, data) \
  110         (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
  111 #define rp_writech4(chp, offset, data) \
  112         (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
  113 #define rp_writemultich1(chp, offset, addr, count) \
  114         (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  115 #define rp_writemultich2(chp, offset, addr, count) \
  116         (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  117 #define rp_writemultich4(chp, offset, addr, count) \
  118         (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
  119 
  120 /*
  121  * End of OS-specific defines
  122  */
  123 
  124 #define ROCKET_H
  125 
  126 #define CTL_SIZE 4
  127 #define AIOP_CTL_SIZE 4
  128 #define CHAN_AIOP_SIZE 8
  129 #define MAX_PORTS_PER_AIOP 8
  130 #define MAX_AIOPS_PER_BOARD 4
  131 #define MAX_PORTS_PER_BOARD 32
  132 
  133 /* Controller ID numbers */
  134 #define CTLID_NULL  -1              /* no controller exists */
  135 #define CTLID_0001  0x0001          /* controller release 1 */
  136 
  137 /* AIOP ID numbers, identifies AIOP type implementing channel */
  138 #define AIOPID_NULL -1              /* no AIOP or channel exists */
  139 #define AIOPID_0001 0x0001          /* AIOP release 1 */
  140 
  141 #define NULLDEV -1                  /* identifies non-existant device */
  142 #define NULLCTL -1                  /* identifies non-existant controller */
  143 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
  144 #define NULLAIOP -1                 /* identifies non-existant AIOP */
  145 #define NULLCHAN -1                 /* identifies non-existant channel */
  146 
  147 /************************************************************************
  148  Global Register Offsets - Direct Access - Fixed values
  149 ************************************************************************/
  150 
  151 #define _CMD_REG   0x38   /* Command Register            8    Write */
  152 #define _INT_CHAN  0x39   /* Interrupt Channel Register  8    Read */
  153 #define _INT_MASK  0x3A   /* Interrupt Mask Register     8    Read / Write */
  154 #define _UNUSED    0x3B   /* Unused                      8 */
  155 #define _INDX_ADDR 0x3C   /* Index Register Address      16   Write */
  156 #define _INDX_DATA 0x3E   /* Index Register Data         8/16 Read / Write */
  157 
  158 /************************************************************************
  159  Channel Register Offsets for 1st channel in AIOP - Direct Access
  160 ************************************************************************/
  161 #define _TD0       0x00  /* Transmit Data               16   Write */
  162 #define _RD0       0x00  /* Receive Data                16   Read */
  163 #define _CHN_STAT0 0x20  /* Channel Status              8/16 Read / Write */
  164 #define _FIFO_CNT0 0x10  /* Transmit/Receive FIFO Count 16   Read */
  165 #define _INT_ID0   0x30  /* Interrupt Identification    8    Read */
  166 
  167 /************************************************************************
  168  Tx Control Register Offsets - Indexed - External - Fixed
  169 ************************************************************************/
  170 #define _TX_ENBLS  0x980    /* Tx Processor Enables Register 8 Read / Write */
  171 #define _TXCMP1    0x988    /* Transmit Compare Value #1     8 Read / Write */
  172 #define _TXCMP2    0x989    /* Transmit Compare Value #2     8 Read / Write */
  173 #define _TXREP1B1  0x98A    /* Tx Replace Value #1 - Byte 1  8 Read / Write */
  174 #define _TXREP1B2  0x98B    /* Tx Replace Value #1 - Byte 2  8 Read / Write */
  175 #define _TXREP2    0x98C    /* Transmit Replace Value #2     8 Read / Write */
  176 
  177 /************************************************************************
  178  Receive FIFO
  179 ************************************************************************/
  180 #define RXFIFO_DATA     0x5f
  181 #define RXFIFO_OUT      0x5c
  182 #define RXFIFO_EN       0x08
  183 #define RXFIFO_DIS      0xa7
  184 
  185 /************************************************************************
  186 Memory Controller Register Offsets - Indexed - External - Fixed
  187 ************************************************************************/
  188 #define _RX_FIFO    0x000    /* Rx FIFO */
  189 #define _TX_FIFO    0x800    /* Tx FIFO */
  190 #define _RXF_OUTP   0x990    /* Rx FIFO OUT pointer        16 Read / Write */
  191 #define _RXF_INP    0x992    /* Rx FIFO IN pointer         16 Read / Write */
  192 #define _TXF_OUTP   0x994    /* Tx FIFO OUT pointer        8  Read / Write */
  193 #define _TXF_INP    0x995    /* Tx FIFO IN pointer         8  Read / Write */
  194 #define _TXP_CNT    0x996    /* Tx Priority Count          8  Read / Write */
  195 #define _TXP_PNTR   0x997    /* Tx Priority Pointer        8  Read / Write */
  196 
  197 #define PRI_PEND    0x80     /* Priority data pending (bit7, Tx pri cnt) */
  198 #define TXFIFO_SIZE 255      /* size of Tx FIFO */
  199 #define RXFIFO_SIZE 1023     /* size of Rx FIFO */
  200 
  201 /************************************************************************
  202 Tx Priority Buffer - Indexed - External - Fixed
  203 ************************************************************************/
  204 #define _TXP_BUF    0x9C0    /* Tx Priority Buffer  32  Bytes   Read / Write */
  205 #define TXP_SIZE    0x20     /* 32 bytes */
  206 
  207 /************************************************************************
  208 Channel Register Offsets - Indexed - Internal - Fixed
  209 ************************************************************************/
  210 
  211 #define _TX_CTRL    0xFF0    /* Transmit Control               16  Write */
  212 #define _RX_CTRL    0xFF2    /* Receive Control                 8  Write */
  213 #define _BAUD       0xFF4    /* Baud Rate                      16  Write */
  214 #define _CLK_PRE    0xFF6    /* Clock Prescaler                 8  Write */
  215 
  216 #define CLOCK_PRESC 0x19          /* mod 9 (divide by 10) prescale */
  217 
  218 #define BRD50             4607
  219 #define BRD75             3071
  220 #define BRD110            2094
  221 #define BRD134            1712
  222 #define BRD150            1535
  223 #define BRD200            1151
  224 #define BRD300            767
  225 #define BRD600            383
  226 #define BRD1200           191
  227 #define BRD1800           127
  228 #define BRD2000           114
  229 #define BRD2400           95
  230 #define BRD3600           64
  231 #define BRD4800           47
  232 #define BRD7200           31
  233 #define BRD9600           23
  234 #define BRD14400          15
  235 #define BRD19200          11
  236 #define BRD38400          5
  237 #define BRD57600          3
  238 #define BRD76800          2
  239 #define BRD115200         1
  240 #define BRD230400         0
  241 
  242 #define STMBREAK   0x08        /* BREAK */
  243 #define STMFRAME   0x04        /* framing error */
  244 #define STMRCVROVR 0x02        /* receiver over run error */
  245 #define STMPARITY  0x01        /* parity error */
  246 #define STMERROR   (STMBREAK | STMFRAME | STMPARITY)
  247 #define STMBREAKH   0x800      /* BREAK */
  248 #define STMFRAMEH   0x400      /* framing error */
  249 #define STMRCVROVRH 0x200      /* receiver over run error */
  250 #define STMPARITYH  0x100      /* parity error */
  251 #define STMERRORH   (STMBREAKH | STMFRAMEH | STMPARITYH)
  252 
  253 #define CTS_ACT   0x20        /* CTS input asserted */
  254 #define DSR_ACT   0x10        /* DSR input asserted */
  255 #define CD_ACT    0x08        /* CD input asserted */
  256 #define TXFIFOMT  0x04        /* Tx FIFO is empty */
  257 #define TXSHRMT   0x02        /* Tx shift register is empty */
  258 #define RDA       0x01        /* Rx data available */
  259 #define DRAINED (TXFIFOMT | TXSHRMT)  /* indicates Tx is drained */
  260 
  261 #define STATMODE  0x8000      /* status mode enable bit */
  262 #define RXFOVERFL 0x2000      /* receive FIFO overflow */
  263 #define RX2MATCH  0x1000      /* receive compare byte 2 match */
  264 #define RX1MATCH  0x0800      /* receive compare byte 1 match */
  265 #define RXBREAK   0x0400      /* received BREAK */
  266 #define RXFRAME   0x0200      /* received framing error */
  267 #define RXPARITY  0x0100      /* received parity error */
  268 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
  269 
  270 #define CTSFC_EN  0x80        /* CTS flow control enable bit */
  271 #define RTSTOG_EN 0x40        /* RTS toggle enable bit */
  272 #define TXINT_EN  0x10        /* transmit interrupt enable */
  273 #define STOP2     0x08        /* enable 2 stop bits (0 = 1 stop) */
  274 #define PARITY_EN 0x04        /* enable parity (0 = no parity) */
  275 #define EVEN_PAR  0x02        /* even parity (0 = odd parity) */
  276 #define DATA8BIT  0x01        /* 8 bit data (0 = 7 bit data) */
  277 
  278 #define SETBREAK  0x10        /* send break condition (must clear) */
  279 #define LOCALLOOP 0x08        /* local loopback set for test */
  280 #define SET_DTR   0x04        /* assert DTR */
  281 #define SET_RTS   0x02        /* assert RTS */
  282 #define TX_ENABLE 0x01        /* enable transmitter */
  283 
  284 #define RTSFC_EN  0x40        /* RTS flow control enable */
  285 #define RXPROC_EN 0x20        /* receive processor enable */
  286 #define TRIG_NO   0x00        /* Rx FIFO trigger level 0 (no trigger) */
  287 #define TRIG_1    0x08        /* trigger level 1 char */
  288 #define TRIG_1_2  0x10        /* trigger level 1/2 */
  289 #define TRIG_7_8  0x18        /* trigger level 7/8 */
  290 #define TRIG_MASK 0x18        /* trigger level mask */
  291 #define SRCINT_EN 0x04        /* special Rx condition interrupt enable */
  292 #define RXINT_EN  0x02        /* Rx interrupt enable */
  293 #define MCINT_EN  0x01        /* modem change interrupt enable */
  294 
  295 #define RXF_TRIG  0x20        /* Rx FIFO trigger level interrupt */
  296 #define TXFIFO_MT 0x10        /* Tx FIFO empty interrupt */
  297 #define SRC_INT   0x08        /* special receive condition interrupt */
  298 #define DELTA_CD  0x04        /* CD change interrupt */
  299 #define DELTA_CTS 0x02        /* CTS change interrupt */
  300 #define DELTA_DSR 0x01        /* DSR change interrupt */
  301 
  302 #define REP1W2_EN 0x10        /* replace byte 1 with 2 bytes enable */
  303 #define IGN2_EN   0x08        /* ignore byte 2 enable */
  304 #define IGN1_EN   0x04        /* ignore byte 1 enable */
  305 #define COMP2_EN  0x02        /* compare byte 2 enable */
  306 #define COMP1_EN  0x01        /* compare byte 1 enable */
  307 
  308 #define RESET_ALL 0x80        /* reset AIOP (all channels) */
  309 #define TXOVERIDE 0x40        /* Transmit software off override */
  310 #define RESETUART 0x20        /* reset channel's UART */
  311 #define RESTXFCNT 0x10        /* reset channel's Tx FIFO count register */
  312 #define RESRXFCNT 0x08        /* reset channel's Rx FIFO count register */
  313 
  314 #define INTSTAT0  0x01        /* AIOP 0 interrupt status */
  315 #define INTSTAT1  0x02        /* AIOP 1 interrupt status */
  316 #define INTSTAT2  0x04        /* AIOP 2 interrupt status */
  317 #define INTSTAT3  0x08        /* AIOP 3 interrupt status */
  318 
  319 #define INTR_EN   0x08        /* allow interrupts to host */
  320 #define INT_STROB 0x04        /* strobe and clear interrupt line (EOI) */
  321 
  322 #define CHAN3_EN  0x08        /* enable AIOP 3 */
  323 #define CHAN2_EN  0x04        /* enable AIOP 2 */
  324 #define CHAN1_EN  0x02        /* enable AIOP 1 */
  325 #define CHAN0_EN  0x01        /* enable AIOP 0 */
  326 #define FREQ_DIS  0x00
  327 #define FREQ_274HZ 0x60
  328 #define FREQ_137HZ 0x50
  329 #define FREQ_69HZ  0x40
  330 #define FREQ_34HZ  0x30
  331 #define FREQ_17HZ  0x20
  332 #define FREQ_9HZ   0x10
  333 #define PERIODIC_ONLY 0x80    /* only PERIODIC interrupt */
  334 
  335 #define CHANINT_EN 0x0100           /* flags to enable/disable channel ints */
  336 
  337 #define RDATASIZE 72
  338 #define RREGDATASIZE 52
  339 
  340 #ifndef TRUE
  341 #define TRUE 1
  342 #endif
  343 
  344 #ifndef FALSE
  345 #define FALSE 0
  346 #endif
  347 
  348 struct CONTROLLER_str;
  349 struct CHANNEL_str;
  350 
  351 /* The types of bus-specific methods */
  352 typedef int rp_aiop2rid_t(int, int);
  353 typedef int rp_aiop2off_t(int, int);
  354 typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
  355 
  356 /* Controller level information structure */
  357 struct CONTROLLER_str
  358 {
  359         int             CtlID;
  360         int             NumAiop;
  361         int             AiopID[AIOP_CTL_SIZE];
  362         int             AiopNumChan[AIOP_CTL_SIZE];
  363 
  364         struct mtx      hwmtx;     /* Spinlock protecting hardware. */
  365         int             hwmtx_init;
  366         int             free;
  367         int             num_ports;
  368 
  369         /* Device and resource management */
  370         device_t                dev;            /* device */
  371         int                     io_num;         /* Number of IO resources */
  372         int                     *io_rid;        /* IO resource IDs */
  373         struct resource         **io;           /* IO resources */
  374 
  375         struct rp_port          *rp;            /* port */
  376 
  377         /* Device nodes */
  378         struct cdev **dev_nodes;
  379 
  380         /* Bus-specific properties */
  381         void                    *bus_ctlp;
  382 
  383         /* Bus-specific methods */
  384         rp_aiop2rid_t           *aiop2rid;      /* (aiop, offset) -> rid */
  385         rp_aiop2off_t           *aiop2off;      /* (aiop, offset) -> off */
  386         rp_ctlmask_t            *ctlmask;       /* Int status */
  387 };
  388 typedef struct CONTROLLER_str CONTROLLER_T;
  389 typedef CONTROLLER_T CONTROLLER_t;
  390 
  391 /* Channel level information structure */
  392 struct CHANNEL_str
  393 {
  394         CONTROLLER_t    *CtlP;
  395         int             AiopNum;
  396         int             ChanID;
  397         int             ChanNum;
  398 
  399         Word_t          TxFIFO;
  400         Word_t          TxFIFOPtrs;
  401         Word_t          RxFIFO;
  402         Word_t          RxFIFOPtrs;
  403         Word_t          TxPrioCnt;
  404         Word_t          TxPrioPtr;
  405         Word_t          TxPrioBuf;
  406 
  407         Byte_t          R[RREGDATASIZE];
  408 
  409         Byte_t          BaudDiv[4];
  410         Byte_t          TxControl[4];
  411         Byte_t          RxControl[4];
  412         Byte_t          TxEnables[4];
  413         Byte_t          TxCompare[4];
  414         Byte_t          TxReplace1[4];
  415         Byte_t          TxReplace2[4];
  416 };
  417 
  418 typedef struct CHANNEL_str CHANNEL_T;
  419 typedef CHANNEL_T CHANNEL_t;
  420 typedef CHANNEL_T * CHANPTR_T;
  421 
  422 #define CHNOFF_TXRXDATA(chp)    ((chp)->ChanNum * 2 + _TD0)
  423 #define CHNOFF_CHANSTAT(chp)    ((chp)->ChanNum * 2 + _CHN_STAT0)
  424 #define CHNOFF_TXRXCOUNT(chp)   ((chp)->ChanNum * 2 + _FIFO_CNT0)
  425 #define CHNOFF_INTID(chp)       ((chp)->ChanNum     + _INT_ID0)
  426 
  427 /***************************************************************************
  428 Function: sClrBreak
  429 Purpose:  Stop sending a transmit BREAK signal
  430 Call:     sClrBreak(ChP)
  431           CHANNEL_T *ChP; Ptr to channel structure
  432 */
  433 #define sClrBreak(ChP) \
  434 { \
  435    (ChP)->TxControl[3] &= ~SETBREAK; \
  436    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  437 }
  438 
  439 /***************************************************************************
  440 Function: sClrDTR
  441 Purpose:  Clr the DTR output
  442 Call:     sClrDTR(ChP)
  443           CHANNEL_T *ChP; Ptr to channel structure
  444 */
  445 #define sClrDTR(ChP) \
  446 { \
  447    (ChP)->TxControl[3] &= ~SET_DTR; \
  448    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  449 }
  450 
  451 /***************************************************************************
  452 Function: sClrRTS
  453 Purpose:  Clr the RTS output
  454 Call:     sClrRTS(ChP)
  455           CHANNEL_T *ChP; Ptr to channel structure
  456 */
  457 #define sClrRTS(ChP) \
  458 { \
  459    (ChP)->TxControl[3] &= ~SET_RTS; \
  460    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  461 }
  462 
  463 /***************************************************************************
  464 Function: sClrTxXOFF
  465 Purpose:  Clear any existing transmit software flow control off condition
  466 Call:     sClrTxXOFF(ChP)
  467           CHANNEL_T *ChP; Ptr to channel structure
  468 */
  469 #define sClrTxXOFF(ChP) \
  470 { \
  471    rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
  472    rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
  473 }
  474 
  475 /***************************************************************************
  476 Function: sDisCTSFlowCtl
  477 Purpose:  Disable output flow control using CTS
  478 Call:     sDisCTSFlowCtl(ChP)
  479           CHANNEL_T *ChP; Ptr to channel structure
  480 */
  481 #define sDisCTSFlowCtl(ChP) \
  482 { \
  483    (ChP)->TxControl[2] &= ~CTSFC_EN; \
  484    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  485 }
  486 
  487 /***************************************************************************
  488 Function: DisParity
  489 Purpose:  Disable parity
  490 Call:     sDisParity(ChP)
  491           CHANNEL_T *ChP; Ptr to channel structure
  492 Comments: Function sSetParity() can be used in place of functions sEnParity(),
  493           sDisParity(), sSetOddParity(), and sSetEvenParity().
  494 */
  495 #define sDisParity(ChP) \
  496 { \
  497    (ChP)->TxControl[2] &= ~PARITY_EN; \
  498    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  499 }
  500 
  501 /***************************************************************************
  502 Function: sDisRxFIFO
  503 Purpose:  Disable Rx FIFO
  504 Call:     sDisRxFIFO(ChP)
  505           CHANNEL_T *ChP; Ptr to channel structure
  506 */
  507 #define sDisRxFIFO(ChP) \
  508 { \
  509    (ChP)->R[0x32] = 0x0a; \
  510    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \
  511 }
  512 
  513 /***************************************************************************
  514 Function: sDisRxStatusMode
  515 Purpose:  Disable the Rx status mode
  516 Call:     sDisRxStatusMode(ChP)
  517           CHANNEL_T *ChP; Ptr to channel structure
  518 Comments: This takes the channel out of the receive status mode.  All
  519           subsequent reads of receive data using sReadRxWord() will return
  520           two data bytes.
  521 */
  522 #define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
  523 
  524 /***************************************************************************
  525 Function: sDisTransmit
  526 Purpose:  Disable transmit
  527 Call:     sDisTransmit(ChP)
  528           CHANNEL_T *ChP; Ptr to channel structure
  529           This disables movement of Tx data from the Tx FIFO into the 1 byte
  530           Tx buffer.  Therefore there could be up to a 2 byte latency
  531           between the time sDisTransmit() is called and the transmit buffer
  532           and transmit shift register going completely empty.
  533 */
  534 #define sDisTransmit(ChP) \
  535 { \
  536    (ChP)->TxControl[3] &= ~TX_ENABLE; \
  537    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  538 }
  539 
  540 /***************************************************************************
  541 Function: sDisTxSoftFlowCtl
  542 Purpose:  Disable Tx Software Flow Control
  543 Call:     sDisTxSoftFlowCtl(ChP)
  544           CHANNEL_T *ChP; Ptr to channel structure
  545 */
  546 #define sDisTxSoftFlowCtl(ChP) \
  547 { \
  548    (ChP)->R[0x06] = 0x8a; \
  549    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x04)); \
  550 }
  551 
  552 /***************************************************************************
  553 Function: sEnCTSFlowCtl
  554 Purpose:  Enable output flow control using CTS
  555 Call:     sEnCTSFlowCtl(ChP)
  556           CHANNEL_T *ChP; Ptr to channel structure
  557 */
  558 #define sEnCTSFlowCtl(ChP) \
  559 { \
  560    (ChP)->TxControl[2] |= CTSFC_EN; \
  561    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  562 }
  563 
  564 /***************************************************************************
  565 Function: EnParity
  566 Purpose:  Enable parity
  567 Call:     sEnParity(ChP)
  568           CHANNEL_T *ChP; Ptr to channel structure
  569 Comments: Function sSetParity() can be used in place of functions sEnParity(),
  570           sDisParity(), sSetOddParity(), and sSetEvenParity().
  571 
  572 Warnings: Before enabling parity odd or even parity should be chosen using
  573           functions sSetOddParity() or sSetEvenParity().
  574 */
  575 #define sEnParity(ChP) \
  576 { \
  577    (ChP)->TxControl[2] |= PARITY_EN; \
  578    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  579 }
  580 
  581 /***************************************************************************
  582 Function: sEnRTSFlowCtl
  583 Return: void
  584 */
  585 #define sEnRTSFlowCtl(ChP) \
  586 { \
  587         (ChP)->TxControl[2] &= ~RTSTOG_EN; \
  588         (ChP)->TxControl[3] &= ~SET_RTS; \
  589    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  590         (ChP)->RxControl[2] |= RTSFC_EN; \
  591    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
  592 }
  593 
  594 /***************************************************************************
  595 Function: sDisRTSFlowCtl
  596 Return: void
  597 */
  598 #define sDisRTSFlowCtl(ChP) \
  599 { \
  600         (ChP)->RxControl[2] &= ~RTSFC_EN; \
  601    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
  602 }
  603 
  604 /***************************************************************************
  605 Function: sEnRxFIFO
  606 Purpose:  Enable Rx FIFO
  607 Call:     sEnRxFIFO(ChP)
  608           CHANNEL_T *ChP; Ptr to channel structure
  609 */
  610 #define sEnRxFIFO(ChP) \
  611 { \
  612    (ChP)->R[0x32] = 0x08; \
  613    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \
  614 }
  615 
  616 /***************************************************************************
  617 Function: sEnRxProcessor
  618 Purpose:  Enable the receive processor
  619 Call:     sEnRxProcessor(ChP)
  620           CHANNEL_T *ChP; Ptr to channel structure
  621 Comments: This function is used to start the receive processor.  When
  622           the channel is in the reset state the receive processor is not
  623           running.  This is done to prevent the receive processor from
  624           executing invalid microcode instructions prior to the
  625           downloading of the microcode.
  626 
  627 Warnings: This function must be called after valid microcode has been
  628           downloaded to the AIOP, and it must not be called before the
  629           microcode has been downloaded.
  630 */
  631 #define sEnRxProcessor(ChP) \
  632 { \
  633    (ChP)->RxControl[2] |= RXPROC_EN; \
  634    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
  635 }
  636 
  637 /***************************************************************************
  638 Function: sEnRxStatusMode
  639 Purpose:  Enable the Rx status mode
  640 Call:     sEnRxStatusMode(ChP)
  641           CHANNEL_T *ChP; Ptr to channel structure
  642 Comments: This places the channel in the receive status mode.  All subsequent
  643           reads of receive data using sReadRxWord() will return a data byte
  644           in the low word and a status byte in the high word.
  645 
  646 */
  647 #define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
  648 
  649 /***************************************************************************
  650 Function: sEnTransmit
  651 Purpose:  Enable transmit
  652 Call:     sEnTransmit(ChP)
  653           CHANNEL_T *ChP; Ptr to channel structure
  654 */
  655 #define sEnTransmit(ChP) \
  656 { \
  657    (ChP)->TxControl[3] |= TX_ENABLE; \
  658    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  659 }
  660 
  661 /***************************************************************************
  662 Function: sGetAiopIntStatus
  663 Purpose:  Get the AIOP interrupt status
  664 Call:     sGetAiopIntStatus(CtlP,AiopNum)
  665           CONTROLLER_T *CtlP; Ptr to controller structure
  666           int AiopNum; AIOP number
  667 Return:   Byte_t: The AIOP interrupt status.  Bits 0 through 7
  668                          represent channels 0 through 7 respectively.  If a
  669                          bit is set that channel is interrupting.
  670 */
  671 #define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
  672 
  673 /***************************************************************************
  674 Function: sGetAiopNumChan
  675 Purpose:  Get the number of channels supported by an AIOP
  676 Call:     sGetAiopNumChan(CtlP,AiopNum)
  677           CONTROLLER_T *CtlP; Ptr to controller structure
  678           int AiopNum; AIOP number
  679 Return:   int: The number of channels supported by the AIOP
  680 */
  681 #define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
  682 
  683 /***************************************************************************
  684 Function: sGetChanIntID
  685 Purpose:  Get a channel's interrupt identification byte
  686 Call:     sGetChanIntID(ChP)
  687           CHANNEL_T *ChP; Ptr to channel structure
  688 Return:   Byte_t: The channel interrupt ID.  Can be any
  689              combination of the following flags:
  690                 RXF_TRIG:     Rx FIFO trigger level interrupt
  691                 TXFIFO_MT:    Tx FIFO empty interrupt
  692                 SRC_INT:      Special receive condition interrupt
  693                 DELTA_CD:     CD change interrupt
  694                 DELTA_CTS:    CTS change interrupt
  695                 DELTA_DSR:    DSR change interrupt
  696 */
  697 #define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
  698 
  699 /***************************************************************************
  700 Function: sGetChanNum
  701 Purpose:  Get the number of a channel within an AIOP
  702 Call:     sGetChanNum(ChP)
  703           CHANNEL_T *ChP; Ptr to channel structure
  704 Return:   int: Channel number within AIOP, or NULLCHAN if channel does
  705                not exist.
  706 */
  707 #define sGetChanNum(ChP) (ChP)->ChanNum
  708 
  709 /***************************************************************************
  710 Function: sGetChanStatus
  711 Purpose:  Get the channel status
  712 Call:     sGetChanStatus(ChP)
  713           CHANNEL_T *ChP; Ptr to channel structure
  714 Return:   Word_t: The channel status.  Can be any combination of
  715              the following flags:
  716                 LOW BYTE FLAGS
  717                 CTS_ACT:      CTS input asserted
  718                 DSR_ACT:      DSR input asserted
  719                 CD_ACT:       CD input asserted
  720                 TXFIFOMT:     Tx FIFO is empty
  721                 TXSHRMT:      Tx shift register is empty
  722                 RDA:          Rx data available
  723 
  724                 HIGH BYTE FLAGS
  725                 STATMODE:     status mode enable bit
  726                 RXFOVERFL:    receive FIFO overflow
  727                 RX2MATCH:     receive compare byte 2 match
  728                 RX1MATCH:     receive compare byte 1 match
  729                 RXBREAK:      received BREAK
  730                 RXFRAME:      received framing error
  731                 RXPARITY:     received parity error
  732 Warnings: This function will clear the high byte flags in the Channel
  733           Status Register.
  734 */
  735 #define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
  736 
  737 /***************************************************************************
  738 Function: sGetChanStatusLo
  739 Purpose:  Get the low byte only of the channel status
  740 Call:     sGetChanStatusLo(ChP)
  741           CHANNEL_T *ChP; Ptr to channel structure
  742 Return:   Byte_t: The channel status low byte.  Can be any combination
  743              of the following flags:
  744                 CTS_ACT:      CTS input asserted
  745                 DSR_ACT:      DSR input asserted
  746                 CD_ACT:       CD input asserted
  747                 TXFIFOMT:     Tx FIFO is empty
  748                 TXSHRMT:      Tx shift register is empty
  749                 RDA:          Rx data available
  750 */
  751 #define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
  752 
  753 /***************************************************************************
  754 Function: sGetRxCnt
  755 Purpose:  Get the number of data bytes in the Rx FIFO
  756 Call:     sGetRxCnt(ChP)
  757           CHANNEL_T *ChP; Ptr to channel structure
  758 Return:   int: The number of data bytes in the Rx FIFO.
  759 Comments: Byte read of count register is required to obtain Rx count.
  760 
  761 */
  762 #define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
  763 
  764 /***************************************************************************
  765 Function: sGetTxCnt
  766 Purpose:  Get the number of data bytes in the Tx FIFO
  767 Call:     sGetTxCnt(ChP)
  768           CHANNEL_T *ChP; Ptr to channel structure
  769 Return:   Byte_t: The number of data bytes in the Tx FIFO.
  770 Comments: Byte read of count register is required to obtain Tx count.
  771 
  772 */
  773 #define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
  774 
  775 /*****************************************************************************
  776 Function: sGetTxRxDataIO
  777 Purpose:  Get the offset of a channel's TxRx Data register
  778 Call:     sGetTxRxDataIO(ChP)
  779           CHANNEL_T *ChP; Ptr to channel structure
  780 Return:   WordIO_t: offset of a channel's TxRx Data register
  781 */
  782 #define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
  783 
  784 /***************************************************************************
  785 Function: sInitChanDefaults
  786 Purpose:  Initialize a channel structure to its default state.
  787 Call:     sInitChanDefaults(ChP)
  788           CHANNEL_T *ChP; Ptr to the channel structure
  789 Comments: This function must be called once for every channel structure
  790           that exists before any other SSCI calls can be made.
  791 
  792 */
  793 #define sInitChanDefaults(ChP) \
  794 { \
  795    (ChP)->CtlP = NULLCTLPTR; \
  796    (ChP)->AiopNum = NULLAIOP; \
  797    (ChP)->ChanID = AIOPID_NULL; \
  798    (ChP)->ChanNum = NULLCHAN; \
  799 }
  800 
  801 /***************************************************************************
  802 Function: sResetAiopByNum
  803 Purpose:  Reset the AIOP by number
  804 Call:     sResetAiopByNum(CTLP,AIOPNUM)
  805         CONTROLLER_T CTLP; Ptr to controller structure
  806         AIOPNUM; AIOP index
  807 */
  808 #define sResetAiopByNum(CTLP,AIOPNUM) \
  809 { \
  810    rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
  811    rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
  812 }
  813 
  814 /***************************************************************************
  815 Function: sSendBreak
  816 Purpose:  Send a transmit BREAK signal
  817 Call:     sSendBreak(ChP)
  818           CHANNEL_T *ChP; Ptr to channel structure
  819 */
  820 #define sSendBreak(ChP) \
  821 { \
  822    (ChP)->TxControl[3] |= SETBREAK; \
  823    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  824 }
  825 
  826 /***************************************************************************
  827 Function: sSetBaud
  828 Purpose:  Set baud rate
  829 Call:     sSetBaud(ChP,Divisor)
  830           CHANNEL_T *ChP; Ptr to channel structure
  831           Word_t Divisor; 16 bit baud rate divisor for channel
  832 */
  833 #define sSetBaud(ChP,DIVISOR) \
  834 { \
  835    (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
  836    (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
  837    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->BaudDiv)); \
  838 }
  839 
  840 /***************************************************************************
  841 Function: sSetData7
  842 Purpose:  Set data bits to 7
  843 Call:     sSetData7(ChP)
  844           CHANNEL_T *ChP; Ptr to channel structure
  845 */
  846 #define sSetData7(ChP) \
  847 { \
  848    (ChP)->TxControl[2] &= ~DATA8BIT; \
  849    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  850 }
  851 
  852 /***************************************************************************
  853 Function: sSetData8
  854 Purpose:  Set data bits to 8
  855 Call:     sSetData8(ChP)
  856           CHANNEL_T *ChP; Ptr to channel structure
  857 */
  858 #define sSetData8(ChP) \
  859 { \
  860    (ChP)->TxControl[2] |= DATA8BIT; \
  861    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  862 }
  863 
  864 /***************************************************************************
  865 Function: sSetDTR
  866 Purpose:  Set the DTR output
  867 Call:     sSetDTR(ChP)
  868           CHANNEL_T *ChP; Ptr to channel structure
  869 */
  870 #define sSetDTR(ChP) \
  871 { \
  872    (ChP)->TxControl[3] |= SET_DTR; \
  873    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  874 }
  875 
  876 /***************************************************************************
  877 Function: sSetEvenParity
  878 Purpose:  Set even parity
  879 Call:     sSetEvenParity(ChP)
  880           CHANNEL_T *ChP; Ptr to channel structure
  881 Comments: Function sSetParity() can be used in place of functions sEnParity(),
  882           sDisParity(), sSetOddParity(), and sSetEvenParity().
  883 
  884 Warnings: This function has no effect unless parity is enabled with function
  885           sEnParity().
  886 */
  887 #define sSetEvenParity(ChP) \
  888 { \
  889    (ChP)->TxControl[2] |= EVEN_PAR; \
  890    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  891 }
  892 
  893 /***************************************************************************
  894 Function: sSetOddParity
  895 Purpose:  Set odd parity
  896 Call:     sSetOddParity(ChP)
  897           CHANNEL_T *ChP; Ptr to channel structure
  898 Comments: Function sSetParity() can be used in place of functions sEnParity(),
  899           sDisParity(), sSetOddParity(), and sSetEvenParity().
  900 
  901 Warnings: This function has no effect unless parity is enabled with function
  902           sEnParity().
  903 */
  904 #define sSetOddParity(ChP) \
  905 { \
  906    (ChP)->TxControl[2] &= ~EVEN_PAR; \
  907    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  908 }
  909 
  910 /***************************************************************************
  911 Function: sSetRTS
  912 Purpose:  Set the RTS output
  913 Call:     sSetRTS(ChP)
  914           CHANNEL_T *ChP; Ptr to channel structure
  915 */
  916 #define sSetRTS(ChP) \
  917 { \
  918    (ChP)->TxControl[3] |= SET_RTS; \
  919    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  920 }
  921 
  922 /***************************************************************************
  923 Function: sSetRxTrigger
  924 Purpose:  Set the Rx FIFO trigger level
  925 Call:     sSetRxProcessor(ChP,Level)
  926           CHANNEL_T *ChP; Ptr to channel structure
  927           Byte_t Level; Number of characters in Rx FIFO at which the
  928              interrupt will be generated.  Can be any of the following flags:
  929 
  930              TRIG_NO:   no trigger
  931              TRIG_1:    1 character in FIFO
  932              TRIG_1_2:  FIFO 1/2 full
  933              TRIG_7_8:  FIFO 7/8 full
  934 Comments: An interrupt will be generated when the trigger level is reached
  935           only if function sEnInterrupt() has been called with flag
  936           RXINT_EN set.  The RXF_TRIG flag in the Interrupt Idenfification
  937           register will be set whenever the trigger level is reached
  938           regardless of the setting of RXINT_EN.
  939 
  940 */
  941 #define sSetRxTrigger(ChP,LEVEL) \
  942 { \
  943    (ChP)->RxControl[2] &= ~TRIG_MASK; \
  944    (ChP)->RxControl[2] |= LEVEL; \
  945    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
  946 }
  947 
  948 /***************************************************************************
  949 Function: sSetStop1
  950 Purpose:  Set stop bits to 1
  951 Call:     sSetStop1(ChP)
  952           CHANNEL_T *ChP; Ptr to channel structure
  953 */
  954 #define sSetStop1(ChP) \
  955 { \
  956    (ChP)->TxControl[2] &= ~STOP2; \
  957    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  958 }
  959 
  960 /***************************************************************************
  961 Function: sSetStop2
  962 Purpose:  Set stop bits to 2
  963 Call:     sSetStop2(ChP)
  964           CHANNEL_T *ChP; Ptr to channel structure
  965 */
  966 #define sSetStop2(ChP) \
  967 { \
  968    (ChP)->TxControl[2] |= STOP2; \
  969    rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
  970 }
  971 
  972 /***************************************************************************
  973 Function: sStartRxProcessor
  974 Purpose:  Start a channel's receive processor
  975 Call:     sStartRxProcessor(ChP)
  976           CHANNEL_T *ChP; Ptr to channel structure
  977 Comments: This function is used to start a Rx processor after it was
  978           stopped with sStopRxProcessor() or sStopSWInFlowCtl().  It
  979           will restart both the Rx processor and software input flow control.
  980 
  981 */
  982 #define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R))
  983 
  984 /***************************************************************************
  985 Function: sWriteTxByte
  986 Purpose:  Write a transmit data byte to a channel.
  987           CHANNEL_T *ChP; Ptr to channel structure
  988           ByteIO_t io: Channel transmit register I/O address.  This can
  989                            be obtained with sGetTxRxDataIO().
  990           Byte_t Data; The transmit data byte.
  991 Warnings: This function writes the data byte without checking to see if
  992           sMaxTxSize is exceeded in the Tx FIFO.
  993 */
  994 #define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
  995 
  996 int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
  997 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
  998 int sInitChan(  CONTROLLER_T *CtlP,
  999                 CHANNEL_T *ChP,
 1000                 int AiopNum,
 1001                 int ChanNum);
 1002 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
 1003 void sStopRxProcessor(CHANNEL_T *ChP);
 1004 void sStopSWInFlowCtl(CHANNEL_T *ChP);
 1005 void sFlushRxFIFO(CHANNEL_T *ChP);
 1006 void sFlushTxFIFO(CHANNEL_T *ChP);
 1007 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
 1008 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
 1009 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
 1010 int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
 1011 void rp_releaseresource(CONTROLLER_t *ctlp);
 1012 static __inline void
 1013 rp_lock(CONTROLLER_T *CtlP)
 1014 {
 1015         if (CtlP->hwmtx_init != 0)
 1016                 mtx_lock(&CtlP->hwmtx);
 1017 }
 1018 static __inline void
 1019 rp_unlock(CONTROLLER_T *CtlP)
 1020 {
 1021         if (CtlP->hwmtx_init != 0)
 1022                 mtx_unlock(&CtlP->hwmtx);
 1023 }
 1024 
 1025 #ifndef ROCKET_C
 1026 extern Byte_t R[RDATASIZE];
 1027 extern CONTROLLER_T sController[CTL_SIZE];
 1028 extern Byte_t sIRQMap[16];
 1029 #endif
 1030 extern Byte_t rp_sBitMapClrTbl[8];
 1031 extern Byte_t rp_sBitMapSetTbl[8];

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