The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/rtwn/rtl8188e/usb/r88eu_init.c

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    1 /*      $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $   */
    2 
    3 /*-
    4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
    5  * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
    6  * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
    7  *
    8  * Permission to use, copy, modify, and distribute this software for any
    9  * purpose with or without fee is hereby granted, provided that the above
   10  * copyright notice and this permission notice appear in all copies.
   11  *
   12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   19  */
   20 
   21 #include <sys/cdefs.h>
   22 __FBSDID("$FreeBSD$");
   23 
   24 #include "opt_wlan.h"
   25 
   26 #include <sys/param.h>
   27 #include <sys/lock.h>
   28 #include <sys/mutex.h>
   29 #include <sys/mbuf.h>
   30 #include <sys/kernel.h>
   31 #include <sys/socket.h>
   32 #include <sys/systm.h>
   33 #include <sys/malloc.h>
   34 #include <sys/queue.h>
   35 #include <sys/taskqueue.h>
   36 #include <sys/bus.h>
   37 #include <sys/endian.h>
   38 #include <sys/linker.h>
   39 
   40 #include <net/if.h>
   41 #include <net/ethernet.h>
   42 #include <net/if_media.h>
   43 
   44 #include <net80211/ieee80211_var.h>
   45 #include <net80211/ieee80211_radiotap.h>
   46 
   47 #include <dev/rtwn/if_rtwnreg.h>
   48 #include <dev/rtwn/if_rtwnvar.h>
   49 
   50 #include <dev/rtwn/rtl8192c/r92c.h>
   51 #include <dev/rtwn/rtl8192c/r92c_var.h>
   52 
   53 #include <dev/rtwn/rtl8188e/usb/r88eu.h>
   54 #include <dev/rtwn/rtl8188e/usb/r88eu_reg.h>
   55 
   56 void
   57 r88eu_init_bb(struct rtwn_softc *sc)
   58 {
   59 
   60         /* Enable BB and RF. */
   61         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
   62             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
   63             R92C_SYS_FUNC_EN_DIO_RF);
   64 
   65         rtwn_write_1(sc, R92C_RF_CTRL,
   66             R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
   67         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
   68             R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
   69             R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
   70 
   71         r88e_init_bb_common(sc);
   72 }
   73 
   74 int
   75 r88eu_power_on(struct rtwn_softc *sc)
   76 {
   77 #define RTWN_CHK(res) do {      \
   78         if (res != 0)           \
   79                 return (EIO);   \
   80 } while(0)
   81         int ntries;
   82 
   83         /* Wait for power ready bit. */
   84         for (ntries = 0; ntries < 5000; ntries++) {
   85                 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
   86                         break;
   87                 rtwn_delay(sc, 10);
   88         }
   89         if (ntries == 5000) {
   90                 device_printf(sc->sc_dev,
   91                     "timeout waiting for chip power up\n");
   92                 return (ETIMEDOUT);
   93         }
   94 
   95         /* Reset BB. */
   96         RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
   97             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
   98 
   99         RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
  100 
  101         /* Disable HWPDN. */
  102         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
  103             R92C_APS_FSMCO_APDM_HPDN, 0, 1));
  104 
  105         /* Disable WL suspend. */
  106         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
  107             R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
  108 
  109         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
  110             0, R92C_APS_FSMCO_APFM_ONMAC, 1));
  111         for (ntries = 0; ntries < 5000; ntries++) {
  112                 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
  113                     R92C_APS_FSMCO_APFM_ONMAC))
  114                         break;
  115                 rtwn_delay(sc, 10);
  116         }
  117         if (ntries == 5000)
  118                 return (ETIMEDOUT);
  119 
  120         /* Enable LDO normal mode. */
  121         RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
  122             R92C_LPLDO_CTRL_SLEEP, 0));
  123 
  124         /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
  125         RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
  126         RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
  127             R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
  128             R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
  129             R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
  130             ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
  131             R92C_CR_CALTMR_EN));
  132 
  133         return (0);
  134 #undef RTWN_CHK
  135 }
  136 
  137 void
  138 r88eu_power_off(struct rtwn_softc *sc)
  139 {
  140         uint8_t reg;
  141         int error, ntries;
  142 
  143         /* Disable any kind of TX reports. */
  144         error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
  145             R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
  146         if (error == ENXIO)     /* hardware gone */
  147                 return;
  148 
  149         /* Stop Rx. */
  150         rtwn_write_1(sc, R92C_CR, 0);
  151 
  152         /* Move card to Low Power State. */
  153         /* Block all Tx queues. */
  154         rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
  155 
  156         for (ntries = 0; ntries < 10; ntries++) {
  157                 /* Should be zero if no packet is transmitting. */
  158                 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
  159                         break;
  160 
  161                 rtwn_delay(sc, 5000);
  162         }
  163         if (ntries == 10) {
  164                 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
  165                     __func__);
  166                 return;
  167         }
  168 
  169         /* CCK and OFDM are disabled, and clock are gated. */
  170         rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
  171 
  172         rtwn_delay(sc, 1);
  173 
  174         /* Reset MAC TRX */
  175         rtwn_write_1(sc, R92C_CR,
  176             R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
  177             R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
  178             R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
  179 
  180         /* check if removed later */
  181         rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
  182 
  183         /* Respond TxOK to scheduler */
  184         rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
  185 
  186         /* If firmware in ram code, do reset. */
  187 #ifndef RTWN_WITHOUT_UCODE
  188         if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
  189                 r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
  190 #endif
  191 
  192         /* Reset MCU ready status. */
  193         rtwn_write_1(sc, R92C_MCUFWDL, 0);
  194 
  195         /* Disable 32k. */
  196         rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
  197 
  198         /* Move card to Disabled state. */
  199         /* Turn off RF. */
  200         rtwn_write_1(sc, R92C_RF_CTRL, 0);
  201 
  202         /* LDO Sleep mode. */
  203         rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
  204 
  205         /* Turn off MAC by HW state machine */
  206         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
  207             R92C_APS_FSMCO_APFM_OFF, 1);
  208 
  209         for (ntries = 0; ntries < 10; ntries++) {
  210                 /* Wait until it will be disabled. */
  211                 if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
  212                     R92C_APS_FSMCO_APFM_OFF) == 0)
  213                         break;
  214 
  215                 rtwn_delay(sc, 5000);
  216         }
  217         if (ntries == 10) {
  218                 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
  219                     __func__);
  220                 return;
  221         }
  222 
  223         /* schmit trigger */
  224         rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
  225 
  226         /* Enable WL suspend. */
  227         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
  228             R92C_APS_FSMCO_AFSM_PCIE, R92C_APS_FSMCO_AFSM_HSUS, 1);
  229 
  230         /* Enable bandgap mbias in suspend. */
  231         rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
  232 
  233         /* Clear SIC_EN register. */
  234         rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
  235 
  236         /* Set USB suspend enable local register */
  237         rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
  238 
  239         /* Reset MCU IO Wrapper. */
  240         reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
  241         rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
  242         rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
  243 
  244         /* marked as 'For Power Consumption' code. */
  245         rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
  246         rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
  247 
  248         rtwn_write_1(sc, R92C_GPIO_IO_SEL,
  249             rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
  250         rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
  251 
  252         /* Set LNA, TRSW, EX_PA Pin to output mode. */
  253         rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
  254 }
  255 
  256 void
  257 r88eu_init_intr(struct rtwn_softc *sc)
  258 {
  259         /* TODO: adjust */
  260         rtwn_write_4(sc, R88E_HISR, 0xffffffff);
  261         rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
  262             R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
  263         rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
  264             R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
  265         rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
  266             R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
  267 }
  268 
  269 void
  270 r88eu_init_rx_agg(struct rtwn_softc *sc)
  271 {
  272         /* XXX merge? */
  273         rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
  274             R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
  275         /* XXX dehardcode */
  276         rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
  277         rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
  278 }
  279 
  280 void
  281 r88eu_post_init(struct rtwn_softc *sc)
  282 {
  283 
  284         /* Enable per-packet TX report. */
  285         rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
  286 
  287         /* Disable Tx if MACID is not associated. */
  288         rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
  289         rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
  290         r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
  291 
  292         /* Perform LO and IQ calibrations. */
  293         r88e_iq_calib(sc);
  294         /* Perform LC calibration. */
  295         r92c_lc_calib(sc);
  296 
  297         rtwn_write_1(sc, R92C_USB_HRPWM, 0);
  298 
  299         if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
  300                 /* No support (yet?) for f/w rate adaptation. */
  301                 sc->sc_ratectl = RTWN_RATECTL_NET80211;
  302         } else
  303                 sc->sc_ratectl = sc->sc_ratectl_sysctl;
  304 }

Cache object: 2cf384b8b0488e84fd4e8c839020e28d


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