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sys/dev/safexcel/safexcel_reg.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _SAFEXCEL_REGS_H_ 30 #define _SAFEXCEL_REGS_H_ 31 32 #define SAFEXCEL_HIA_VERSION_LE 0x35ca 33 #define SAFEXCEL_HIA_VERSION_BE 0xca35 34 #define EIP201_VERSION_LE 0x36c9 35 #define SAFEXCEL_REG_LO16(_reg) ((_reg) & 0xffff) 36 #define SAFEXCEL_REG_HI16(_reg) (((_reg) >> 16) & 0xffff) 37 38 /* HIA, Command Descriptor Ring Manager */ 39 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12)) 40 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12)) 41 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12)) 42 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12)) 43 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12)) 44 #define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12)) 45 #define CDR_RING_SIZE(x) (0x18 + ((x) << 12)) 46 #define CDR_DESC_SIZE(x) (0x1C + ((x) << 12)) 47 #define CDR_CFG(x) (0x20 + ((x) << 12)) 48 #define CDR_DMA_CFG(x) (0x24 + ((x) << 12)) 49 #define CDR_THR(x) (0x28 + ((x) << 12)) 50 #define CDR_PREP_COUNT(x) (0x2C + ((x) << 12)) 51 #define CDR_PROC_COUNT(x) (0x30 + ((x) << 12)) 52 #define CDR_PREP_PNTR(x) (0x34 + ((x) << 12)) 53 #define CDR_PROC_PNTR(x) (0x38 + ((x) << 12)) 54 #define CDR_STAT(x) (0x3C + ((x) << 12)) 55 56 /* HIA, Result Descriptor Ring Manager */ 57 #define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12)) 58 #define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12)) 59 #define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12)) 60 #define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12)) 61 #define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12)) 62 #define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12)) 63 #define RDR_RING_SIZE(x) (0x818 + ((x) << 12)) 64 #define RDR_DESC_SIZE(x) (0x81C + ((x) << 12)) 65 #define RDR_CFG(x) (0x820 + ((x) << 12)) 66 #define RDR_DMA_CFG(x) (0x824 + ((x) << 12)) 67 #define RDR_THR(x) (0x828 + ((x) << 12)) 68 #define RDR_PREP_COUNT(x) (0x82C + ((x) << 12)) 69 #define RDR_PROC_COUNT(x) (0x830 + ((x) << 12)) 70 #define RDR_PREP_PNTR(x) (0x834 + ((x) << 12)) 71 #define RDR_PROC_PNTR(x) (0x838 + ((x) << 12)) 72 #define RDR_STAT(x) (0x83C + ((x) << 12)) 73 74 /* HIA, Ring AIC */ 75 #define AIC_POL_CTRL(x) (0xE000 - ((x) << 12)) 76 #define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12)) 77 #define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12)) 78 #define AIC_RAW_STAL(x) (0xE00C - ((x) << 12)) 79 #define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12)) 80 #define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12)) 81 #define AIC_ACK(x) (0xE010 - ((x) << 12)) 82 #define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12)) 83 #define AIC_OPTIONS(x) (0xE018 - ((x) << 12)) 84 #define AIC_VERSION(x) (0xE01C - ((x) << 12)) 85 86 /* HIA, Global AIC */ 87 #define AIC_G_POL_CTRL 0xF800 88 #define AIC_G_TYPE_CTRL 0xF804 89 #define AIC_G_ENABLE_CTRL 0xF808 90 #define AIC_G_RAW_STAT 0xF80C 91 #define AIC_G_ENABLE_SET 0xF80C 92 #define AIC_G_ENABLED_STAT 0xF810 93 #define AIC_G_ACK 0xF810 94 #define AIC_G_ENABLE_CLR 0xF814 95 #define AIC_G_OPTIONS 0xF818 96 #define AIC_G_VERSION 0xF81C 97 98 /* HIA, Data Fetch Engine */ 99 #define DFE_CFG 0xF000 100 #define DFE_PRIO_0 0xF010 101 #define DFE_PRIO_1 0xF014 102 #define DFE_PRIO_2 0xF018 103 #define DFE_PRIO_3 0xF01C 104 105 /* HIA, Data Fetch Engine access monitoring for CDR */ 106 #define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3)) 107 #define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3)) 108 109 /* HIA, Data Fetch Engine thread control and status for thread */ 110 #define DFE_THR_CTRL 0xF200 111 #define DFE_THR_STAT 0xF204 112 #define DFE_THR_DESC_CTRL 0xF208 113 #define DFE_THR_DESC_DPTR_LO 0xF210 114 #define DFE_THR_DESC_DPTR_HI 0xF214 115 #define DFE_THR_DESC_ACDPTR_LO 0xF218 116 #define DFE_THR_DESC_ACDPTR_HI 0xF21C 117 118 /* HIA, Data Store Engine */ 119 #define DSE_CFG 0xF400 120 #define DSE_PRIO_0 0xF410 121 #define DSE_PRIO_1 0xF414 122 #define DSE_PRIO_2 0xF418 123 #define DSE_PRIO_3 0xF41C 124 125 /* HIA, Data Store Engine access monitoring for RDR */ 126 #define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3)) 127 #define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3)) 128 129 /* HIA, Data Store Engine thread control and status for thread */ 130 #define DSE_THR_CTRL 0xF600 131 #define DSE_THR_STAT 0xF604 132 #define DSE_THR_DESC_CTRL 0xF608 133 #define DSE_THR_DESC_DPTR_LO 0xF610 134 #define DSE_THR_DESC_DPTR_HI 0xF614 135 #define DSE_THR_DESC_S_DPTR_LO 0xF618 136 #define DSE_THR_DESC_S_DPTR_HI 0xF61C 137 #define DSE_THR_ERROR_STAT 0xF620 138 139 /* HIA Global */ 140 #define HIA_MST_CTRL 0xFFF4 141 #define HIA_OPTIONS 0xFFF8 142 #define HIA_VERSION 0xFFFC 143 144 /* Processing Engine Input Side, Processing Engine */ 145 #define PE_IN_DBUF_THRESH 0x10000 146 #define PE_IN_TBUF_THRESH 0x10100 147 148 /* Packet Engine Configuration / Status Registers */ 149 #define PE_TOKEN_CTRL_STAT 0x11000 150 #define PE_FUNCTION_EN 0x11004 151 #define PE_CONTEXT_CTRL 0x11008 152 #define PE_INTERRUPT_CTRL_STAT 0x11010 153 #define PE_CONTEXT_STAT 0x1100C 154 #define PE_OUT_TRANS_CTRL_STAT 0x11018 155 #define PE_OUT_BUF_CTRL 0x1101C 156 157 /* Packet Engine AIC */ 158 #define PE_EIP96_AIC_POL_CTRL 0x113C0 159 #define PE_EIP96_AIC_TYPE_CTRL 0x113C4 160 #define PE_EIP96_AIC_ENABLE_CTRL 0x113C8 161 #define PE_EIP96_AIC_RAW_STAT 0x113CC 162 #define PE_EIP96_AIC_ENABLE_SET 0x113CC 163 #define PE_EIP96_AIC_ENABLED_STAT 0x113D0 164 #define PE_EIP96_AIC_ACK 0x113D0 165 #define PE_EIP96_AIC_ENABLE_CLR 0x113D4 166 #define PE_EIP96_AIC_OPTIONS 0x113D8 167 #define PE_EIP96_AIC_VERSION 0x113DC 168 169 /* Packet Engine Options & Version Registers */ 170 #define PE_EIP96_OPTIONS 0x113F8 171 #define PE_EIP96_VERSION 0x113FC 172 173 #define SAFEXCEL_OPT 174 175 /* Processing Engine Output Side */ 176 #define PE_OUT_DBUF_THRESH 0x11C00 177 #define PE_OUT_TBUF_THRESH 0x11D00 178 179 /* Processing Engine Local AIC */ 180 #define PE_AIC_POL_CTRL 0x11F00 181 #define PE_AIC_TYPE_CTRL 0x11F04 182 #define PE_AIC_ENABLE_CTRL 0x11F08 183 #define PE_AIC_RAW_STAT 0x11F0C 184 #define PE_AIC_ENABLE_SET 0x11F0C 185 #define PE_AIC_ENABLED_STAT 0x11F10 186 #define PE_AIC_ENABLE_CLR 0x11F14 187 #define PE_AIC_OPTIONS 0x11F18 188 #define PE_AIC_VERSION 0x11F1C 189 190 /* Processing Engine General Configuration and Version */ 191 #define PE_IN_FLIGHT 0x11FF0 192 #define PE_OPTIONS 0x11FF8 193 #define PE_VERSION 0x11FFC 194 195 /* EIP-97 - Global */ 196 #define EIP97_CLOCK_STATE 0x1FFE4 197 #define EIP97_FORCE_CLOCK_ON 0x1FFE8 198 #define EIP97_FORCE_CLOCK_OFF 0x1FFEC 199 #define EIP97_MST_CTRL 0x1FFF4 200 #define EIP97_OPTIONS 0x1FFF8 201 #define EIP97_VERSION 0x1FFFC 202 203 /* Register base offsets */ 204 #define SAFEXCEL_HIA_AIC(_sc) ((_sc)->sc_offsets.hia_aic) 205 #define SAFEXCEL_HIA_AIC_G(_sc) ((_sc)->sc_offsets.hia_aic_g) 206 #define SAFEXCEL_HIA_AIC_R(_sc) ((_sc)->sc_offsets.hia_aic_r) 207 #define SAFEXCEL_HIA_AIC_xDR(_sc) ((_sc)->sc_offsets.hia_aic_xdr) 208 #define SAFEXCEL_HIA_DFE(_sc) ((_sc)->sc_offsets.hia_dfe) 209 #define SAFEXCEL_HIA_DFE_THR(_sc) ((_sc)->sc_offsets.hia_dfe_thr) 210 #define SAFEXCEL_HIA_DSE(_sc) ((_sc)->sc_offsets.hia_dse) 211 #define SAFEXCEL_HIA_DSE_THR(_sc) ((_sc)->sc_offsets.hia_dse_thr) 212 #define SAFEXCEL_HIA_GEN_CFG(_sc) ((_sc)->sc_offsets.hia_gen_cfg) 213 #define SAFEXCEL_PE(_sc) ((_sc)->sc_offsets.pe) 214 215 /* EIP197 base offsets */ 216 #define SAFEXCEL_EIP197_HIA_AIC_BASE 0x90000 217 #define SAFEXCEL_EIP197_HIA_AIC_G_BASE 0x90000 218 #define SAFEXCEL_EIP197_HIA_AIC_R_BASE 0x90800 219 #define SAFEXCEL_EIP197_HIA_AIC_xDR_BASE 0x80000 220 #define SAFEXCEL_EIP197_HIA_DFE_BASE 0x8c000 221 #define SAFEXCEL_EIP197_HIA_DFE_THR_BASE 0x8c040 222 #define SAFEXCEL_EIP197_HIA_DSE_BASE 0x8d000 223 #define SAFEXCEL_EIP197_HIA_DSE_THR_BASE 0x8d040 224 #define SAFEXCEL_EIP197_HIA_GEN_CFG_BASE 0xf0000 225 #define SAFEXCEL_EIP197_PE_BASE 0xa0000 226 227 /* EIP97 base offsets */ 228 #define SAFEXCEL_EIP97_HIA_AIC_BASE 0x0 229 #define SAFEXCEL_EIP97_HIA_AIC_G_BASE 0x0 230 #define SAFEXCEL_EIP97_HIA_AIC_R_BASE 0x0 231 #define SAFEXCEL_EIP97_HIA_AIC_xDR_BASE 0x0 232 #define SAFEXCEL_EIP97_HIA_DFE_BASE 0xf000 233 #define SAFEXCEL_EIP97_HIA_DFE_THR_BASE 0xf200 234 #define SAFEXCEL_EIP97_HIA_DSE_BASE 0xf400 235 #define SAFEXCEL_EIP97_HIA_DSE_THR_BASE 0xf600 236 #define SAFEXCEL_EIP97_HIA_GEN_CFG_BASE 0x10000 237 #define SAFEXCEL_EIP97_PE_BASE 0x10000 238 239 /* CDR/RDR register offsets */ 240 #define SAFEXCEL_HIA_xDR_OFF(priv, r) (SAFEXCEL_HIA_AIC_xDR(priv) + (r) * 0x1000) 241 #define SAFEXCEL_HIA_CDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r)) 242 #define SAFEXCEL_HIA_RDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r) + 0x800) 243 #define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO 0x0000 244 #define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI 0x0004 245 #define SAFEXCEL_HIA_xDR_RING_SIZE 0x0018 246 #define SAFEXCEL_HIA_xDR_DESC_SIZE 0x001c 247 #define SAFEXCEL_HIA_xDR_CFG 0x0020 248 #define SAFEXCEL_HIA_xDR_DMA_CFG 0x0024 249 #define SAFEXCEL_HIA_xDR_THRESH 0x0028 250 #define SAFEXCEL_HIA_xDR_PREP_COUNT 0x002c 251 #define SAFEXCEL_HIA_xDR_PROC_COUNT 0x0030 252 #define SAFEXCEL_HIA_xDR_PREP_PNTR 0x0034 253 #define SAFEXCEL_HIA_xDR_PROC_PNTR 0x0038 254 #define SAFEXCEL_HIA_xDR_STAT 0x003c 255 256 /* register offsets */ 257 #define SAFEXCEL_HIA_DFE_CFG(n) (0x000 + (128 * (n))) 258 #define SAFEXCEL_HIA_DFE_THR_CTRL(n) (0x000 + (128 * (n))) 259 #define SAFEXCEL_HIA_DFE_THR_STAT(n) (0x004 + (128 * (n))) 260 #define SAFEXCEL_HIA_DSE_CFG(n) (0x000 + (128 * (n))) 261 #define SAFEXCEL_HIA_DSE_THR_CTRL(n) (0x000 + (128 * (n))) 262 #define SAFEXCEL_HIA_DSE_THR_STAT(n) (0x004 + (128 * (n))) 263 #define SAFEXCEL_HIA_RA_PE_CTRL(n) (0x010 + (8 * (n))) 264 #define SAFEXCEL_HIA_RA_PE_STAT 0x0014 265 #define SAFEXCEL_HIA_AIC_R_OFF(r) ((r) * 0x1000) 266 #define SAFEXCEL_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - SAFEXCEL_HIA_AIC_R_OFF(r)) 267 #define SAFEXCEL_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) 268 #define SAFEXCEL_HIA_AIC_R_ACK(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) 269 #define SAFEXCEL_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - SAFEXCEL_HIA_AIC_R_OFF(r)) 270 #define SAFEXCEL_HIA_AIC_R_VERSION(r) (0xe01c - SAFEXCEL_HIA_AIC_R_OFF(r)) 271 #define SAFEXCEL_HIA_AIC_G_ENABLE_CTRL 0xf808 272 #define SAFEXCEL_HIA_AIC_G_ENABLED_STAT 0xf810 273 #define SAFEXCEL_HIA_AIC_G_ACK 0xf810 274 #define SAFEXCEL_HIA_MST_CTRL 0xfff4 275 #define SAFEXCEL_HIA_OPTIONS 0xfff8 276 #define SAFEXCEL_HIA_VERSION 0xfffc 277 #define SAFEXCEL_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) 278 #define SAFEXCEL_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) 279 #define SAFEXCEL_PE_ICE_SCRATCH_RAM(x, n) ((0x800 + (x) * 4) + 0x2000 * (n)) 280 #define SAFEXCEL_PE_ICE_PUE_CTRL(n) (0xc80 + (0x2000 * (n))) 281 #define SAFEXCEL_PE_ICE_SCRATCH_CTRL 0x0d04 282 #define SAFEXCEL_PE_ICE_FPP_CTRL(n) (0xd80 + (0x2000 * (n))) 283 #define SAFEXCEL_PE_ICE_RAM_CTRL(n) (0xff0 + (0x2000 * (n))) 284 #define SAFEXCEL_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) 285 #define SAFEXCEL_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) 286 #define SAFEXCEL_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) 287 #define SAFEXCEL_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) 288 #define SAFEXCEL_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) 289 #define SAFEXCEL_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) 290 291 /* EIP-197 Classification Engine */ 292 293 /* Classification regs */ 294 #define SAFEXCEL_CS_RAM_CTRL 0xf7ff0 295 296 /* SAFEXCEL_HIA_xDR_DESC_SIZE */ 297 #define SAFEXCEL_xDR_DESC_MODE_64BIT (1U << 31) 298 #define SAFEXCEL_CDR_DESC_MODE_ADCP (1 << 30) 299 #define SAFEXCEL_xDR_DESC_xD_OFFSET 16 300 301 /* SAFEXCEL_DIA_xDR_CFG */ 302 #define SAFEXCEL_xDR_xD_FETCH_THRESH 16 303 304 /* SAFEXCEL_HIA_xDR_DMA_CFG */ 305 #define SAFEXCEL_HIA_xDR_WR_RES_BUF (1 << 22) 306 #define SAFEXCEL_HIA_xDR_WR_CTRL_BUF (1 << 23) 307 #define SAFEXCEL_HIA_xDR_WR_OWN_BUF (1 << 24) 308 #define SAFEXCEL_HIA_xDR_CFG_xD_PROT(n) (((n) & 0xf) << 4) 309 #define SAFEXCEL_HIA_xDR_CFG_DATA_PROT(n) (((n) & 0xf) << 12) 310 #define SAFEXCEL_HIA_xDR_CFG_ACD_PROT(n) (((n) & 0xf) << 20) 311 #define SAFEXCEL_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 312 #define SAFEXCEL_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 313 314 /* SAFEXCEL_HIA_CDR_THRESH */ 315 #define SAFEXCEL_HIA_CDR_THRESH_PROC_PKT(n) ((n) & 0xffff) 316 #define SAFEXCEL_HIA_CDR_THRESH_PROC_MODE (1 << 22) 317 #define SAFEXCEL_HIA_CDR_THRESH_PKT_MODE (1 << 23) 318 /* x256 clk cycles */ 319 #define SAFEXCEL_HIA_CDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) 320 321 /* SAFEXCEL_HIA_RDR_THRESH */ 322 #define SAFEXCEL_HIA_RDR_THRESH_PROC_PKT(n) ((n) & 0xffff) 323 #define SAFEXCEL_HIA_RDR_THRESH_PKT_MODE (1 << 23) 324 /* x256 clk cycles */ 325 #define SAFEXCEL_HIA_RDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) 326 327 /* SAFEXCEL_HIA_xDR_PREP_COUNT */ 328 #define SAFEXCEL_xDR_PREP_CLR_COUNT (1U << 31) 329 #define SAFEXCEL_xDR_PREP_xD_COUNT_INCR_OFFSET 2 330 #define SAFEXCEL_xDR_PREP_RD_COUNT_INCR_MASK 0x3fff 331 332 /* SAFEXCEL_HIA_xDR_PROC_COUNT */ 333 #define SAFEXCEL_xDR_PROC_xD_PKT_OFFSET 24 334 #define SAFEXCEL_xDR_PROC_xD_PKT_MASK 0x7f 335 #define SAFEXCEL_xDR_PROC_xD_COUNT(n) ((n) << 2) 336 #define SAFEXCEL_xDR_PROC_xD_PKT(n) \ 337 (((n) & SAFEXCEL_xDR_PROC_xD_PKT_MASK) << SAFEXCEL_xDR_PROC_xD_PKT_OFFSET) 338 #define SAFEXCEL_xDR_PROC_CLR_COUNT (1U << 31) 339 340 /* SAFEXCEL_HIA_xDR_STAT */ 341 #define SAFEXCEL_xDR_DMA_ERR (1 << 0) 342 #define SAFEXCEL_xDR_PREP_CMD_THRES (1 << 1) 343 #define SAFEXCEL_xDR_ERR (1 << 2) 344 #define SAFEXCEL_xDR_THRESH (1 << 4) 345 #define SAFEXCEL_xDR_TIMEOUT (1 << 5) 346 #define SAFEXCEL_CDR_INTR_MASK 0x3f 347 #define SAFEXCEL_RDR_INTR_MASK 0xff 348 349 #define SAFEXCEL_HIA_RA_PE_CTRL_RESET (1U << 31) 350 #define SAFEXCEL_HIA_RA_PE_CTRL_EN (1 << 30) 351 352 /* Register offsets */ 353 354 /* SAFEXCEL_HIA_DSE_THR_STAT */ 355 #define SAFEXCEL_DSE_THR_RDR_ID_MASK 0xf000 356 357 /* SAFEXCEL_HIA_OPTIONS */ 358 #define SAFEXCEL_OPT_ADDR_64 (1U << 31) 359 #define SAFEXCEL_OPT_TGT_ALIGN_OFFSET 28 360 #define SAFEXCEL_OPT_TGT_ALIGN_MASK 0x70000000 361 #define SAFEXCEL_xDR_HDW_OFFSET 25 362 #define SAFEXCEL_xDR_HDW_MASK 0x6000000 363 #define SAFEXCEL_N_RINGS_MASK 0xf 364 #define SAFEXCEL_N_PES_OFFSET 4 365 #define SAFEXCEL_N_PES_MASK 0x1f0 366 #define EIP97_N_PES_MASK 0x70 367 368 /* SAFEXCEL_HIA_AIC_R_ENABLE_CTRL */ 369 #define SAFEXCEL_CDR_IRQ(n) (1 << ((n) * 2)) 370 #define SAFEXCEL_RDR_IRQ(n) (1 << ((n) * 2 + 1)) 371 372 /* SAFEXCEL_HIA_DFE/DSE_CFG */ 373 #define SAFEXCEL_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 374 #define SAFEXCEL_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 375 #define SAFEXCEL_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 376 #define SAFEXCEL_HIA_DSE_CFG_ALLWAYS_BUFFERABLE 0xc000 377 #define SAFEXCEL_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 378 #define SAFEXCEL_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 379 #define SAFEXCEL_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 380 #define SAFEXCEL_HIA_DFE_CFG_DIS_DEBUG 0xe0000000 381 #define SAFEXCEL_HIA_DSE_CFG_EN_SINGLE_WR (1 << 29) 382 #define SAFEXCEL_HIA_DSE_CFG_DIS_DEBUG 0xc0000000 383 384 /* SAFEXCEL_HIA_DFE/DSE_THR_CTRL */ 385 #define SAFEXCEL_DxE_THR_CTRL_EN (1 << 30) 386 #define SAFEXCEL_DxE_THR_CTRL_RESET_PE (1U << 31) 387 388 /* SAFEXCEL_HIA_AIC_G_ENABLED_STAT */ 389 #define SAFEXCEL_G_IRQ_DFE(n) (1 << ((n) << 1)) 390 #define SAFEXCEL_G_IRQ_DSE(n) (1 << (((n) << 1) + 1)) 391 #define SAFEXCEL_G_IRQ_RING (1 << 16) 392 #define SAFEXCEL_G_IRQ_PE(n) (1 << ((n) + 20)) 393 394 /* SAFEXCEL_HIA_MST_CTRL */ 395 #define RD_CACHE_3BITS 0x5U 396 #define WR_CACHE_3BITS 0x3U 397 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | (1 << 0)) 398 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | (1 << 0)) 399 #define SAFEXCEL_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 400 #define SAFEXCEL_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 401 #define MST_CTRL_SUPPORT_PROT(n) (((n) & 0xf) << 12) 402 #define SAFEXCEL_MST_CTRL_BYTE_SWAP (1 << 24) 403 #define SAFEXCEL_MST_CTRL_NO_BYTE_SWAP (1 << 25) 404 405 /* SAFEXCEL_PE_IN_DBUF/TBUF_THRES */ 406 #define SAFEXCEL_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 407 #define SAFEXCEL_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 408 409 /* SAFEXCEL_PE_OUT_DBUF_THRES */ 410 #define SAFEXCEL_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 411 #define SAFEXCEL_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 412 413 /* SAFEXCEL_HIA_AIC_G_ACK */ 414 #define SAFEXCEL_AIC_G_ACK_ALL_MASK 0xffffffff 415 #define SAFEXCEL_AIC_G_ACK_HIA_MASK 0x7ff00000 416 417 /* SAFEXCEL_HIA_AIC_R_ENABLE_CLR */ 418 #define SAFEXCEL_HIA_AIC_R_ENABLE_CLR_ALL_MASK 0xffffffff 419 420 /* SAFEXCEL_PE_EIP96_CONTEXT_CTRL */ 421 #define SAFEXCEL_CONTEXT_SIZE(n) (n) 422 #define SAFEXCEL_ADDRESS_MODE (1 << 8) 423 #define SAFEXCEL_CONTROL_MODE (1 << 9) 424 425 /* SAFEXCEL_PE_EIP96_FUNCTION_EN */ 426 #define SAFEXCEL_FUNCTION_RSVD ((1U << 6) | (1U << 15) | (1U << 20) | (1U << 23)) 427 #define SAFEXCEL_PROTOCOL_HASH_ONLY (1U << 0) 428 #define SAFEXCEL_PROTOCOL_ENCRYPT_ONLY (1U << 1) 429 #define SAFEXCEL_PROTOCOL_HASH_ENCRYPT (1U << 2) 430 #define SAFEXCEL_PROTOCOL_HASH_DECRYPT (1U << 3) 431 #define SAFEXCEL_PROTOCOL_ENCRYPT_HASH (1U << 4) 432 #define SAFEXCEL_PROTOCOL_DECRYPT_HASH (1U << 5) 433 #define SAFEXCEL_ALG_ARC4 (1U << 7) 434 #define SAFEXCEL_ALG_AES_ECB (1U << 8) 435 #define SAFEXCEL_ALG_AES_CBC (1U << 9) 436 #define SAFEXCEL_ALG_AES_CTR_ICM (1U << 10) 437 #define SAFEXCEL_ALG_AES_OFB (1U << 11) 438 #define SAFEXCEL_ALG_AES_CFB (1U << 12) 439 #define SAFEXCEL_ALG_DES_ECB (1U << 13) 440 #define SAFEXCEL_ALG_DES_CBC (1U << 14) 441 #define SAFEXCEL_ALG_DES_OFB (1U << 16) 442 #define SAFEXCEL_ALG_DES_CFB (1U << 17) 443 #define SAFEXCEL_ALG_3DES_ECB (1U << 18) 444 #define SAFEXCEL_ALG_3DES_CBC (1U << 19) 445 #define SAFEXCEL_ALG_3DES_OFB (1U << 21) 446 #define SAFEXCEL_ALG_3DES_CFB (1U << 22) 447 #define SAFEXCEL_ALG_MD5 (1U << 24) 448 #define SAFEXCEL_ALG_HMAC_MD5 (1U << 25) 449 #define SAFEXCEL_ALG_SHA1 (1U << 26) 450 #define SAFEXCEL_ALG_HMAC_SHA1 (1U << 27) 451 #define SAFEXCEL_ALG_SHA2 (1U << 28) 452 #define SAFEXCEL_ALG_HMAC_SHA2 (1U << 29) 453 #define SAFEXCEL_ALG_AES_XCBC_MAC (1U << 30) 454 #define SAFEXCEL_ALG_GCM_HASH (1U << 31) 455 456 #endif /* _SAFEXCEL_REGS_H_ */
Cache object: e3075a639fc380e41fd29504cdca8479
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