Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sbsh/if_sbshreg.h
Version:
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1 /*- 2 * Granch SBNI16 G.SHDSL Modem driver definitions 3 * Written by Denis I. Timofeev, 2002-2003. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* SBNI16 controller chip definitions */ 30 31 /* CR bits */ 32 #define TXEN 0x01 /* transmitter enable */ 33 #define RXEN 0x02 /* receiver enable */ 34 #define NCRC 0x04 /* ignore received CRC */ 35 #define DLBK 0x08 /* digital loopback */ 36 #define CMOD 0x10 /* 0 - use CRC-32, 1 - CRC-16 */ 37 #define FMOD 0x20 /* interframe fill: 0 - all ones, 1 - 0xfe */ 38 #define PMOD 0x40 /* data polarity: 0 - normal, 1 - invert */ 39 #define XRST 0x80 /* reset the transceiver */ 40 41 /* CRB bits */ 42 #define RDBE 0x01 /* read burst enable */ 43 #define WTBE 0x02 /* write burst enable */ 44 #define RODD 0x04 /* receive 2-byte alignment */ 45 #define RXDE 0x08 /* receive data enable */ 46 47 /* SR and IMR bits */ 48 #define TXS 0x01 /* transmit success */ 49 #define RXS 0x02 /* receive success */ 50 /* SR only */ 51 #define CRC 0x04 /* CRC error */ 52 #define OFL 0x08 /* fifo overflow error */ 53 #define UFL 0x10 /* fifo underflow error */ 54 #define EXT 0x20 /* interrupt from sk70725 */ 55 /* IMR only */ 56 #define TSI 0x80 /* generate test interrupt */ 57 58 #define LAST_FRAG 0x00008000 59 60 #define SBNI16_MAX_FRAME (1536 + 16) 61 62 /* We don't have official vendor id yet... */ 63 #define SBNI16_VENDOR 0x55 64 #define SBNI16_DEVICE 0x9d 65 #define SBNI16_SUBDEV 3 66 67 /* transceiver chip set definitions */ 68 enum CX28975_API_commands { 69 _DSL_RESET_SYSTEM = 0x00, 70 _DSL_SYSTEM_ENABLE = 0x01, 71 _DSL_AFE_CONFIG = 0x02, 72 _DSL_TRAINING_MODE = 0x03, 73 _DSL_CLOCK_CONFIG = 0x04, 74 _DSL_PCM_MF_LEN = 0x05, 75 _DSL_SYSTEM_CONFIG = 0x06, 76 _DSL_LOOPBACK = 0x09, 77 _DSL_ACTIVATION = 0x0b, 78 _DSL_FORCE_DEACTIVATE = 0x0c, 79 _DSL_TEST_MODE = 0x0d, 80 _DSL_DATA_RATE = 0x0e, 81 _DSL_PREACTIVATION_CFG = 0x0f, 82 _DSL_FR_PCM_CONFIG = 0x10, 83 _DSL_FR_HDSL_CONFIG = 0x11, 84 _DSL_PCM_CLK_CONF = 0x12, 85 _AFE_TX_GAIN = 0x13, 86 _DSL_PREACT_USER_INFO = 0x14, 87 _DSL_PREACT_RATE_LIST = 0x15, 88 _DSL_TX_ISO_PULSE = 0x16, 89 _BP_ERLE_TEST_MODE = 0x18, 90 _DSL_MULTI_PAIR_CONFIG = 0x19, 91 _DSL_NB_MULTI_RATE_CONFIG = 0x1a, 92 _DSL_MULTI_RATE_CONFIG = 0x1b, 93 _ATM_PHY_MODE = 0x1c, 94 _ATM_PHY_UTOPIA_CONFIG = 0x1d, 95 _ATM_PHY_IF_MODE = 0x1e, 96 _ATM_PHY_INJECT_HEC_ERROR = 0x1f, 97 _ATM_PHY_CONFIG = 0x20, 98 _DSL_TNB_BER_STATE = 0x21, 99 _DSL_RNB_BER_STATE = 0x22, 100 _DSL_TP_BER_STATE = 0x23, 101 _DSL_RP_BER_STATE = 0x24, 102 _DSL_PRBS_CONFIGURE = 0x25, 103 _DSL_CONST_FILL = 0x26, 104 _DSL_DBANK = 0x27, 105 _DSL_NB_CONFIG = 0x28, 106 _DSL_TNB_FRM_OFST = 0x29, 107 _DSL_RNB_FRM_OFST = 0x2a, 108 _DSL_TP_FRM_OFST = 0x2e, 109 _DSL_RP_FRM_OFST = 0x2f, 110 _DSL_TP_MAPPER_VALUE = 0x30, 111 _DSL_TP_MAPPER_WRITE = 0x31, 112 _DSL_RP_MAPPER_VALUE = 0x32, 113 _DSL_RP_MAPPER_WRITE = 0x33, 114 _DSL_TH_MAPPER_VALUE = 0x34, 115 _DSL_TH_MAPPER_WRITE = 0x35, 116 _DSL_RH_MAPPER_VALUE = 0x36, 117 _DSL_RH_MAPPER_WRITE = 0x37, 118 _DSL_TNB_MAPPER_VALUE = 0x38, 119 _DSL_TNB_MAPPER_WRITE = 0x39, 120 _DSL_RNB_MAPPER_VALUE = 0x3a, 121 _DSL_RNB_MAPPER_WRITE = 0x3b, 122 _DSL_CLEAR_ERROR_CTRS = 0x40, 123 _DSL_INJECT_CRC_ERROR = 0x41, 124 _DSL_THRESHOLDS = 0x43, 125 _DSL_FR_SET_STATE_MACHINE = 0x4a, 126 _DSL_FR_TNB_RESET = 0x4b, 127 _DSL_FR_RNB_RESET = 0x4c, 128 _EOC_RESET = 0x4d, 129 _DSL_FR_TX_RESET = 0x4e, 130 _DSL_FR_RX_RESET = 0x4f, 131 _DSL_INTR_HOST_MASK = 0x50, 132 _DSL_INTR_API_SUBMASK = 0x51, 133 _DSL_DOWNLOAD_START = 0x53, 134 _DSL_DOWNLOAD_DATA = 0x54, 135 _DSL_DOWNLOAD_END = 0x55, 136 _DSL_DPLL_CLOCK_GEN = 0x58, 137 _DSL_NB_DPLL_CLOCK_GEN = 0x59, 138 _DSL_WRITE_REG = 0x75, 139 _DSL_WRITE_AFE = 0x76 140 }; 141 142 enum CX28975_status_commands { 143 _DSL_READ_CONTROL = 0x80, 144 _DSL_FAR_END_ATTEN = 0x82, 145 _DSL_NOISE_MARGIN = 0x83, 146 _DSL_STATUS = 0x85, 147 _DSL_PREACT_GET_FE_CAPS = 0x88, 148 _DSL_PREACT_GET_OPT_DATA_RATE = 0x89, 149 _DSL_VERSIONS = 0x8a, 150 _DSL_TP_BER_RESULTS = 0x8c, 151 _DSL_RP_BER_RESULTS = 0x8d, 152 _DSL_STAGE_NUMBER = 0x8f, 153 _DSL_AFE_SETTING = 0x90, 154 _DSL_TNB_BER_RESULTS = 0x91, 155 _DSL_RNB_BER_RESULTS = 0x92, 156 _BP_ERLE_RESULTS = 0x93, 157 _DSL_POWER_BACK_OFF_RESULT = 0x94, 158 _DSL_OPER_ERR_CTRS = 0x9c, 159 _DSL_TIME = 0x9d, 160 _DSL_HDSL_PERF_ERR_CTRS = 0x9e, 161 _DSL_READ_REG = 0xa0, 162 _DSL_READ_AFE = 0xa1, 163 _DSL_SYSTEM_PERF_ERR_CTRS = 0xa2, 164 _DSL_TP_MAPPER_READ = 0xa3, 165 _DSL_RP_MAPPER_READ = 0xa4, 166 _DSL_TH_MAPPER_READ = 0xa5, 167 _DSL_RH_MAPPER_READ = 0xa6, 168 _DSL_TNB_MAPPER_READ = 0xa7, 169 _DSL_RNB_MAPPER_READ = 0xa8, 170 _EOC_RX_GET_STATS = 0xae, 171 _EOC_TX_SEND_COMMAND = 0xb0, 172 _EOC_RX_GET_MSG = 0xb1, 173 _EOC_TX_GET_MSG_STATUS = 0xb2, 174 _EOC_TX_DELETE_MSG = 0xb3, 175 _ATM_PHY_OPER_ERR_CTRS = 0xb8, 176 _ATM_PHY_PERF_ERR_CTRS = 0xb9, 177 _ATM_PHY_CELL_CTRS = 0xba 178 }; 179 180 enum CX28975_acknoledge_status_codes { 181 _ACK_NOT_COMPLETE = 0x00, 182 _ACK_PASS = 0x01, 183 _ACK_BUSY = 0x02, 184 _ACK_NOT_APPLICABLE = 0x03, 185 _ACK_INVALID_DEST = 0x04, 186 _ACK_INVALID_OPCODE = 0x05, 187 _ACK_INVALID_LENGTH = 0x06, 188 _ACK_INVALID_DATA = 0x07, 189 _ACK_INVALID_CHKSUM = 0x08, 190 _ACK_NO_RESULT = 0x09, 191 _ACK_NOT_AVAILABLE = 0x0a, 192 _ACK_BOOT_WAKE_UP = 0x0d, 193 _ACK_OPER_WAKE_UP = 0x0e 194 };
Cache object: 2ab5e5abfc2abb20936ada08d100d06f
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