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sys/dev/sdhci/fsl_sdhci.c
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1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36 #include "opt_mmccam.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/bus.h> 42 #include <sys/callout.h> 43 #include <sys/kernel.h> 44 #include <sys/libkern.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/resource.h> 50 #include <sys/rman.h> 51 #include <sys/sysctl.h> 52 #include <sys/taskqueue.h> 53 #include <sys/time.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 #ifdef __arm__ 58 #include <machine/intr.h> 59 60 #include <arm/freescale/imx/imx_ccmvar.h> 61 #endif 62 63 #ifdef __powerpc__ 64 #include <powerpc/mpc85xx/mpc85xx.h> 65 #endif 66 67 #include <dev/gpio/gpiobusvar.h> 68 69 #include <dev/ofw/ofw_bus.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include <dev/mmc/bridge.h> 73 74 #include <dev/sdhci/sdhci.h> 75 #include <dev/sdhci/sdhci_fdt_gpio.h> 76 77 #include "mmcbr_if.h" 78 #include "sdhci_if.h" 79 80 struct fsl_sdhci_softc { 81 device_t dev; 82 struct resource * mem_res; 83 struct resource * irq_res; 84 void * intr_cookie; 85 struct sdhci_slot slot; 86 struct callout r1bfix_callout; 87 sbintime_t r1bfix_timeout_at; 88 struct sdhci_fdt_gpio * gpio; 89 uint32_t baseclk_hz; 90 uint32_t cmd_and_mode; 91 uint32_t r1bfix_intmask; 92 uint16_t sdclockreg_freq_bits; 93 uint8_t r1bfix_type; 94 uint8_t hwtype; 95 bool slot_init_done; 96 }; 97 98 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 99 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 100 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 101 102 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 103 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ 104 #define HWTYPE_USDHC 2 /* fsl6. */ 105 106 /* 107 * Freescale-specific registers, or in some cases the layout of bits within the 108 * sdhci-defined register is different on Freescale. These names all begin with 109 * SDHC_ (not SDHCI_). 110 */ 111 112 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 113 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 114 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 115 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 116 #define SDHC_VEND_IPGEN (1 << 11) 117 #define SDHC_VEND_HCKEN (1 << 12) 118 #define SDHC_VEND_PEREN (1 << 13) 119 120 #define SDHC_PRES_STATE 0x24 121 #define SDHC_PRES_CIHB (1 << 0) 122 #define SDHC_PRES_CDIHB (1 << 1) 123 #define SDHC_PRES_DLA (1 << 2) 124 #define SDHC_PRES_SDSTB (1 << 3) 125 #define SDHC_PRES_IPGOFF (1 << 4) 126 #define SDHC_PRES_HCKOFF (1 << 5) 127 #define SDHC_PRES_PEROFF (1 << 6) 128 #define SDHC_PRES_SDOFF (1 << 7) 129 #define SDHC_PRES_WTA (1 << 8) 130 #define SDHC_PRES_RTA (1 << 9) 131 #define SDHC_PRES_BWEN (1 << 10) 132 #define SDHC_PRES_BREN (1 << 11) 133 #define SDHC_PRES_RTR (1 << 12) 134 #define SDHC_PRES_CINST (1 << 16) 135 #define SDHC_PRES_CDPL (1 << 18) 136 #define SDHC_PRES_WPSPL (1 << 19) 137 #define SDHC_PRES_CLSL (1 << 23) 138 #define SDHC_PRES_DLSL_SHIFT 24 139 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 140 141 #define SDHC_PROT_CTRL 0x28 142 #define SDHC_PROT_LED (1 << 0) 143 #define SDHC_PROT_WIDTH_1BIT (0 << 1) 144 #define SDHC_PROT_WIDTH_4BIT (1 << 1) 145 #define SDHC_PROT_WIDTH_8BIT (2 << 1) 146 #define SDHC_PROT_WIDTH_MASK (3 << 1) 147 #define SDHC_PROT_D3CD (1 << 3) 148 #define SDHC_PROT_EMODE_BIG (0 << 4) 149 #define SDHC_PROT_EMODE_HALF (1 << 4) 150 #define SDHC_PROT_EMODE_LITTLE (2 << 4) 151 #define SDHC_PROT_EMODE_MASK (3 << 4) 152 #define SDHC_PROT_SDMA (0 << 8) 153 #define SDHC_PROT_ADMA1 (1 << 8) 154 #define SDHC_PROT_ADMA2 (2 << 8) 155 #define SDHC_PROT_ADMA264 (3 << 8) 156 #define SDHC_PROT_DMA_MASK (3 << 8) 157 #define SDHC_PROT_CDTL (1 << 6) 158 #define SDHC_PROT_CDSS (1 << 7) 159 160 #define SDHC_SYS_CTRL 0x2c 161 162 /* 163 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 164 * they are the same bits in both cases. The divisor values go into the 165 * standard sdhci clock register, but in different bit positions and meanings 166 than the sdhci spec values. 167 */ 168 #define SDHC_CLK_IPGEN (1 << 0) 169 #define SDHC_CLK_HCKEN (1 << 1) 170 #define SDHC_CLK_PEREN (1 << 2) 171 #define SDHC_CLK_SDCLKEN (1 << 3) 172 #define SDHC_CLK_ENABLE_MASK 0x0000000f 173 #define SDHC_CLK_DIVISOR_MASK 0x000000f0 174 #define SDHC_CLK_DIVISOR_SHIFT 4 175 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00 176 #define SDHC_CLK_PRESCALE_SHIFT 8 177 178 static struct ofw_compat_data compat_data[] = { 179 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 180 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 181 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 182 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 183 {"fsl,esdhc", HWTYPE_ESDHC}, 184 {NULL, HWTYPE_NONE}, 185 }; 186 187 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); 188 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); 189 static void fsl_sdhci_r1bfix_func(void *arg); 190 191 static inline uint32_t 192 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) 193 { 194 195 return (bus_read_4(sc->mem_res, off)); 196 } 197 198 static inline void 199 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) 200 { 201 202 bus_write_4(sc->mem_res, off, val); 203 } 204 205 static uint8_t 206 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 207 { 208 struct fsl_sdhci_softc *sc = device_get_softc(dev); 209 uint32_t val32, wrk32; 210 211 /* 212 * Most of the things in the standard host control register are in the 213 * hardware's wider protocol control register, but some of the bits are 214 * moved around. 215 */ 216 if (off == SDHCI_HOST_CONTROL) { 217 wrk32 = RD4(sc, SDHC_PROT_CTRL); 218 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 219 SDHCI_CTRL_FORCE_CARD); 220 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 221 case SDHC_PROT_WIDTH_1BIT: 222 /* Value is already 0. */ 223 break; 224 case SDHC_PROT_WIDTH_4BIT: 225 val32 |= SDHCI_CTRL_4BITBUS; 226 break; 227 case SDHC_PROT_WIDTH_8BIT: 228 val32 |= SDHCI_CTRL_8BITBUS; 229 break; 230 } 231 switch (wrk32 & SDHC_PROT_DMA_MASK) { 232 case SDHC_PROT_SDMA: 233 /* Value is already 0. */ 234 break; 235 case SDHC_PROT_ADMA1: 236 /* This value is deprecated, should never appear. */ 237 break; 238 case SDHC_PROT_ADMA2: 239 val32 |= SDHCI_CTRL_ADMA2; 240 break; 241 case SDHC_PROT_ADMA264: 242 val32 |= SDHCI_CTRL_ADMA264; 243 break; 244 } 245 return val32; 246 } 247 248 /* 249 * XXX can't find the bus power on/off knob. For now we have to say the 250 * power is always on and always set to the same voltage. 251 */ 252 if (off == SDHCI_POWER_CONTROL) { 253 return (SDHCI_POWER_ON | SDHCI_POWER_300); 254 } 255 256 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 257 } 258 259 static uint16_t 260 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 261 { 262 struct fsl_sdhci_softc *sc = device_get_softc(dev); 263 uint32_t val32; 264 265 if (sc->hwtype == HWTYPE_USDHC) { 266 /* 267 * The USDHC hardware has nothing in the version register, but 268 * it's v3 compatible with all our translation code. 269 */ 270 if (off == SDHCI_HOST_VERSION) { 271 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 272 } 273 /* 274 * The USDHC hardware moved the transfer mode bits to the mixed 275 * control register, fetch them from there. 276 */ 277 if (off == SDHCI_TRANSFER_MODE) 278 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 279 280 } else if (sc->hwtype == HWTYPE_ESDHC) { 281 /* 282 * The ESDHC hardware has the typical 32-bit combined "command 283 * and mode" register that we have to cache so that command 284 * isn't written until after mode. On a read, just retrieve the 285 * cached values last written. 286 */ 287 if (off == SDHCI_TRANSFER_MODE) { 288 return (sc->cmd_and_mode & 0x0000ffff); 289 } else if (off == SDHCI_COMMAND_FLAGS) { 290 return (sc->cmd_and_mode >> 16); 291 } 292 } 293 294 /* 295 * This hardware only manages one slot. Synthesize a slot interrupt 296 * status register... if there are any enabled interrupts active they 297 * must be coming from our one and only slot. 298 */ 299 if (off == SDHCI_SLOT_INT_STATUS) { 300 val32 = RD4(sc, SDHCI_INT_STATUS); 301 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 302 return (val32 ? 1 : 0); 303 } 304 305 /* 306 * Clock bits are scattered into various registers which differ by 307 * hardware type, complex enough to have their own function. 308 */ 309 if (off == SDHCI_CLOCK_CONTROL) { 310 return (fsl_sdhc_get_clock(sc)); 311 } 312 313 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 314 } 315 316 static uint32_t 317 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 318 { 319 struct fsl_sdhci_softc *sc = device_get_softc(dev); 320 uint32_t val32, wrk32; 321 322 val32 = RD4(sc, off); 323 324 /* 325 * The hardware leaves the base clock frequency out of the capabilities 326 * register, but we filled it in by setting slot->max_clk at attach time 327 * rather than here, because we can't represent frequencies above 63MHz 328 * in an sdhci 2.0 capabliities register. The timeout clock is the same 329 * as the active output sdclock; we indicate that with a quirk setting 330 * so don't populate the timeout frequency bits. 331 * 332 * XXX Turn off (for now) features the hardware can do but this driver 333 * doesn't yet handle (1.8v, suspend/resume, etc). 334 */ 335 if (off == SDHCI_CAPABILITIES) { 336 val32 &= ~SDHCI_CAN_VDD_180; 337 val32 &= ~SDHCI_CAN_DO_SUSPEND; 338 val32 |= SDHCI_CAN_DO_8BITBUS; 339 return (val32); 340 } 341 342 /* 343 * The hardware moves bits around in the present state register to make 344 * room for all 8 data line state bits. To translate, mask out all the 345 * bits which are not in the same position in both registers (this also 346 * masks out some Freescale-specific bits in locations defined as 347 * reserved by sdhci), then shift the data line and retune request bits 348 * down to their standard locations. 349 */ 350 if (off == SDHCI_PRESENT_STATE) { 351 wrk32 = val32; 352 val32 &= 0x000F0F07; 353 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 354 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 355 return (val32); 356 } 357 358 /* 359 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a 360 * command with an R1B response, mix it into the hardware status. 361 */ 362 if (off == SDHCI_INT_STATUS) { 363 return (val32 | sc->r1bfix_intmask); 364 } 365 366 return val32; 367 } 368 369 static void 370 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 371 uint32_t *data, bus_size_t count) 372 { 373 struct fsl_sdhci_softc *sc = device_get_softc(dev); 374 375 bus_read_multi_4(sc->mem_res, off, data, count); 376 } 377 378 static void 379 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 380 { 381 struct fsl_sdhci_softc *sc = device_get_softc(dev); 382 uint32_t val32; 383 384 /* 385 * Most of the things in the standard host control register are in the 386 * hardware's wider protocol control register, but some of the bits are 387 * moved around. 388 */ 389 if (off == SDHCI_HOST_CONTROL) { 390 val32 = RD4(sc, SDHC_PROT_CTRL); 391 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 392 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 393 val32 |= (val & SDHCI_CTRL_LED); 394 if (val & SDHCI_CTRL_8BITBUS) 395 val32 |= SDHC_PROT_WIDTH_8BIT; 396 else 397 val32 |= (val & SDHCI_CTRL_4BITBUS); 398 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 399 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 400 WR4(sc, SDHC_PROT_CTRL, val32); 401 return; 402 } 403 404 /* XXX I can't find the bus power on/off knob; do nothing. */ 405 if (off == SDHCI_POWER_CONTROL) { 406 return; 407 } 408 #ifdef __powerpc__ 409 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ 410 if (off == SDHCI_SOFTWARE_RESET) 411 return; 412 #endif 413 414 val32 = RD4(sc, off & ~3); 415 val32 &= ~(0xff << (off & 3) * 8); 416 val32 |= (val << (off & 3) * 8); 417 418 WR4(sc, off & ~3, val32); 419 } 420 421 static void 422 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 423 { 424 struct fsl_sdhci_softc *sc = device_get_softc(dev); 425 uint32_t val32; 426 427 /* 428 * The clock control stuff is complex enough to have its own function 429 * that can handle the ESDHC versus USDHC differences. 430 */ 431 if (off == SDHCI_CLOCK_CONTROL) { 432 fsl_sdhc_set_clock(sc, val); 433 return; 434 } 435 436 /* 437 * Figure out whether we need to check the DAT0 line for busy status at 438 * interrupt time. The controller should be doing this, but for some 439 * reason it doesn't. There are two cases: 440 * - R1B response with no data transfer should generate a DATA_END (aka 441 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 442 * there's no data transfer there's no DATA_END interrupt. This is 443 * documented; they seem to think it's a feature. 444 * - R1B response after Auto-CMD12 appears to not work, even though 445 * there's a control bit for it (bit 3) in the vendor register. 446 * When we're starting a command that needs a manual DAT0 line check at 447 * interrupt time, we leave ourselves a note in r1bfix_type so that we 448 * can do the extra work in fsl_sdhci_intr(). 449 */ 450 if (off == SDHCI_COMMAND_FLAGS) { 451 if (val & SDHCI_CMD_DATA) { 452 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 453 val32 = RD4(sc, USDHC_MIX_CONTROL); 454 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 455 sc->r1bfix_type = R1BFIX_AC12; 456 } else { 457 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 458 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 459 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 460 sc->r1bfix_type = R1BFIX_NODATA; 461 } 462 } 463 } 464 465 /* 466 * The USDHC hardware moved the transfer mode bits to mixed control; we 467 * just write them there and we're done. The ESDHC hardware has the 468 * typical combined cmd-and-mode register that allows only 32-bit 469 * access, so when writing the mode bits just save them, then later when 470 * writing the command bits, add in the saved mode bits. 471 */ 472 if (sc->hwtype == HWTYPE_USDHC) { 473 if (off == SDHCI_TRANSFER_MODE) { 474 val32 = RD4(sc, USDHC_MIX_CONTROL); 475 val32 &= ~0x3f; 476 val32 |= val & 0x37; 477 // XXX acmd23 not supported here (or by sdhci driver) 478 WR4(sc, USDHC_MIX_CONTROL, val32); 479 return; 480 } 481 } else if (sc->hwtype == HWTYPE_ESDHC) { 482 if (off == SDHCI_TRANSFER_MODE) { 483 sc->cmd_and_mode = 484 (sc->cmd_and_mode & 0xffff0000) | val; 485 return; 486 } else if (off == SDHCI_COMMAND_FLAGS) { 487 sc->cmd_and_mode = 488 (sc->cmd_and_mode & 0xffff) | (val << 16); 489 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 490 return; 491 } 492 } 493 494 val32 = RD4(sc, off & ~3); 495 val32 &= ~(0xffff << (off & 3) * 8); 496 val32 |= ((val & 0xffff) << (off & 3) * 8); 497 WR4(sc, off & ~3, val32); 498 } 499 500 static void 501 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 502 { 503 struct fsl_sdhci_softc *sc = device_get_softc(dev); 504 505 /* Clear synthesized interrupts, then pass the value to the hardware. */ 506 if (off == SDHCI_INT_STATUS) { 507 sc->r1bfix_intmask &= ~val; 508 } 509 510 WR4(sc, off, val); 511 } 512 513 static void 514 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 515 uint32_t *data, bus_size_t count) 516 { 517 struct fsl_sdhci_softc *sc = device_get_softc(dev); 518 519 bus_write_multi_4(sc->mem_res, off, data, count); 520 } 521 522 static uint16_t 523 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) 524 { 525 uint16_t val; 526 527 /* 528 * Whenever the sdhci driver writes the clock register we save a 529 * snapshot of just the frequency bits, so that we can play them back 530 * here on a register read without recalculating the frequency from the 531 * prescalar and divisor bits in the real register. We'll start with 532 * those bits, and mix in the clock status and enable bits that come 533 * from different places depending on which hardware we've got. 534 */ 535 val = sc->sdclockreg_freq_bits; 536 537 /* 538 * The internal clock is always enabled (actually, the hardware manages 539 * it). Whether the internal clock is stable yet after a frequency 540 * change comes from the present-state register on both hardware types. 541 */ 542 val |= SDHCI_CLOCK_INT_EN; 543 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) 544 val |= SDHCI_CLOCK_INT_STABLE; 545 546 /* 547 * On i.MX ESDHC hardware the card bus clock enable is in the usual 548 * sdhci register but it's a different bit, so transcribe it (note the 549 * difference between standard SDHCI_ and Freescale SDHC_ prefixes 550 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but 551 * no force-off for the card bus clock (the hardware runs the clock when 552 * transfers are active no matter what), so we always say the clock is 553 * on. 554 * XXX Maybe we should say it's in whatever state the sdhci driver last 555 * set it to. 556 */ 557 if (sc->hwtype == HWTYPE_ESDHC) { 558 #ifdef __arm__ 559 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) 560 #endif 561 val |= SDHCI_CLOCK_CARD_EN; 562 } else { 563 val |= SDHCI_CLOCK_CARD_EN; 564 } 565 566 return (val); 567 } 568 569 static void 570 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) 571 { 572 uint32_t divisor, freq, prescale, val32; 573 574 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 575 576 /* 577 * Save the frequency-setting bits in SDHCI format so that we can play 578 * them back in get_clock without complex decoding of hardware regs, 579 * then deal with the freqency part of the value based on hardware type. 580 */ 581 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; 582 if (sc->hwtype == HWTYPE_ESDHC) { 583 /* 584 * The i.MX5 ESDHC hardware requires the driver to manually 585 * start and stop the sd bus clock. If the enable bit is not 586 * set, turn off the clock in hardware and we're done, otherwise 587 * decode the requested frequency. ESDHC hardware is sdhci 2.0; 588 * the sdhci driver will use the original 8-bit divisor field 589 * and the "base / 2^N" divisor scheme. 590 */ 591 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 592 #ifdef __arm__ 593 /* On QorIQ, this is a reserved bit. */ 594 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); 595 #endif 596 return; 597 } 598 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 599 freq = sc->baseclk_hz >> ffs(divisor); 600 } else { 601 /* 602 * The USDHC hardware provides only "force always on" control 603 * over the sd bus clock, but no way to turn it off. (If a cmd 604 * or data transfer is in progress the clock is on, otherwise it 605 * is off.) If the clock is being disabled, we can just return 606 * now, otherwise we decode the requested frequency. USDHC 607 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit 608 * divisor using the "base / 2*N" divisor scheme. 609 */ 610 if ((val & SDHCI_CLOCK_CARD_EN) == 0) 611 return; 612 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 613 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 614 SDHCI_DIVIDER_MASK_LEN; 615 if (divisor == 0) 616 freq = sc->baseclk_hz; 617 else 618 freq = sc->baseclk_hz / (2 * divisor); 619 } 620 621 /* 622 * Get a prescaler and final divisor to achieve the desired frequency. 623 */ 624 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 625 prescale <<= 1; 626 627 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 628 ++divisor; 629 630 #ifdef DEBUG 631 device_printf(sc->dev, 632 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 633 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 634 prescale, divisor); 635 #endif 636 637 /* 638 * Adjust to zero-based values, and store them to the hardware. 639 */ 640 prescale >>= 1; 641 divisor -= 1; 642 643 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); 644 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 645 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 646 val32 |= SDHC_CLK_IPGEN; 647 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 648 } 649 650 static boolean_t 651 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) 652 { 653 uint32_t inhibit; 654 655 mtx_assert(&sc->slot.mtx, MA_OWNED); 656 657 /* 658 * Check the DAT0 line status using both the DLA (data line active) and 659 * CDIHB (data inhibit) bits in the present state register. In theory 660 * just DLA should do the trick, but in practice it takes both. If the 661 * DAT0 line is still being held and we're not yet beyond the timeout 662 * point, just schedule another callout to check again later. 663 */ 664 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 665 666 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 667 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 668 fsl_sdhci_r1bfix_func, sc, 0); 669 return (false); 670 } 671 672 /* 673 * If we reach this point with the inhibit bits still set, we've got a 674 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 675 * line has been released, and we synthesize a DATA_END, and if the type 676 * of fix needed was on a command-without-data we also now add in the 677 * original INT_RESPONSE that we suppressed earlier. 678 */ 679 if (inhibit) 680 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 681 else { 682 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 683 if (sc->r1bfix_type == R1BFIX_NODATA) 684 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 685 } 686 687 sc->r1bfix_type = R1BFIX_NONE; 688 return (true); 689 } 690 691 static void 692 fsl_sdhci_r1bfix_func(void * arg) 693 { 694 struct fsl_sdhci_softc *sc = arg; 695 boolean_t r1bwait_done; 696 697 mtx_lock(&sc->slot.mtx); 698 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); 699 mtx_unlock(&sc->slot.mtx); 700 if (r1bwait_done) 701 sdhci_generic_intr(&sc->slot); 702 } 703 704 static void 705 fsl_sdhci_intr(void *arg) 706 { 707 struct fsl_sdhci_softc *sc = arg; 708 uint32_t intmask; 709 710 mtx_lock(&sc->slot.mtx); 711 712 /* 713 * Manually check the DAT0 line for R1B response types that the 714 * controller fails to handle properly. The controller asserts the done 715 * interrupt while the card is still asserting busy with the DAT0 line. 716 * 717 * We check DAT0 immediately because most of the time, especially on a 718 * read, the card will actually be done by time we get here. If it's 719 * not, then the wait_done routine will schedule a callout to re-check 720 * periodically until it is done. In that case we clear the interrupt 721 * out of the hardware now so that we can present it later when the DAT0 722 * line is released. 723 * 724 * If we need to wait for the DAT0 line to be released, we set up a 725 * timeout point 250ms in the future. This number comes from the SD 726 * spec, which allows a command to take that long. In the real world, 727 * cards tend to take 10-20ms for a long-running command such as a write 728 * or erase that spans two pages. 729 */ 730 switch (sc->r1bfix_type) { 731 case R1BFIX_NODATA: 732 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; 733 break; 734 case R1BFIX_AC12: 735 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; 736 break; 737 default: 738 intmask = 0; 739 break; 740 } 741 if (intmask) { 742 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 743 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { 744 WR4(sc, SDHCI_INT_STATUS, intmask); 745 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, 746 BUS_SPACE_BARRIER_WRITE); 747 } 748 } 749 750 mtx_unlock(&sc->slot.mtx); 751 sdhci_generic_intr(&sc->slot); 752 } 753 754 static int 755 fsl_sdhci_get_ro(device_t bus, device_t child) 756 { 757 struct fsl_sdhci_softc *sc = device_get_softc(bus); 758 759 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 760 } 761 762 static bool 763 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 764 { 765 struct fsl_sdhci_softc *sc = device_get_softc(dev); 766 767 return (sdhci_fdt_gpio_get_present(sc->gpio)); 768 } 769 770 #ifdef __powerpc__ 771 static uint32_t 772 fsl_sdhci_get_platform_clock(device_t dev) 773 { 774 phandle_t node; 775 uint32_t clock; 776 777 node = ofw_bus_get_node(dev); 778 779 /* Get sdhci node properties */ 780 if((OF_getprop(node, "clock-frequency", (void *)&clock, 781 sizeof(clock)) <= 0) || (clock == 0)) { 782 clock = mpc85xx_get_system_clock(); 783 784 if (clock == 0) { 785 device_printf(dev,"Cannot acquire correct sdhci " 786 "frequency from DTS.\n"); 787 788 return (0); 789 } 790 } 791 792 if (bootverbose) 793 device_printf(dev, "Acquired clock: %d from DTS\n", clock); 794 795 return (clock); 796 } 797 #endif 798 799 static int 800 fsl_sdhci_detach(device_t dev) 801 { 802 struct fsl_sdhci_softc *sc = device_get_softc(dev); 803 804 if (sc->gpio != NULL) 805 sdhci_fdt_gpio_teardown(sc->gpio); 806 807 callout_drain(&sc->r1bfix_callout); 808 809 if (sc->slot_init_done) 810 sdhci_cleanup_slot(&sc->slot); 811 812 if (sc->intr_cookie != NULL) 813 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 814 if (sc->irq_res != NULL) 815 bus_release_resource(dev, SYS_RES_IRQ, 816 rman_get_rid(sc->irq_res), sc->irq_res); 817 818 if (sc->mem_res != NULL) { 819 bus_release_resource(dev, SYS_RES_MEMORY, 820 rman_get_rid(sc->mem_res), sc->mem_res); 821 } 822 823 return (0); 824 } 825 826 static int 827 fsl_sdhci_attach(device_t dev) 828 { 829 struct fsl_sdhci_softc *sc = device_get_softc(dev); 830 int rid, err; 831 #ifdef __powerpc__ 832 phandle_t node; 833 uint32_t protctl; 834 #endif 835 836 sc->dev = dev; 837 838 callout_init(&sc->r1bfix_callout, 1); 839 840 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 841 if (sc->hwtype == HWTYPE_NONE) 842 panic("Impossible: not compatible in fsl_sdhci_attach()"); 843 844 rid = 0; 845 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 846 RF_ACTIVE); 847 if (!sc->mem_res) { 848 device_printf(dev, "cannot allocate memory window\n"); 849 err = ENXIO; 850 goto fail; 851 } 852 853 rid = 0; 854 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 855 RF_ACTIVE); 856 if (!sc->irq_res) { 857 device_printf(dev, "cannot allocate interrupt\n"); 858 err = ENXIO; 859 goto fail; 860 } 861 862 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 863 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { 864 device_printf(dev, "cannot setup interrupt handler\n"); 865 err = ENXIO; 866 goto fail; 867 } 868 869 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 870 871 /* 872 * DMA is not really broken, I just haven't implemented it yet. 873 */ 874 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 875 876 /* 877 * Set the buffer watermark level to 128 words (512 bytes) for both read 878 * and write. The hardware has a restriction that when the read or 879 * write ready status is asserted, that means you can read exactly the 880 * number of words set in the watermark register before you have to 881 * re-check the status and potentially wait for more data. The main 882 * sdhci driver provides no hook for doing status checking on less than 883 * a full block boundary, so we set the watermark level to be a full 884 * block. Reads and writes where the block size is less than the 885 * watermark size will work correctly too, no need to change the 886 * watermark for different size blocks. However, 128 is the maximum 887 * allowed for the watermark, so PIO is limitted to 512 byte blocks 888 * (which works fine for SD cards, may be a problem for SDIO some day). 889 * 890 * XXX need named constants for this stuff. 891 */ 892 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ 893 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) 894 WR4(sc, SDHC_WTMK_LVL, 0x10801080); 895 else 896 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 897 898 /* 899 * We read in native byte order in the main driver, but the register 900 * defaults to little endian. 901 */ 902 #ifdef __powerpc__ 903 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); 904 #else 905 sc->baseclk_hz = imx_ccm_sdhci_hz(); 906 #endif 907 sc->slot.max_clk = sc->baseclk_hz; 908 909 /* 910 * Set up any gpio pin handling described in the FDT data. This cannot 911 * fail; see comments in sdhci_fdt_gpio.h for details. 912 */ 913 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 914 915 #ifdef __powerpc__ 916 node = ofw_bus_get_node(dev); 917 /* Default to big-endian on powerpc */ 918 protctl = RD4(sc, SDHC_PROT_CTRL); 919 protctl &= ~SDHC_PROT_EMODE_MASK; 920 if (OF_hasprop(node, "little-endian")) 921 protctl |= SDHC_PROT_EMODE_LITTLE; 922 else 923 protctl |= SDHC_PROT_EMODE_BIG; 924 WR4(sc, SDHC_PROT_CTRL, protctl); 925 #endif 926 927 sdhci_init_slot(dev, &sc->slot, 0); 928 sc->slot_init_done = true; 929 930 bus_generic_probe(dev); 931 bus_generic_attach(dev); 932 933 sdhci_start_slot(&sc->slot); 934 935 return (0); 936 937 fail: 938 fsl_sdhci_detach(dev); 939 return (err); 940 } 941 942 static int 943 fsl_sdhci_probe(device_t dev) 944 { 945 946 if (!ofw_bus_status_okay(dev)) 947 return (ENXIO); 948 949 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 950 case HWTYPE_ESDHC: 951 device_set_desc(dev, "Freescale eSDHC controller"); 952 return (BUS_PROBE_DEFAULT); 953 case HWTYPE_USDHC: 954 device_set_desc(dev, "Freescale uSDHC controller"); 955 return (BUS_PROBE_DEFAULT); 956 default: 957 break; 958 } 959 return (ENXIO); 960 } 961 962 static device_method_t fsl_sdhci_methods[] = { 963 /* Device interface */ 964 DEVMETHOD(device_probe, fsl_sdhci_probe), 965 DEVMETHOD(device_attach, fsl_sdhci_attach), 966 DEVMETHOD(device_detach, fsl_sdhci_detach), 967 968 /* Bus interface */ 969 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 970 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 971 972 /* MMC bridge interface */ 973 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 974 DEVMETHOD(mmcbr_request, sdhci_generic_request), 975 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), 976 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 977 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 978 979 /* SDHCI accessors */ 980 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), 981 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), 982 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), 983 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), 984 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), 985 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), 986 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), 987 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), 988 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), 989 990 DEVMETHOD_END 991 }; 992 993 static driver_t fsl_sdhci_driver = { 994 "sdhci_fsl", 995 fsl_sdhci_methods, 996 sizeof(struct fsl_sdhci_softc), 997 }; 998 999 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, NULL, NULL); 1000 SDHCI_DEPEND(sdhci_fsl); 1001 1002 #ifndef MMCCAM 1003 MMC_DECLARE_BRIDGE(sdhci_fsl); 1004 #endif
Cache object: 399e31b9928850551697c5d9de66ed67
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