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sys/dev/sdhci/sdhci.c
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1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD: releng/8.4/sys/dev/sdhci/sdhci.c 234492 2012-04-20 14:45:57Z marius $"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include "mmcbr_if.h" 54 #include "sdhci.h" 55 56 #define DMA_BLOCK_SIZE 4096 57 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 58 59 /* Controller doesn't honor resets unless we touch the clock register */ 60 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 61 /* Controller really supports DMA */ 62 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 63 /* Controller has unusable DMA engine */ 64 #define SDHCI_QUIRK_BROKEN_DMA (1<<2) 65 /* Controller doesn't like to be reset when there is no card inserted. */ 66 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 67 /* Controller has flaky internal state so reset it on each ios change */ 68 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 69 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 70 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 71 /* Controller needs to be reset after each request to stay stable */ 72 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 73 /* Controller has an off-by-one issue with timeout value */ 74 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 75 /* Controller has broken read timings */ 76 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 77 78 static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 char *desc; 82 u_int quirks; 83 } sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 87 SDHCI_QUIRK_FORCE_DMA }, 88 { 0x05501524, 0xffff, "ENE CB712 SD", 89 SDHCI_QUIRK_BROKEN_TIMINGS }, 90 { 0x05511524, 0xffff, "ENE CB712 SD 2", 91 SDHCI_QUIRK_BROKEN_TIMINGS }, 92 { 0x07501524, 0xffff, "ENE CB714 SD", 93 SDHCI_QUIRK_RESET_ON_IOS | 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x07511524, 0xffff, "ENE CB714 SD 2", 96 SDHCI_QUIRK_RESET_ON_IOS | 97 SDHCI_QUIRK_BROKEN_TIMINGS }, 98 { 0x410111ab, 0xffff, "Marvell CaFe SD", 99 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 100 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 101 SDHCI_QUIRK_32BIT_DMA_SIZE | 102 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 103 { 0, 0xffff, NULL, 104 0 } 105 }; 106 107 struct sdhci_softc; 108 109 struct sdhci_slot { 110 struct sdhci_softc *sc; 111 device_t dev; /* Slot device */ 112 u_char num; /* Slot number */ 113 u_char opt; /* Slot options */ 114 #define SDHCI_HAVE_DMA 1 115 uint32_t max_clk; /* Max possible freq */ 116 uint32_t timeout_clk; /* Timeout freq */ 117 struct resource *mem_res; /* Memory resource */ 118 int mem_rid; 119 bus_dma_tag_t dmatag; 120 bus_dmamap_t dmamap; 121 u_char *dmamem; 122 bus_addr_t paddr; /* DMA buffer address */ 123 struct task card_task; /* Card presence check task */ 124 struct callout card_callout; /* Card insert delay callout */ 125 struct mmc_host host; /* Host parameters */ 126 struct mmc_request *req; /* Current request */ 127 struct mmc_command *curcmd; /* Current command of current request */ 128 129 uint32_t intmask; /* Current interrupt mask */ 130 uint32_t clock; /* Current clock freq. */ 131 size_t offset; /* Data buffer offset */ 132 uint8_t hostctrl; /* Current host control register */ 133 u_char power; /* Current power */ 134 u_char bus_busy; /* Bus busy status */ 135 u_char cmd_done; /* CMD command part done flag */ 136 u_char data_done; /* DAT command part done flag */ 137 u_char flags; /* Request execution flags */ 138 #define CMD_STARTED 1 139 #define STOP_STARTED 2 140 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 141 struct mtx mtx; /* Slot mutex */ 142 }; 143 144 struct sdhci_softc { 145 device_t dev; /* Controller device */ 146 u_int quirks; /* Chip specific quirks */ 147 struct resource *irq_res; /* IRQ resource */ 148 int irq_rid; 149 void *intrhand; /* Interrupt handle */ 150 151 int num_slots; /* Number of slots on this controller */ 152 struct sdhci_slot slots[6]; 153 }; 154 155 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 156 157 int sdhci_debug; 158 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 159 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 160 161 static inline uint8_t 162 RD1(struct sdhci_slot *slot, bus_size_t off) 163 { 164 bus_barrier(slot->mem_res, 0, 0xFF, 165 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 166 return bus_read_1(slot->mem_res, off); 167 } 168 169 static inline void 170 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) 171 { 172 bus_barrier(slot->mem_res, 0, 0xFF, 173 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 174 bus_write_1(slot->mem_res, off, val); 175 } 176 177 static inline uint16_t 178 RD2(struct sdhci_slot *slot, bus_size_t off) 179 { 180 bus_barrier(slot->mem_res, 0, 0xFF, 181 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182 return bus_read_2(slot->mem_res, off); 183 } 184 185 static inline void 186 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) 187 { 188 bus_barrier(slot->mem_res, 0, 0xFF, 189 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 190 bus_write_2(slot->mem_res, off, val); 191 } 192 193 static inline uint32_t 194 RD4(struct sdhci_slot *slot, bus_size_t off) 195 { 196 bus_barrier(slot->mem_res, 0, 0xFF, 197 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 198 return bus_read_4(slot->mem_res, off); 199 } 200 201 static inline void 202 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) 203 { 204 bus_barrier(slot->mem_res, 0, 0xFF, 205 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 206 bus_write_4(slot->mem_res, off, val); 207 } 208 209 /* bus entry points */ 210 static int sdhci_probe(device_t dev); 211 static int sdhci_attach(device_t dev); 212 static int sdhci_detach(device_t dev); 213 static void sdhci_intr(void *); 214 215 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 216 static void sdhci_start(struct sdhci_slot *slot); 217 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 218 219 static void sdhci_card_task(void *, int); 220 221 /* helper routines */ 222 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 223 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 224 #define SDHCI_LOCK_INIT(_slot) \ 225 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 226 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 227 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 228 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 229 230 static int 231 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 232 { 233 va_list ap; 234 int retval; 235 236 retval = printf("%s-slot%d: ", 237 device_get_nameunit(slot->sc->dev), slot->num); 238 239 va_start(ap, fmt); 240 retval += vprintf(fmt, ap); 241 va_end(ap); 242 return (retval); 243 } 244 245 static void 246 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 247 { 248 if (error != 0) { 249 printf("getaddr: error %d\n", error); 250 return; 251 } 252 *(bus_addr_t *)arg = segs[0].ds_addr; 253 } 254 255 static void 256 sdhci_dumpregs(struct sdhci_slot *slot) 257 { 258 slot_printf(slot, 259 "============== REGISTER DUMP ==============\n"); 260 261 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 262 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 263 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 264 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 265 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 266 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 267 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 268 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 269 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 270 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 271 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 272 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 273 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 274 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 275 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 276 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 277 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 278 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 279 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 280 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 281 282 slot_printf(slot, 283 "===========================================\n"); 284 } 285 286 static void 287 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 288 { 289 int timeout; 290 uint8_t res; 291 292 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 293 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 294 SDHCI_CARD_PRESENT)) 295 return; 296 } 297 298 /* Some controllers need this kick or reset won't work. */ 299 if ((mask & SDHCI_RESET_ALL) == 0 && 300 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 301 uint32_t clock; 302 303 /* This is to force an update */ 304 clock = slot->clock; 305 slot->clock = 0; 306 sdhci_set_clock(slot, clock); 307 } 308 309 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 310 311 if (mask & SDHCI_RESET_ALL) { 312 slot->clock = 0; 313 slot->power = 0; 314 } 315 316 /* Wait max 100 ms */ 317 timeout = 100; 318 /* Controller clears the bits when it's done */ 319 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 320 if (timeout == 0) { 321 slot_printf(slot, 322 "Reset 0x%x never completed - 0x%x.\n", 323 (int)mask, (int)res); 324 sdhci_dumpregs(slot); 325 return; 326 } 327 timeout--; 328 DELAY(1000); 329 } 330 } 331 332 static void 333 sdhci_init(struct sdhci_slot *slot) 334 { 335 336 sdhci_reset(slot, SDHCI_RESET_ALL); 337 338 /* Enable interrupts. */ 339 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 340 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 341 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 342 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 343 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 344 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 345 SDHCI_INT_ACMD12ERR; 346 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 347 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 348 } 349 350 static void 351 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 352 { 353 uint32_t res; 354 uint16_t clk; 355 int timeout; 356 357 if (clock == slot->clock) 358 return; 359 slot->clock = clock; 360 361 /* Turn off the clock. */ 362 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 363 /* If no clock requested - left it so. */ 364 if (clock == 0) 365 return; 366 /* Looking for highest freq <= clock. */ 367 res = slot->max_clk; 368 for (clk = 1; clk < 256; clk <<= 1) { 369 if (res <= clock) 370 break; 371 res >>= 1; 372 } 373 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 374 clk >>= 1; 375 /* Now we have got divider, set it. */ 376 clk <<= SDHCI_DIVIDER_SHIFT; 377 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 378 /* Enable clock. */ 379 clk |= SDHCI_CLOCK_INT_EN; 380 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 381 /* Wait up to 10 ms until it stabilize. */ 382 timeout = 10; 383 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 384 & SDHCI_CLOCK_INT_STABLE)) { 385 if (timeout == 0) { 386 slot_printf(slot, 387 "Internal clock never stabilised.\n"); 388 sdhci_dumpregs(slot); 389 return; 390 } 391 timeout--; 392 DELAY(1000); 393 } 394 /* Pass clock signal to the bus. */ 395 clk |= SDHCI_CLOCK_CARD_EN; 396 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 397 } 398 399 static void 400 sdhci_set_power(struct sdhci_slot *slot, u_char power) 401 { 402 uint8_t pwr; 403 404 if (slot->power == power) 405 return; 406 slot->power = power; 407 408 /* Turn off the power. */ 409 pwr = 0; 410 WR1(slot, SDHCI_POWER_CONTROL, pwr); 411 /* If power down requested - left it so. */ 412 if (power == 0) 413 return; 414 /* Set voltage. */ 415 switch (1 << power) { 416 case MMC_OCR_LOW_VOLTAGE: 417 pwr |= SDHCI_POWER_180; 418 break; 419 case MMC_OCR_290_300: 420 case MMC_OCR_300_310: 421 pwr |= SDHCI_POWER_300; 422 break; 423 case MMC_OCR_320_330: 424 case MMC_OCR_330_340: 425 pwr |= SDHCI_POWER_330; 426 break; 427 } 428 WR1(slot, SDHCI_POWER_CONTROL, pwr); 429 /* Turn on the power. */ 430 pwr |= SDHCI_POWER_ON; 431 WR1(slot, SDHCI_POWER_CONTROL, pwr); 432 } 433 434 static void 435 sdhci_read_block_pio(struct sdhci_slot *slot) 436 { 437 uint32_t data; 438 char *buffer; 439 size_t left; 440 441 buffer = slot->curcmd->data->data; 442 buffer += slot->offset; 443 /* Transfer one block at a time. */ 444 left = min(512, slot->curcmd->data->len - slot->offset); 445 slot->offset += left; 446 447 /* If we are too fast, broken controllers return zeroes. */ 448 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 449 DELAY(10); 450 /* Handle unalligned and alligned buffer cases. */ 451 if ((intptr_t)buffer & 3) { 452 while (left > 3) { 453 data = RD4(slot, SDHCI_BUFFER); 454 buffer[0] = data; 455 buffer[1] = (data >> 8); 456 buffer[2] = (data >> 16); 457 buffer[3] = (data >> 24); 458 buffer += 4; 459 left -= 4; 460 } 461 } else { 462 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 463 (uint32_t *)buffer, left >> 2); 464 left &= 3; 465 } 466 /* Handle uneven size case. */ 467 if (left > 0) { 468 data = RD4(slot, SDHCI_BUFFER); 469 while (left > 0) { 470 *(buffer++) = data; 471 data >>= 8; 472 left--; 473 } 474 } 475 } 476 477 static void 478 sdhci_write_block_pio(struct sdhci_slot *slot) 479 { 480 uint32_t data = 0; 481 char *buffer; 482 size_t left; 483 484 buffer = slot->curcmd->data->data; 485 buffer += slot->offset; 486 /* Transfer one block at a time. */ 487 left = min(512, slot->curcmd->data->len - slot->offset); 488 slot->offset += left; 489 490 /* Handle unalligned and alligned buffer cases. */ 491 if ((intptr_t)buffer & 3) { 492 while (left > 3) { 493 data = buffer[0] + 494 (buffer[1] << 8) + 495 (buffer[2] << 16) + 496 (buffer[3] << 24); 497 left -= 4; 498 buffer += 4; 499 WR4(slot, SDHCI_BUFFER, data); 500 } 501 } else { 502 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 503 (uint32_t *)buffer, left >> 2); 504 left &= 3; 505 } 506 /* Handle uneven size case. */ 507 if (left > 0) { 508 while (left > 0) { 509 data <<= 8; 510 data += *(buffer++); 511 left--; 512 } 513 WR4(slot, SDHCI_BUFFER, data); 514 } 515 } 516 517 static void 518 sdhci_transfer_pio(struct sdhci_slot *slot) 519 { 520 521 /* Read as many blocks as possible. */ 522 if (slot->curcmd->data->flags & MMC_DATA_READ) { 523 while (RD4(slot, SDHCI_PRESENT_STATE) & 524 SDHCI_DATA_AVAILABLE) { 525 sdhci_read_block_pio(slot); 526 if (slot->offset >= slot->curcmd->data->len) 527 break; 528 } 529 } else { 530 while (RD4(slot, SDHCI_PRESENT_STATE) & 531 SDHCI_SPACE_AVAILABLE) { 532 sdhci_write_block_pio(slot); 533 if (slot->offset >= slot->curcmd->data->len) 534 break; 535 } 536 } 537 } 538 539 static void 540 sdhci_card_delay(void *arg) 541 { 542 struct sdhci_slot *slot = arg; 543 544 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 545 } 546 547 static void 548 sdhci_card_task(void *arg, int pending) 549 { 550 struct sdhci_slot *slot = arg; 551 552 SDHCI_LOCK(slot); 553 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 554 if (slot->dev == NULL) { 555 /* If card is present - attach mmc bus. */ 556 slot->dev = device_add_child(slot->sc->dev, "mmc", -1); 557 device_set_ivars(slot->dev, slot); 558 SDHCI_UNLOCK(slot); 559 device_probe_and_attach(slot->dev); 560 } else 561 SDHCI_UNLOCK(slot); 562 } else { 563 if (slot->dev != NULL) { 564 /* If no card present - detach mmc bus. */ 565 device_t d = slot->dev; 566 slot->dev = NULL; 567 SDHCI_UNLOCK(slot); 568 device_delete_child(slot->sc->dev, d); 569 } else 570 SDHCI_UNLOCK(slot); 571 } 572 } 573 574 static int 575 sdhci_probe(device_t dev) 576 { 577 uint32_t model; 578 uint16_t subvendor; 579 uint8_t class, subclass; 580 int i, result; 581 582 model = (uint32_t)pci_get_device(dev) << 16; 583 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 584 subvendor = pci_get_subvendor(dev); 585 class = pci_get_class(dev); 586 subclass = pci_get_subclass(dev); 587 588 result = ENXIO; 589 for (i = 0; sdhci_devices[i].model != 0; i++) { 590 if (sdhci_devices[i].model == model && 591 (sdhci_devices[i].subvendor == 0xffff || 592 sdhci_devices[i].subvendor == subvendor)) { 593 device_set_desc(dev, sdhci_devices[i].desc); 594 result = BUS_PROBE_DEFAULT; 595 break; 596 } 597 } 598 if (result == ENXIO && class == PCIC_BASEPERIPH && 599 subclass == PCIS_BASEPERIPH_SDHC) { 600 device_set_desc(dev, "Generic SD HCI"); 601 result = BUS_PROBE_GENERIC; 602 } 603 604 return (result); 605 } 606 607 static int 608 sdhci_attach(device_t dev) 609 { 610 struct sdhci_softc *sc = device_get_softc(dev); 611 uint32_t model; 612 uint16_t subvendor; 613 uint8_t class, subclass, progif; 614 int err, slots, bar, i; 615 616 sc->dev = dev; 617 model = (uint32_t)pci_get_device(dev) << 16; 618 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 619 subvendor = pci_get_subvendor(dev); 620 class = pci_get_class(dev); 621 subclass = pci_get_subclass(dev); 622 progif = pci_get_progif(dev); 623 /* Apply chip specific quirks. */ 624 for (i = 0; sdhci_devices[i].model != 0; i++) { 625 if (sdhci_devices[i].model == model && 626 (sdhci_devices[i].subvendor == 0xffff || 627 sdhci_devices[i].subvendor == subvendor)) { 628 sc->quirks = sdhci_devices[i].quirks; 629 break; 630 } 631 } 632 /* Read slots info from PCI registers. */ 633 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 634 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 635 slots = PCI_SLOT_INFO_SLOTS(slots); 636 if (slots > 6 || bar > 5) { 637 device_printf(dev, "Incorrect slots information (%d, %d).\n", 638 slots, bar); 639 return (EINVAL); 640 } 641 /* Allocate IRQ. */ 642 sc->irq_rid = 0; 643 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 644 RF_SHAREABLE | RF_ACTIVE); 645 if (sc->irq_res == NULL) { 646 device_printf(dev, "Can't allocate IRQ\n"); 647 return (ENOMEM); 648 } 649 /* Scan all slots. */ 650 for (i = 0; i < slots; i++) { 651 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 652 uint32_t caps; 653 654 SDHCI_LOCK_INIT(slot); 655 slot->sc = sc; 656 slot->num = sc->num_slots; 657 /* Allocate memory. */ 658 slot->mem_rid = PCIR_BAR(bar + i); 659 slot->mem_res = bus_alloc_resource(dev, 660 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 661 if (slot->mem_res == NULL) { 662 device_printf(dev, "Can't allocate memory\n"); 663 SDHCI_LOCK_DESTROY(slot); 664 continue; 665 } 666 /* Allocate DMA tag. */ 667 err = bus_dma_tag_create(bus_get_dma_tag(dev), 668 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 669 BUS_SPACE_MAXADDR, NULL, NULL, 670 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 671 BUS_DMA_ALLOCNOW, NULL, NULL, 672 &slot->dmatag); 673 if (err != 0) { 674 device_printf(dev, "Can't create DMA tag\n"); 675 SDHCI_LOCK_DESTROY(slot); 676 continue; 677 } 678 /* Allocate DMA memory. */ 679 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 680 BUS_DMA_NOWAIT, &slot->dmamap); 681 if (err != 0) { 682 device_printf(dev, "Can't alloc DMA memory\n"); 683 SDHCI_LOCK_DESTROY(slot); 684 continue; 685 } 686 /* Map the memory. */ 687 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 688 (void *)slot->dmamem, DMA_BLOCK_SIZE, 689 sdhci_getaddr, &slot->paddr, 0); 690 if (err != 0 || slot->paddr == 0) { 691 device_printf(dev, "Can't load DMA memory\n"); 692 SDHCI_LOCK_DESTROY(slot); 693 continue; 694 } 695 /* Initialize slot. */ 696 sdhci_init(slot); 697 caps = RD4(slot, SDHCI_CAPABILITIES); 698 /* Calculate base clock frequency. */ 699 slot->max_clk = 700 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 701 if (slot->max_clk == 0) { 702 device_printf(dev, "Hardware doesn't specify base clock " 703 "frequency.\n"); 704 } 705 slot->max_clk *= 1000000; 706 /* Calculate timeout clock frequency. */ 707 slot->timeout_clk = 708 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 709 if (slot->timeout_clk == 0) { 710 device_printf(dev, "Hardware doesn't specify timeout clock " 711 "frequency.\n"); 712 } 713 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 714 slot->timeout_clk *= 1000; 715 716 slot->host.f_min = slot->max_clk / 256; 717 slot->host.f_max = slot->max_clk; 718 slot->host.host_ocr = 0; 719 if (caps & SDHCI_CAN_VDD_330) 720 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 721 if (caps & SDHCI_CAN_VDD_300) 722 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 723 if (caps & SDHCI_CAN_VDD_180) 724 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 725 if (slot->host.host_ocr == 0) { 726 device_printf(dev, "Hardware doesn't report any " 727 "support voltages.\n"); 728 } 729 slot->host.caps = MMC_CAP_4_BIT_DATA; 730 if (caps & SDHCI_CAN_DO_HISPD) 731 slot->host.caps |= MMC_CAP_HSPEED; 732 /* Decide if we have usable DMA. */ 733 if (caps & SDHCI_CAN_DO_DMA) 734 slot->opt |= SDHCI_HAVE_DMA; 735 if (class == PCIC_BASEPERIPH && 736 subclass == PCIS_BASEPERIPH_SDHC && 737 progif != PCI_SDHCI_IFDMA) 738 slot->opt &= ~SDHCI_HAVE_DMA; 739 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) 740 slot->opt &= ~SDHCI_HAVE_DMA; 741 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) 742 slot->opt |= SDHCI_HAVE_DMA; 743 744 if (bootverbose || sdhci_debug) { 745 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 746 slot->max_clk / 1000000, 747 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 748 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 749 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 750 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 751 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 752 sdhci_dumpregs(slot); 753 } 754 755 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 756 callout_init(&slot->card_callout, 1); 757 sc->num_slots++; 758 } 759 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 760 /* Activate the interrupt */ 761 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 762 NULL, sdhci_intr, sc, &sc->intrhand); 763 if (err) 764 device_printf(dev, "Can't setup IRQ\n"); 765 pci_enable_busmaster(dev); 766 /* Process cards detection. */ 767 for (i = 0; i < sc->num_slots; i++) { 768 struct sdhci_slot *slot = &sc->slots[i]; 769 770 sdhci_card_task(slot, 0); 771 } 772 773 return (0); 774 } 775 776 static int 777 sdhci_detach(device_t dev) 778 { 779 struct sdhci_softc *sc = device_get_softc(dev); 780 int i; 781 782 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 783 bus_release_resource(dev, SYS_RES_IRQ, 784 sc->irq_rid, sc->irq_res); 785 786 for (i = 0; i < sc->num_slots; i++) { 787 struct sdhci_slot *slot = &sc->slots[i]; 788 device_t d; 789 790 callout_drain(&slot->card_callout); 791 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 792 793 SDHCI_LOCK(slot); 794 d = slot->dev; 795 slot->dev = NULL; 796 SDHCI_UNLOCK(slot); 797 if (d != NULL) 798 device_delete_child(dev, d); 799 800 SDHCI_LOCK(slot); 801 sdhci_reset(slot, SDHCI_RESET_ALL); 802 SDHCI_UNLOCK(slot); 803 bus_dmamap_unload(slot->dmatag, slot->dmamap); 804 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 805 bus_dma_tag_destroy(slot->dmatag); 806 bus_release_resource(dev, SYS_RES_MEMORY, 807 slot->mem_rid, slot->mem_res); 808 SDHCI_LOCK_DESTROY(slot); 809 } 810 return (0); 811 } 812 813 static int 814 sdhci_suspend(device_t dev) 815 { 816 struct sdhci_softc *sc = device_get_softc(dev); 817 int i, err; 818 819 err = bus_generic_suspend(dev); 820 if (err) 821 return (err); 822 for (i = 0; i < sc->num_slots; i++) 823 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); 824 return (0); 825 } 826 827 static int 828 sdhci_resume(device_t dev) 829 { 830 struct sdhci_softc *sc = device_get_softc(dev); 831 int i; 832 833 for (i = 0; i < sc->num_slots; i++) 834 sdhci_init(&sc->slots[i]); 835 return (bus_generic_resume(dev)); 836 } 837 838 static int 839 sdhci_update_ios(device_t brdev, device_t reqdev) 840 { 841 struct sdhci_slot *slot = device_get_ivars(reqdev); 842 struct mmc_ios *ios = &slot->host.ios; 843 844 SDHCI_LOCK(slot); 845 /* Do full reset on bus power down to clear from any state. */ 846 if (ios->power_mode == power_off) { 847 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 848 sdhci_init(slot); 849 } 850 /* Configure the bus. */ 851 sdhci_set_clock(slot, ios->clock); 852 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 853 if (ios->bus_width == bus_width_4) 854 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 855 else 856 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 857 if (ios->timing == bus_timing_hs) 858 slot->hostctrl |= SDHCI_CTRL_HISPD; 859 else 860 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 861 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 862 /* Some controllers like reset after bus changes. */ 863 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) 864 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 865 866 SDHCI_UNLOCK(slot); 867 return (0); 868 } 869 870 static void 871 sdhci_set_transfer_mode(struct sdhci_slot *slot, 872 struct mmc_data *data) 873 { 874 uint16_t mode; 875 876 if (data == NULL) 877 return; 878 879 mode = SDHCI_TRNS_BLK_CNT_EN; 880 if (data->len > 512) 881 mode |= SDHCI_TRNS_MULTI; 882 if (data->flags & MMC_DATA_READ) 883 mode |= SDHCI_TRNS_READ; 884 if (slot->req->stop) 885 mode |= SDHCI_TRNS_ACMD12; 886 if (slot->flags & SDHCI_USE_DMA) 887 mode |= SDHCI_TRNS_DMA; 888 889 WR2(slot, SDHCI_TRANSFER_MODE, mode); 890 } 891 892 static void 893 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 894 { 895 struct mmc_request *req = slot->req; 896 int flags, timeout; 897 uint32_t mask, state; 898 899 slot->curcmd = cmd; 900 slot->cmd_done = 0; 901 902 cmd->error = MMC_ERR_NONE; 903 904 /* This flags combination is not supported by controller. */ 905 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 906 slot_printf(slot, "Unsupported response type!\n"); 907 cmd->error = MMC_ERR_FAILED; 908 slot->req = NULL; 909 slot->curcmd = NULL; 910 req->done(req); 911 return; 912 } 913 914 /* Read controller present state. */ 915 state = RD4(slot, SDHCI_PRESENT_STATE); 916 /* Do not issue command if there is no card, clock or power. 917 * Controller will not detect timeout without clock active. */ 918 if ((state & SDHCI_CARD_PRESENT) == 0 || 919 slot->power == 0 || 920 slot->clock == 0) { 921 cmd->error = MMC_ERR_FAILED; 922 slot->req = NULL; 923 slot->curcmd = NULL; 924 req->done(req); 925 return; 926 } 927 /* Always wait for free CMD bus. */ 928 mask = SDHCI_CMD_INHIBIT; 929 /* Wait for free DAT if we have data or busy signal. */ 930 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 931 mask |= SDHCI_DAT_INHIBIT; 932 /* We shouldn't wait for DAT for stop commands. */ 933 if (cmd == slot->req->stop) 934 mask &= ~SDHCI_DAT_INHIBIT; 935 /* Wait for bus no more then 10 ms. */ 936 timeout = 10; 937 while (state & mask) { 938 if (timeout == 0) { 939 slot_printf(slot, "Controller never released " 940 "inhibit bit(s).\n"); 941 sdhci_dumpregs(slot); 942 cmd->error = MMC_ERR_FAILED; 943 slot->req = NULL; 944 slot->curcmd = NULL; 945 req->done(req); 946 return; 947 } 948 timeout--; 949 DELAY(1000); 950 state = RD4(slot, SDHCI_PRESENT_STATE); 951 } 952 953 /* Prepare command flags. */ 954 if (!(cmd->flags & MMC_RSP_PRESENT)) 955 flags = SDHCI_CMD_RESP_NONE; 956 else if (cmd->flags & MMC_RSP_136) 957 flags = SDHCI_CMD_RESP_LONG; 958 else if (cmd->flags & MMC_RSP_BUSY) 959 flags = SDHCI_CMD_RESP_SHORT_BUSY; 960 else 961 flags = SDHCI_CMD_RESP_SHORT; 962 if (cmd->flags & MMC_RSP_CRC) 963 flags |= SDHCI_CMD_CRC; 964 if (cmd->flags & MMC_RSP_OPCODE) 965 flags |= SDHCI_CMD_INDEX; 966 if (cmd->data) 967 flags |= SDHCI_CMD_DATA; 968 if (cmd->opcode == MMC_STOP_TRANSMISSION) 969 flags |= SDHCI_CMD_TYPE_ABORT; 970 /* Prepare data. */ 971 sdhci_start_data(slot, cmd->data); 972 /* 973 * Interrupt aggregation: To reduce total number of interrupts 974 * group response interrupt with data interrupt when possible. 975 * If there going to be data interrupt, mask response one. 976 */ 977 if (slot->data_done == 0) { 978 WR4(slot, SDHCI_SIGNAL_ENABLE, 979 slot->intmask &= ~SDHCI_INT_RESPONSE); 980 } 981 /* Set command argument. */ 982 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 983 /* Set data transfer mode. */ 984 sdhci_set_transfer_mode(slot, cmd->data); 985 /* Set command flags. */ 986 WR1(slot, SDHCI_COMMAND_FLAGS, flags); 987 /* Start command. */ 988 WR1(slot, SDHCI_COMMAND, cmd->opcode); 989 } 990 991 static void 992 sdhci_finish_command(struct sdhci_slot *slot) 993 { 994 int i; 995 996 slot->cmd_done = 1; 997 /* Interrupt aggregation: Restore command interrupt. 998 * Main restore point for the case when command interrupt 999 * happened first. */ 1000 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1001 /* In case of error - reset host and return. */ 1002 if (slot->curcmd->error) { 1003 sdhci_reset(slot, SDHCI_RESET_CMD); 1004 sdhci_reset(slot, SDHCI_RESET_DATA); 1005 sdhci_start(slot); 1006 return; 1007 } 1008 /* If command has response - fetch it. */ 1009 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1010 if (slot->curcmd->flags & MMC_RSP_136) { 1011 /* CRC is stripped so we need one byte shift. */ 1012 uint8_t extra = 0; 1013 for (i = 0; i < 4; i++) { 1014 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1015 slot->curcmd->resp[3 - i] = (val << 8) + extra; 1016 extra = val >> 24; 1017 } 1018 } else 1019 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1020 } 1021 /* If data ready - finish. */ 1022 if (slot->data_done) 1023 sdhci_start(slot); 1024 } 1025 1026 static void 1027 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1028 { 1029 uint32_t target_timeout, current_timeout; 1030 uint8_t div; 1031 1032 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1033 slot->data_done = 1; 1034 return; 1035 } 1036 1037 slot->data_done = 0; 1038 1039 /* Calculate and set data timeout.*/ 1040 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1041 target_timeout = 1000000; 1042 div = 0; 1043 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1044 while (current_timeout < target_timeout) { 1045 div++; 1046 current_timeout <<= 1; 1047 if (div >= 0xF) 1048 break; 1049 } 1050 /* Compensate for an off-by-one error in the CaFe chip.*/ 1051 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 1052 div++; 1053 if (div >= 0xF) { 1054 slot_printf(slot, "Timeout too large!\n"); 1055 div = 0xE; 1056 } 1057 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1058 1059 if (data == NULL) 1060 return; 1061 1062 /* Use DMA if possible. */ 1063 if ((slot->opt & SDHCI_HAVE_DMA)) 1064 slot->flags |= SDHCI_USE_DMA; 1065 /* If data is small, broken DMA may return zeroes instead of data, */ 1066 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1067 (data->len <= 512)) 1068 slot->flags &= ~SDHCI_USE_DMA; 1069 /* Some controllers require even block sizes. */ 1070 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1071 ((data->len) & 0x3)) 1072 slot->flags &= ~SDHCI_USE_DMA; 1073 /* Load DMA buffer. */ 1074 if (slot->flags & SDHCI_USE_DMA) { 1075 if (data->flags & MMC_DATA_READ) 1076 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 1077 else { 1078 memcpy(slot->dmamem, data->data, 1079 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 1080 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 1081 } 1082 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1083 /* Interrupt aggregation: Mask border interrupt 1084 * for the last page and unmask else. */ 1085 if (data->len == DMA_BLOCK_SIZE) 1086 slot->intmask &= ~SDHCI_INT_DMA_END; 1087 else 1088 slot->intmask |= SDHCI_INT_DMA_END; 1089 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1090 } 1091 /* Current data offset for both PIO and DMA. */ 1092 slot->offset = 0; 1093 /* Set block size and request IRQ on 4K border. */ 1094 WR2(slot, SDHCI_BLOCK_SIZE, 1095 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1096 /* Set block count. */ 1097 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1098 } 1099 1100 static void 1101 sdhci_finish_data(struct sdhci_slot *slot) 1102 { 1103 struct mmc_data *data = slot->curcmd->data; 1104 1105 slot->data_done = 1; 1106 /* Interrupt aggregation: Restore command interrupt. 1107 * Auxillary restore point for the case when data interrupt 1108 * happened first. */ 1109 if (!slot->cmd_done) { 1110 WR4(slot, SDHCI_SIGNAL_ENABLE, 1111 slot->intmask |= SDHCI_INT_RESPONSE); 1112 } 1113 /* Unload rest of data from DMA buffer. */ 1114 if (slot->flags & SDHCI_USE_DMA) { 1115 if (data->flags & MMC_DATA_READ) { 1116 size_t left = data->len - slot->offset; 1117 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1118 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1119 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1120 } else 1121 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1122 } 1123 /* If there was error - reset the host. */ 1124 if (slot->curcmd->error) { 1125 sdhci_reset(slot, SDHCI_RESET_CMD); 1126 sdhci_reset(slot, SDHCI_RESET_DATA); 1127 sdhci_start(slot); 1128 return; 1129 } 1130 /* If we already have command response - finish. */ 1131 if (slot->cmd_done) 1132 sdhci_start(slot); 1133 } 1134 1135 static void 1136 sdhci_start(struct sdhci_slot *slot) 1137 { 1138 struct mmc_request *req; 1139 1140 req = slot->req; 1141 if (req == NULL) 1142 return; 1143 1144 if (!(slot->flags & CMD_STARTED)) { 1145 slot->flags |= CMD_STARTED; 1146 sdhci_start_command(slot, req->cmd); 1147 return; 1148 } 1149 /* We don't need this until using Auto-CMD12 feature 1150 if (!(slot->flags & STOP_STARTED) && req->stop) { 1151 slot->flags |= STOP_STARTED; 1152 sdhci_start_command(slot, req->stop); 1153 return; 1154 } 1155 */ 1156 if (sdhci_debug > 1) 1157 slot_printf(slot, "result: %d\n", req->cmd->error); 1158 if (!req->cmd->error && 1159 (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1160 sdhci_reset(slot, SDHCI_RESET_CMD); 1161 sdhci_reset(slot, SDHCI_RESET_DATA); 1162 } 1163 1164 /* We must be done -- bad idea to do this while locked? */ 1165 slot->req = NULL; 1166 slot->curcmd = NULL; 1167 req->done(req); 1168 } 1169 1170 static int 1171 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1172 { 1173 struct sdhci_slot *slot = device_get_ivars(reqdev); 1174 1175 SDHCI_LOCK(slot); 1176 if (slot->req != NULL) { 1177 SDHCI_UNLOCK(slot); 1178 return (EBUSY); 1179 } 1180 if (sdhci_debug > 1) { 1181 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1182 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1183 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1184 (req->cmd->data)?req->cmd->data->flags:0); 1185 } 1186 slot->req = req; 1187 slot->flags = 0; 1188 sdhci_start(slot); 1189 SDHCI_UNLOCK(slot); 1190 if (dumping) { 1191 while (slot->req != NULL) { 1192 sdhci_intr(slot->sc); 1193 DELAY(10); 1194 } 1195 } 1196 return (0); 1197 } 1198 1199 static int 1200 sdhci_get_ro(device_t brdev, device_t reqdev) 1201 { 1202 struct sdhci_slot *slot = device_get_ivars(reqdev); 1203 uint32_t val; 1204 1205 SDHCI_LOCK(slot); 1206 val = RD4(slot, SDHCI_PRESENT_STATE); 1207 SDHCI_UNLOCK(slot); 1208 return (!(val & SDHCI_WRITE_PROTECT)); 1209 } 1210 1211 static int 1212 sdhci_acquire_host(device_t brdev, device_t reqdev) 1213 { 1214 struct sdhci_slot *slot = device_get_ivars(reqdev); 1215 int err = 0; 1216 1217 SDHCI_LOCK(slot); 1218 while (slot->bus_busy) 1219 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1220 slot->bus_busy++; 1221 /* Activate led. */ 1222 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1223 SDHCI_UNLOCK(slot); 1224 return (err); 1225 } 1226 1227 static int 1228 sdhci_release_host(device_t brdev, device_t reqdev) 1229 { 1230 struct sdhci_slot *slot = device_get_ivars(reqdev); 1231 1232 SDHCI_LOCK(slot); 1233 /* Deactivate led. */ 1234 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1235 slot->bus_busy--; 1236 SDHCI_UNLOCK(slot); 1237 wakeup(slot); 1238 return (0); 1239 } 1240 1241 static void 1242 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1243 { 1244 1245 if (!slot->curcmd) { 1246 slot_printf(slot, "Got command interrupt 0x%08x, but " 1247 "there is no active command.\n", intmask); 1248 sdhci_dumpregs(slot); 1249 return; 1250 } 1251 if (intmask & SDHCI_INT_TIMEOUT) 1252 slot->curcmd->error = MMC_ERR_TIMEOUT; 1253 else if (intmask & SDHCI_INT_CRC) 1254 slot->curcmd->error = MMC_ERR_BADCRC; 1255 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1256 slot->curcmd->error = MMC_ERR_FIFO; 1257 1258 sdhci_finish_command(slot); 1259 } 1260 1261 static void 1262 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1263 { 1264 1265 if (!slot->curcmd) { 1266 slot_printf(slot, "Got data interrupt 0x%08x, but " 1267 "there is no active command.\n", intmask); 1268 sdhci_dumpregs(slot); 1269 return; 1270 } 1271 if (slot->curcmd->data == NULL && 1272 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1273 slot_printf(slot, "Got data interrupt 0x%08x, but " 1274 "there is no active data operation.\n", 1275 intmask); 1276 sdhci_dumpregs(slot); 1277 return; 1278 } 1279 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1280 slot->curcmd->error = MMC_ERR_TIMEOUT; 1281 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1282 slot->curcmd->error = MMC_ERR_BADCRC; 1283 if (slot->curcmd->data == NULL && 1284 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1285 SDHCI_INT_DMA_END))) { 1286 slot_printf(slot, "Got data interrupt 0x%08x, but " 1287 "there is busy-only command.\n", intmask); 1288 sdhci_dumpregs(slot); 1289 slot->curcmd->error = MMC_ERR_INVALID; 1290 } 1291 if (slot->curcmd->error) { 1292 /* No need to continue after any error. */ 1293 sdhci_finish_data(slot); 1294 return; 1295 } 1296 1297 /* Handle PIO interrupt. */ 1298 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1299 sdhci_transfer_pio(slot); 1300 /* Handle DMA border. */ 1301 if (intmask & SDHCI_INT_DMA_END) { 1302 struct mmc_data *data = slot->curcmd->data; 1303 size_t left; 1304 1305 /* Unload DMA buffer... */ 1306 left = data->len - slot->offset; 1307 if (data->flags & MMC_DATA_READ) { 1308 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1309 BUS_DMASYNC_POSTREAD); 1310 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1311 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1312 } else { 1313 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1314 BUS_DMASYNC_POSTWRITE); 1315 } 1316 /* ... and reload it again. */ 1317 slot->offset += DMA_BLOCK_SIZE; 1318 left = data->len - slot->offset; 1319 if (data->flags & MMC_DATA_READ) { 1320 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1321 BUS_DMASYNC_PREREAD); 1322 } else { 1323 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1324 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1325 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1326 BUS_DMASYNC_PREWRITE); 1327 } 1328 /* Interrupt aggregation: Mask border interrupt 1329 * for the last page. */ 1330 if (left == DMA_BLOCK_SIZE) { 1331 slot->intmask &= ~SDHCI_INT_DMA_END; 1332 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1333 } 1334 /* Restart DMA. */ 1335 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1336 } 1337 /* We have got all data. */ 1338 if (intmask & SDHCI_INT_DATA_END) 1339 sdhci_finish_data(slot); 1340 } 1341 1342 static void 1343 sdhci_acmd_irq(struct sdhci_slot *slot) 1344 { 1345 uint16_t err; 1346 1347 err = RD4(slot, SDHCI_ACMD12_ERR); 1348 if (!slot->curcmd) { 1349 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1350 "there is no active command.\n", err); 1351 sdhci_dumpregs(slot); 1352 return; 1353 } 1354 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1355 sdhci_reset(slot, SDHCI_RESET_CMD); 1356 } 1357 1358 static void 1359 sdhci_intr(void *arg) 1360 { 1361 struct sdhci_softc *sc = (struct sdhci_softc *)arg; 1362 int i; 1363 1364 for (i = 0; i < sc->num_slots; i++) { 1365 struct sdhci_slot *slot = &sc->slots[i]; 1366 uint32_t intmask; 1367 1368 SDHCI_LOCK(slot); 1369 /* Read slot interrupt status. */ 1370 intmask = RD4(slot, SDHCI_INT_STATUS); 1371 if (intmask == 0 || intmask == 0xffffffff) { 1372 SDHCI_UNLOCK(slot); 1373 continue; 1374 } 1375 if (sdhci_debug > 2) 1376 slot_printf(slot, "Interrupt %#x\n", intmask); 1377 1378 /* Handle card presence interrupts. */ 1379 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1380 WR4(slot, SDHCI_INT_STATUS, intmask & 1381 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1382 1383 if (intmask & SDHCI_INT_CARD_REMOVE) { 1384 if (bootverbose || sdhci_debug) 1385 slot_printf(slot, "Card removed\n"); 1386 callout_stop(&slot->card_callout); 1387 taskqueue_enqueue(taskqueue_swi_giant, 1388 &slot->card_task); 1389 } 1390 if (intmask & SDHCI_INT_CARD_INSERT) { 1391 if (bootverbose || sdhci_debug) 1392 slot_printf(slot, "Card inserted\n"); 1393 callout_reset(&slot->card_callout, hz / 2, 1394 sdhci_card_delay, slot); 1395 } 1396 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1397 } 1398 /* Handle command interrupts. */ 1399 if (intmask & SDHCI_INT_CMD_MASK) { 1400 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1401 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1402 } 1403 /* Handle data interrupts. */ 1404 if (intmask & SDHCI_INT_DATA_MASK) { 1405 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1406 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1407 } 1408 /* Handle AutoCMD12 error interrupt. */ 1409 if (intmask & SDHCI_INT_ACMD12ERR) { 1410 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1411 sdhci_acmd_irq(slot); 1412 } 1413 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1414 intmask &= ~SDHCI_INT_ACMD12ERR; 1415 intmask &= ~SDHCI_INT_ERROR; 1416 /* Handle bus power interrupt. */ 1417 if (intmask & SDHCI_INT_BUS_POWER) { 1418 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1419 slot_printf(slot, 1420 "Card is consuming too much power!\n"); 1421 intmask &= ~SDHCI_INT_BUS_POWER; 1422 } 1423 /* The rest is unknown. */ 1424 if (intmask) { 1425 WR4(slot, SDHCI_INT_STATUS, intmask); 1426 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1427 intmask); 1428 sdhci_dumpregs(slot); 1429 } 1430 1431 SDHCI_UNLOCK(slot); 1432 } 1433 } 1434 1435 static int 1436 sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1437 { 1438 struct sdhci_slot *slot = device_get_ivars(child); 1439 1440 switch (which) { 1441 default: 1442 return (EINVAL); 1443 case MMCBR_IVAR_BUS_MODE: 1444 *result = slot->host.ios.bus_mode; 1445 break; 1446 case MMCBR_IVAR_BUS_WIDTH: 1447 *result = slot->host.ios.bus_width; 1448 break; 1449 case MMCBR_IVAR_CHIP_SELECT: 1450 *result = slot->host.ios.chip_select; 1451 break; 1452 case MMCBR_IVAR_CLOCK: 1453 *result = slot->host.ios.clock; 1454 break; 1455 case MMCBR_IVAR_F_MIN: 1456 *result = slot->host.f_min; 1457 break; 1458 case MMCBR_IVAR_F_MAX: 1459 *result = slot->host.f_max; 1460 break; 1461 case MMCBR_IVAR_HOST_OCR: 1462 *result = slot->host.host_ocr; 1463 break; 1464 case MMCBR_IVAR_MODE: 1465 *result = slot->host.mode; 1466 break; 1467 case MMCBR_IVAR_OCR: 1468 *result = slot->host.ocr; 1469 break; 1470 case MMCBR_IVAR_POWER_MODE: 1471 *result = slot->host.ios.power_mode; 1472 break; 1473 case MMCBR_IVAR_VDD: 1474 *result = slot->host.ios.vdd; 1475 break; 1476 case MMCBR_IVAR_CAPS: 1477 *result = slot->host.caps; 1478 break; 1479 case MMCBR_IVAR_TIMING: 1480 *result = slot->host.ios.timing; 1481 break; 1482 case MMCBR_IVAR_MAX_DATA: 1483 *result = 65535; 1484 break; 1485 } 1486 return (0); 1487 } 1488 1489 static int 1490 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1491 { 1492 struct sdhci_slot *slot = device_get_ivars(child); 1493 1494 switch (which) { 1495 default: 1496 return (EINVAL); 1497 case MMCBR_IVAR_BUS_MODE: 1498 slot->host.ios.bus_mode = value; 1499 break; 1500 case MMCBR_IVAR_BUS_WIDTH: 1501 slot->host.ios.bus_width = value; 1502 break; 1503 case MMCBR_IVAR_CHIP_SELECT: 1504 slot->host.ios.chip_select = value; 1505 break; 1506 case MMCBR_IVAR_CLOCK: 1507 if (value > 0) { 1508 uint32_t clock = slot->max_clk; 1509 int i; 1510 1511 for (i = 0; i < 8; i++) { 1512 if (clock <= value) 1513 break; 1514 clock >>= 1; 1515 } 1516 slot->host.ios.clock = clock; 1517 } else 1518 slot->host.ios.clock = 0; 1519 break; 1520 case MMCBR_IVAR_MODE: 1521 slot->host.mode = value; 1522 break; 1523 case MMCBR_IVAR_OCR: 1524 slot->host.ocr = value; 1525 break; 1526 case MMCBR_IVAR_POWER_MODE: 1527 slot->host.ios.power_mode = value; 1528 break; 1529 case MMCBR_IVAR_VDD: 1530 slot->host.ios.vdd = value; 1531 break; 1532 case MMCBR_IVAR_TIMING: 1533 slot->host.ios.timing = value; 1534 break; 1535 case MMCBR_IVAR_CAPS: 1536 case MMCBR_IVAR_HOST_OCR: 1537 case MMCBR_IVAR_F_MIN: 1538 case MMCBR_IVAR_F_MAX: 1539 case MMCBR_IVAR_MAX_DATA: 1540 return (EINVAL); 1541 } 1542 return (0); 1543 } 1544 1545 static device_method_t sdhci_methods[] = { 1546 /* device_if */ 1547 DEVMETHOD(device_probe, sdhci_probe), 1548 DEVMETHOD(device_attach, sdhci_attach), 1549 DEVMETHOD(device_detach, sdhci_detach), 1550 DEVMETHOD(device_suspend, sdhci_suspend), 1551 DEVMETHOD(device_resume, sdhci_resume), 1552 1553 /* Bus interface */ 1554 DEVMETHOD(bus_read_ivar, sdhci_read_ivar), 1555 DEVMETHOD(bus_write_ivar, sdhci_write_ivar), 1556 1557 /* mmcbr_if */ 1558 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), 1559 DEVMETHOD(mmcbr_request, sdhci_request), 1560 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), 1561 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), 1562 DEVMETHOD(mmcbr_release_host, sdhci_release_host), 1563 1564 {0, 0}, 1565 }; 1566 1567 static driver_t sdhci_driver = { 1568 "sdhci", 1569 sdhci_methods, 1570 sizeof(struct sdhci_softc), 1571 }; 1572 static devclass_t sdhci_devclass; 1573 1574 1575 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0);
Cache object: e6af7155663a0b355e73e5604ab2001d
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