Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sdhci/sdhci.h
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1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: releng/8.4/sys/dev/sdhci/sdhci.h 184138 2008-10-21 20:33:40Z mav $ 26 */ 27 28 /* 29 * PCI registers 30 */ 31 32 #define PCI_SDHCI_IFPIO 0x00 33 #define PCI_SDHCI_IFDMA 0x01 34 #define PCI_SDHCI_IFVENDOR 0x02 35 36 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 37 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 38 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 39 40 /* 41 * Controller registers 42 */ 43 44 #define SDHCI_DMA_ADDRESS 0x00 45 46 #define SDHCI_BLOCK_SIZE 0x04 47 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 48 49 #define SDHCI_BLOCK_COUNT 0x06 50 51 #define SDHCI_ARGUMENT 0x08 52 53 #define SDHCI_TRANSFER_MODE 0x0C 54 #define SDHCI_TRNS_DMA 0x01 55 #define SDHCI_TRNS_BLK_CNT_EN 0x02 56 #define SDHCI_TRNS_ACMD12 0x04 57 #define SDHCI_TRNS_READ 0x10 58 #define SDHCI_TRNS_MULTI 0x20 59 60 #define SDHCI_COMMAND_FLAGS 0x0E 61 #define SDHCI_CMD_RESP_NONE 0x00 62 #define SDHCI_CMD_RESP_LONG 0x01 63 #define SDHCI_CMD_RESP_SHORT 0x02 64 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 65 #define SDHCI_CMD_RESP_MASK 0x03 66 #define SDHCI_CMD_CRC 0x08 67 #define SDHCI_CMD_INDEX 0x10 68 #define SDHCI_CMD_DATA 0x20 69 #define SDHCI_CMD_TYPE_NORMAL 0x00 70 #define SDHCI_CMD_TYPE_SUSPEND 0x40 71 #define SDHCI_CMD_TYPE_RESUME 0x80 72 #define SDHCI_CMD_TYPE_ABORT 0xc0 73 #define SDHCI_CMD_TYPE_MASK 0xc0 74 75 #define SDHCI_COMMAND 0x0F 76 77 #define SDHCI_RESPONSE 0x10 78 79 #define SDHCI_BUFFER 0x20 80 81 #define SDHCI_PRESENT_STATE 0x24 82 #define SDHCI_CMD_INHIBIT 0x00000001 83 #define SDHCI_DAT_INHIBIT 0x00000002 84 #define SDHCI_DAT_ACTIVE 0x00000004 85 #define SDHCI_DOING_WRITE 0x00000100 86 #define SDHCI_DOING_READ 0x00000200 87 #define SDHCI_SPACE_AVAILABLE 0x00000400 88 #define SDHCI_DATA_AVAILABLE 0x00000800 89 #define SDHCI_CARD_PRESENT 0x00010000 90 #define SDHCI_CARD_STABLE 0x00020000 91 #define SDHCI_CARD_PIN 0x00040000 92 #define SDHCI_WRITE_PROTECT 0x00080000 93 #define SDHCI_STATE_DAT 0x00700000 94 #define SDHCI_STATE_CMD 0x00800000 95 96 #define SDHCI_HOST_CONTROL 0x28 97 #define SDHCI_CTRL_LED 0x01 98 #define SDHCI_CTRL_4BITBUS 0x02 99 #define SDHCI_CTRL_HISPD 0x04 100 #define SDHCI_CTRL_SDMA 0x08 101 #define SDHCI_CTRL_ADMA2 0x10 102 #define SDHCI_CTRL_ADMA264 0x18 103 #define SDHCI_CTRL_CARD_DET 0x40 104 #define SDHCI_CTRL_FORCE_CARD 0x80 105 106 #define SDHCI_POWER_CONTROL 0x29 107 #define SDHCI_POWER_ON 0x01 108 #define SDHCI_POWER_180 0x0A 109 #define SDHCI_POWER_300 0x0C 110 #define SDHCI_POWER_330 0x0E 111 112 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 113 114 #define SDHCI_WAKE_UP_CONTROL 0x2B 115 116 #define SDHCI_CLOCK_CONTROL 0x2C 117 #define SDHCI_DIVIDER_SHIFT 8 118 #define SDHCI_CLOCK_CARD_EN 0x0004 119 #define SDHCI_CLOCK_INT_STABLE 0x0002 120 #define SDHCI_CLOCK_INT_EN 0x0001 121 122 #define SDHCI_TIMEOUT_CONTROL 0x2E 123 124 #define SDHCI_SOFTWARE_RESET 0x2F 125 #define SDHCI_RESET_ALL 0x01 126 #define SDHCI_RESET_CMD 0x02 127 #define SDHCI_RESET_DATA 0x04 128 129 #define SDHCI_INT_STATUS 0x30 130 #define SDHCI_INT_ENABLE 0x34 131 #define SDHCI_SIGNAL_ENABLE 0x38 132 #define SDHCI_INT_RESPONSE 0x00000001 133 #define SDHCI_INT_DATA_END 0x00000002 134 #define SDHCI_INT_BLOCK_GAP 0x00000004 135 #define SDHCI_INT_DMA_END 0x00000008 136 #define SDHCI_INT_SPACE_AVAIL 0x00000010 137 #define SDHCI_INT_DATA_AVAIL 0x00000020 138 #define SDHCI_INT_CARD_INSERT 0x00000040 139 #define SDHCI_INT_CARD_REMOVE 0x00000080 140 #define SDHCI_INT_CARD_INT 0x00000100 141 #define SDHCI_INT_ERROR 0x00008000 142 #define SDHCI_INT_TIMEOUT 0x00010000 143 #define SDHCI_INT_CRC 0x00020000 144 #define SDHCI_INT_END_BIT 0x00040000 145 #define SDHCI_INT_INDEX 0x00080000 146 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 147 #define SDHCI_INT_DATA_CRC 0x00200000 148 #define SDHCI_INT_DATA_END_BIT 0x00400000 149 #define SDHCI_INT_BUS_POWER 0x00800000 150 #define SDHCI_INT_ACMD12ERR 0x01000000 151 #define SDHCI_INT_ADMAERR 0x02000000 152 153 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 154 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 155 156 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 157 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 158 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 159 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 160 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 161 SDHCI_INT_DATA_END_BIT) 162 163 #define SDHCI_ACMD12_ERR 0x3C 164 165 #define SDHCI_CAPABILITIES 0x40 166 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 167 #define SDHCI_TIMEOUT_CLK_SHIFT 0 168 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 169 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 170 #define SDHCI_CLOCK_BASE_SHIFT 8 171 #define SDHCI_MAX_BLOCK_MASK 0x00030000 172 #define SDHCI_MAX_BLOCK_SHIFT 16 173 #define SDHCI_CAN_DO_ADMA2 0x00080000 174 #define SDHCI_CAN_DO_HISPD 0x00200000 175 #define SDHCI_CAN_DO_DMA 0x00400000 176 #define SDHCI_CAN_DO_SUSPEND 0x00800000 177 #define SDHCI_CAN_VDD_330 0x01000000 178 #define SDHCI_CAN_VDD_300 0x02000000 179 #define SDHCI_CAN_VDD_180 0x04000000 180 #define SDHCI_CAN_DO_64BIT 0x10000000 181 182 #define SDHCI_MAX_CURRENT 0x48 183 184 #define SDHCI_SLOT_INT_STATUS 0xFC 185 186 #define SDHCI_HOST_VERSION 0xFE 187 #define SDHCI_VENDOR_VER_MASK 0xFF00 188 #define SDHCI_VENDOR_VER_SHIFT 8 189 #define SDHCI_SPEC_VER_MASK 0x00FF 190 #define SDHCI_SPEC_VER_SHIFT 0
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