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sys/dev/sdhci/sdhci_fsl_fdt.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 - 2021 Alstom Group. 5 * Copyright (c) 2020 - 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include <dev/extres/clk/clk.h> 46 #include <dev/extres/syscon/syscon.h> 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcbrvar.h> 49 #include <dev/mmc/mmc_fdt_helpers.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/sdhci/sdhci.h> 53 #include <dev/sdhci/sdhci_fdt_gpio.h> 54 55 #include "mmcbr_if.h" 56 #include "sdhci_if.h" 57 #include "syscon_if.h" 58 59 #define RD4 (sc->read) 60 #define WR4 (sc->write) 61 62 #define SDHCI_FSL_PRES_STATE 0x24 63 #define SDHCI_FSL_PRES_SDSTB (1 << 3) 64 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 65 66 #define SDHCI_FSL_PROT_CTRL 0x28 67 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 68 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 69 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 70 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 71 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 72 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 73 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 74 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 75 #define SDHCI_FSL_PROT_CTRL_VOLT_SEL (1 << 10) 76 77 #define SDHCI_FSL_IRQSTAT 0x30 78 #define SDHCI_FSL_IRQSTAT_BRR (1 << 5) 79 #define SDHCI_FSL_IRQSTAT_CINTSEN (1 << 8) 80 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12) 81 #define SDHCI_FSL_IRQSTAT_TNE (1 << 26) 82 83 #define SDHCI_FSL_SYS_CTRL 0x2c 84 #define SDHCI_FSL_CLK_IPGEN (1 << 0) 85 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 86 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 87 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 88 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 89 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 90 91 #define SDHCI_FSL_WTMK_LVL 0x44 92 #define SDHCI_FSL_WTMK_RD_512B (0 << 0) 93 #define SDHCI_FSL_WTMK_WR_512B (0 << 15) 94 95 #define SDHCI_FSL_AUTOCERR 0x3C 96 #define SDHCI_FSL_AUTOCERR_UHMS_HS200 (3 << 16) 97 #define SDHCI_FSL_AUTOCERR_UHMS (7 << 16) 98 #define SDHCI_FSL_AUTOCERR_EXTN (1 << 22) 99 #define SDHCI_FSL_AUTOCERR_SMPCLKSEL (1 << 23) 100 #define SDHCI_FSL_AUTOCERR_UHMS_SHIFT 16 101 102 #define SDHCI_FSL_HOST_VERSION 0xfc 103 #define SDHCI_FSL_VENDOR_V23 0x13 104 105 #define SDHCI_FSL_CAPABILITIES2 0x114 106 107 #define SDHCI_FSL_TBCTL 0x120 108 109 #define SDHCI_FSL_TBSTAT 0x124 110 #define SDHCI_FSL_TBCTL_TBEN (1 << 2) 111 #define SDHCI_FSL_TBCTL_HS400_EN (1 << 4) 112 #define SDHCI_FSL_TBCTL_SAMP_CMD_DQS (1 << 5) 113 #define SDHCI_FSL_TBCTL_HS400_WND_ADJ (1 << 6) 114 #define SDHCI_FSL_TBCTL_TB_MODE_MASK 0x3 115 #define SDHCI_FSL_TBCTL_MODE_1 0 116 #define SDHCI_FSL_TBCTL_MODE_2 1 117 #define SDHCI_FSL_TBCTL_MODE_3 2 118 #define SDHCI_FSL_TBCTL_MODE_SW 3 119 120 #define SDHCI_FSL_TBPTR 0x128 121 #define SDHCI_FSL_TBPTR_WND_START_SHIFT 8 122 #define SDHCI_FSL_TBPTR_WND_MASK 0x7F 123 124 #define SDHCI_FSL_SDCLKCTL 0x144 125 #define SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL (1 << 15) 126 #define SDHCI_FSL_SDCLKCTL_LPBK_CLK_SEL (1 << 31) 127 128 #define SDHCI_FSL_SDTIMINGCTL 0x148 129 #define SDHCI_FSL_SDTIMINGCTL_FLW_CTL (1 << 15) 130 131 #define SDHCI_FSL_DLLCFG0 0x160 132 #define SDHCI_FSL_DLLCFG0_FREQ_SEL (1 << 27) 133 #define SDHCI_FSL_DLLCFG0_RESET (1 << 30) 134 #define SDHCI_FSL_DLLCFG0_EN (1 << 31) 135 136 #define SDHCI_FSL_DLLCFG1 0x164 137 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) 138 139 #define SDHCI_FSL_DLLSTAT0 0x170 140 #define SDHCI_FSL_DLLSTAT0_SLV_STS (1 << 27) 141 142 #define SDHCI_FSL_ESDHC_CTRL 0x40c 143 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 144 #define SDHCI_FSL_ESDHC_CTRL_FAF (1 << 18) 145 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 146 147 #define SCFG_SDHCIOVSELCR 0x408 148 #define SCFG_SDHCIOVSELCR_TGLEN (1 << 0) 149 #define SCFG_SDHCIOVSELCR_VS (1 << 31) 150 #define SCFG_SDHCIOVSELCR_VSELVAL_MASK (3 << 1) 151 #define SCFG_SDHCIOVSELCR_VSELVAL_1_8 0x0 152 #define SCFG_SDHCIOVSELCR_VSELVAL_3_3 0x2 153 154 #define SDHCI_FSL_CAN_VDD_MASK \ 155 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) 156 157 /* Some platforms do not detect pulse width correctly. */ 158 #define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0) 159 /* On some platforms switching voltage to 1.8V is not supported */ 160 #define SDHCI_FSL_UNSUPP_1_8V (1 << 1) 161 /* Hardware tuning can fail, fallback to SW tuning in that case. */ 162 #define SDHCI_FSL_TUNING_ERRATUM_TYPE1 (1 << 2) 163 /* 164 * Pointer window might not be set properly on some platforms. 165 * Check window and perform SW tuning. 166 */ 167 #define SDHCI_FSL_TUNING_ERRATUM_TYPE2 (1 << 3) 168 /* 169 * In HS400 mode only 4, 8, 12 clock dividers can be used. 170 * Use the smallest value, bigger than requested in that case. 171 */ 172 #define SDHCI_FSL_HS400_LIMITED_CLK_DIV (1 << 4) 173 174 /* 175 * Some SoCs don't have a fixed regulator. Switching voltage 176 * requires special routine including syscon registers. 177 */ 178 #define SDHCI_FSL_MISSING_VCCQ_REG (1 << 5) 179 180 /* 181 * HS400 tuning is done in HS200 mode, but it has to be done using 182 * the target frequency. In order to apply the errata above we need to 183 * know the target mode during tuning procedure. Use this flag for just that. 184 */ 185 #define SDHCI_FSL_HS400_FLAG (1 << 0) 186 187 #define SDHCI_FSL_MAX_RETRIES 20000 /* DELAY(10) * this = 200ms */ 188 189 struct sdhci_fsl_fdt_softc { 190 device_t dev; 191 const struct sdhci_fsl_fdt_soc_data *soc_data; 192 struct resource *mem_res; 193 struct resource *irq_res; 194 void *irq_cookie; 195 uint32_t baseclk_hz; 196 uint32_t maxclk_hz; 197 struct sdhci_fdt_gpio *gpio; 198 struct sdhci_slot slot; 199 bool slot_init_done; 200 uint32_t cmd_and_mode; 201 uint16_t sdclk_bits; 202 struct mmc_helper fdt_helper; 203 uint32_t div_ratio; 204 uint8_t vendor_ver; 205 uint32_t flags; 206 207 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 208 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 209 }; 210 211 struct sdhci_fsl_fdt_soc_data { 212 int quirks; 213 int baseclk_div; 214 uint8_t errata; 215 char *syscon_compat; 216 }; 217 218 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1012a_soc_data = { 219 .quirks = 0, 220 .baseclk_div = 1, 221 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 222 .syscon_compat = "fsl,ls1012a-scfg", 223 }; 224 225 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { 226 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | 227 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 228 .baseclk_div = 2, 229 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 230 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 231 }; 232 233 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 234 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP, 235 .baseclk_div = 2, 236 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 237 .syscon_compat = "fsl,ls1046a-scfg", 238 }; 239 240 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_lx2160a_soc_data = { 241 .quirks = 0, 242 .baseclk_div = 2, 243 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 244 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 245 }; 246 247 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 248 .quirks = 0, 249 .baseclk_div = 1, 250 }; 251 252 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 253 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data}, 254 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data}, 255 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 256 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 257 {NULL, 0} 258 }; 259 260 static uint32_t 261 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 262 { 263 264 return (be32toh(bus_read_4(sc->mem_res, off))); 265 } 266 267 static void 268 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 269 { 270 271 bus_write_4(sc->mem_res, off, htobe32(val)); 272 } 273 274 static uint32_t 275 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 276 { 277 278 return (bus_read_4(sc->mem_res, off)); 279 } 280 281 static void 282 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 283 { 284 285 bus_write_4(sc->mem_res, off, val); 286 } 287 288 289 static uint16_t 290 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 291 { 292 uint16_t val; 293 294 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 295 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 296 val |= SDHCI_CLOCK_INT_STABLE; 297 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 298 val |= SDHCI_CLOCK_CARD_EN; 299 300 return (val); 301 } 302 303 /* 304 * Calculate clock prescaler and divisor values based on the following formula: 305 * `frequency = base clock / (prescaler * divisor)`. 306 */ 307 #define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \ 308 do { \ 309 (pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\ 310 while ((freq) < (base) / ((pre) * 16) && (pre) < 256) \ 311 (pre) <<= 1; \ 312 /* div/pre can't both be set to 1, according to PM. */ \ 313 (div) = ((pre) == 1 ? 2 : 1); \ 314 while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \ 315 ++(div); \ 316 } while (0) 317 318 static void 319 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot, 320 uint16_t val) 321 { 322 uint32_t prescale, div, val32, div_ratio; 323 324 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 325 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 326 327 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 328 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 329 return; 330 } 331 332 /* 333 * Ignore dividers provided by core in `sdhci_set_clock` and calculate 334 * them anew with higher accuracy. 335 */ 336 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div); 337 338 div_ratio = prescale * div; 339 340 /* 341 * According to limited clock division erratum, clock dividers in hs400 342 * can be only 4, 8 or 12 343 */ 344 if ((sc->soc_data->errata & SDHCI_FSL_HS400_LIMITED_CLK_DIV) && 345 (sc->slot.host.ios.timing == bus_timing_mmc_hs400 || 346 (sc->flags & SDHCI_FSL_HS400_FLAG))) { 347 if (div_ratio <= 4) { 348 prescale = 4; 349 div = 1; 350 } else if (div_ratio <= 8) { 351 prescale = 4; 352 div = 2; 353 } else if (div_ratio <= 12) { 354 prescale = 4; 355 div = 3; 356 } else { 357 device_printf(sc->dev, "Unsupported clock divider.\n"); 358 } 359 } 360 361 sc->div_ratio = prescale * div; 362 if (bootverbose) 363 device_printf(sc->dev, 364 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 365 slot->clock, sc->baseclk_hz / (prescale * div), 366 sc->baseclk_hz, prescale, div); 367 368 prescale >>= 1; 369 div -= 1; 370 371 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 372 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 373 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 374 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 375 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 376 } 377 378 static uint8_t 379 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 380 { 381 struct sdhci_fsl_fdt_softc *sc; 382 uint32_t wrk32, val32; 383 384 sc = device_get_softc(dev); 385 386 switch (off) { 387 case SDHCI_HOST_CONTROL: 388 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 389 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 390 SDHCI_CTRL_FORCE_CARD); 391 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 392 val32 |= SDHCI_CTRL_4BITBUS; 393 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 394 val32 |= SDHCI_CTRL_8BITBUS; 395 return (val32); 396 case SDHCI_POWER_CONTROL: 397 return (SDHCI_POWER_ON | SDHCI_POWER_300); 398 default: 399 break; 400 } 401 402 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 403 } 404 405 static uint16_t 406 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 407 { 408 struct sdhci_fsl_fdt_softc *sc; 409 uint32_t val32; 410 411 sc = device_get_softc(dev); 412 413 switch (off) { 414 case SDHCI_CLOCK_CONTROL: 415 return (sdhci_fsl_fdt_get_clock(sc)); 416 case SDHCI_HOST_VERSION: 417 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 418 case SDHCI_TRANSFER_MODE: 419 return (sc->cmd_and_mode & UINT16_MAX); 420 case SDHCI_COMMAND_FLAGS: 421 return (sc->cmd_and_mode >> 16); 422 case SDHCI_SLOT_INT_STATUS: 423 /* 424 * eSDHC hardware manages only a single slot. 425 * Synthesize a slot interrupt status register for slot 1 below. 426 */ 427 val32 = RD4(sc, SDHCI_INT_STATUS); 428 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 429 return (!!val32); 430 default: 431 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 432 } 433 } 434 435 static uint32_t 436 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 437 { 438 struct sdhci_fsl_fdt_softc *sc; 439 uint32_t wrk32, val32; 440 441 sc = device_get_softc(dev); 442 443 if (off == SDHCI_BUFFER) 444 return (bus_read_4(sc->mem_res, off)); 445 if (off == SDHCI_CAPABILITIES2) 446 off = SDHCI_FSL_CAPABILITIES2; 447 448 val32 = RD4(sc, off); 449 450 if (off == SDHCI_PRESENT_STATE) { 451 wrk32 = val32; 452 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 453 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 454 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 455 } 456 457 return (val32); 458 } 459 460 static void 461 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 462 uint32_t *data, bus_size_t count) 463 { 464 struct sdhci_fsl_fdt_softc *sc; 465 466 sc = device_get_softc(dev); 467 bus_read_multi_4(sc->mem_res, off, data, count); 468 } 469 470 static void 471 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 472 uint8_t val) 473 { 474 struct sdhci_fsl_fdt_softc *sc; 475 uint32_t val32; 476 477 sc = device_get_softc(dev); 478 479 switch (off) { 480 case SDHCI_HOST_CONTROL: 481 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 482 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 483 val32 |= (val & SDHCI_CTRL_LED); 484 485 if (val & SDHCI_CTRL_8BITBUS) 486 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 487 else 488 /* Bus width is 1-bit when this flag is not set. */ 489 val32 |= (val & SDHCI_CTRL_4BITBUS); 490 /* Enable SDMA by masking out this field. */ 491 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 492 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 493 val32 |= (val & (SDHCI_CTRL_CARD_DET | 494 SDHCI_CTRL_FORCE_CARD)); 495 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 496 return; 497 case SDHCI_POWER_CONTROL: 498 return; 499 default: 500 val32 = RD4(sc, off & ~3); 501 val32 &= ~(UINT8_MAX << (off & 3) * 8); 502 val32 |= (val << (off & 3) * 8); 503 WR4(sc, off & ~3, val32); 504 return; 505 } 506 } 507 508 static void 509 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 510 uint16_t val) 511 { 512 struct sdhci_fsl_fdt_softc *sc; 513 uint32_t val32; 514 515 sc = device_get_softc(dev); 516 517 switch (off) { 518 case SDHCI_CLOCK_CONTROL: 519 fsl_sdhc_fdt_set_clock(sc, slot, val); 520 return; 521 /* 522 * eSDHC hardware combines command and mode into a single 523 * register. Cache it here, so that command isn't written 524 * until after mode. 525 */ 526 case SDHCI_TRANSFER_MODE: 527 sc->cmd_and_mode = val; 528 return; 529 case SDHCI_COMMAND_FLAGS: 530 sc->cmd_and_mode = 531 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 532 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 533 sc->cmd_and_mode = 0; 534 return; 535 case SDHCI_HOST_CONTROL2: 536 /* 537 * Switching to HS400 requires a special procedure, 538 * which is done in sdhci_fsl_fdt_set_uhs_timing. 539 */ 540 if ((val & SDHCI_CTRL2_UHS_MASK) == SDHCI_CTRL2_MMC_HS400) 541 val &= ~SDHCI_CTRL2_MMC_HS400; 542 default: 543 val32 = RD4(sc, off & ~3); 544 val32 &= ~(UINT16_MAX << (off & 3) * 8); 545 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 546 WR4(sc, off & ~3, val32); 547 return; 548 } 549 } 550 551 static void 552 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 553 uint32_t val) 554 { 555 struct sdhci_fsl_fdt_softc *sc; 556 557 sc = device_get_softc(dev); 558 559 switch (off) { 560 case SDHCI_BUFFER: 561 bus_write_4(sc->mem_res, off, val); 562 return; 563 /* 564 * eSDHC hardware lacks support for the SDMA buffer boundary 565 * feature and instead generates SDHCI_INT_DMA_END interrupts 566 * after each completed DMA data transfer. 567 * Since this duplicates the SDHCI_INT_DATA_END functionality, 568 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 569 */ 570 case SDHCI_INT_ENABLE: 571 case SDHCI_SIGNAL_ENABLE: 572 val &= ~SDHCI_INT_DMA_END; 573 /* FALLTHROUGH. */ 574 default: 575 WR4(sc, off, val); 576 return; 577 } 578 } 579 580 static void 581 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 582 bus_size_t off, uint32_t *data, bus_size_t count) 583 { 584 struct sdhci_fsl_fdt_softc *sc; 585 586 sc = device_get_softc(dev); 587 bus_write_multi_4(sc->mem_res, off, data, count); 588 } 589 590 static void 591 sdhci_fsl_fdt_irq(void *arg) 592 { 593 struct sdhci_fsl_fdt_softc *sc; 594 595 sc = arg; 596 sdhci_generic_intr(&sc->slot); 597 return; 598 } 599 600 static int 601 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev) 602 { 603 int err; 604 struct sdhci_fsl_fdt_softc *sc; 605 struct mmc_ios *ios; 606 struct sdhci_slot *slot; 607 608 err = sdhci_generic_update_ios(brdev, reqdev); 609 if (err != 0) 610 return (err); 611 612 sc = device_get_softc(brdev); 613 slot = device_get_ivars(reqdev); 614 ios = &slot->host.ios; 615 616 switch (ios->power_mode) { 617 case power_on: 618 break; 619 case power_off: 620 if (bootverbose) 621 device_printf(sc->dev, "Powering down sd/mmc\n"); 622 623 if (sc->fdt_helper.vmmc_supply) 624 regulator_disable(sc->fdt_helper.vmmc_supply); 625 if (sc->fdt_helper.vqmmc_supply) 626 regulator_disable(sc->fdt_helper.vqmmc_supply); 627 break; 628 case power_up: 629 if (bootverbose) 630 device_printf(sc->dev, "Powering up sd/mmc\n"); 631 632 if (sc->fdt_helper.vmmc_supply) 633 regulator_enable(sc->fdt_helper.vmmc_supply); 634 if (sc->fdt_helper.vqmmc_supply) 635 regulator_enable(sc->fdt_helper.vqmmc_supply); 636 break; 637 }; 638 639 return (0); 640 } 641 642 static int 643 sdhci_fsl_fdt_switch_syscon_voltage(device_t dev, 644 struct sdhci_fsl_fdt_softc *sc, enum mmc_vccq vccq) 645 { 646 struct syscon *syscon; 647 phandle_t syscon_node; 648 uint32_t reg; 649 650 if (sc->soc_data->syscon_compat == NULL) { 651 device_printf(dev, "Empty syscon compat string.\n"); 652 return (ENXIO); 653 } 654 655 syscon_node = ofw_bus_find_compatible(OF_finddevice("/"), 656 sc->soc_data->syscon_compat); 657 658 if (syscon_get_by_ofw_node(dev, syscon_node, &syscon) != 0) { 659 device_printf(dev, "Could not find syscon node.\n"); 660 return (ENXIO); 661 } 662 663 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 664 reg &= ~SCFG_SDHCIOVSELCR_VSELVAL_MASK; 665 reg |= SCFG_SDHCIOVSELCR_TGLEN; 666 667 switch (vccq) { 668 case vccq_180: 669 reg |= SCFG_SDHCIOVSELCR_VSELVAL_1_8; 670 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 671 672 DELAY(5000); 673 674 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 675 reg |= SCFG_SDHCIOVSELCR_VS; 676 break; 677 case vccq_330: 678 reg |= SCFG_SDHCIOVSELCR_VSELVAL_3_3; 679 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 680 681 DELAY(5000); 682 683 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 684 reg &= ~SCFG_SDHCIOVSELCR_VS; 685 break; 686 default: 687 device_printf(dev, "Unsupported voltage requested.\n"); 688 return (ENXIO); 689 } 690 691 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 692 693 return (0); 694 } 695 696 static int 697 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev) 698 { 699 struct sdhci_fsl_fdt_softc *sc; 700 struct sdhci_slot *slot; 701 regulator_t vqmmc_supply; 702 uint32_t val_old, val; 703 int uvolt, err = 0; 704 705 sc = device_get_softc(brdev); 706 slot = device_get_ivars(reqdev); 707 708 val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL); 709 710 switch (slot->host.ios.vccq) { 711 case vccq_180: 712 if (sc->soc_data->errata & SDHCI_FSL_UNSUPP_1_8V) 713 return (EOPNOTSUPP); 714 715 val |= SDHCI_FSL_PROT_CTRL_VOLT_SEL; 716 uvolt = 1800000; 717 break; 718 case vccq_330: 719 val &= ~SDHCI_FSL_PROT_CTRL_VOLT_SEL; 720 uvolt = 3300000; 721 break; 722 default: 723 return (EOPNOTSUPP); 724 } 725 726 WR4(sc, SDHCI_FSL_PROT_CTRL, val); 727 728 if (sc->soc_data->errata & SDHCI_FSL_MISSING_VCCQ_REG) { 729 err = sdhci_fsl_fdt_switch_syscon_voltage(brdev, sc, 730 slot->host.ios.vccq); 731 if (err != 0) 732 goto vccq_fail; 733 } 734 735 vqmmc_supply = sc->fdt_helper.vqmmc_supply; 736 /* 737 * Even though we expect to find a fixed regulator in this controller 738 * family, let's play safe. 739 */ 740 if (vqmmc_supply != NULL) { 741 err = regulator_set_voltage(vqmmc_supply, uvolt, uvolt); 742 if (err != 0) 743 goto vccq_fail; 744 } 745 746 return (0); 747 748 vccq_fail: 749 device_printf(sc->dev, "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt); 750 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); 751 752 return (err); 753 } 754 755 static int 756 sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 757 { 758 struct sdhci_fsl_fdt_softc *sc; 759 760 sc = device_get_softc(bus); 761 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 762 } 763 764 static bool 765 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 766 { 767 struct sdhci_fsl_fdt_softc *sc; 768 769 sc = device_get_softc(dev); 770 return (sdhci_fdt_gpio_get_present(sc->gpio)); 771 } 772 773 static uint32_t 774 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len) 775 { 776 uint32_t vdd_min, vdd_max; 777 uint32_t vdd_mask = 0; 778 int i; 779 780 /* Ranges are organized as pairs of values. */ 781 if ((len % 2) != 0) { 782 device_printf(dev, "Invalid voltage range\n"); 783 return (0); 784 } 785 len = len / 2; 786 787 for (i = 0; i < len; i++) { 788 vdd_min = vdd_ranges[2 * i]; 789 vdd_max = vdd_ranges[2 * i + 1]; 790 791 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 || 792 vdd_max < 1650 || vdd_max > 3600) { 793 device_printf(dev, "Voltage range %d - %d is out of bounds\n", 794 vdd_min, vdd_max); 795 return (0); 796 } 797 798 if (vdd_min <= 1800 && vdd_max >= 1800) 799 vdd_mask |= SDHCI_CAN_VDD_180; 800 if (vdd_min <= 3000 && vdd_max >= 3000) 801 vdd_mask |= SDHCI_CAN_VDD_300; 802 if (vdd_min <= 3300 && vdd_max >= 3300) 803 vdd_mask |= SDHCI_CAN_VDD_330; 804 } 805 806 return (vdd_mask); 807 } 808 809 static void 810 sdhci_fsl_fdt_of_parse(device_t dev) 811 { 812 struct sdhci_fsl_fdt_softc *sc; 813 phandle_t node; 814 pcell_t *voltage_ranges; 815 uint32_t vdd_mask = 0; 816 ssize_t num_ranges; 817 818 sc = device_get_softc(dev); 819 node = ofw_bus_get_node(dev); 820 821 /* Call mmc_fdt_parse in order to get mmc related properties. */ 822 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host); 823 824 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot, 825 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND); 826 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot, 827 SDHCI_CAPABILITIES2); 828 829 /* Parse the "voltage-ranges" dts property. */ 830 num_ranges = OF_getencprop_alloc(node, "voltage-ranges", 831 (void **) &voltage_ranges); 832 if (num_ranges <= 0) 833 return; 834 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges, 835 num_ranges / sizeof(uint32_t)); 836 OF_prop_free(voltage_ranges); 837 838 /* Overwrite voltage caps only if we got something from dts. */ 839 if (vdd_mask != 0 && 840 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) { 841 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK); 842 sc->slot.caps |= vdd_mask; 843 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS; 844 } 845 } 846 847 static int 848 sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc *sc, 849 uint32_t reg, uint32_t mask, int value) 850 { 851 int retries; 852 853 retries = SDHCI_FSL_MAX_RETRIES; 854 855 while ((RD4(sc, reg) & mask) != value) { 856 if (!retries--) 857 return (ENXIO); 858 859 DELAY(10); 860 } 861 862 return (0); 863 } 864 865 static int 866 sdhci_fsl_fdt_attach(device_t dev) 867 { 868 struct sdhci_fsl_fdt_softc *sc; 869 struct mmc_host *host; 870 uint32_t val, buf_order; 871 uintptr_t ocd_data; 872 uint64_t clk_hz; 873 phandle_t node; 874 int rid, ret; 875 clk_t clk; 876 877 node = ofw_bus_get_node(dev); 878 sc = device_get_softc(dev); 879 ocd_data = ofw_bus_search_compatible(dev, 880 sdhci_fsl_fdt_compat_data)->ocd_data; 881 sc->dev = dev; 882 sc->flags = 0; 883 host = &sc->slot.host; 884 rid = 0; 885 886 /* 887 * LX2160A needs its own soc_data in order to apply SoC 888 * specific quriks. Since the controller is identified 889 * only with a generic compatible string we need to do this dance here. 890 */ 891 if (ofw_bus_node_is_compatible(OF_finddevice("/"), "fsl,lx2160a")) 892 sc->soc_data = &sdhci_fsl_fdt_lx2160a_soc_data; 893 else 894 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 895 896 sc->slot.quirks = sc->soc_data->quirks; 897 898 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 899 RF_ACTIVE); 900 if (sc->mem_res == NULL) { 901 device_printf(dev, 902 "Could not allocate resources for controller\n"); 903 return (ENOMEM); 904 } 905 906 rid = 0; 907 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 908 RF_ACTIVE); 909 if (sc->irq_res == NULL) { 910 device_printf(dev, 911 "Could not allocate irq resources for controller\n"); 912 ret = ENOMEM; 913 goto err_free_mem; 914 } 915 916 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 917 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 918 if (ret != 0) { 919 device_printf(dev, "Could not setup IRQ handler\n"); 920 goto err_free_irq_res; 921 } 922 923 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 924 if (ret != 0) { 925 device_printf(dev, "Parent clock not found\n"); 926 goto err_free_irq; 927 } 928 929 ret = clk_get_freq(clk, &clk_hz); 930 if (ret != 0) { 931 device_printf(dev, 932 "Could not get parent clock frequency\n"); 933 goto err_free_irq; 934 } 935 936 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div; 937 938 /* Figure out eSDHC block endianness before we touch any HW regs. */ 939 if (OF_hasprop(node, "little-endian")) { 940 sc->read = read_le; 941 sc->write = write_le; 942 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 943 } else { 944 sc->read = read_be; 945 sc->write = write_be; 946 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 947 } 948 949 sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) & 950 SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; 951 952 sdhci_fsl_fdt_of_parse(dev); 953 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz; 954 955 /* 956 * Setting this register affects byte order in SDHCI_BUFFER only. 957 * If the eSDHC block is connected over a big-endian bus, the data 958 * read from/written to the buffer will be already byte swapped. 959 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 960 * the byte order again, resulting in a native byte order. 961 * The read/write callbacks accommodate for this behavior. 962 */ 963 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 964 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 965 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 966 967 /* 968 * Gate the SD clock and set its source to 969 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set 970 * to match this. 971 */ 972 val = RD4(sc, SDHCI_CLOCK_CONTROL); 973 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 974 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 975 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 976 sc->slot.max_clk = sc->maxclk_hz; 977 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 978 979 /* 980 * Set the buffer watermark level to 128 words (512 bytes) for both 981 * read and write. The hardware has a restriction that when the read or 982 * write ready status is asserted, that means you can read exactly the 983 * number of words set in the watermark register before you have to 984 * re-check the status and potentially wait for more data. The main 985 * sdhci driver provides no hook for doing status checking on less than 986 * a full block boundary, so we set the watermark level to be a full 987 * block. Reads and writes where the block size is less than the 988 * watermark size will work correctly too, no need to change the 989 * watermark for different size blocks. However, 128 is the maximum 990 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 991 */ 992 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 993 SDHCI_FSL_WTMK_RD_512B); 994 995 ret = sdhci_init_slot(dev, &sc->slot, 0); 996 if (ret != 0) 997 goto err_free_gpio; 998 sc->slot_init_done = true; 999 sdhci_start_slot(&sc->slot); 1000 1001 return (bus_generic_attach(dev)); 1002 1003 err_free_gpio: 1004 sdhci_fdt_gpio_teardown(sc->gpio); 1005 err_free_irq: 1006 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1007 err_free_irq_res: 1008 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1009 err_free_mem: 1010 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1011 return (ret); 1012 } 1013 1014 static int 1015 sdhci_fsl_fdt_detach(device_t dev) 1016 { 1017 struct sdhci_fsl_fdt_softc *sc; 1018 1019 sc = device_get_softc(dev); 1020 if (sc->slot_init_done) 1021 sdhci_cleanup_slot(&sc->slot); 1022 if (sc->gpio != NULL) 1023 sdhci_fdt_gpio_teardown(sc->gpio); 1024 if (sc->irq_cookie != NULL) 1025 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1026 if (sc->irq_res != NULL) 1027 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1028 if (sc->mem_res != NULL) 1029 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1030 return (0); 1031 } 1032 1033 static int 1034 sdhci_fsl_fdt_probe(device_t dev) 1035 { 1036 1037 if (!ofw_bus_status_okay(dev)) 1038 return (ENXIO); 1039 1040 if (!ofw_bus_search_compatible(dev, 1041 sdhci_fsl_fdt_compat_data)->ocd_data) 1042 return (ENXIO); 1043 1044 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 1045 return (BUS_PROBE_DEFAULT); 1046 } 1047 1048 static int 1049 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 1050 uintptr_t *result) 1051 { 1052 struct sdhci_slot *slot = device_get_ivars(child); 1053 1054 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 1055 /* 1056 * In the absence of SDMA buffer boundary functionality, 1057 * limit the maximum data length per read/write command 1058 * to bounce buffer size. 1059 */ 1060 *result = howmany(slot->sdma_bbufsz, 512); 1061 return (0); 1062 } 1063 return (sdhci_generic_read_ivar(bus, child, which, result)); 1064 } 1065 1066 static int 1067 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which, 1068 uintptr_t value) 1069 { 1070 struct sdhci_fsl_fdt_softc *sc; 1071 struct sdhci_slot *slot = device_get_ivars(child); 1072 uint32_t prescale, div; 1073 1074 /* Don't depend on clock resolution limits from sdhci core. */ 1075 if (which == MMCBR_IVAR_CLOCK) { 1076 if (value == 0) { 1077 slot->host.ios.clock = 0; 1078 return (0); 1079 } 1080 1081 sc = device_get_softc(bus); 1082 1083 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div); 1084 slot->host.ios.clock = sc->baseclk_hz / (prescale * div); 1085 1086 return (0); 1087 } 1088 1089 return (sdhci_generic_write_ivar(bus, child, which, value)); 1090 } 1091 1092 static void 1093 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask) 1094 { 1095 struct sdhci_fsl_fdt_softc *sc; 1096 uint32_t val; 1097 1098 sdhci_generic_reset(dev, slot, mask); 1099 1100 if (!(mask & SDHCI_RESET_ALL)) 1101 return; 1102 1103 sc = device_get_softc(dev); 1104 1105 /* Some registers have to be cleared by hand. */ 1106 if (slot->version >= SDHCI_SPEC_300) { 1107 val = RD4(sc, SDHCI_FSL_TBCTL); 1108 val &= ~SDHCI_FSL_TBCTL_TBEN; 1109 WR4(sc, SDHCI_FSL_TBCTL, val); 1110 } 1111 1112 /* 1113 * Pulse width detection is not reliable on some boards. Perform 1114 * workaround by clearing register's bit according to errata. 1115 */ 1116 if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) { 1117 val = RD4(sc, SDHCI_FSL_DLLCFG1); 1118 val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH; 1119 WR4(sc, SDHCI_FSL_DLLCFG1, val); 1120 } 1121 1122 sc->flags = 0; 1123 } 1124 1125 static void 1126 sdhci_fsl_switch_tuning_block(device_t dev, bool enable) 1127 { 1128 struct sdhci_fsl_fdt_softc *sc; 1129 uint32_t reg; 1130 1131 sc = device_get_softc(dev); 1132 1133 reg = RD4(sc, SDHCI_FSL_TBCTL); 1134 1135 if (enable) 1136 reg |= SDHCI_FSL_TBCTL_TBEN; 1137 else 1138 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1139 1140 WR4(sc, SDHCI_FSL_TBCTL, reg); 1141 } 1142 1143 static int 1144 sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus, 1145 device_t child, bool hs400, uint32_t wnd_start, uint32_t wnd_end) 1146 { 1147 uint32_t reg; 1148 int error; 1149 1150 if (sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE1 || 1151 abs(wnd_start - wnd_end) <= (4 * sc->div_ratio + 2)) { 1152 wnd_start = 5 * sc->div_ratio; 1153 wnd_end = 3 * sc->div_ratio; 1154 } else { 1155 wnd_start = 8 * sc->div_ratio; 1156 wnd_end = 4 * sc->div_ratio; 1157 } 1158 1159 reg = RD4(sc, SDHCI_FSL_TBPTR); 1160 reg &= ~SDHCI_FSL_TBPTR_WND_MASK; 1161 reg &= ~(SDHCI_FSL_TBPTR_WND_MASK << SDHCI_FSL_TBPTR_WND_START_SHIFT); 1162 reg |= wnd_start << SDHCI_FSL_TBPTR_WND_START_SHIFT; 1163 reg |= wnd_end; 1164 WR4(sc, SDHCI_FSL_TBPTR, reg); 1165 1166 /* 1167 * Normally those are supposed to be set in sdhci_execute_tuning. 1168 * However in our case we need a small delay between setting the two. 1169 */ 1170 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1171 reg |= SDHCI_FSL_AUTOCERR_EXTN; 1172 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1173 DELAY(10); 1174 reg |= SDHCI_FSL_AUTOCERR_SMPCLKSEL; 1175 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1176 1177 reg = RD4(sc, SDHCI_FSL_TBCTL); 1178 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1179 reg |= SDHCI_FSL_TBCTL_MODE_SW; 1180 WR4(sc, SDHCI_FSL_TBCTL, reg); 1181 1182 error = sdhci_generic_tune(bus, child, hs400); 1183 if (error != 0) { 1184 device_printf(bus, 1185 "Failed to execute generic tune while performing software tuning.\n"); 1186 } 1187 1188 return (error); 1189 } 1190 1191 static int 1192 sdhci_fsl_fdt_tune(device_t bus, device_t child, bool hs400) 1193 { 1194 struct sdhci_fsl_fdt_softc *sc; 1195 uint32_t wnd_start, wnd_end; 1196 uint32_t clk_divider, reg; 1197 struct sdhci_slot *slot; 1198 int error; 1199 1200 sc = device_get_softc(bus); 1201 slot = device_get_ivars(child); 1202 error = 0; 1203 clk_divider = sc->baseclk_hz / slot->clock; 1204 1205 switch (sc->slot.host.ios.timing) { 1206 case bus_timing_mmc_hs400: 1207 return (EINVAL); 1208 case bus_timing_mmc_hs200: 1209 case bus_timing_uhs_ddr50: 1210 case bus_timing_uhs_sdr104: 1211 break; 1212 case bus_timing_uhs_sdr50: 1213 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1214 break; 1215 default: 1216 return (0); 1217 } 1218 1219 /* 1220 * For tuning mode SD clock divider must be within 3 to 16. 1221 * We also need to match the frequency to whatever mode is used. 1222 * For that reason we're just bailing if the dividers don't match 1223 * that requirement. 1224 */ 1225 if (clk_divider < 3 || clk_divider > 16) 1226 return (ENXIO); 1227 1228 if (hs400) 1229 sc->flags |= SDHCI_FSL_HS400_FLAG; 1230 1231 /* Disable clock. */ 1232 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1233 1234 /* Wait for PRSSTAT[SDSTB] to be set by hardware. */ 1235 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1236 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1237 if (error != 0) 1238 device_printf(bus, 1239 "Timeout while waiting for clock to stabilize.\n"); 1240 1241 /* Flush async IO. */ 1242 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1243 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1244 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1245 1246 /* Wait for ESDHC[FAF] to be cleared by hardware. */ 1247 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1248 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1249 if (error) 1250 device_printf(bus, 1251 "Timeout while waiting for hardware.\n"); 1252 1253 /* 1254 * Set TBCTL[TB_EN] register and program valid tuning mode. 1255 * According to RM MODE_3 means that: 1256 * "eSDHC takes care of the re-tuning during data transfer 1257 * (auto re-tuning).". 1258 * Tuning mode can only be changed while the clock is disabled. 1259 */ 1260 reg = RD4(sc, SDHCI_FSL_TBCTL); 1261 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1262 reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3; 1263 WR4(sc, SDHCI_FSL_TBCTL, reg); 1264 1265 /* Enable clock. */ 1266 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | sc->sdclk_bits); 1267 1268 /* Wait for clock to stabilize. */ 1269 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1270 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1271 if (error) 1272 device_printf(bus, 1273 "Timeout while waiting for clock to stabilize.\n"); 1274 1275 /* Perform hardware tuning. */ 1276 error = sdhci_generic_tune(bus, child, hs400); 1277 1278 reg = RD4(sc, SDHCI_FSL_TBPTR); 1279 wnd_start = reg >> SDHCI_FSL_TBPTR_WND_START_SHIFT; 1280 wnd_start &= SDHCI_FSL_TBPTR_WND_MASK; 1281 wnd_end = reg & SDHCI_FSL_TBPTR_WND_MASK; 1282 1283 /* 1284 * For erratum type2 affected platforms, the controller can erroneously 1285 * declare that the tuning was successful. Verify the tuning window to 1286 * make sure that we're fine. 1287 */ 1288 if (error == 0 && 1289 sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE2 && 1290 abs(wnd_start - wnd_end) > (4 * sc->div_ratio + 2)) { 1291 error = EIO; 1292 } 1293 1294 /* If hardware tuning failed, try software tuning. */ 1295 if (error != 0 && 1296 (sc->soc_data->errata & 1297 (SDHCI_FSL_TUNING_ERRATUM_TYPE1 | 1298 SDHCI_FSL_TUNING_ERRATUM_TYPE2))) { 1299 error = sdhci_fsl_sw_tuning(sc, bus, child, hs400, wnd_start, 1300 wnd_end); 1301 if (error != 0) 1302 device_printf(bus, "Software tuning failed.\n"); 1303 } 1304 1305 if (error != 0) { 1306 sdhci_fsl_switch_tuning_block(bus, false); 1307 return (error); 1308 } 1309 if (hs400) { 1310 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1311 reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1312 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1313 } 1314 1315 return (0); 1316 } 1317 1318 static int 1319 sdhci_fsl_fdt_retune(device_t bus, device_t child, bool reset) 1320 { 1321 struct sdhci_slot *slot; 1322 struct sdhci_fsl_fdt_softc *sc; 1323 1324 slot = device_get_ivars(child); 1325 sc = device_get_softc(bus); 1326 1327 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1328 return (0); 1329 1330 /* HS400 must be tuned in HS200 mode. */ 1331 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1332 return (EINVAL); 1333 1334 /* 1335 * Only re-tuning with full reset is supported. 1336 * The controller is normally put in "mode 3", which means that 1337 * periodic re-tuning is done automatically. See comment in 1338 * sdhci_fsl_fdt_tune for details. 1339 * Because of that re-tuning should only be triggered as a result 1340 * of a CRC error. 1341 */ 1342 if (!reset) 1343 return (ENOTSUP); 1344 1345 return (sdhci_fsl_fdt_tune(bus, child, 1346 sc->flags & SDHCI_FSL_HS400_FLAG)); 1347 } 1348 static void 1349 sdhci_fsl_disable_hs400_mode(device_t dev, struct sdhci_fsl_fdt_softc *sc) 1350 { 1351 uint32_t reg; 1352 int error; 1353 1354 /* Check if HS400 is enabled right now. */ 1355 reg = RD4(sc, SDHCI_FSL_TBCTL); 1356 if ((reg & SDHCI_FSL_TBCTL_HS400_EN) == 0) 1357 return; 1358 1359 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1360 reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1361 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1362 1363 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1364 reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1365 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1366 1367 fsl_sdhc_fdt_set_clock(sc, &sc->slot, sc->sdclk_bits); 1368 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1369 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1370 if (error != 0) 1371 device_printf(dev, 1372 "Internal clock never stabilized.\n"); 1373 1374 reg = RD4(sc, SDHCI_FSL_TBCTL); 1375 reg &= ~SDHCI_FSL_TBCTL_HS400_EN; 1376 WR4(sc, SDHCI_FSL_TBCTL, reg); 1377 1378 fsl_sdhc_fdt_set_clock(sc, &sc->slot, SDHCI_CLOCK_CARD_EN | 1379 sc->sdclk_bits); 1380 1381 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1382 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1383 if (error != 0) 1384 device_printf(dev, 1385 "Internal clock never stabilized.\n"); 1386 1387 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1388 reg &= ~(SDHCI_FSL_DLLCFG0_EN | 1389 SDHCI_FSL_DLLCFG0_FREQ_SEL); 1390 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1391 1392 reg = RD4(sc, SDHCI_FSL_TBCTL); 1393 reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1394 WR4(sc, SDHCI_FSL_TBCTL, reg); 1395 1396 sdhci_fsl_switch_tuning_block(dev, false); 1397 } 1398 1399 static void 1400 sdhci_fsl_enable_hs400_mode(device_t dev, struct sdhci_slot *slot, 1401 struct sdhci_fsl_fdt_softc *sc) 1402 { 1403 uint32_t reg; 1404 int error; 1405 1406 sdhci_fsl_switch_tuning_block(dev, true); 1407 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1408 1409 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1410 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1411 if (error != 0) 1412 device_printf(dev, 1413 "Timeout while waiting for clock to stabilize.\n"); 1414 1415 reg = RD4(sc, SDHCI_FSL_TBCTL); 1416 reg |= SDHCI_FSL_TBCTL_HS400_EN; 1417 WR4(sc, SDHCI_FSL_TBCTL, reg); 1418 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1419 reg |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1420 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1421 1422 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1423 sc->sdclk_bits); 1424 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1425 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1426 if (error != 0) 1427 device_printf(dev, 1428 "Timeout while waiting for clock to stabilize.\n"); 1429 1430 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1431 reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_RESET | 1432 SDHCI_FSL_DLLCFG0_FREQ_SEL; 1433 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1434 1435 /* 1436 * The reset bit is not a self clearing one. 1437 * Give it some time and clear it manually. 1438 */ 1439 DELAY(100); 1440 reg &= ~SDHCI_FSL_DLLCFG0_RESET; 1441 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1442 1443 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_DLLSTAT0, 1444 SDHCI_FSL_DLLSTAT0_SLV_STS, SDHCI_FSL_DLLSTAT0_SLV_STS); 1445 if (error != 0) 1446 device_printf(dev, 1447 "Timeout while waiting for DLL0.\n"); 1448 1449 reg = RD4(sc, SDHCI_FSL_TBCTL); 1450 reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1451 WR4(sc, SDHCI_FSL_TBCTL, reg); 1452 1453 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1454 1455 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1456 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1457 if (error != 0) 1458 device_printf(dev, 1459 "timeout while waiting for clock to stabilize.\n"); 1460 1461 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1462 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1463 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1464 1465 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1466 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1467 if (error != 0) 1468 device_printf(dev, 1469 "Timeout while waiting for hardware.\n"); 1470 1471 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1472 sc->sdclk_bits); 1473 1474 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1475 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1476 if (error != 0) 1477 device_printf(dev, 1478 "Timeout while waiting for clock to stabilize.\n"); 1479 } 1480 1481 static void 1482 sdhci_fsl_fdt_set_uhs_timing(device_t dev, struct sdhci_slot *slot) 1483 { 1484 struct sdhci_fsl_fdt_softc *sc; 1485 const struct mmc_ios *ios; 1486 uint32_t mode, reg; 1487 1488 sc = device_get_softc(dev); 1489 ios = &slot->host.ios; 1490 mode = 0; 1491 1492 /* 1493 * When we switch to HS400 this function is called twice. 1494 * First after the timing is set, and then after the clock 1495 * is changed to the target frequency. 1496 * The controller can be switched to HS400 only after the latter 1497 * is done. 1498 */ 1499 if (slot->host.ios.timing == bus_timing_mmc_hs400 && 1500 ios->clock > SD_SDR50_MAX) 1501 sdhci_fsl_enable_hs400_mode(dev, slot, sc); 1502 else if (slot->host.ios.timing < bus_timing_mmc_hs400) { 1503 sdhci_fsl_disable_hs400_mode(dev, sc); 1504 1505 /* 1506 * Switching to HS400 requires a custom procedure executed in 1507 * sdhci_fsl_enable_hs400_mode in case above. 1508 * For all other modes we just need to set the corresponding flag. 1509 */ 1510 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1511 reg &= ~SDHCI_FSL_AUTOCERR_UHMS; 1512 if (ios->clock > SD_SDR50_MAX) 1513 mode = SDHCI_CTRL2_UHS_SDR104; 1514 else if (ios->clock > SD_SDR25_MAX) 1515 mode = SDHCI_CTRL2_UHS_SDR50; 1516 else if (ios->clock > SD_SDR12_MAX) { 1517 if (ios->timing == bus_timing_uhs_ddr50 || 1518 ios->timing == bus_timing_mmc_ddr52) 1519 mode = SDHCI_CTRL2_UHS_DDR50; 1520 else 1521 mode = SDHCI_CTRL2_UHS_SDR25; 1522 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1523 mode = SDHCI_CTRL2_UHS_SDR12; 1524 1525 reg |= mode << SDHCI_FSL_AUTOCERR_UHMS_SHIFT; 1526 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1527 } 1528 } 1529 1530 static const device_method_t sdhci_fsl_fdt_methods[] = { 1531 /* Device interface. */ 1532 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 1533 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 1534 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 1535 1536 /* Bus interface. */ 1537 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 1538 DEVMETHOD(bus_write_ivar, sdhci_fsl_fdt_write_ivar), 1539 1540 /* MMC bridge interface. */ 1541 DEVMETHOD(mmcbr_request, sdhci_generic_request), 1542 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 1543 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 1544 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 1545 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq), 1546 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios), 1547 DEVMETHOD(mmcbr_tune, sdhci_fsl_fdt_tune), 1548 DEVMETHOD(mmcbr_retune, sdhci_fsl_fdt_retune), 1549 1550 /* SDHCI accessors. */ 1551 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 1552 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 1553 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 1554 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 1555 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 1556 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 1557 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 1558 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 1559 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 1560 DEVMETHOD(sdhci_reset, sdhci_fsl_fdt_reset), 1561 DEVMETHOD(sdhci_set_uhs_timing, sdhci_fsl_fdt_set_uhs_timing), 1562 DEVMETHOD_END 1563 }; 1564 1565 static driver_t sdhci_fsl_fdt_driver = { 1566 "sdhci_fsl_fdt", 1567 sdhci_fsl_fdt_methods, 1568 sizeof(struct sdhci_fsl_fdt_softc), 1569 }; 1570 1571 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, NULL, NULL); 1572 SDHCI_DEPEND(sdhci_fsl_fdt); 1573 1574 #ifndef MMCCAM 1575 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 1576 #endif
Cache object: d55ce8192c9ce52ca793ac052350022d
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