Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sfxge/common/ef10_impl.h
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1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EF10_IMPL_H 34 #define _SYS_EF10_IMPL_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* Number of hardware PIO buffers (for compile-time resource dimensions) */ 41 #define EF10_MAX_PIOBUF_NBUFS (16) 42 43 #if EFSYS_OPT_HUNTINGTON 44 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS) 45 # error "EF10_MAX_PIOBUF_NBUFS too small" 46 # endif 47 #endif /* EFSYS_OPT_HUNTINGTON */ 48 #if EFSYS_OPT_MEDFORD 49 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS) 50 # error "EF10_MAX_PIOBUF_NBUFS too small" 51 # endif 52 #endif /* EFSYS_OPT_MEDFORD */ 53 #if EFSYS_OPT_MEDFORD2 54 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS) 55 # error "EF10_MAX_PIOBUF_NBUFS too small" 56 # endif 57 #endif /* EFSYS_OPT_MEDFORD2 */ 58 59 /* 60 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 61 * possibly be increased, or the write size reported by newer firmware used 62 * instead. 63 */ 64 #define EF10_NVRAM_CHUNK 0x80 65 66 /* 67 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned 68 * to an 8 descriptor boundary. 69 */ 70 #define EF10_RX_WPTR_ALIGN 8 71 72 /* 73 * Max byte offset into the packet the TCP header must start for the hardware 74 * to be able to parse the packet correctly. 75 */ 76 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 77 78 /* Invalid RSS context handle */ 79 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 80 81 /* EV */ 82 83 __checkReturn efx_rc_t 84 ef10_ev_init( 85 __in efx_nic_t *enp); 86 87 void 88 ef10_ev_fini( 89 __in efx_nic_t *enp); 90 91 __checkReturn efx_rc_t 92 ef10_ev_qcreate( 93 __in efx_nic_t *enp, 94 __in unsigned int index, 95 __in efsys_mem_t *esmp, 96 __in size_t ndescs, 97 __in uint32_t id, 98 __in uint32_t us, 99 __in uint32_t flags, 100 __in efx_evq_t *eep); 101 102 void 103 ef10_ev_qdestroy( 104 __in efx_evq_t *eep); 105 106 __checkReturn efx_rc_t 107 ef10_ev_qprime( 108 __in efx_evq_t *eep, 109 __in unsigned int count); 110 111 void 112 ef10_ev_qpost( 113 __in efx_evq_t *eep, 114 __in uint16_t data); 115 116 __checkReturn efx_rc_t 117 ef10_ev_qmoderate( 118 __in efx_evq_t *eep, 119 __in unsigned int us); 120 121 #if EFSYS_OPT_QSTATS 122 void 123 ef10_ev_qstats_update( 124 __in efx_evq_t *eep, 125 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 126 #endif /* EFSYS_OPT_QSTATS */ 127 128 void 129 ef10_ev_rxlabel_init( 130 __in efx_evq_t *eep, 131 __in efx_rxq_t *erp, 132 __in unsigned int label, 133 __in efx_rxq_type_t type); 134 135 void 136 ef10_ev_rxlabel_fini( 137 __in efx_evq_t *eep, 138 __in unsigned int label); 139 140 /* INTR */ 141 142 __checkReturn efx_rc_t 143 ef10_intr_init( 144 __in efx_nic_t *enp, 145 __in efx_intr_type_t type, 146 __in efsys_mem_t *esmp); 147 148 void 149 ef10_intr_enable( 150 __in efx_nic_t *enp); 151 152 void 153 ef10_intr_disable( 154 __in efx_nic_t *enp); 155 156 void 157 ef10_intr_disable_unlocked( 158 __in efx_nic_t *enp); 159 160 __checkReturn efx_rc_t 161 ef10_intr_trigger( 162 __in efx_nic_t *enp, 163 __in unsigned int level); 164 165 void 166 ef10_intr_status_line( 167 __in efx_nic_t *enp, 168 __out boolean_t *fatalp, 169 __out uint32_t *qmaskp); 170 171 void 172 ef10_intr_status_message( 173 __in efx_nic_t *enp, 174 __in unsigned int message, 175 __out boolean_t *fatalp); 176 177 void 178 ef10_intr_fatal( 179 __in efx_nic_t *enp); 180 void 181 ef10_intr_fini( 182 __in efx_nic_t *enp); 183 184 /* NIC */ 185 186 extern __checkReturn efx_rc_t 187 ef10_nic_probe( 188 __in efx_nic_t *enp); 189 190 extern __checkReturn efx_rc_t 191 ef10_nic_set_drv_limits( 192 __inout efx_nic_t *enp, 193 __in efx_drv_limits_t *edlp); 194 195 extern __checkReturn efx_rc_t 196 ef10_nic_get_vi_pool( 197 __in efx_nic_t *enp, 198 __out uint32_t *vi_countp); 199 200 extern __checkReturn efx_rc_t 201 ef10_nic_get_bar_region( 202 __in efx_nic_t *enp, 203 __in efx_nic_region_t region, 204 __out uint32_t *offsetp, 205 __out size_t *sizep); 206 207 extern __checkReturn efx_rc_t 208 ef10_nic_reset( 209 __in efx_nic_t *enp); 210 211 extern __checkReturn efx_rc_t 212 ef10_nic_init( 213 __in efx_nic_t *enp); 214 215 extern __checkReturn boolean_t 216 ef10_nic_hw_unavailable( 217 __in efx_nic_t *enp); 218 219 extern void 220 ef10_nic_set_hw_unavailable( 221 __in efx_nic_t *enp); 222 223 #if EFSYS_OPT_DIAG 224 225 extern __checkReturn efx_rc_t 226 ef10_nic_register_test( 227 __in efx_nic_t *enp); 228 229 #endif /* EFSYS_OPT_DIAG */ 230 231 extern void 232 ef10_nic_fini( 233 __in efx_nic_t *enp); 234 235 extern void 236 ef10_nic_unprobe( 237 __in efx_nic_t *enp); 238 239 /* MAC */ 240 241 extern __checkReturn efx_rc_t 242 ef10_mac_poll( 243 __in efx_nic_t *enp, 244 __out efx_link_mode_t *link_modep); 245 246 extern __checkReturn efx_rc_t 247 ef10_mac_up( 248 __in efx_nic_t *enp, 249 __out boolean_t *mac_upp); 250 251 extern __checkReturn efx_rc_t 252 ef10_mac_addr_set( 253 __in efx_nic_t *enp); 254 255 extern __checkReturn efx_rc_t 256 ef10_mac_pdu_set( 257 __in efx_nic_t *enp); 258 259 extern __checkReturn efx_rc_t 260 ef10_mac_pdu_get( 261 __in efx_nic_t *enp, 262 __out size_t *pdu); 263 264 extern __checkReturn efx_rc_t 265 ef10_mac_reconfigure( 266 __in efx_nic_t *enp); 267 268 extern __checkReturn efx_rc_t 269 ef10_mac_multicast_list_set( 270 __in efx_nic_t *enp); 271 272 extern __checkReturn efx_rc_t 273 ef10_mac_filter_default_rxq_set( 274 __in efx_nic_t *enp, 275 __in efx_rxq_t *erp, 276 __in boolean_t using_rss); 277 278 extern void 279 ef10_mac_filter_default_rxq_clear( 280 __in efx_nic_t *enp); 281 282 #if EFSYS_OPT_LOOPBACK 283 284 extern __checkReturn efx_rc_t 285 ef10_mac_loopback_set( 286 __in efx_nic_t *enp, 287 __in efx_link_mode_t link_mode, 288 __in efx_loopback_type_t loopback_type); 289 290 #endif /* EFSYS_OPT_LOOPBACK */ 291 292 #if EFSYS_OPT_MAC_STATS 293 294 extern __checkReturn efx_rc_t 295 ef10_mac_stats_get_mask( 296 __in efx_nic_t *enp, 297 __inout_bcount(mask_size) uint32_t *maskp, 298 __in size_t mask_size); 299 300 extern __checkReturn efx_rc_t 301 ef10_mac_stats_update( 302 __in efx_nic_t *enp, 303 __in efsys_mem_t *esmp, 304 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 305 __inout_opt uint32_t *generationp); 306 307 #endif /* EFSYS_OPT_MAC_STATS */ 308 309 /* MCDI */ 310 311 #if EFSYS_OPT_MCDI 312 313 extern __checkReturn efx_rc_t 314 ef10_mcdi_init( 315 __in efx_nic_t *enp, 316 __in const efx_mcdi_transport_t *mtp); 317 318 extern void 319 ef10_mcdi_fini( 320 __in efx_nic_t *enp); 321 322 extern void 323 ef10_mcdi_send_request( 324 __in efx_nic_t *enp, 325 __in_bcount(hdr_len) void *hdrp, 326 __in size_t hdr_len, 327 __in_bcount(sdu_len) void *sdup, 328 __in size_t sdu_len); 329 330 extern __checkReturn boolean_t 331 ef10_mcdi_poll_response( 332 __in efx_nic_t *enp); 333 334 extern void 335 ef10_mcdi_read_response( 336 __in efx_nic_t *enp, 337 __out_bcount(length) void *bufferp, 338 __in size_t offset, 339 __in size_t length); 340 341 extern efx_rc_t 342 ef10_mcdi_poll_reboot( 343 __in efx_nic_t *enp); 344 345 extern __checkReturn efx_rc_t 346 ef10_mcdi_feature_supported( 347 __in efx_nic_t *enp, 348 __in efx_mcdi_feature_id_t id, 349 __out boolean_t *supportedp); 350 351 extern void 352 ef10_mcdi_get_timeout( 353 __in efx_nic_t *enp, 354 __in efx_mcdi_req_t *emrp, 355 __out uint32_t *timeoutp); 356 357 #endif /* EFSYS_OPT_MCDI */ 358 359 /* NVRAM */ 360 361 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 362 363 extern __checkReturn efx_rc_t 364 ef10_nvram_buf_read_tlv( 365 __in efx_nic_t *enp, 366 __in_bcount(max_seg_size) caddr_t seg_data, 367 __in size_t max_seg_size, 368 __in uint32_t tag, 369 __deref_out_bcount_opt(*sizep) caddr_t *datap, 370 __out size_t *sizep); 371 372 extern __checkReturn efx_rc_t 373 ef10_nvram_buf_write_tlv( 374 __inout_bcount(partn_size) caddr_t partn_data, 375 __in size_t partn_size, 376 __in uint32_t tag, 377 __in_bcount(tag_size) caddr_t tag_data, 378 __in size_t tag_size, 379 __out size_t *total_lengthp); 380 381 extern __checkReturn efx_rc_t 382 ef10_nvram_partn_read_tlv( 383 __in efx_nic_t *enp, 384 __in uint32_t partn, 385 __in uint32_t tag, 386 __deref_out_bcount_opt(*sizep) caddr_t *datap, 387 __out size_t *sizep); 388 389 extern __checkReturn efx_rc_t 390 ef10_nvram_partn_write_tlv( 391 __in efx_nic_t *enp, 392 __in uint32_t partn, 393 __in uint32_t tag, 394 __in_bcount(size) caddr_t data, 395 __in size_t size); 396 397 extern __checkReturn efx_rc_t 398 ef10_nvram_partn_write_segment_tlv( 399 __in efx_nic_t *enp, 400 __in uint32_t partn, 401 __in uint32_t tag, 402 __in_bcount(size) caddr_t data, 403 __in size_t size, 404 __in boolean_t all_segments); 405 406 extern __checkReturn efx_rc_t 407 ef10_nvram_partn_lock( 408 __in efx_nic_t *enp, 409 __in uint32_t partn); 410 411 extern __checkReturn efx_rc_t 412 ef10_nvram_partn_unlock( 413 __in efx_nic_t *enp, 414 __in uint32_t partn, 415 __out_opt uint32_t *resultp); 416 417 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 418 419 #if EFSYS_OPT_NVRAM 420 421 #if EFSYS_OPT_DIAG 422 423 extern __checkReturn efx_rc_t 424 ef10_nvram_test( 425 __in efx_nic_t *enp); 426 427 #endif /* EFSYS_OPT_DIAG */ 428 429 extern __checkReturn efx_rc_t 430 ef10_nvram_type_to_partn( 431 __in efx_nic_t *enp, 432 __in efx_nvram_type_t type, 433 __out uint32_t *partnp); 434 435 extern __checkReturn efx_rc_t 436 ef10_nvram_partn_size( 437 __in efx_nic_t *enp, 438 __in uint32_t partn, 439 __out size_t *sizep); 440 441 extern __checkReturn efx_rc_t 442 ef10_nvram_partn_rw_start( 443 __in efx_nic_t *enp, 444 __in uint32_t partn, 445 __out size_t *chunk_sizep); 446 447 extern __checkReturn efx_rc_t 448 ef10_nvram_partn_read_mode( 449 __in efx_nic_t *enp, 450 __in uint32_t partn, 451 __in unsigned int offset, 452 __out_bcount(size) caddr_t data, 453 __in size_t size, 454 __in uint32_t mode); 455 456 extern __checkReturn efx_rc_t 457 ef10_nvram_partn_read( 458 __in efx_nic_t *enp, 459 __in uint32_t partn, 460 __in unsigned int offset, 461 __in_bcount(size) caddr_t data, 462 __in size_t size); 463 464 extern __checkReturn efx_rc_t 465 ef10_nvram_partn_read_backup( 466 __in efx_nic_t *enp, 467 __in uint32_t partn, 468 __in unsigned int offset, 469 __out_bcount(size) caddr_t data, 470 __in size_t size); 471 472 extern __checkReturn efx_rc_t 473 ef10_nvram_partn_erase( 474 __in efx_nic_t *enp, 475 __in uint32_t partn, 476 __in unsigned int offset, 477 __in size_t size); 478 479 extern __checkReturn efx_rc_t 480 ef10_nvram_partn_write( 481 __in efx_nic_t *enp, 482 __in uint32_t partn, 483 __in unsigned int offset, 484 __out_bcount(size) caddr_t data, 485 __in size_t size); 486 487 extern __checkReturn efx_rc_t 488 ef10_nvram_partn_rw_finish( 489 __in efx_nic_t *enp, 490 __in uint32_t partn, 491 __out_opt uint32_t *verify_resultp); 492 493 extern __checkReturn efx_rc_t 494 ef10_nvram_partn_get_version( 495 __in efx_nic_t *enp, 496 __in uint32_t partn, 497 __out uint32_t *subtypep, 498 __out_ecount(4) uint16_t version[4]); 499 500 extern __checkReturn efx_rc_t 501 ef10_nvram_partn_set_version( 502 __in efx_nic_t *enp, 503 __in uint32_t partn, 504 __in_ecount(4) uint16_t version[4]); 505 506 extern __checkReturn efx_rc_t 507 ef10_nvram_buffer_validate( 508 __in uint32_t partn, 509 __in_bcount(buffer_size) 510 caddr_t bufferp, 511 __in size_t buffer_size); 512 513 extern void 514 ef10_nvram_buffer_init( 515 __out_bcount(buffer_size) 516 caddr_t bufferp, 517 __in size_t buffer_size); 518 519 extern __checkReturn efx_rc_t 520 ef10_nvram_buffer_create( 521 __in uint32_t partn_type, 522 __out_bcount(buffer_size) 523 caddr_t bufferp, 524 __in size_t buffer_size); 525 526 extern __checkReturn efx_rc_t 527 ef10_nvram_buffer_find_item_start( 528 __in_bcount(buffer_size) 529 caddr_t bufferp, 530 __in size_t buffer_size, 531 __out uint32_t *startp); 532 533 extern __checkReturn efx_rc_t 534 ef10_nvram_buffer_find_end( 535 __in_bcount(buffer_size) 536 caddr_t bufferp, 537 __in size_t buffer_size, 538 __in uint32_t offset, 539 __out uint32_t *endp); 540 541 extern __checkReturn __success(return != B_FALSE) boolean_t 542 ef10_nvram_buffer_find_item( 543 __in_bcount(buffer_size) 544 caddr_t bufferp, 545 __in size_t buffer_size, 546 __in uint32_t offset, 547 __out uint32_t *startp, 548 __out uint32_t *lengthp); 549 550 extern __checkReturn efx_rc_t 551 ef10_nvram_buffer_peek_item( 552 __in_bcount(buffer_size) 553 caddr_t bufferp, 554 __in size_t buffer_size, 555 __in uint32_t offset, 556 __out uint32_t *tagp, 557 __out uint32_t *lengthp, 558 __out uint32_t *value_offsetp); 559 560 extern __checkReturn efx_rc_t 561 ef10_nvram_buffer_get_item( 562 __in_bcount(buffer_size) 563 caddr_t bufferp, 564 __in size_t buffer_size, 565 __in uint32_t offset, 566 __in uint32_t length, 567 __out uint32_t *tagp, 568 __out_bcount_part(value_max_size, *lengthp) 569 caddr_t valuep, 570 __in size_t value_max_size, 571 __out uint32_t *lengthp); 572 573 extern __checkReturn efx_rc_t 574 ef10_nvram_buffer_insert_item( 575 __in_bcount(buffer_size) 576 caddr_t bufferp, 577 __in size_t buffer_size, 578 __in uint32_t offset, 579 __in uint32_t tag, 580 __in_bcount(length) caddr_t valuep, 581 __in uint32_t length, 582 __out uint32_t *lengthp); 583 584 extern __checkReturn efx_rc_t 585 ef10_nvram_buffer_modify_item( 586 __in_bcount(buffer_size) 587 caddr_t bufferp, 588 __in size_t buffer_size, 589 __in uint32_t offset, 590 __in uint32_t tag, 591 __in_bcount(length) caddr_t valuep, 592 __in uint32_t length, 593 __out uint32_t *lengthp); 594 595 extern __checkReturn efx_rc_t 596 ef10_nvram_buffer_delete_item( 597 __in_bcount(buffer_size) 598 caddr_t bufferp, 599 __in size_t buffer_size, 600 __in uint32_t offset, 601 __in uint32_t length, 602 __in uint32_t end); 603 604 extern __checkReturn efx_rc_t 605 ef10_nvram_buffer_finish( 606 __in_bcount(buffer_size) 607 caddr_t bufferp, 608 __in size_t buffer_size); 609 610 #endif /* EFSYS_OPT_NVRAM */ 611 612 /* PHY */ 613 614 typedef struct ef10_link_state_s { 615 efx_phy_link_state_t epls; 616 #if EFSYS_OPT_LOOPBACK 617 efx_loopback_type_t els_loopback; 618 #endif 619 boolean_t els_mac_up; 620 } ef10_link_state_t; 621 622 extern void 623 ef10_phy_link_ev( 624 __in efx_nic_t *enp, 625 __in efx_qword_t *eqp, 626 __out efx_link_mode_t *link_modep); 627 628 extern __checkReturn efx_rc_t 629 ef10_phy_get_link( 630 __in efx_nic_t *enp, 631 __out ef10_link_state_t *elsp); 632 633 extern __checkReturn efx_rc_t 634 ef10_phy_power( 635 __in efx_nic_t *enp, 636 __in boolean_t on); 637 638 extern __checkReturn efx_rc_t 639 ef10_phy_reconfigure( 640 __in efx_nic_t *enp); 641 642 extern __checkReturn efx_rc_t 643 ef10_phy_verify( 644 __in efx_nic_t *enp); 645 646 extern __checkReturn efx_rc_t 647 ef10_phy_oui_get( 648 __in efx_nic_t *enp, 649 __out uint32_t *ouip); 650 651 extern __checkReturn efx_rc_t 652 ef10_phy_link_state_get( 653 __in efx_nic_t *enp, 654 __out efx_phy_link_state_t *eplsp); 655 656 #if EFSYS_OPT_PHY_STATS 657 658 extern __checkReturn efx_rc_t 659 ef10_phy_stats_update( 660 __in efx_nic_t *enp, 661 __in efsys_mem_t *esmp, 662 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 663 664 #endif /* EFSYS_OPT_PHY_STATS */ 665 666 #if EFSYS_OPT_BIST 667 668 extern __checkReturn efx_rc_t 669 ef10_bist_enable_offline( 670 __in efx_nic_t *enp); 671 672 extern __checkReturn efx_rc_t 673 ef10_bist_start( 674 __in efx_nic_t *enp, 675 __in efx_bist_type_t type); 676 677 extern __checkReturn efx_rc_t 678 ef10_bist_poll( 679 __in efx_nic_t *enp, 680 __in efx_bist_type_t type, 681 __out efx_bist_result_t *resultp, 682 __out_opt __drv_when(count > 0, __notnull) 683 uint32_t *value_maskp, 684 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 685 unsigned long *valuesp, 686 __in size_t count); 687 688 extern void 689 ef10_bist_stop( 690 __in efx_nic_t *enp, 691 __in efx_bist_type_t type); 692 693 #endif /* EFSYS_OPT_BIST */ 694 695 /* TX */ 696 697 extern __checkReturn efx_rc_t 698 ef10_tx_init( 699 __in efx_nic_t *enp); 700 701 extern void 702 ef10_tx_fini( 703 __in efx_nic_t *enp); 704 705 extern __checkReturn efx_rc_t 706 ef10_tx_qcreate( 707 __in efx_nic_t *enp, 708 __in unsigned int index, 709 __in unsigned int label, 710 __in efsys_mem_t *esmp, 711 __in size_t ndescs, 712 __in uint32_t id, 713 __in uint16_t flags, 714 __in efx_evq_t *eep, 715 __in efx_txq_t *etp, 716 __out unsigned int *addedp); 717 718 extern void 719 ef10_tx_qdestroy( 720 __in efx_txq_t *etp); 721 722 extern __checkReturn efx_rc_t 723 ef10_tx_qpost( 724 __in efx_txq_t *etp, 725 __in_ecount(ndescs) efx_buffer_t *ebp, 726 __in unsigned int ndescs, 727 __in unsigned int completed, 728 __inout unsigned int *addedp); 729 730 extern void 731 ef10_tx_qpush( 732 __in efx_txq_t *etp, 733 __in unsigned int added, 734 __in unsigned int pushed); 735 736 #if EFSYS_OPT_RX_PACKED_STREAM 737 extern void 738 ef10_rx_qpush_ps_credits( 739 __in efx_rxq_t *erp); 740 741 extern __checkReturn uint8_t * 742 ef10_rx_qps_packet_info( 743 __in efx_rxq_t *erp, 744 __in uint8_t *buffer, 745 __in uint32_t buffer_length, 746 __in uint32_t current_offset, 747 __out uint16_t *lengthp, 748 __out uint32_t *next_offsetp, 749 __out uint32_t *timestamp); 750 #endif 751 752 extern __checkReturn efx_rc_t 753 ef10_tx_qpace( 754 __in efx_txq_t *etp, 755 __in unsigned int ns); 756 757 extern __checkReturn efx_rc_t 758 ef10_tx_qflush( 759 __in efx_txq_t *etp); 760 761 extern void 762 ef10_tx_qenable( 763 __in efx_txq_t *etp); 764 765 extern __checkReturn efx_rc_t 766 ef10_tx_qpio_enable( 767 __in efx_txq_t *etp); 768 769 extern void 770 ef10_tx_qpio_disable( 771 __in efx_txq_t *etp); 772 773 extern __checkReturn efx_rc_t 774 ef10_tx_qpio_write( 775 __in efx_txq_t *etp, 776 __in_ecount(buf_length) uint8_t *buffer, 777 __in size_t buf_length, 778 __in size_t pio_buf_offset); 779 780 extern __checkReturn efx_rc_t 781 ef10_tx_qpio_post( 782 __in efx_txq_t *etp, 783 __in size_t pkt_length, 784 __in unsigned int completed, 785 __inout unsigned int *addedp); 786 787 extern __checkReturn efx_rc_t 788 ef10_tx_qdesc_post( 789 __in efx_txq_t *etp, 790 __in_ecount(n) efx_desc_t *ed, 791 __in unsigned int n, 792 __in unsigned int completed, 793 __inout unsigned int *addedp); 794 795 extern void 796 ef10_tx_qdesc_dma_create( 797 __in efx_txq_t *etp, 798 __in efsys_dma_addr_t addr, 799 __in size_t size, 800 __in boolean_t eop, 801 __out efx_desc_t *edp); 802 803 extern void 804 ef10_tx_qdesc_tso_create( 805 __in efx_txq_t *etp, 806 __in uint16_t ipv4_id, 807 __in uint32_t tcp_seq, 808 __in uint8_t tcp_flags, 809 __out efx_desc_t *edp); 810 811 extern void 812 ef10_tx_qdesc_tso2_create( 813 __in efx_txq_t *etp, 814 __in uint16_t ipv4_id, 815 __in uint16_t outer_ipv4_id, 816 __in uint32_t tcp_seq, 817 __in uint16_t tcp_mss, 818 __out_ecount(count) efx_desc_t *edp, 819 __in int count); 820 821 extern void 822 ef10_tx_qdesc_vlantci_create( 823 __in efx_txq_t *etp, 824 __in uint16_t vlan_tci, 825 __out efx_desc_t *edp); 826 827 extern void 828 ef10_tx_qdesc_checksum_create( 829 __in efx_txq_t *etp, 830 __in uint16_t flags, 831 __out efx_desc_t *edp); 832 833 #if EFSYS_OPT_QSTATS 834 835 extern void 836 ef10_tx_qstats_update( 837 __in efx_txq_t *etp, 838 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 839 840 #endif /* EFSYS_OPT_QSTATS */ 841 842 typedef uint32_t efx_piobuf_handle_t; 843 844 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1) 845 846 extern __checkReturn efx_rc_t 847 ef10_nic_pio_alloc( 848 __inout efx_nic_t *enp, 849 __out uint32_t *bufnump, 850 __out efx_piobuf_handle_t *handlep, 851 __out uint32_t *blknump, 852 __out uint32_t *offsetp, 853 __out size_t *sizep); 854 855 extern __checkReturn efx_rc_t 856 ef10_nic_pio_free( 857 __inout efx_nic_t *enp, 858 __in uint32_t bufnum, 859 __in uint32_t blknum); 860 861 extern __checkReturn efx_rc_t 862 ef10_nic_pio_link( 863 __inout efx_nic_t *enp, 864 __in uint32_t vi_index, 865 __in efx_piobuf_handle_t handle); 866 867 extern __checkReturn efx_rc_t 868 ef10_nic_pio_unlink( 869 __inout efx_nic_t *enp, 870 __in uint32_t vi_index); 871 872 /* VPD */ 873 874 #if EFSYS_OPT_VPD 875 876 extern __checkReturn efx_rc_t 877 ef10_vpd_init( 878 __in efx_nic_t *enp); 879 880 extern __checkReturn efx_rc_t 881 ef10_vpd_size( 882 __in efx_nic_t *enp, 883 __out size_t *sizep); 884 885 extern __checkReturn efx_rc_t 886 ef10_vpd_read( 887 __in efx_nic_t *enp, 888 __out_bcount(size) caddr_t data, 889 __in size_t size); 890 891 extern __checkReturn efx_rc_t 892 ef10_vpd_verify( 893 __in efx_nic_t *enp, 894 __in_bcount(size) caddr_t data, 895 __in size_t size); 896 897 extern __checkReturn efx_rc_t 898 ef10_vpd_reinit( 899 __in efx_nic_t *enp, 900 __in_bcount(size) caddr_t data, 901 __in size_t size); 902 903 extern __checkReturn efx_rc_t 904 ef10_vpd_get( 905 __in efx_nic_t *enp, 906 __in_bcount(size) caddr_t data, 907 __in size_t size, 908 __inout efx_vpd_value_t *evvp); 909 910 extern __checkReturn efx_rc_t 911 ef10_vpd_set( 912 __in efx_nic_t *enp, 913 __in_bcount(size) caddr_t data, 914 __in size_t size, 915 __in efx_vpd_value_t *evvp); 916 917 extern __checkReturn efx_rc_t 918 ef10_vpd_next( 919 __in efx_nic_t *enp, 920 __in_bcount(size) caddr_t data, 921 __in size_t size, 922 __out efx_vpd_value_t *evvp, 923 __inout unsigned int *contp); 924 925 extern __checkReturn efx_rc_t 926 ef10_vpd_write( 927 __in efx_nic_t *enp, 928 __in_bcount(size) caddr_t data, 929 __in size_t size); 930 931 extern void 932 ef10_vpd_fini( 933 __in efx_nic_t *enp); 934 935 #endif /* EFSYS_OPT_VPD */ 936 937 /* RX */ 938 939 extern __checkReturn efx_rc_t 940 ef10_rx_init( 941 __in efx_nic_t *enp); 942 943 #if EFSYS_OPT_RX_SCATTER 944 extern __checkReturn efx_rc_t 945 ef10_rx_scatter_enable( 946 __in efx_nic_t *enp, 947 __in unsigned int buf_size); 948 #endif /* EFSYS_OPT_RX_SCATTER */ 949 950 #if EFSYS_OPT_RX_SCALE 951 952 extern __checkReturn efx_rc_t 953 ef10_rx_scale_context_alloc( 954 __in efx_nic_t *enp, 955 __in efx_rx_scale_context_type_t type, 956 __in uint32_t num_queues, 957 __out uint32_t *rss_contextp); 958 959 extern __checkReturn efx_rc_t 960 ef10_rx_scale_context_free( 961 __in efx_nic_t *enp, 962 __in uint32_t rss_context); 963 964 extern __checkReturn efx_rc_t 965 ef10_rx_scale_mode_set( 966 __in efx_nic_t *enp, 967 __in uint32_t rss_context, 968 __in efx_rx_hash_alg_t alg, 969 __in efx_rx_hash_type_t type, 970 __in boolean_t insert); 971 972 extern __checkReturn efx_rc_t 973 ef10_rx_scale_key_set( 974 __in efx_nic_t *enp, 975 __in uint32_t rss_context, 976 __in_ecount(n) uint8_t *key, 977 __in size_t n); 978 979 extern __checkReturn efx_rc_t 980 ef10_rx_scale_tbl_set( 981 __in efx_nic_t *enp, 982 __in uint32_t rss_context, 983 __in_ecount(n) unsigned int *table, 984 __in size_t n); 985 986 extern __checkReturn uint32_t 987 ef10_rx_prefix_hash( 988 __in efx_nic_t *enp, 989 __in efx_rx_hash_alg_t func, 990 __in uint8_t *buffer); 991 992 #endif /* EFSYS_OPT_RX_SCALE */ 993 994 extern __checkReturn efx_rc_t 995 ef10_rx_prefix_pktlen( 996 __in efx_nic_t *enp, 997 __in uint8_t *buffer, 998 __out uint16_t *lengthp); 999 1000 extern void 1001 ef10_rx_qpost( 1002 __in efx_rxq_t *erp, 1003 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 1004 __in size_t size, 1005 __in unsigned int ndescs, 1006 __in unsigned int completed, 1007 __in unsigned int added); 1008 1009 extern void 1010 ef10_rx_qpush( 1011 __in efx_rxq_t *erp, 1012 __in unsigned int added, 1013 __inout unsigned int *pushedp); 1014 1015 extern __checkReturn efx_rc_t 1016 ef10_rx_qflush( 1017 __in efx_rxq_t *erp); 1018 1019 extern void 1020 ef10_rx_qenable( 1021 __in efx_rxq_t *erp); 1022 1023 union efx_rxq_type_data_u; 1024 1025 extern __checkReturn efx_rc_t 1026 ef10_rx_qcreate( 1027 __in efx_nic_t *enp, 1028 __in unsigned int index, 1029 __in unsigned int label, 1030 __in efx_rxq_type_t type, 1031 __in_opt const union efx_rxq_type_data_u *type_data, 1032 __in efsys_mem_t *esmp, 1033 __in size_t ndescs, 1034 __in uint32_t id, 1035 __in unsigned int flags, 1036 __in efx_evq_t *eep, 1037 __in efx_rxq_t *erp); 1038 1039 extern void 1040 ef10_rx_qdestroy( 1041 __in efx_rxq_t *erp); 1042 1043 extern void 1044 ef10_rx_fini( 1045 __in efx_nic_t *enp); 1046 1047 #if EFSYS_OPT_FILTER 1048 1049 typedef struct ef10_filter_handle_s { 1050 uint32_t efh_lo; 1051 uint32_t efh_hi; 1052 } ef10_filter_handle_t; 1053 1054 typedef struct ef10_filter_entry_s { 1055 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 1056 ef10_filter_handle_t efe_handle; 1057 } ef10_filter_entry_t; 1058 1059 /* 1060 * BUSY flag indicates that an update is in progress. 1061 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 1062 */ 1063 #define EFX_EF10_FILTER_FLAG_BUSY 1U 1064 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 1065 #define EFX_EF10_FILTER_FLAGS 3U 1066 1067 /* 1068 * Size of the hash table used by the driver. Doesn't need to be the 1069 * same size as the hardware's table. 1070 */ 1071 #define EFX_EF10_FILTER_TBL_ROWS 8192 1072 1073 /* Only need to allow for one directed and one unknown unicast filter */ 1074 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 1075 1076 /* Allow for the broadcast address to be added to the multicast list */ 1077 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 1078 1079 /* 1080 * For encapsulated packets, there is one filter each for each combination of 1081 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or 1082 * multicast inner frames. 1083 */ 1084 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12 1085 1086 typedef struct ef10_filter_table_s { 1087 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 1088 efx_rxq_t *eft_default_rxq; 1089 boolean_t eft_using_rss; 1090 uint32_t eft_unicst_filter_indexes[ 1091 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 1092 uint32_t eft_unicst_filter_count; 1093 uint32_t eft_mulcst_filter_indexes[ 1094 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 1095 uint32_t eft_mulcst_filter_count; 1096 boolean_t eft_using_all_mulcst; 1097 uint32_t eft_encap_filter_indexes[ 1098 EFX_EF10_FILTER_ENCAP_FILTERS_MAX]; 1099 uint32_t eft_encap_filter_count; 1100 } ef10_filter_table_t; 1101 1102 __checkReturn efx_rc_t 1103 ef10_filter_init( 1104 __in efx_nic_t *enp); 1105 1106 void 1107 ef10_filter_fini( 1108 __in efx_nic_t *enp); 1109 1110 __checkReturn efx_rc_t 1111 ef10_filter_restore( 1112 __in efx_nic_t *enp); 1113 1114 __checkReturn efx_rc_t 1115 ef10_filter_add( 1116 __in efx_nic_t *enp, 1117 __inout efx_filter_spec_t *spec, 1118 __in boolean_t may_replace); 1119 1120 __checkReturn efx_rc_t 1121 ef10_filter_delete( 1122 __in efx_nic_t *enp, 1123 __inout efx_filter_spec_t *spec); 1124 1125 extern __checkReturn efx_rc_t 1126 ef10_filter_supported_filters( 1127 __in efx_nic_t *enp, 1128 __out_ecount(buffer_length) uint32_t *buffer, 1129 __in size_t buffer_length, 1130 __out size_t *list_lengthp); 1131 1132 extern __checkReturn efx_rc_t 1133 ef10_filter_reconfigure( 1134 __in efx_nic_t *enp, 1135 __in_ecount(6) uint8_t const *mac_addr, 1136 __in boolean_t all_unicst, 1137 __in boolean_t mulcst, 1138 __in boolean_t all_mulcst, 1139 __in boolean_t brdcst, 1140 __in_ecount(6*count) uint8_t const *addrs, 1141 __in uint32_t count); 1142 1143 extern void 1144 ef10_filter_get_default_rxq( 1145 __in efx_nic_t *enp, 1146 __out efx_rxq_t **erpp, 1147 __out boolean_t *using_rss); 1148 1149 extern void 1150 ef10_filter_default_rxq_set( 1151 __in efx_nic_t *enp, 1152 __in efx_rxq_t *erp, 1153 __in boolean_t using_rss); 1154 1155 extern void 1156 ef10_filter_default_rxq_clear( 1157 __in efx_nic_t *enp); 1158 1159 #endif /* EFSYS_OPT_FILTER */ 1160 1161 extern __checkReturn efx_rc_t 1162 efx_mcdi_get_function_info( 1163 __in efx_nic_t *enp, 1164 __out uint32_t *pfp, 1165 __out_opt uint32_t *vfp); 1166 1167 extern __checkReturn efx_rc_t 1168 efx_mcdi_privilege_mask( 1169 __in efx_nic_t *enp, 1170 __in uint32_t pf, 1171 __in uint32_t vf, 1172 __out uint32_t *maskp); 1173 1174 extern __checkReturn efx_rc_t 1175 efx_mcdi_get_port_assignment( 1176 __in efx_nic_t *enp, 1177 __out uint32_t *portp); 1178 1179 extern __checkReturn efx_rc_t 1180 efx_mcdi_get_port_modes( 1181 __in efx_nic_t *enp, 1182 __out uint32_t *modesp, 1183 __out_opt uint32_t *current_modep, 1184 __out_opt uint32_t *default_modep); 1185 1186 extern __checkReturn efx_rc_t 1187 ef10_nic_get_port_mode_bandwidth( 1188 __in efx_nic_t *enp, 1189 __out uint32_t *bandwidth_mbpsp); 1190 1191 extern __checkReturn efx_rc_t 1192 efx_mcdi_get_mac_address_pf( 1193 __in efx_nic_t *enp, 1194 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1195 1196 extern __checkReturn efx_rc_t 1197 efx_mcdi_get_mac_address_vf( 1198 __in efx_nic_t *enp, 1199 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1200 1201 extern __checkReturn efx_rc_t 1202 efx_mcdi_get_clock( 1203 __in efx_nic_t *enp, 1204 __out uint32_t *sys_freqp, 1205 __out uint32_t *dpcpu_freqp); 1206 1207 extern __checkReturn efx_rc_t 1208 efx_mcdi_get_rxdp_config( 1209 __in efx_nic_t *enp, 1210 __out uint32_t *end_paddingp); 1211 1212 extern __checkReturn efx_rc_t 1213 efx_mcdi_get_vector_cfg( 1214 __in efx_nic_t *enp, 1215 __out_opt uint32_t *vec_basep, 1216 __out_opt uint32_t *pf_nvecp, 1217 __out_opt uint32_t *vf_nvecp); 1218 1219 extern __checkReturn efx_rc_t 1220 ef10_get_privilege_mask( 1221 __in efx_nic_t *enp, 1222 __out uint32_t *maskp); 1223 1224 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 1225 1226 extern __checkReturn efx_rc_t 1227 efx_mcdi_get_nic_global( 1228 __in efx_nic_t *enp, 1229 __in uint32_t key, 1230 __out uint32_t *valuep); 1231 1232 extern __checkReturn efx_rc_t 1233 efx_mcdi_set_nic_global( 1234 __in efx_nic_t *enp, 1235 __in uint32_t key, 1236 __in uint32_t value); 1237 1238 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 1239 1240 #if EFSYS_OPT_RX_PACKED_STREAM 1241 1242 /* Data space per credit in packed stream mode */ 1243 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16) 1244 1245 /* 1246 * Received packets are always aligned at this boundary. Also there always 1247 * exists a gap of this size between packets. 1248 * (see SF-112241-TC, 4.5) 1249 */ 1250 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64 1251 1252 /* 1253 * Size of a pseudo-header prepended to received packets 1254 * in packed stream mode 1255 */ 1256 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8 1257 1258 /* Minimum space for packet in packed stream mode */ 1259 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \ 1260 EFX_P2ROUNDUP(size_t, \ 1261 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \ 1262 EFX_MAC_PDU_MIN + \ 1263 EFX_RX_PACKED_STREAM_ALIGNMENT, \ 1264 EFX_RX_PACKED_STREAM_ALIGNMENT) 1265 1266 /* Maximum number of credits */ 1267 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127 1268 1269 #endif /* EFSYS_OPT_RX_PACKED_STREAM */ 1270 1271 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 1272 1273 /* 1274 * Maximum DMA length and buffer stride alignment. 1275 * (see SF-119419-TC, 3.2) 1276 */ 1277 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64 1278 1279 #endif 1280 1281 #ifdef __cplusplus 1282 } 1283 #endif 1284 1285 #endif /* _SYS_EF10_IMPL_H */
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