Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sfxge/common/efx_impl.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_IMPL_H 36 #define _SYS_EFX_IMPL_H 37 38 #include "efx.h" 39 #include "efx_regs.h" 40 #include "efx_regs_ef10.h" 41 42 /* FIXME: Add definition for driver generated software events */ 43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 45 #endif 46 47 #if EFSYS_OPT_SIENA 48 #include "siena_impl.h" 49 #endif /* EFSYS_OPT_SIENA */ 50 51 #if EFSYS_OPT_HUNTINGTON 52 #include "hunt_impl.h" 53 #endif /* EFSYS_OPT_HUNTINGTON */ 54 55 #if EFSYS_OPT_MEDFORD 56 #include "medford_impl.h" 57 #endif /* EFSYS_OPT_MEDFORD */ 58 59 #if EFSYS_OPT_MEDFORD2 60 #include "medford2_impl.h" 61 #endif /* EFSYS_OPT_MEDFORD2 */ 62 63 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 64 #include "ef10_impl.h" 65 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 66 67 #ifdef __cplusplus 68 extern "C" { 69 #endif 70 71 #define EFX_MOD_MCDI 0x00000001 72 #define EFX_MOD_PROBE 0x00000002 73 #define EFX_MOD_NVRAM 0x00000004 74 #define EFX_MOD_VPD 0x00000008 75 #define EFX_MOD_NIC 0x00000010 76 #define EFX_MOD_INTR 0x00000020 77 #define EFX_MOD_EV 0x00000040 78 #define EFX_MOD_RX 0x00000080 79 #define EFX_MOD_TX 0x00000100 80 #define EFX_MOD_PORT 0x00000200 81 #define EFX_MOD_MON 0x00000400 82 #define EFX_MOD_FILTER 0x00001000 83 #define EFX_MOD_LIC 0x00002000 84 #define EFX_MOD_TUNNEL 0x00004000 85 86 #define EFX_RESET_PHY 0x00000001 87 #define EFX_RESET_RXQ_ERR 0x00000002 88 #define EFX_RESET_TXQ_ERR 0x00000004 89 #define EFX_RESET_HW_UNAVAIL 0x00000008 90 91 typedef enum efx_mac_type_e { 92 EFX_MAC_INVALID = 0, 93 EFX_MAC_SIENA, 94 EFX_MAC_HUNTINGTON, 95 EFX_MAC_MEDFORD, 96 EFX_MAC_MEDFORD2, 97 EFX_MAC_NTYPES 98 } efx_mac_type_t; 99 100 typedef struct efx_ev_ops_s { 101 efx_rc_t (*eevo_init)(efx_nic_t *); 102 void (*eevo_fini)(efx_nic_t *); 103 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 104 efsys_mem_t *, size_t, uint32_t, 105 uint32_t, uint32_t, efx_evq_t *); 106 void (*eevo_qdestroy)(efx_evq_t *); 107 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 108 void (*eevo_qpost)(efx_evq_t *, uint16_t); 109 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 110 #if EFSYS_OPT_QSTATS 111 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 112 #endif 113 } efx_ev_ops_t; 114 115 typedef struct efx_tx_ops_s { 116 efx_rc_t (*etxo_init)(efx_nic_t *); 117 void (*etxo_fini)(efx_nic_t *); 118 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 119 unsigned int, unsigned int, 120 efsys_mem_t *, size_t, 121 uint32_t, uint16_t, 122 efx_evq_t *, efx_txq_t *, 123 unsigned int *); 124 void (*etxo_qdestroy)(efx_txq_t *); 125 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 126 unsigned int, unsigned int, 127 unsigned int *); 128 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 129 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 130 efx_rc_t (*etxo_qflush)(efx_txq_t *); 131 void (*etxo_qenable)(efx_txq_t *); 132 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 133 void (*etxo_qpio_disable)(efx_txq_t *); 134 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 135 size_t); 136 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 137 unsigned int *); 138 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 139 unsigned int, unsigned int, 140 unsigned int *); 141 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 142 size_t, boolean_t, 143 efx_desc_t *); 144 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 145 uint32_t, uint8_t, 146 efx_desc_t *); 147 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 148 uint16_t, uint32_t, uint16_t, 149 efx_desc_t *, int); 150 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 151 efx_desc_t *); 152 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 153 efx_desc_t *); 154 #if EFSYS_OPT_QSTATS 155 void (*etxo_qstats_update)(efx_txq_t *, 156 efsys_stat_t *); 157 #endif 158 } efx_tx_ops_t; 159 160 typedef union efx_rxq_type_data_u { 161 /* Dummy member to have non-empty union if no options are enabled */ 162 uint32_t ertd_dummy; 163 #if EFSYS_OPT_RX_PACKED_STREAM 164 struct { 165 uint32_t eps_buf_size; 166 } ertd_packed_stream; 167 #endif 168 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 169 struct { 170 uint32_t eessb_bufs_per_desc; 171 uint32_t eessb_max_dma_len; 172 uint32_t eessb_buf_stride; 173 uint32_t eessb_hol_block_timeout; 174 } ertd_es_super_buffer; 175 #endif 176 } efx_rxq_type_data_t; 177 178 typedef struct efx_rx_ops_s { 179 efx_rc_t (*erxo_init)(efx_nic_t *); 180 void (*erxo_fini)(efx_nic_t *); 181 #if EFSYS_OPT_RX_SCATTER 182 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 183 #endif 184 #if EFSYS_OPT_RX_SCALE 185 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 186 efx_rx_scale_context_type_t, 187 uint32_t, uint32_t *); 188 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 189 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 190 efx_rx_hash_alg_t, 191 efx_rx_hash_type_t, boolean_t); 192 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 193 uint8_t *, size_t); 194 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 195 unsigned int *, size_t); 196 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 197 uint8_t *); 198 #endif /* EFSYS_OPT_RX_SCALE */ 199 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 200 uint16_t *); 201 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 202 unsigned int, unsigned int, 203 unsigned int); 204 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 205 #if EFSYS_OPT_RX_PACKED_STREAM 206 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 207 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 208 uint32_t, uint32_t, 209 uint16_t *, uint32_t *, uint32_t *); 210 #endif 211 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 212 void (*erxo_qenable)(efx_rxq_t *); 213 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 214 unsigned int, efx_rxq_type_t, 215 const efx_rxq_type_data_t *, 216 efsys_mem_t *, size_t, uint32_t, 217 unsigned int, 218 efx_evq_t *, efx_rxq_t *); 219 void (*erxo_qdestroy)(efx_rxq_t *); 220 } efx_rx_ops_t; 221 222 typedef struct efx_mac_ops_s { 223 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 224 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 225 efx_rc_t (*emo_addr_set)(efx_nic_t *); 226 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 227 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 228 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 229 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 230 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 231 efx_rxq_t *, boolean_t); 232 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 233 #if EFSYS_OPT_LOOPBACK 234 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 235 efx_loopback_type_t); 236 #endif /* EFSYS_OPT_LOOPBACK */ 237 #if EFSYS_OPT_MAC_STATS 238 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 239 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 240 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 241 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 242 uint16_t, boolean_t); 243 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 244 efsys_stat_t *, uint32_t *); 245 #endif /* EFSYS_OPT_MAC_STATS */ 246 } efx_mac_ops_t; 247 248 typedef struct efx_phy_ops_s { 249 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 250 efx_rc_t (*epo_reset)(efx_nic_t *); 251 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 252 efx_rc_t (*epo_verify)(efx_nic_t *); 253 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 254 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 255 #if EFSYS_OPT_PHY_STATS 256 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 257 uint32_t *); 258 #endif /* EFSYS_OPT_PHY_STATS */ 259 #if EFSYS_OPT_BIST 260 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 261 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 262 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 263 efx_bist_result_t *, uint32_t *, 264 unsigned long *, size_t); 265 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 266 #endif /* EFSYS_OPT_BIST */ 267 } efx_phy_ops_t; 268 269 #if EFSYS_OPT_FILTER 270 typedef struct efx_filter_ops_s { 271 efx_rc_t (*efo_init)(efx_nic_t *); 272 void (*efo_fini)(efx_nic_t *); 273 efx_rc_t (*efo_restore)(efx_nic_t *); 274 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 275 boolean_t may_replace); 276 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 277 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 278 size_t, size_t *); 279 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 280 boolean_t, boolean_t, boolean_t, 281 uint8_t const *, uint32_t); 282 } efx_filter_ops_t; 283 284 extern __checkReturn efx_rc_t 285 efx_filter_reconfigure( 286 __in efx_nic_t *enp, 287 __in_ecount(6) uint8_t const *mac_addr, 288 __in boolean_t all_unicst, 289 __in boolean_t mulcst, 290 __in boolean_t all_mulcst, 291 __in boolean_t brdcst, 292 __in_ecount(6*count) uint8_t const *addrs, 293 __in uint32_t count); 294 295 #endif /* EFSYS_OPT_FILTER */ 296 297 #if EFSYS_OPT_TUNNEL 298 typedef struct efx_tunnel_ops_s { 299 boolean_t (*eto_udp_encap_supported)(efx_nic_t *); 300 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 301 } efx_tunnel_ops_t; 302 #endif /* EFSYS_OPT_TUNNEL */ 303 304 typedef struct efx_port_s { 305 efx_mac_type_t ep_mac_type; 306 uint32_t ep_phy_type; 307 uint8_t ep_port; 308 uint32_t ep_mac_pdu; 309 uint8_t ep_mac_addr[6]; 310 efx_link_mode_t ep_link_mode; 311 boolean_t ep_all_unicst; 312 boolean_t ep_mulcst; 313 boolean_t ep_all_mulcst; 314 boolean_t ep_brdcst; 315 unsigned int ep_fcntl; 316 boolean_t ep_fcntl_autoneg; 317 efx_oword_t ep_multicst_hash[2]; 318 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 319 EFX_MAC_MULTICAST_LIST_MAX]; 320 uint32_t ep_mulcst_addr_count; 321 #if EFSYS_OPT_LOOPBACK 322 efx_loopback_type_t ep_loopback_type; 323 efx_link_mode_t ep_loopback_link_mode; 324 #endif /* EFSYS_OPT_LOOPBACK */ 325 #if EFSYS_OPT_PHY_FLAGS 326 uint32_t ep_phy_flags; 327 #endif /* EFSYS_OPT_PHY_FLAGS */ 328 #if EFSYS_OPT_PHY_LED_CONTROL 329 efx_phy_led_mode_t ep_phy_led_mode; 330 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 331 efx_phy_media_type_t ep_fixed_port_type; 332 efx_phy_media_type_t ep_module_type; 333 uint32_t ep_adv_cap_mask; 334 uint32_t ep_lp_cap_mask; 335 uint32_t ep_default_adv_cap_mask; 336 uint32_t ep_phy_cap_mask; 337 boolean_t ep_mac_drain; 338 #if EFSYS_OPT_BIST 339 efx_bist_type_t ep_current_bist; 340 #endif 341 const efx_mac_ops_t *ep_emop; 342 const efx_phy_ops_t *ep_epop; 343 } efx_port_t; 344 345 typedef struct efx_mon_ops_s { 346 #if EFSYS_OPT_MON_STATS 347 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 348 efx_mon_stat_value_t *); 349 efx_rc_t (*emo_limits_update)(efx_nic_t *, 350 efx_mon_stat_limits_t *); 351 #endif /* EFSYS_OPT_MON_STATS */ 352 } efx_mon_ops_t; 353 354 typedef struct efx_mon_s { 355 efx_mon_type_t em_type; 356 const efx_mon_ops_t *em_emop; 357 } efx_mon_t; 358 359 typedef struct efx_intr_ops_s { 360 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 361 void (*eio_enable)(efx_nic_t *); 362 void (*eio_disable)(efx_nic_t *); 363 void (*eio_disable_unlocked)(efx_nic_t *); 364 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 365 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 366 void (*eio_status_message)(efx_nic_t *, unsigned int, 367 boolean_t *); 368 void (*eio_fatal)(efx_nic_t *); 369 void (*eio_fini)(efx_nic_t *); 370 } efx_intr_ops_t; 371 372 typedef struct efx_intr_s { 373 const efx_intr_ops_t *ei_eiop; 374 efsys_mem_t *ei_esmp; 375 efx_intr_type_t ei_type; 376 unsigned int ei_level; 377 } efx_intr_t; 378 379 typedef struct efx_nic_ops_s { 380 efx_rc_t (*eno_probe)(efx_nic_t *); 381 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 382 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 383 efx_rc_t (*eno_reset)(efx_nic_t *); 384 efx_rc_t (*eno_init)(efx_nic_t *); 385 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 386 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 387 uint32_t *, size_t *); 388 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 389 void (*eno_set_hw_unavailable)(efx_nic_t *); 390 #if EFSYS_OPT_DIAG 391 efx_rc_t (*eno_register_test)(efx_nic_t *); 392 #endif /* EFSYS_OPT_DIAG */ 393 void (*eno_fini)(efx_nic_t *); 394 void (*eno_unprobe)(efx_nic_t *); 395 } efx_nic_ops_t; 396 397 #ifndef EFX_TXQ_LIMIT_TARGET 398 #define EFX_TXQ_LIMIT_TARGET 259 399 #endif 400 #ifndef EFX_RXQ_LIMIT_TARGET 401 #define EFX_RXQ_LIMIT_TARGET 512 402 #endif 403 404 #if EFSYS_OPT_FILTER 405 406 #if EFSYS_OPT_SIENA 407 408 typedef struct siena_filter_spec_s { 409 uint8_t sfs_type; 410 uint32_t sfs_flags; 411 uint32_t sfs_dmaq_id; 412 uint32_t sfs_dword[3]; 413 } siena_filter_spec_t; 414 415 typedef enum siena_filter_type_e { 416 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 417 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 418 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 419 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 420 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 421 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 422 423 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 424 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 425 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 426 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 427 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 428 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 429 430 EFX_SIENA_FILTER_NTYPES 431 } siena_filter_type_t; 432 433 typedef enum siena_filter_tbl_id_e { 434 EFX_SIENA_FILTER_TBL_RX_IP = 0, 435 EFX_SIENA_FILTER_TBL_RX_MAC, 436 EFX_SIENA_FILTER_TBL_TX_IP, 437 EFX_SIENA_FILTER_TBL_TX_MAC, 438 EFX_SIENA_FILTER_NTBLS 439 } siena_filter_tbl_id_t; 440 441 typedef struct siena_filter_tbl_s { 442 int sft_size; /* number of entries */ 443 int sft_used; /* active count */ 444 uint32_t *sft_bitmap; /* active bitmap */ 445 siena_filter_spec_t *sft_spec; /* array of saved specs */ 446 } siena_filter_tbl_t; 447 448 typedef struct siena_filter_s { 449 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 450 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 451 } siena_filter_t; 452 453 #endif /* EFSYS_OPT_SIENA */ 454 455 typedef struct efx_filter_s { 456 #if EFSYS_OPT_SIENA 457 siena_filter_t *ef_siena_filter; 458 #endif /* EFSYS_OPT_SIENA */ 459 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 460 ef10_filter_table_t *ef_ef10_filter_table; 461 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 462 } efx_filter_t; 463 464 #if EFSYS_OPT_SIENA 465 466 extern void 467 siena_filter_tbl_clear( 468 __in efx_nic_t *enp, 469 __in siena_filter_tbl_id_t tbl); 470 471 #endif /* EFSYS_OPT_SIENA */ 472 473 #endif /* EFSYS_OPT_FILTER */ 474 475 #if EFSYS_OPT_MCDI 476 477 #define EFX_TUNNEL_MAXNENTRIES (16) 478 479 #if EFSYS_OPT_TUNNEL 480 481 typedef struct efx_tunnel_udp_entry_s { 482 uint16_t etue_port; /* host/cpu-endian */ 483 uint16_t etue_protocol; 484 } efx_tunnel_udp_entry_t; 485 486 typedef struct efx_tunnel_cfg_s { 487 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 488 unsigned int etc_udp_entries_num; 489 } efx_tunnel_cfg_t; 490 491 #endif /* EFSYS_OPT_TUNNEL */ 492 493 typedef struct efx_mcdi_ops_s { 494 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 495 void (*emco_send_request)(efx_nic_t *, void *, size_t, 496 void *, size_t); 497 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 498 boolean_t (*emco_poll_response)(efx_nic_t *); 499 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 500 void (*emco_fini)(efx_nic_t *); 501 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 502 efx_mcdi_feature_id_t, boolean_t *); 503 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 504 uint32_t *); 505 } efx_mcdi_ops_t; 506 507 typedef struct efx_mcdi_s { 508 const efx_mcdi_ops_t *em_emcop; 509 const efx_mcdi_transport_t *em_emtp; 510 efx_mcdi_iface_t em_emip; 511 } efx_mcdi_t; 512 513 #endif /* EFSYS_OPT_MCDI */ 514 515 #if EFSYS_OPT_NVRAM 516 517 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 518 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 519 520 typedef struct efx_nvram_ops_s { 521 #if EFSYS_OPT_DIAG 522 efx_rc_t (*envo_test)(efx_nic_t *); 523 #endif /* EFSYS_OPT_DIAG */ 524 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 525 uint32_t *); 526 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 527 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 528 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 529 unsigned int, caddr_t, size_t); 530 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 531 unsigned int, caddr_t, size_t); 532 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 533 unsigned int, size_t); 534 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 535 unsigned int, caddr_t, size_t); 536 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 537 uint32_t *); 538 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 539 uint32_t *, uint16_t *); 540 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 541 uint16_t *); 542 efx_rc_t (*envo_buffer_validate)(uint32_t, 543 caddr_t, size_t); 544 } efx_nvram_ops_t; 545 #endif /* EFSYS_OPT_NVRAM */ 546 547 #if EFSYS_OPT_VPD 548 typedef struct efx_vpd_ops_s { 549 efx_rc_t (*evpdo_init)(efx_nic_t *); 550 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 551 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 552 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 553 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 554 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 555 efx_vpd_value_t *); 556 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 557 efx_vpd_value_t *); 558 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 559 efx_vpd_value_t *, unsigned int *); 560 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 561 void (*evpdo_fini)(efx_nic_t *); 562 } efx_vpd_ops_t; 563 #endif /* EFSYS_OPT_VPD */ 564 565 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 566 567 __checkReturn efx_rc_t 568 efx_mcdi_nvram_partitions( 569 __in efx_nic_t *enp, 570 __out_bcount(size) caddr_t data, 571 __in size_t size, 572 __out unsigned int *npartnp); 573 574 __checkReturn efx_rc_t 575 efx_mcdi_nvram_metadata( 576 __in efx_nic_t *enp, 577 __in uint32_t partn, 578 __out uint32_t *subtypep, 579 __out_ecount(4) uint16_t version[4], 580 __out_bcount_opt(size) char *descp, 581 __in size_t size); 582 583 __checkReturn efx_rc_t 584 efx_mcdi_nvram_info( 585 __in efx_nic_t *enp, 586 __in uint32_t partn, 587 __out_opt size_t *sizep, 588 __out_opt uint32_t *addressp, 589 __out_opt uint32_t *erase_sizep, 590 __out_opt uint32_t *write_sizep); 591 592 __checkReturn efx_rc_t 593 efx_mcdi_nvram_update_start( 594 __in efx_nic_t *enp, 595 __in uint32_t partn); 596 597 __checkReturn efx_rc_t 598 efx_mcdi_nvram_read( 599 __in efx_nic_t *enp, 600 __in uint32_t partn, 601 __in uint32_t offset, 602 __out_bcount(size) caddr_t data, 603 __in size_t size, 604 __in uint32_t mode); 605 606 __checkReturn efx_rc_t 607 efx_mcdi_nvram_erase( 608 __in efx_nic_t *enp, 609 __in uint32_t partn, 610 __in uint32_t offset, 611 __in size_t size); 612 613 __checkReturn efx_rc_t 614 efx_mcdi_nvram_write( 615 __in efx_nic_t *enp, 616 __in uint32_t partn, 617 __in uint32_t offset, 618 __in_bcount(size) caddr_t data, 619 __in size_t size); 620 621 __checkReturn efx_rc_t 622 efx_mcdi_nvram_update_finish( 623 __in efx_nic_t *enp, 624 __in uint32_t partn, 625 __in boolean_t reboot, 626 __out_opt uint32_t *verify_resultp); 627 628 #if EFSYS_OPT_DIAG 629 630 __checkReturn efx_rc_t 631 efx_mcdi_nvram_test( 632 __in efx_nic_t *enp, 633 __in uint32_t partn); 634 635 #endif /* EFSYS_OPT_DIAG */ 636 637 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 638 639 #if EFSYS_OPT_LICENSING 640 641 typedef struct efx_lic_ops_s { 642 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 643 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 644 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 645 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 646 size_t *, uint8_t *); 647 efx_rc_t (*elo_find_start) 648 (efx_nic_t *, caddr_t, size_t, uint32_t *); 649 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 650 uint32_t, uint32_t *); 651 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 652 uint32_t, uint32_t *, uint32_t *); 653 boolean_t (*elo_validate_key)(efx_nic_t *, 654 caddr_t, uint32_t); 655 efx_rc_t (*elo_read_key)(efx_nic_t *, 656 caddr_t, size_t, uint32_t, uint32_t, 657 caddr_t, size_t, uint32_t *); 658 efx_rc_t (*elo_write_key)(efx_nic_t *, 659 caddr_t, size_t, uint32_t, 660 caddr_t, uint32_t, uint32_t *); 661 efx_rc_t (*elo_delete_key)(efx_nic_t *, 662 caddr_t, size_t, uint32_t, 663 uint32_t, uint32_t, uint32_t *); 664 efx_rc_t (*elo_create_partition)(efx_nic_t *, 665 caddr_t, size_t); 666 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 667 caddr_t, size_t); 668 } efx_lic_ops_t; 669 670 #endif 671 672 typedef struct efx_drv_cfg_s { 673 uint32_t edc_min_vi_count; 674 uint32_t edc_max_vi_count; 675 676 uint32_t edc_max_piobuf_count; 677 uint32_t edc_pio_alloc_size; 678 } efx_drv_cfg_t; 679 680 struct efx_nic_s { 681 uint32_t en_magic; 682 efx_family_t en_family; 683 uint32_t en_features; 684 efsys_identifier_t *en_esip; 685 efsys_lock_t *en_eslp; 686 efsys_bar_t *en_esbp; 687 unsigned int en_mod_flags; 688 unsigned int en_reset_flags; 689 efx_nic_cfg_t en_nic_cfg; 690 efx_drv_cfg_t en_drv_cfg; 691 efx_port_t en_port; 692 efx_mon_t en_mon; 693 efx_intr_t en_intr; 694 uint32_t en_ev_qcount; 695 uint32_t en_rx_qcount; 696 uint32_t en_tx_qcount; 697 const efx_nic_ops_t *en_enop; 698 const efx_ev_ops_t *en_eevop; 699 const efx_tx_ops_t *en_etxop; 700 const efx_rx_ops_t *en_erxop; 701 efx_fw_variant_t efv; 702 #if EFSYS_OPT_FILTER 703 efx_filter_t en_filter; 704 const efx_filter_ops_t *en_efop; 705 #endif /* EFSYS_OPT_FILTER */ 706 #if EFSYS_OPT_TUNNEL 707 efx_tunnel_cfg_t en_tunnel_cfg; 708 const efx_tunnel_ops_t *en_etop; 709 #endif /* EFSYS_OPT_TUNNEL */ 710 #if EFSYS_OPT_MCDI 711 efx_mcdi_t en_mcdi; 712 #endif /* EFSYS_OPT_MCDI */ 713 #if EFSYS_OPT_NVRAM 714 uint32_t en_nvram_partn_locked; 715 const efx_nvram_ops_t *en_envop; 716 #endif /* EFSYS_OPT_NVRAM */ 717 #if EFSYS_OPT_VPD 718 const efx_vpd_ops_t *en_evpdop; 719 #endif /* EFSYS_OPT_VPD */ 720 #if EFSYS_OPT_RX_SCALE 721 efx_rx_hash_support_t en_hash_support; 722 efx_rx_scale_context_type_t en_rss_context_type; 723 uint32_t en_rss_context; 724 #endif /* EFSYS_OPT_RX_SCALE */ 725 uint32_t en_vport_id; 726 #if EFSYS_OPT_LICENSING 727 const efx_lic_ops_t *en_elop; 728 boolean_t en_licensing_supported; 729 #endif 730 union { 731 #if EFSYS_OPT_SIENA 732 struct { 733 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 734 unsigned int enu_partn_mask; 735 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 736 #if EFSYS_OPT_VPD 737 caddr_t enu_svpd; 738 size_t enu_svpd_length; 739 #endif /* EFSYS_OPT_VPD */ 740 int enu_unused; 741 } siena; 742 #endif /* EFSYS_OPT_SIENA */ 743 int enu_unused; 744 } en_u; 745 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 746 union en_arch { 747 struct { 748 int ena_vi_base; 749 int ena_vi_count; 750 int ena_vi_shift; 751 #if EFSYS_OPT_VPD 752 caddr_t ena_svpd; 753 size_t ena_svpd_length; 754 #endif /* EFSYS_OPT_VPD */ 755 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 756 uint32_t ena_piobuf_count; 757 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 758 uint32_t ena_pio_write_vi_base; 759 /* Memory BAR mapping regions */ 760 uint32_t ena_uc_mem_map_offset; 761 size_t ena_uc_mem_map_size; 762 uint32_t ena_wc_mem_map_offset; 763 size_t ena_wc_mem_map_size; 764 } ef10; 765 } en_arch; 766 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 767 }; 768 769 #define EFX_NIC_MAGIC 0x02121996 770 771 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 772 const efx_ev_callbacks_t *, void *); 773 774 typedef struct efx_evq_rxq_state_s { 775 unsigned int eers_rx_read_ptr; 776 unsigned int eers_rx_mask; 777 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 778 unsigned int eers_rx_stream_npackets; 779 boolean_t eers_rx_packed_stream; 780 #endif 781 #if EFSYS_OPT_RX_PACKED_STREAM 782 unsigned int eers_rx_packed_stream_credits; 783 #endif 784 } efx_evq_rxq_state_t; 785 786 struct efx_evq_s { 787 uint32_t ee_magic; 788 efx_nic_t *ee_enp; 789 unsigned int ee_index; 790 unsigned int ee_mask; 791 efsys_mem_t *ee_esmp; 792 #if EFSYS_OPT_QSTATS 793 uint32_t ee_stat[EV_NQSTATS]; 794 #endif /* EFSYS_OPT_QSTATS */ 795 796 efx_ev_handler_t ee_rx; 797 efx_ev_handler_t ee_tx; 798 efx_ev_handler_t ee_driver; 799 efx_ev_handler_t ee_global; 800 efx_ev_handler_t ee_drv_gen; 801 #if EFSYS_OPT_MCDI 802 efx_ev_handler_t ee_mcdi; 803 #endif /* EFSYS_OPT_MCDI */ 804 805 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 806 807 uint32_t ee_flags; 808 }; 809 810 #define EFX_EVQ_MAGIC 0x08081997 811 812 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 813 814 struct efx_rxq_s { 815 uint32_t er_magic; 816 efx_nic_t *er_enp; 817 efx_evq_t *er_eep; 818 unsigned int er_index; 819 unsigned int er_label; 820 unsigned int er_mask; 821 efsys_mem_t *er_esmp; 822 efx_evq_rxq_state_t *er_ev_qstate; 823 }; 824 825 #define EFX_RXQ_MAGIC 0x15022005 826 827 struct efx_txq_s { 828 uint32_t et_magic; 829 efx_nic_t *et_enp; 830 unsigned int et_index; 831 unsigned int et_mask; 832 efsys_mem_t *et_esmp; 833 #if EFSYS_OPT_HUNTINGTON 834 uint32_t et_pio_bufnum; 835 uint32_t et_pio_blknum; 836 uint32_t et_pio_write_offset; 837 uint32_t et_pio_offset; 838 size_t et_pio_size; 839 #endif 840 #if EFSYS_OPT_QSTATS 841 uint32_t et_stat[TX_NQSTATS]; 842 #endif /* EFSYS_OPT_QSTATS */ 843 }; 844 845 #define EFX_TXQ_MAGIC 0x05092005 846 847 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 848 do { \ 849 (_dst)[0] = (_src)[0]; \ 850 (_dst)[1] = (_src)[1]; \ 851 (_dst)[2] = (_src)[2]; \ 852 (_dst)[3] = (_src)[3]; \ 853 (_dst)[4] = (_src)[4]; \ 854 (_dst)[5] = (_src)[5]; \ 855 _NOTE(CONSTANTCONDITION) \ 856 } while (B_FALSE) 857 858 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 859 do { \ 860 uint16_t *_d = (uint16_t *)(_dst); \ 861 _d[0] = 0xffff; \ 862 _d[1] = 0xffff; \ 863 _d[2] = 0xffff; \ 864 _NOTE(CONSTANTCONDITION) \ 865 } while (B_FALSE) 866 867 #if EFSYS_OPT_CHECK_REG 868 #define EFX_CHECK_REG(_enp, _reg) \ 869 do { \ 870 const char *name = #_reg; \ 871 char min = name[4]; \ 872 char max = name[5]; \ 873 char rev; \ 874 \ 875 switch ((_enp)->en_family) { \ 876 case EFX_FAMILY_SIENA: \ 877 rev = 'C'; \ 878 break; \ 879 \ 880 case EFX_FAMILY_HUNTINGTON: \ 881 rev = 'D'; \ 882 break; \ 883 \ 884 case EFX_FAMILY_MEDFORD: \ 885 rev = 'E'; \ 886 break; \ 887 \ 888 case EFX_FAMILY_MEDFORD2: \ 889 rev = 'F'; \ 890 break; \ 891 \ 892 default: \ 893 rev = '?'; \ 894 break; \ 895 } \ 896 \ 897 EFSYS_ASSERT3S(rev, >=, min); \ 898 EFSYS_ASSERT3S(rev, <=, max); \ 899 \ 900 _NOTE(CONSTANTCONDITION) \ 901 } while (B_FALSE) 902 #else 903 #define EFX_CHECK_REG(_enp, _reg) do { \ 904 _NOTE(CONSTANTCONDITION) \ 905 } while (B_FALSE) 906 #endif 907 908 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 909 do { \ 910 EFX_CHECK_REG((_enp), (_reg)); \ 911 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 912 (_edp), (_lock)); \ 913 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 914 uint32_t, _reg ## _OFST, \ 915 uint32_t, (_edp)->ed_u32[0]); \ 916 _NOTE(CONSTANTCONDITION) \ 917 } while (B_FALSE) 918 919 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 920 do { \ 921 EFX_CHECK_REG((_enp), (_reg)); \ 922 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 923 uint32_t, _reg ## _OFST, \ 924 uint32_t, (_edp)->ed_u32[0]); \ 925 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 926 (_edp), (_lock)); \ 927 _NOTE(CONSTANTCONDITION) \ 928 } while (B_FALSE) 929 930 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 931 do { \ 932 EFX_CHECK_REG((_enp), (_reg)); \ 933 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 934 (_eqp)); \ 935 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 936 uint32_t, _reg ## _OFST, \ 937 uint32_t, (_eqp)->eq_u32[1], \ 938 uint32_t, (_eqp)->eq_u32[0]); \ 939 _NOTE(CONSTANTCONDITION) \ 940 } while (B_FALSE) 941 942 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 943 do { \ 944 EFX_CHECK_REG((_enp), (_reg)); \ 945 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 946 uint32_t, _reg ## _OFST, \ 947 uint32_t, (_eqp)->eq_u32[1], \ 948 uint32_t, (_eqp)->eq_u32[0]); \ 949 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 950 (_eqp)); \ 951 _NOTE(CONSTANTCONDITION) \ 952 } while (B_FALSE) 953 954 #define EFX_BAR_READO(_enp, _reg, _eop) \ 955 do { \ 956 EFX_CHECK_REG((_enp), (_reg)); \ 957 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 958 (_eop), B_TRUE); \ 959 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 960 uint32_t, _reg ## _OFST, \ 961 uint32_t, (_eop)->eo_u32[3], \ 962 uint32_t, (_eop)->eo_u32[2], \ 963 uint32_t, (_eop)->eo_u32[1], \ 964 uint32_t, (_eop)->eo_u32[0]); \ 965 _NOTE(CONSTANTCONDITION) \ 966 } while (B_FALSE) 967 968 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 969 do { \ 970 EFX_CHECK_REG((_enp), (_reg)); \ 971 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 972 uint32_t, _reg ## _OFST, \ 973 uint32_t, (_eop)->eo_u32[3], \ 974 uint32_t, (_eop)->eo_u32[2], \ 975 uint32_t, (_eop)->eo_u32[1], \ 976 uint32_t, (_eop)->eo_u32[0]); \ 977 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 978 (_eop), B_TRUE); \ 979 _NOTE(CONSTANTCONDITION) \ 980 } while (B_FALSE) 981 982 /* 983 * Accessors for memory BAR non-VI tables. 984 * 985 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 986 * to ensure the correct runtime VI window size is used on Medford2. 987 * 988 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 989 */ 990 991 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 992 do { \ 993 EFX_CHECK_REG((_enp), (_reg)); \ 994 EFSYS_BAR_READD((_enp)->en_esbp, \ 995 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 996 (_edp), (_lock)); \ 997 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 998 uint32_t, (_index), \ 999 uint32_t, _reg ## _OFST, \ 1000 uint32_t, (_edp)->ed_u32[0]); \ 1001 _NOTE(CONSTANTCONDITION) \ 1002 } while (B_FALSE) 1003 1004 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1005 do { \ 1006 EFX_CHECK_REG((_enp), (_reg)); \ 1007 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1008 uint32_t, (_index), \ 1009 uint32_t, _reg ## _OFST, \ 1010 uint32_t, (_edp)->ed_u32[0]); \ 1011 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1012 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1013 (_edp), (_lock)); \ 1014 _NOTE(CONSTANTCONDITION) \ 1015 } while (B_FALSE) 1016 1017 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1018 do { \ 1019 EFX_CHECK_REG((_enp), (_reg)); \ 1020 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1021 uint32_t, (_index), \ 1022 uint32_t, _reg ## _OFST, \ 1023 uint32_t, (_edp)->ed_u32[0]); \ 1024 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1025 (_reg ## _OFST + \ 1026 (3 * sizeof (efx_dword_t)) + \ 1027 ((_index) * _reg ## _STEP)), \ 1028 (_edp), (_lock)); \ 1029 _NOTE(CONSTANTCONDITION) \ 1030 } while (B_FALSE) 1031 1032 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1033 do { \ 1034 EFX_CHECK_REG((_enp), (_reg)); \ 1035 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1036 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1037 (_eqp)); \ 1038 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1039 uint32_t, (_index), \ 1040 uint32_t, _reg ## _OFST, \ 1041 uint32_t, (_eqp)->eq_u32[1], \ 1042 uint32_t, (_eqp)->eq_u32[0]); \ 1043 _NOTE(CONSTANTCONDITION) \ 1044 } while (B_FALSE) 1045 1046 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1047 do { \ 1048 EFX_CHECK_REG((_enp), (_reg)); \ 1049 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1050 uint32_t, (_index), \ 1051 uint32_t, _reg ## _OFST, \ 1052 uint32_t, (_eqp)->eq_u32[1], \ 1053 uint32_t, (_eqp)->eq_u32[0]); \ 1054 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1055 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1056 (_eqp)); \ 1057 _NOTE(CONSTANTCONDITION) \ 1058 } while (B_FALSE) 1059 1060 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1061 do { \ 1062 EFX_CHECK_REG((_enp), (_reg)); \ 1063 EFSYS_BAR_READO((_enp)->en_esbp, \ 1064 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1065 (_eop), (_lock)); \ 1066 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1067 uint32_t, (_index), \ 1068 uint32_t, _reg ## _OFST, \ 1069 uint32_t, (_eop)->eo_u32[3], \ 1070 uint32_t, (_eop)->eo_u32[2], \ 1071 uint32_t, (_eop)->eo_u32[1], \ 1072 uint32_t, (_eop)->eo_u32[0]); \ 1073 _NOTE(CONSTANTCONDITION) \ 1074 } while (B_FALSE) 1075 1076 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1077 do { \ 1078 EFX_CHECK_REG((_enp), (_reg)); \ 1079 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1080 uint32_t, (_index), \ 1081 uint32_t, _reg ## _OFST, \ 1082 uint32_t, (_eop)->eo_u32[3], \ 1083 uint32_t, (_eop)->eo_u32[2], \ 1084 uint32_t, (_eop)->eo_u32[1], \ 1085 uint32_t, (_eop)->eo_u32[0]); \ 1086 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1087 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1088 (_eop), (_lock)); \ 1089 _NOTE(CONSTANTCONDITION) \ 1090 } while (B_FALSE) 1091 1092 /* 1093 * Accessors for memory BAR per-VI registers. 1094 * 1095 * The VI window size is 8KB for Medford and all earlier controllers. 1096 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1097 */ 1098 1099 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1100 do { \ 1101 EFX_CHECK_REG((_enp), (_reg)); \ 1102 EFSYS_BAR_READD((_enp)->en_esbp, \ 1103 ((_reg ## _OFST) + \ 1104 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1105 (_edp), (_lock)); \ 1106 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1107 uint32_t, (_index), \ 1108 uint32_t, _reg ## _OFST, \ 1109 uint32_t, (_edp)->ed_u32[0]); \ 1110 _NOTE(CONSTANTCONDITION) \ 1111 } while (B_FALSE) 1112 1113 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1114 do { \ 1115 EFX_CHECK_REG((_enp), (_reg)); \ 1116 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1117 uint32_t, (_index), \ 1118 uint32_t, _reg ## _OFST, \ 1119 uint32_t, (_edp)->ed_u32[0]); \ 1120 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1121 ((_reg ## _OFST) + \ 1122 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1123 (_edp), (_lock)); \ 1124 _NOTE(CONSTANTCONDITION) \ 1125 } while (B_FALSE) 1126 1127 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1128 do { \ 1129 EFX_CHECK_REG((_enp), (_reg)); \ 1130 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1131 uint32_t, (_index), \ 1132 uint32_t, _reg ## _OFST, \ 1133 uint32_t, (_edp)->ed_u32[0]); \ 1134 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1135 ((_reg ## _OFST) + \ 1136 (2 * sizeof (efx_dword_t)) + \ 1137 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1138 (_edp), (_lock)); \ 1139 _NOTE(CONSTANTCONDITION) \ 1140 } while (B_FALSE) 1141 1142 /* 1143 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1144 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1145 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1146 * the need for locking in the host, and are the only ones known to be safe to 1147 * use 128-bites write with. 1148 */ 1149 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1150 do { \ 1151 EFX_CHECK_REG((_enp), (_reg)); \ 1152 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1153 const char *, #_reg, \ 1154 uint32_t, (_index), \ 1155 uint32_t, _reg ## _OFST, \ 1156 uint32_t, (_eop)->eo_u32[3], \ 1157 uint32_t, (_eop)->eo_u32[2], \ 1158 uint32_t, (_eop)->eo_u32[1], \ 1159 uint32_t, (_eop)->eo_u32[0]); \ 1160 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1161 (_reg ## _OFST + \ 1162 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1163 (_eop)); \ 1164 _NOTE(CONSTANTCONDITION) \ 1165 } while (B_FALSE) 1166 1167 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1168 do { \ 1169 unsigned int _new = (_wptr); \ 1170 unsigned int _old = (_owptr); \ 1171 \ 1172 if ((_new) >= (_old)) \ 1173 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1174 (_old) * sizeof (efx_desc_t), \ 1175 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1176 else \ 1177 /* \ 1178 * It is cheaper to sync entire map than sync \ 1179 * two parts especially when offset/size are \ 1180 * ignored and entire map is synced in any case.\ 1181 */ \ 1182 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1183 0, \ 1184 (_entries) * sizeof (efx_desc_t)); \ 1185 _NOTE(CONSTANTCONDITION) \ 1186 } while (B_FALSE) 1187 1188 extern __checkReturn efx_rc_t 1189 efx_mac_select( 1190 __in efx_nic_t *enp); 1191 1192 extern void 1193 efx_mac_multicast_hash_compute( 1194 __in_ecount(6*count) uint8_t const *addrs, 1195 __in int count, 1196 __out efx_oword_t *hash_low, 1197 __out efx_oword_t *hash_high); 1198 1199 extern __checkReturn efx_rc_t 1200 efx_phy_probe( 1201 __in efx_nic_t *enp); 1202 1203 extern void 1204 efx_phy_unprobe( 1205 __in efx_nic_t *enp); 1206 1207 #if EFSYS_OPT_VPD 1208 1209 /* VPD utility functions */ 1210 1211 extern __checkReturn efx_rc_t 1212 efx_vpd_hunk_length( 1213 __in_bcount(size) caddr_t data, 1214 __in size_t size, 1215 __out size_t *lengthp); 1216 1217 extern __checkReturn efx_rc_t 1218 efx_vpd_hunk_verify( 1219 __in_bcount(size) caddr_t data, 1220 __in size_t size, 1221 __out_opt boolean_t *cksummedp); 1222 1223 extern __checkReturn efx_rc_t 1224 efx_vpd_hunk_reinit( 1225 __in_bcount(size) caddr_t data, 1226 __in size_t size, 1227 __in boolean_t wantpid); 1228 1229 extern __checkReturn efx_rc_t 1230 efx_vpd_hunk_get( 1231 __in_bcount(size) caddr_t data, 1232 __in size_t size, 1233 __in efx_vpd_tag_t tag, 1234 __in efx_vpd_keyword_t keyword, 1235 __out unsigned int *payloadp, 1236 __out uint8_t *paylenp); 1237 1238 extern __checkReturn efx_rc_t 1239 efx_vpd_hunk_next( 1240 __in_bcount(size) caddr_t data, 1241 __in size_t size, 1242 __out efx_vpd_tag_t *tagp, 1243 __out efx_vpd_keyword_t *keyword, 1244 __out_opt unsigned int *payloadp, 1245 __out_opt uint8_t *paylenp, 1246 __inout unsigned int *contp); 1247 1248 extern __checkReturn efx_rc_t 1249 efx_vpd_hunk_set( 1250 __in_bcount(size) caddr_t data, 1251 __in size_t size, 1252 __in efx_vpd_value_t *evvp); 1253 1254 #endif /* EFSYS_OPT_VPD */ 1255 1256 #if EFSYS_OPT_MCDI 1257 1258 extern __checkReturn efx_rc_t 1259 efx_mcdi_set_workaround( 1260 __in efx_nic_t *enp, 1261 __in uint32_t type, 1262 __in boolean_t enabled, 1263 __out_opt uint32_t *flagsp); 1264 1265 extern __checkReturn efx_rc_t 1266 efx_mcdi_get_workarounds( 1267 __in efx_nic_t *enp, 1268 __out_opt uint32_t *implementedp, 1269 __out_opt uint32_t *enabledp); 1270 1271 #endif /* EFSYS_OPT_MCDI */ 1272 1273 #if EFSYS_OPT_MAC_STATS 1274 1275 /* 1276 * Closed range of stats (i.e. the first and the last are included). 1277 * The last must be greater or equal (if the range is one item only) to 1278 * the first. 1279 */ 1280 struct efx_mac_stats_range { 1281 efx_mac_stat_t first; 1282 efx_mac_stat_t last; 1283 }; 1284 1285 extern efx_rc_t 1286 efx_mac_stats_mask_add_ranges( 1287 __inout_bcount(mask_size) uint32_t *maskp, 1288 __in size_t mask_size, 1289 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1290 __in unsigned int rng_count); 1291 1292 #endif /* EFSYS_OPT_MAC_STATS */ 1293 1294 #ifdef __cplusplus 1295 } 1296 #endif 1297 1298 #endif /* _SYS_EFX_IMPL_H */
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