Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/sfxge/common/siena_mac.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "efx.h" 37 #include "efx_impl.h" 38 39 #if EFSYS_OPT_SIENA 40 41 __checkReturn efx_rc_t 42 siena_mac_poll( 43 __in efx_nic_t *enp, 44 __out efx_link_mode_t *link_modep) 45 { 46 efx_port_t *epp = &(enp->en_port); 47 siena_link_state_t sls; 48 efx_rc_t rc; 49 50 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 51 goto fail1; 52 53 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; 54 epp->ep_fcntl = sls.sls_fcntl; 55 56 *link_modep = sls.sls_link_mode; 57 58 return (0); 59 60 fail1: 61 EFSYS_PROBE1(fail1, efx_rc_t, rc); 62 63 *link_modep = EFX_LINK_UNKNOWN; 64 65 return (rc); 66 } 67 68 __checkReturn efx_rc_t 69 siena_mac_up( 70 __in efx_nic_t *enp, 71 __out boolean_t *mac_upp) 72 { 73 siena_link_state_t sls; 74 efx_rc_t rc; 75 76 /* 77 * Because Siena doesn't *require* polling, we can't rely on 78 * siena_mac_poll() being executed to populate epp->ep_mac_up. 79 */ 80 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 81 goto fail1; 82 83 *mac_upp = sls.sls_mac_up; 84 85 return (0); 86 87 fail1: 88 EFSYS_PROBE1(fail1, efx_rc_t, rc); 89 90 return (rc); 91 } 92 93 __checkReturn efx_rc_t 94 siena_mac_reconfigure( 95 __in efx_nic_t *enp) 96 { 97 efx_port_t *epp = &(enp->en_port); 98 efx_oword_t multicast_hash[2]; 99 efx_mcdi_req_t req; 100 EFX_MCDI_DECLARE_BUF(payload, 101 MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MCAST_HASH_IN_LEN), 102 MAX(MC_CMD_SET_MAC_OUT_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN)); 103 104 unsigned int fcntl; 105 efx_rc_t rc; 106 107 req.emr_cmd = MC_CMD_SET_MAC; 108 req.emr_in_buf = payload; 109 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; 110 req.emr_out_buf = payload; 111 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; 112 113 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); 114 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); 115 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), 116 epp->ep_mac_addr); 117 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, 118 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, 119 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); 120 121 if (epp->ep_fcntl_autoneg) 122 /* efx_fcntl_set() has already set the phy capabilities */ 123 fcntl = MC_CMD_FCNTL_AUTO; 124 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) 125 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) 126 ? MC_CMD_FCNTL_BIDIR 127 : MC_CMD_FCNTL_RESPOND; 128 else 129 fcntl = MC_CMD_FCNTL_OFF; 130 131 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); 132 133 efx_mcdi_execute(enp, &req); 134 135 if (req.emr_rc != 0) { 136 rc = req.emr_rc; 137 goto fail1; 138 } 139 140 /* Push multicast hash */ 141 142 if (epp->ep_all_mulcst) { 143 /* A hash matching all multicast is all 1s */ 144 EFX_SET_OWORD(multicast_hash[0]); 145 EFX_SET_OWORD(multicast_hash[1]); 146 } else if (epp->ep_mulcst) { 147 /* Use the hash set by the multicast list */ 148 multicast_hash[0] = epp->ep_multicst_hash[0]; 149 multicast_hash[1] = epp->ep_multicst_hash[1]; 150 } else { 151 /* A hash matching no traffic is simply 0 */ 152 EFX_ZERO_OWORD(multicast_hash[0]); 153 EFX_ZERO_OWORD(multicast_hash[1]); 154 } 155 156 /* 157 * Broadcast packets go through the multicast hash filter. 158 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff 159 * so we always add bit 0xff to the mask (bit 0x7f in the 160 * second octword). 161 */ 162 if (epp->ep_brdcst) { 163 /* 164 * NOTE: due to constant folding, some of this evaluates 165 * to null expressions, giving E_EXPR_NULL_EFFECT during 166 * lint on Illumos. No good way to fix this without 167 * explicit coding the individual word/bit setting. 168 * So just suppress lint for this one line. 169 */ 170 /* LINTED */ 171 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); 172 } 173 174 (void) memset(payload, 0, sizeof (payload)); 175 req.emr_cmd = MC_CMD_SET_MCAST_HASH; 176 req.emr_in_buf = payload; 177 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; 178 req.emr_out_buf = payload; 179 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; 180 181 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), 182 multicast_hash, sizeof (multicast_hash)); 183 184 efx_mcdi_execute(enp, &req); 185 186 if (req.emr_rc != 0) { 187 rc = req.emr_rc; 188 goto fail2; 189 } 190 191 return (0); 192 193 fail2: 194 EFSYS_PROBE(fail2); 195 fail1: 196 EFSYS_PROBE1(fail1, efx_rc_t, rc); 197 198 return (rc); 199 } 200 201 #if EFSYS_OPT_LOOPBACK 202 203 __checkReturn efx_rc_t 204 siena_mac_loopback_set( 205 __in efx_nic_t *enp, 206 __in efx_link_mode_t link_mode, 207 __in efx_loopback_type_t loopback_type) 208 { 209 efx_port_t *epp = &(enp->en_port); 210 const efx_phy_ops_t *epop = epp->ep_epop; 211 efx_loopback_type_t old_loopback_type; 212 efx_link_mode_t old_loopback_link_mode; 213 efx_rc_t rc; 214 215 /* The PHY object handles this on Siena */ 216 old_loopback_type = epp->ep_loopback_type; 217 old_loopback_link_mode = epp->ep_loopback_link_mode; 218 epp->ep_loopback_type = loopback_type; 219 epp->ep_loopback_link_mode = link_mode; 220 221 if ((rc = epop->epo_reconfigure(enp)) != 0) 222 goto fail1; 223 224 return (0); 225 226 fail1: 227 EFSYS_PROBE1(fail1, efx_rc_t, rc); 228 229 epp->ep_loopback_type = old_loopback_type; 230 epp->ep_loopback_link_mode = old_loopback_link_mode; 231 232 return (rc); 233 } 234 235 #endif /* EFSYS_OPT_LOOPBACK */ 236 237 #if EFSYS_OPT_MAC_STATS 238 239 __checkReturn efx_rc_t 240 siena_mac_stats_get_mask( 241 __in efx_nic_t *enp, 242 __inout_bcount(mask_size) uint32_t *maskp, 243 __in size_t mask_size) 244 { 245 const struct efx_mac_stats_range siena_stats[] = { 246 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS }, 247 /* EFX_MAC_RX_ERRORS is not supported */ 248 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS }, 249 }; 250 efx_rc_t rc; 251 252 _NOTE(ARGUNUSED(enp)) 253 254 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size, 255 siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0) 256 goto fail1; 257 258 return (0); 259 260 fail1: 261 EFSYS_PROBE1(fail1, efx_rc_t, rc); 262 263 return (rc); 264 } 265 266 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ 267 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) 268 269 __checkReturn efx_rc_t 270 siena_mac_stats_update( 271 __in efx_nic_t *enp, 272 __in efsys_mem_t *esmp, 273 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 274 __inout_opt uint32_t *generationp) 275 { 276 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; 277 efx_qword_t generation_start; 278 efx_qword_t generation_end; 279 efx_qword_t value; 280 efx_rc_t rc; 281 282 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { 283 /* MAC stats count too small */ 284 rc = ENOSPC; 285 goto fail1; 286 } 287 if (EFSYS_MEM_SIZE(esmp) < 288 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) { 289 /* DMA buffer too small */ 290 rc = ENOSPC; 291 goto fail2; 292 } 293 294 /* Read END first so we don't race with the MC */ 295 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 296 SIENA_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1), 297 &generation_end); 298 EFSYS_MEM_READ_BARRIER(); 299 300 /* TX */ 301 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); 302 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 303 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); 304 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 305 306 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); 307 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); 308 309 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); 310 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); 311 312 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); 313 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); 314 315 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); 316 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); 317 318 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); 319 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); 320 321 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); 322 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 323 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); 324 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 325 326 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); 327 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); 328 329 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); 330 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); 331 332 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); 333 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); 334 335 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); 336 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); 337 338 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); 339 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); 340 341 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); 342 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 343 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); 344 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 345 346 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); 347 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); 348 349 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); 350 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); 351 352 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, 353 &value); 354 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); 355 356 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, 357 &value); 358 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); 359 360 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); 361 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); 362 363 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); 364 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); 365 366 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, 367 &value); 368 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); 369 370 /* RX */ 371 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); 372 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); 373 374 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); 375 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); 376 377 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); 378 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); 379 380 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); 381 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); 382 383 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); 384 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); 385 386 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); 387 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); 388 389 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); 390 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 391 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); 392 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 393 394 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); 395 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); 396 397 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); 398 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); 399 400 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); 401 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); 402 403 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); 404 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); 405 406 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); 407 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); 408 409 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); 410 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 411 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); 412 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 413 414 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); 415 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); 416 417 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); 418 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); 419 420 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); 421 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); 422 423 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); 424 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); 425 426 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); 427 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); 428 429 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); 430 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); 431 432 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); 433 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); 434 435 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); 436 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), 437 &(value.eq_dword[0])); 438 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), 439 &(value.eq_dword[1])); 440 441 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); 442 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), 443 &(value.eq_dword[0])); 444 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), 445 &(value.eq_dword[1])); 446 447 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); 448 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), 449 &(value.eq_dword[0])); 450 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), 451 &(value.eq_dword[1])); 452 453 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); 454 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), 455 &(value.eq_dword[0])); 456 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), 457 &(value.eq_dword[1])); 458 459 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); 460 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); 461 462 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); 463 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); 464 465 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp)); 466 EFSYS_MEM_READ_BARRIER(); 467 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, 468 &generation_start); 469 470 /* Check that we didn't read the stats in the middle of a DMA */ 471 /* Not a good enough check ? */ 472 if (memcmp(&generation_start, &generation_end, 473 sizeof (generation_start))) 474 return (EAGAIN); 475 476 if (generationp) 477 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); 478 479 return (0); 480 481 fail2: 482 EFSYS_PROBE(fail2); 483 fail1: 484 EFSYS_PROBE1(fail1, efx_rc_t, rc); 485 486 return (rc); 487 } 488 489 #endif /* EFSYS_OPT_MAC_STATS */ 490 491 __checkReturn efx_rc_t 492 siena_mac_pdu_get( 493 __in efx_nic_t *enp, 494 __out size_t *pdu) 495 { 496 return (ENOTSUP); 497 } 498 499 #endif /* EFSYS_OPT_SIENA */
Cache object: 79d39e91bd9ea5400dc4c32379654a3b
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