FreeBSD/Linux Kernel Cross Reference
sys/dev/sge/if_sge.c
1 /*-
2 * Copyright (c) 2008-2010 Nikolay Denev <ndenev@gmail.com>
3 * Copyright (c) 2007-2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
26 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD: releng/8.1/sys/dev/sge/if_sge.c 208923 2010-06-08 19:26:22Z yongari $");
38
39 /*
40 * SiS 190/191 PCI Ethernet NIC driver.
41 *
42 * Adapted to SiS 190 NIC by Alexander Pohoyda based on the original
43 * SiS 900 driver by Bill Paul, using SiS 190/191 Solaris driver by
44 * Masayuki Murayama and SiS 190/191 GNU/Linux driver by K.M. Liu
45 * <kmliu@sis.com>. Thanks to Pyun YongHyeon <pyunyh@gmail.com> for
46 * review and very useful comments.
47 *
48 * Adapted to SiS 191 NIC by Nikolay Denev with further ideas from the
49 * Linux and Solaris drivers.
50 */
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/bus.h>
55 #include <sys/endian.h>
56 #include <sys/kernel.h>
57 #include <sys/lock.h>
58 #include <sys/malloc.h>
59 #include <sys/mbuf.h>
60 #include <sys/module.h>
61 #include <sys/mutex.h>
62 #include <sys/rman.h>
63 #include <sys/socket.h>
64 #include <sys/sockio.h>
65
66 #include <net/bpf.h>
67 #include <net/if.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_dl.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
73 #include <net/if_vlan_var.h>
74
75 #include <netinet/in.h>
76 #include <netinet/in_systm.h>
77 #include <netinet/ip.h>
78 #include <netinet/tcp.h>
79
80 #include <machine/bus.h>
81 #include <machine/in_cksum.h>
82
83 #include <dev/mii/mii.h>
84 #include <dev/mii/miivar.h>
85
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88
89 #include <dev/sge/if_sgereg.h>
90
91 MODULE_DEPEND(sge, pci, 1, 1, 1);
92 MODULE_DEPEND(sge, ether, 1, 1, 1);
93 MODULE_DEPEND(sge, miibus, 1, 1, 1);
94
95 /* "device miibus0" required. See GENERIC if you get errors here. */
96 #include "miibus_if.h"
97
98 /*
99 * Various supported device vendors/types and their names.
100 */
101 static struct sge_type sge_devs[] = {
102 { SIS_VENDORID, SIS_DEVICEID_190, "SiS190 Fast Ethernet" },
103 { SIS_VENDORID, SIS_DEVICEID_191, "SiS191 Fast/Gigabit Ethernet" },
104 { 0, 0, NULL }
105 };
106
107 static int sge_probe(device_t);
108 static int sge_attach(device_t);
109 static int sge_detach(device_t);
110 static int sge_shutdown(device_t);
111 static int sge_suspend(device_t);
112 static int sge_resume(device_t);
113
114 static int sge_miibus_readreg(device_t, int, int);
115 static int sge_miibus_writereg(device_t, int, int, int);
116 static void sge_miibus_statchg(device_t);
117
118 static int sge_newbuf(struct sge_softc *, int);
119 static int sge_encap(struct sge_softc *, struct mbuf **);
120 static __inline void
121 sge_discard_rxbuf(struct sge_softc *, int);
122 static void sge_rxeof(struct sge_softc *);
123 static void sge_txeof(struct sge_softc *);
124 static void sge_intr(void *);
125 static void sge_tick(void *);
126 static void sge_start(struct ifnet *);
127 static void sge_start_locked(struct ifnet *);
128 static int sge_ioctl(struct ifnet *, u_long, caddr_t);
129 static void sge_init(void *);
130 static void sge_init_locked(struct sge_softc *);
131 static void sge_stop(struct sge_softc *);
132 static void sge_watchdog(struct sge_softc *);
133 static int sge_ifmedia_upd(struct ifnet *);
134 static void sge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135
136 static int sge_get_mac_addr_apc(struct sge_softc *, uint8_t *);
137 static int sge_get_mac_addr_eeprom(struct sge_softc *, uint8_t *);
138 static uint16_t sge_read_eeprom(struct sge_softc *, int);
139
140 static void sge_rxfilter(struct sge_softc *);
141 static void sge_setvlan(struct sge_softc *);
142 static void sge_reset(struct sge_softc *);
143 static int sge_list_rx_init(struct sge_softc *);
144 static int sge_list_rx_free(struct sge_softc *);
145 static int sge_list_tx_init(struct sge_softc *);
146 static int sge_list_tx_free(struct sge_softc *);
147
148 static int sge_dma_alloc(struct sge_softc *);
149 static void sge_dma_free(struct sge_softc *);
150 static void sge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
151
152 static device_method_t sge_methods[] = {
153 /* Device interface */
154 DEVMETHOD(device_probe, sge_probe),
155 DEVMETHOD(device_attach, sge_attach),
156 DEVMETHOD(device_detach, sge_detach),
157 DEVMETHOD(device_suspend, sge_suspend),
158 DEVMETHOD(device_resume, sge_resume),
159 DEVMETHOD(device_shutdown, sge_shutdown),
160
161 /* Bus interface */
162 DEVMETHOD(bus_print_child, bus_generic_print_child),
163 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
164
165 /* MII interface */
166 DEVMETHOD(miibus_readreg, sge_miibus_readreg),
167 DEVMETHOD(miibus_writereg, sge_miibus_writereg),
168 DEVMETHOD(miibus_statchg, sge_miibus_statchg),
169
170 KOBJMETHOD_END
171 };
172
173 static driver_t sge_driver = {
174 "sge", sge_methods, sizeof(struct sge_softc)
175 };
176
177 static devclass_t sge_devclass;
178
179 DRIVER_MODULE(sge, pci, sge_driver, sge_devclass, 0, 0);
180 DRIVER_MODULE(miibus, sge, miibus_driver, miibus_devclass, 0, 0);
181
182 /*
183 * Register space access macros.
184 */
185 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)
186 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
187 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)
188
189 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)
190 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)
191 #define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg)
192
193 /* Define to show Tx/Rx error status. */
194 #undef SGE_SHOW_ERRORS
195
196 #define SGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
197
198 static void
199 sge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
200 {
201 bus_addr_t *p;
202
203 if (error != 0)
204 return;
205 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
206 p = arg;
207 *p = segs->ds_addr;
208 }
209
210 /*
211 * Read a sequence of words from the EEPROM.
212 */
213 static uint16_t
214 sge_read_eeprom(struct sge_softc *sc, int offset)
215 {
216 uint32_t val;
217 int i;
218
219 KASSERT(offset <= EI_OFFSET, ("EEPROM offset too big"));
220 CSR_WRITE_4(sc, ROMInterface,
221 EI_REQ | EI_OP_RD | (offset << EI_OFFSET_SHIFT));
222 DELAY(500);
223 for (i = 0; i < SGE_TIMEOUT; i++) {
224 val = CSR_READ_4(sc, ROMInterface);
225 if ((val & EI_REQ) == 0)
226 break;
227 DELAY(100);
228 }
229 if (i == SGE_TIMEOUT) {
230 device_printf(sc->sge_dev,
231 "EEPROM read timeout : 0x%08x\n", val);
232 return (0xffff);
233 }
234
235 return ((val & EI_DATA) >> EI_DATA_SHIFT);
236 }
237
238 static int
239 sge_get_mac_addr_eeprom(struct sge_softc *sc, uint8_t *dest)
240 {
241 uint16_t val;
242 int i;
243
244 val = sge_read_eeprom(sc, EEPROMSignature);
245 if (val == 0xffff || val == 0) {
246 device_printf(sc->sge_dev,
247 "invalid EEPROM signature : 0x%04x\n", val);
248 return (EINVAL);
249 }
250
251 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
252 val = sge_read_eeprom(sc, EEPROMMACAddr + i / 2);
253 dest[i + 0] = (uint8_t)val;
254 dest[i + 1] = (uint8_t)(val >> 8);
255 }
256
257 if ((sge_read_eeprom(sc, EEPROMInfo) & 0x80) != 0)
258 sc->sge_flags |= SGE_FLAG_RGMII;
259 return (0);
260 }
261
262 /*
263 * For SiS96x, APC CMOS RAM is used to store ethernet address.
264 * APC CMOS RAM is accessed through ISA bridge.
265 */
266 static int
267 sge_get_mac_addr_apc(struct sge_softc *sc, uint8_t *dest)
268 {
269 #if defined(__amd64__) || defined(__i386__)
270 devclass_t pci;
271 device_t bus, dev = NULL;
272 device_t *kids;
273 struct apc_tbl {
274 uint16_t vid;
275 uint16_t did;
276 } *tp, apc_tbls[] = {
277 { SIS_VENDORID, 0x0965 },
278 { SIS_VENDORID, 0x0966 },
279 { SIS_VENDORID, 0x0968 }
280 };
281 uint8_t reg;
282 int busnum, cnt, i, j, numkids;
283
284 cnt = sizeof(apc_tbls) / sizeof(apc_tbls[0]);
285 pci = devclass_find("pci");
286 for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) {
287 bus = devclass_get_device(pci, busnum);
288 if (!bus)
289 continue;
290 if (device_get_children(bus, &kids, &numkids) != 0)
291 continue;
292 for (i = 0; i < numkids; i++) {
293 dev = kids[i];
294 if (pci_get_class(dev) == PCIC_BRIDGE &&
295 pci_get_subclass(dev) == PCIS_BRIDGE_ISA) {
296 tp = apc_tbls;
297 for (j = 0; j < cnt; j++) {
298 if (pci_get_vendor(dev) == tp->vid &&
299 pci_get_device(dev) == tp->did) {
300 free(kids, M_TEMP);
301 goto apc_found;
302 }
303 tp++;
304 }
305 }
306 }
307 free(kids, M_TEMP);
308 }
309 device_printf(sc->sge_dev, "couldn't find PCI-ISA bridge\n");
310 return (EINVAL);
311 apc_found:
312 /* Enable port 0x78 and 0x79 to access APC registers. */
313 reg = pci_read_config(dev, 0x48, 1);
314 pci_write_config(dev, 0x48, reg & ~0x02, 1);
315 DELAY(50);
316 pci_read_config(dev, 0x48, 1);
317 /* Read stored ethernet address. */
318 for (i = 0; i < ETHER_ADDR_LEN; i++) {
319 outb(0x78, 0x09 + i);
320 dest[i] = inb(0x79);
321 }
322 outb(0x78, 0x12);
323 if ((inb(0x79) & 0x80) != 0)
324 sc->sge_flags |= SGE_FLAG_RGMII;
325 /* Restore access to APC registers. */
326 pci_write_config(dev, 0x48, reg, 1);
327
328 return (0);
329 #else
330 return (EINVAL);
331 #endif
332 }
333
334 static int
335 sge_miibus_readreg(device_t dev, int phy, int reg)
336 {
337 struct sge_softc *sc;
338 uint32_t val;
339 int i;
340
341 sc = device_get_softc(dev);
342 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
343 (reg << GMI_REG_SHIFT) | GMI_OP_RD | GMI_REQ);
344 DELAY(10);
345 for (i = 0; i < SGE_TIMEOUT; i++) {
346 val = CSR_READ_4(sc, GMIIControl);
347 if ((val & GMI_REQ) == 0)
348 break;
349 DELAY(10);
350 }
351 if (i == SGE_TIMEOUT) {
352 device_printf(sc->sge_dev, "PHY read timeout : %d\n", reg);
353 return (0);
354 }
355 return ((val & GMI_DATA) >> GMI_DATA_SHIFT);
356 }
357
358 static int
359 sge_miibus_writereg(device_t dev, int phy, int reg, int data)
360 {
361 struct sge_softc *sc;
362 uint32_t val;
363 int i;
364
365 sc = device_get_softc(dev);
366 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
367 (reg << GMI_REG_SHIFT) | (data << GMI_DATA_SHIFT) |
368 GMI_OP_WR | GMI_REQ);
369 DELAY(10);
370 for (i = 0; i < SGE_TIMEOUT; i++) {
371 val = CSR_READ_4(sc, GMIIControl);
372 if ((val & GMI_REQ) == 0)
373 break;
374 DELAY(10);
375 }
376 if (i == SGE_TIMEOUT)
377 device_printf(sc->sge_dev, "PHY write timeout : %d\n", reg);
378 return (0);
379 }
380
381 static void
382 sge_miibus_statchg(device_t dev)
383 {
384 struct sge_softc *sc;
385 struct mii_data *mii;
386 struct ifnet *ifp;
387 uint32_t ctl, speed;
388
389 sc = device_get_softc(dev);
390 mii = device_get_softc(sc->sge_miibus);
391 ifp = sc->sge_ifp;
392 if (mii == NULL || ifp == NULL ||
393 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
394 return;
395 speed = 0;
396 sc->sge_flags &= ~SGE_FLAG_LINK;
397 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
398 (IFM_ACTIVE | IFM_AVALID)) {
399 switch (IFM_SUBTYPE(mii->mii_media_active)) {
400 case IFM_10_T:
401 sc->sge_flags |= SGE_FLAG_LINK;
402 speed = SC_SPEED_10;
403 break;
404 case IFM_100_TX:
405 sc->sge_flags |= SGE_FLAG_LINK;
406 speed = SC_SPEED_100;
407 break;
408 case IFM_1000_T:
409 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) {
410 sc->sge_flags |= SGE_FLAG_LINK;
411 speed = SC_SPEED_1000;
412 }
413 break;
414 default:
415 break;
416 }
417 }
418 if ((sc->sge_flags & SGE_FLAG_LINK) == 0)
419 return;
420 /* Reprogram MAC to resolved speed/duplex/flow-control parameters. */
421 ctl = CSR_READ_4(sc, StationControl);
422 ctl &= ~(0x0f000000 | SC_FDX | SC_SPEED_MASK);
423 if (speed == SC_SPEED_1000) {
424 ctl |= 0x07000000;
425 sc->sge_flags |= SGE_FLAG_SPEED_1000;
426 } else {
427 ctl |= 0x04000000;
428 sc->sge_flags &= ~SGE_FLAG_SPEED_1000;
429 }
430 #ifdef notyet
431 if ((sc->sge_flags & SGE_FLAG_GMII) != 0)
432 ctl |= 0x03000000;
433 #endif
434 ctl |= speed;
435 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
436 ctl |= SC_FDX;
437 sc->sge_flags |= SGE_FLAG_FDX;
438 } else
439 sc->sge_flags &= ~SGE_FLAG_FDX;
440 CSR_WRITE_4(sc, StationControl, ctl);
441 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) {
442 CSR_WRITE_4(sc, RGMIIDelay, 0x0441);
443 CSR_WRITE_4(sc, RGMIIDelay, 0x0440);
444 }
445 }
446
447 static void
448 sge_rxfilter(struct sge_softc *sc)
449 {
450 struct ifnet *ifp;
451 struct ifmultiaddr *ifma;
452 uint32_t crc, hashes[2];
453 uint16_t rxfilt;
454
455 SGE_LOCK_ASSERT(sc);
456
457 ifp = sc->sge_ifp;
458 rxfilt = CSR_READ_2(sc, RxMacControl);
459 rxfilt &= ~(AcceptBroadcast | AcceptAllPhys | AcceptMulticast);
460 rxfilt |= AcceptMyPhys;
461 if ((ifp->if_flags & IFF_BROADCAST) != 0)
462 rxfilt |= AcceptBroadcast;
463 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
464 if ((ifp->if_flags & IFF_PROMISC) != 0)
465 rxfilt |= AcceptAllPhys;
466 rxfilt |= AcceptMulticast;
467 hashes[0] = 0xFFFFFFFF;
468 hashes[1] = 0xFFFFFFFF;
469 } else {
470 rxfilt |= AcceptMulticast;
471 hashes[0] = hashes[1] = 0;
472 /* Now program new ones. */
473 if_maddr_rlock(ifp);
474 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
475 if (ifma->ifma_addr->sa_family != AF_LINK)
476 continue;
477 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
478 ifma->ifma_addr), ETHER_ADDR_LEN);
479 hashes[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
480 }
481 if_maddr_runlock(ifp);
482 }
483 CSR_WRITE_2(sc, RxMacControl, rxfilt | 0x02);
484 CSR_WRITE_4(sc, RxHashTable, hashes[0]);
485 CSR_WRITE_4(sc, RxHashTable2, hashes[1]);
486 }
487
488 static void
489 sge_setvlan(struct sge_softc *sc)
490 {
491 struct ifnet *ifp;
492 uint16_t rxfilt;
493
494 SGE_LOCK_ASSERT(sc);
495
496 ifp = sc->sge_ifp;
497 if ((ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) == 0)
498 return;
499 rxfilt = CSR_READ_2(sc, RxMacControl);
500 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
501 rxfilt |= RXMAC_STRIP_VLAN;
502 else
503 rxfilt &= ~RXMAC_STRIP_VLAN;
504 CSR_WRITE_2(sc, RxMacControl, rxfilt);
505 }
506
507 static void
508 sge_reset(struct sge_softc *sc)
509 {
510
511 CSR_WRITE_4(sc, IntrMask, 0);
512 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
513
514 /* Soft reset. */
515 CSR_WRITE_4(sc, IntrControl, 0x8000);
516 CSR_READ_4(sc, IntrControl);
517 DELAY(100);
518 CSR_WRITE_4(sc, IntrControl, 0);
519 /* Stop MAC. */
520 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
521 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
522
523 CSR_WRITE_4(sc, IntrMask, 0);
524 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
525
526 CSR_WRITE_4(sc, GMIIControl, 0);
527 }
528
529 /*
530 * Probe for an SiS chip. Check the PCI vendor and device
531 * IDs against our list and return a device name if we find a match.
532 */
533 static int
534 sge_probe(device_t dev)
535 {
536 struct sge_type *t;
537
538 t = sge_devs;
539 while (t->sge_name != NULL) {
540 if ((pci_get_vendor(dev) == t->sge_vid) &&
541 (pci_get_device(dev) == t->sge_did)) {
542 device_set_desc(dev, t->sge_name);
543 return (BUS_PROBE_DEFAULT);
544 }
545 t++;
546 }
547
548 return (ENXIO);
549 }
550
551 /*
552 * Attach the interface. Allocate softc structures, do ifmedia
553 * setup and ethernet/BPF attach.
554 */
555 static int
556 sge_attach(device_t dev)
557 {
558 struct sge_softc *sc;
559 struct ifnet *ifp;
560 uint8_t eaddr[ETHER_ADDR_LEN];
561 int error = 0, rid;
562
563 sc = device_get_softc(dev);
564 sc->sge_dev = dev;
565
566 mtx_init(&sc->sge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
567 MTX_DEF);
568 callout_init_mtx(&sc->sge_stat_ch, &sc->sge_mtx, 0);
569
570 /*
571 * Map control/status registers.
572 */
573 pci_enable_busmaster(dev);
574
575 /* Allocate resources. */
576 sc->sge_res_id = PCIR_BAR(0);
577 sc->sge_res_type = SYS_RES_MEMORY;
578 sc->sge_res = bus_alloc_resource_any(dev, sc->sge_res_type,
579 &sc->sge_res_id, RF_ACTIVE);
580 if (sc->sge_res == NULL) {
581 device_printf(dev, "couldn't allocate resource\n");
582 error = ENXIO;
583 goto fail;
584 }
585
586 rid = 0;
587 sc->sge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
588 RF_SHAREABLE | RF_ACTIVE);
589 if (sc->sge_irq == NULL) {
590 device_printf(dev, "couldn't allocate IRQ resources\n");
591 error = ENXIO;
592 goto fail;
593 }
594 sc->sge_rev = pci_get_revid(dev);
595 if (pci_get_device(dev) == SIS_DEVICEID_190)
596 sc->sge_flags |= SGE_FLAG_FASTETHER | SGE_FLAG_SIS190;
597 /* Reset the adapter. */
598 sge_reset(sc);
599
600 /* Get MAC address from the EEPROM. */
601 if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0)
602 sge_get_mac_addr_apc(sc, eaddr);
603 else
604 sge_get_mac_addr_eeprom(sc, eaddr);
605
606 if ((error = sge_dma_alloc(sc)) != 0)
607 goto fail;
608
609 ifp = sc->sge_ifp = if_alloc(IFT_ETHER);
610 if (ifp == NULL) {
611 device_printf(dev, "cannot allocate ifnet structure.\n");
612 error = ENOSPC;
613 goto fail;
614 }
615 ifp->if_softc = sc;
616 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
618 ifp->if_ioctl = sge_ioctl;
619 ifp->if_start = sge_start;
620 ifp->if_init = sge_init;
621 ifp->if_snd.ifq_drv_maxlen = SGE_TX_RING_CNT - 1;
622 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
623 IFQ_SET_READY(&ifp->if_snd);
624 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM | IFCAP_TSO4;
625 ifp->if_hwassist = SGE_CSUM_FEATURES | CSUM_TSO;
626 ifp->if_capenable = ifp->if_capabilities;
627 /*
628 * Do MII setup.
629 */
630 if (mii_phy_probe(dev, &sc->sge_miibus, sge_ifmedia_upd,
631 sge_ifmedia_sts)) {
632 device_printf(dev, "no PHY found!\n");
633 error = ENXIO;
634 goto fail;
635 }
636
637 /*
638 * Call MI attach routine.
639 */
640 ether_ifattach(ifp, eaddr);
641
642 /* VLAN setup. */
643 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM |
644 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
645 ifp->if_capenable = ifp->if_capabilities;
646 /* Tell the upper layer(s) we support long frames. */
647 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
648
649 /* Hook interrupt last to avoid having to lock softc */
650 error = bus_setup_intr(dev, sc->sge_irq, INTR_TYPE_NET | INTR_MPSAFE,
651 NULL, sge_intr, sc, &sc->sge_intrhand);
652 if (error) {
653 device_printf(dev, "couldn't set up irq\n");
654 ether_ifdetach(ifp);
655 goto fail;
656 }
657
658 fail:
659 if (error)
660 sge_detach(dev);
661
662 return (error);
663 }
664
665 /*
666 * Shutdown hardware and free up resources. This can be called any
667 * time after the mutex has been initialized. It is called in both
668 * the error case in attach and the normal detach case so it needs
669 * to be careful about only freeing resources that have actually been
670 * allocated.
671 */
672 static int
673 sge_detach(device_t dev)
674 {
675 struct sge_softc *sc;
676 struct ifnet *ifp;
677
678 sc = device_get_softc(dev);
679 ifp = sc->sge_ifp;
680 /* These should only be active if attach succeeded. */
681 if (device_is_attached(dev)) {
682 ether_ifdetach(ifp);
683 SGE_LOCK(sc);
684 sge_stop(sc);
685 SGE_UNLOCK(sc);
686 callout_drain(&sc->sge_stat_ch);
687 }
688 if (sc->sge_miibus)
689 device_delete_child(dev, sc->sge_miibus);
690 bus_generic_detach(dev);
691
692 if (sc->sge_intrhand)
693 bus_teardown_intr(dev, sc->sge_irq, sc->sge_intrhand);
694 if (sc->sge_irq)
695 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sge_irq);
696 if (sc->sge_res)
697 bus_release_resource(dev, sc->sge_res_type, sc->sge_res_id,
698 sc->sge_res);
699 if (ifp)
700 if_free(ifp);
701 sge_dma_free(sc);
702 mtx_destroy(&sc->sge_mtx);
703
704 return (0);
705 }
706
707 /*
708 * Stop all chip I/O so that the kernel's probe routines don't
709 * get confused by errant DMAs when rebooting.
710 */
711 static int
712 sge_shutdown(device_t dev)
713 {
714 struct sge_softc *sc;
715
716 sc = device_get_softc(dev);
717 SGE_LOCK(sc);
718 sge_stop(sc);
719 SGE_UNLOCK(sc);
720 return (0);
721 }
722
723 static int
724 sge_suspend(device_t dev)
725 {
726 struct sge_softc *sc;
727 struct ifnet *ifp;
728
729 sc = device_get_softc(dev);
730 SGE_LOCK(sc);
731 ifp = sc->sge_ifp;
732 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
733 sge_stop(sc);
734 SGE_UNLOCK(sc);
735 return (0);
736 }
737
738 static int
739 sge_resume(device_t dev)
740 {
741 struct sge_softc *sc;
742 struct ifnet *ifp;
743
744 sc = device_get_softc(dev);
745 SGE_LOCK(sc);
746 ifp = sc->sge_ifp;
747 if ((ifp->if_flags & IFF_UP) != 0)
748 sge_init_locked(sc);
749 SGE_UNLOCK(sc);
750 return (0);
751 }
752
753 static int
754 sge_dma_alloc(struct sge_softc *sc)
755 {
756 struct sge_chain_data *cd;
757 struct sge_list_data *ld;
758 struct sge_rxdesc *rxd;
759 struct sge_txdesc *txd;
760 int error, i;
761
762 cd = &sc->sge_cdata;
763 ld = &sc->sge_ldata;
764 error = bus_dma_tag_create(bus_get_dma_tag(sc->sge_dev),
765 1, 0, /* alignment, boundary */
766 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
767 BUS_SPACE_MAXADDR, /* highaddr */
768 NULL, NULL, /* filter, filterarg */
769 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
770 1, /* nsegments */
771 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
772 0, /* flags */
773 NULL, /* lockfunc */
774 NULL, /* lockarg */
775 &cd->sge_tag);
776 if (error != 0) {
777 device_printf(sc->sge_dev,
778 "could not create parent DMA tag.\n");
779 goto fail;
780 }
781
782 /* RX descriptor ring */
783 error = bus_dma_tag_create(cd->sge_tag,
784 SGE_DESC_ALIGN, 0, /* alignment, boundary */
785 BUS_SPACE_MAXADDR, /* lowaddr */
786 BUS_SPACE_MAXADDR, /* highaddr */
787 NULL, NULL, /* filter, filterarg */
788 SGE_RX_RING_SZ, 1, /* maxsize,nsegments */
789 SGE_RX_RING_SZ, /* maxsegsize */
790 0, /* flags */
791 NULL, /* lockfunc */
792 NULL, /* lockarg */
793 &cd->sge_rx_tag);
794 if (error != 0) {
795 device_printf(sc->sge_dev,
796 "could not create Rx ring DMA tag.\n");
797 goto fail;
798 }
799 /* Allocate DMA'able memory and load DMA map for RX ring. */
800 error = bus_dmamem_alloc(cd->sge_rx_tag, (void **)&ld->sge_rx_ring,
801 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
802 &cd->sge_rx_dmamap);
803 if (error != 0) {
804 device_printf(sc->sge_dev,
805 "could not allocate DMA'able memory for Rx ring.\n");
806 goto fail;
807 }
808 error = bus_dmamap_load(cd->sge_rx_tag, cd->sge_rx_dmamap,
809 ld->sge_rx_ring, SGE_RX_RING_SZ, sge_dma_map_addr,
810 &ld->sge_rx_paddr, BUS_DMA_NOWAIT);
811 if (error != 0) {
812 device_printf(sc->sge_dev,
813 "could not load DMA'able memory for Rx ring.\n");
814 }
815
816 /* TX descriptor ring */
817 error = bus_dma_tag_create(cd->sge_tag,
818 SGE_DESC_ALIGN, 0, /* alignment, boundary */
819 BUS_SPACE_MAXADDR, /* lowaddr */
820 BUS_SPACE_MAXADDR, /* highaddr */
821 NULL, NULL, /* filter, filterarg */
822 SGE_TX_RING_SZ, 1, /* maxsize,nsegments */
823 SGE_TX_RING_SZ, /* maxsegsize */
824 0, /* flags */
825 NULL, /* lockfunc */
826 NULL, /* lockarg */
827 &cd->sge_tx_tag);
828 if (error != 0) {
829 device_printf(sc->sge_dev,
830 "could not create Rx ring DMA tag.\n");
831 goto fail;
832 }
833 /* Allocate DMA'able memory and load DMA map for TX ring. */
834 error = bus_dmamem_alloc(cd->sge_tx_tag, (void **)&ld->sge_tx_ring,
835 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
836 &cd->sge_tx_dmamap);
837 if (error != 0) {
838 device_printf(sc->sge_dev,
839 "could not allocate DMA'able memory for Tx ring.\n");
840 goto fail;
841 }
842 error = bus_dmamap_load(cd->sge_tx_tag, cd->sge_tx_dmamap,
843 ld->sge_tx_ring, SGE_TX_RING_SZ, sge_dma_map_addr,
844 &ld->sge_tx_paddr, BUS_DMA_NOWAIT);
845 if (error != 0) {
846 device_printf(sc->sge_dev,
847 "could not load DMA'able memory for Rx ring.\n");
848 goto fail;
849 }
850
851 /* Create DMA tag for Tx buffers. */
852 error = bus_dma_tag_create(cd->sge_tag, 1, 0, BUS_SPACE_MAXADDR,
853 BUS_SPACE_MAXADDR, NULL, NULL, SGE_TSO_MAXSIZE, SGE_MAXTXSEGS,
854 SGE_TSO_MAXSEGSIZE, 0, NULL, NULL, &cd->sge_txmbuf_tag);
855 if (error != 0) {
856 device_printf(sc->sge_dev,
857 "could not create Tx mbuf DMA tag.\n");
858 goto fail;
859 }
860
861 /* Create DMA tag for Rx buffers. */
862 error = bus_dma_tag_create(cd->sge_tag, SGE_RX_BUF_ALIGN, 0,
863 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
864 MCLBYTES, 0, NULL, NULL, &cd->sge_rxmbuf_tag);
865 if (error != 0) {
866 device_printf(sc->sge_dev,
867 "could not create Rx mbuf DMA tag.\n");
868 goto fail;
869 }
870
871 /* Create DMA maps for Tx buffers. */
872 for (i = 0; i < SGE_TX_RING_CNT; i++) {
873 txd = &cd->sge_txdesc[i];
874 txd->tx_m = NULL;
875 txd->tx_dmamap = NULL;
876 txd->tx_ndesc = 0;
877 error = bus_dmamap_create(cd->sge_txmbuf_tag, 0,
878 &txd->tx_dmamap);
879 if (error != 0) {
880 device_printf(sc->sge_dev,
881 "could not create Tx DMA map.\n");
882 goto fail;
883 }
884 }
885 /* Create spare DMA map for Rx buffer. */
886 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, &cd->sge_rx_spare_map);
887 if (error != 0) {
888 device_printf(sc->sge_dev,
889 "could not create spare Rx DMA map.\n");
890 goto fail;
891 }
892 /* Create DMA maps for Rx buffers. */
893 for (i = 0; i < SGE_RX_RING_CNT; i++) {
894 rxd = &cd->sge_rxdesc[i];
895 rxd->rx_m = NULL;
896 rxd->rx_dmamap = NULL;
897 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0,
898 &rxd->rx_dmamap);
899 if (error) {
900 device_printf(sc->sge_dev,
901 "could not create Rx DMA map.\n");
902 goto fail;
903 }
904 }
905 fail:
906 return (error);
907 }
908
909 static void
910 sge_dma_free(struct sge_softc *sc)
911 {
912 struct sge_chain_data *cd;
913 struct sge_list_data *ld;
914 struct sge_rxdesc *rxd;
915 struct sge_txdesc *txd;
916 int i;
917
918 cd = &sc->sge_cdata;
919 ld = &sc->sge_ldata;
920 /* Rx ring. */
921 if (cd->sge_rx_tag != NULL) {
922 if (cd->sge_rx_dmamap != NULL)
923 bus_dmamap_unload(cd->sge_rx_tag, cd->sge_rx_dmamap);
924 if (cd->sge_rx_dmamap != NULL && ld->sge_rx_ring != NULL)
925 bus_dmamem_free(cd->sge_rx_tag, ld->sge_rx_ring,
926 cd->sge_rx_dmamap);
927 ld->sge_rx_ring = NULL;
928 cd->sge_rx_dmamap = NULL;
929 bus_dma_tag_destroy(cd->sge_rx_tag);
930 cd->sge_rx_tag = NULL;
931 }
932 /* Tx ring. */
933 if (cd->sge_tx_tag != NULL) {
934 if (cd->sge_tx_dmamap != NULL)
935 bus_dmamap_unload(cd->sge_tx_tag, cd->sge_tx_dmamap);
936 if (cd->sge_tx_dmamap != NULL && ld->sge_tx_ring != NULL)
937 bus_dmamem_free(cd->sge_tx_tag, ld->sge_tx_ring,
938 cd->sge_tx_dmamap);
939 ld->sge_tx_ring = NULL;
940 cd->sge_tx_dmamap = NULL;
941 bus_dma_tag_destroy(cd->sge_tx_tag);
942 cd->sge_tx_tag = NULL;
943 }
944 /* Rx buffers. */
945 if (cd->sge_rxmbuf_tag != NULL) {
946 for (i = 0; i < SGE_RX_RING_CNT; i++) {
947 rxd = &cd->sge_rxdesc[i];
948 if (rxd->rx_dmamap != NULL) {
949 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
950 rxd->rx_dmamap);
951 rxd->rx_dmamap = NULL;
952 }
953 }
954 if (cd->sge_rx_spare_map != NULL) {
955 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
956 cd->sge_rx_spare_map);
957 cd->sge_rx_spare_map = NULL;
958 }
959 bus_dma_tag_destroy(cd->sge_rxmbuf_tag);
960 cd->sge_rxmbuf_tag = NULL;
961 }
962 /* Tx buffers. */
963 if (cd->sge_txmbuf_tag != NULL) {
964 for (i = 0; i < SGE_TX_RING_CNT; i++) {
965 txd = &cd->sge_txdesc[i];
966 if (txd->tx_dmamap != NULL) {
967 bus_dmamap_destroy(cd->sge_txmbuf_tag,
968 txd->tx_dmamap);
969 txd->tx_dmamap = NULL;
970 }
971 }
972 bus_dma_tag_destroy(cd->sge_txmbuf_tag);
973 cd->sge_txmbuf_tag = NULL;
974 }
975 if (cd->sge_tag != NULL)
976 bus_dma_tag_destroy(cd->sge_tag);
977 cd->sge_tag = NULL;
978 }
979
980 /*
981 * Initialize the TX descriptors.
982 */
983 static int
984 sge_list_tx_init(struct sge_softc *sc)
985 {
986 struct sge_list_data *ld;
987 struct sge_chain_data *cd;
988
989 SGE_LOCK_ASSERT(sc);
990 ld = &sc->sge_ldata;
991 cd = &sc->sge_cdata;
992 bzero(ld->sge_tx_ring, SGE_TX_RING_SZ);
993 ld->sge_tx_ring[SGE_TX_RING_CNT - 1].sge_flags = htole32(RING_END);
994 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
996 cd->sge_tx_prod = 0;
997 cd->sge_tx_cons = 0;
998 cd->sge_tx_cnt = 0;
999 return (0);
1000 }
1001
1002 static int
1003 sge_list_tx_free(struct sge_softc *sc)
1004 {
1005 struct sge_chain_data *cd;
1006 struct sge_txdesc *txd;
1007 int i;
1008
1009 SGE_LOCK_ASSERT(sc);
1010 cd = &sc->sge_cdata;
1011 for (i = 0; i < SGE_TX_RING_CNT; i++) {
1012 txd = &cd->sge_txdesc[i];
1013 if (txd->tx_m != NULL) {
1014 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1015 BUS_DMASYNC_POSTWRITE);
1016 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1017 m_freem(txd->tx_m);
1018 txd->tx_m = NULL;
1019 txd->tx_ndesc = 0;
1020 }
1021 }
1022
1023 return (0);
1024 }
1025
1026 /*
1027 * Initialize the RX descriptors and allocate mbufs for them. Note that
1028 * we arrange the descriptors in a closed ring, so that the last descriptor
1029 * has RING_END flag set.
1030 */
1031 static int
1032 sge_list_rx_init(struct sge_softc *sc)
1033 {
1034 struct sge_chain_data *cd;
1035 int i;
1036
1037 SGE_LOCK_ASSERT(sc);
1038 cd = &sc->sge_cdata;
1039 cd->sge_rx_cons = 0;
1040 bzero(sc->sge_ldata.sge_rx_ring, SGE_RX_RING_SZ);
1041 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1042 if (sge_newbuf(sc, i) != 0)
1043 return (ENOBUFS);
1044 }
1045 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1047 return (0);
1048 }
1049
1050 static int
1051 sge_list_rx_free(struct sge_softc *sc)
1052 {
1053 struct sge_chain_data *cd;
1054 struct sge_rxdesc *rxd;
1055 int i;
1056
1057 SGE_LOCK_ASSERT(sc);
1058 cd = &sc->sge_cdata;
1059 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1060 rxd = &cd->sge_rxdesc[i];
1061 if (rxd->rx_m != NULL) {
1062 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1063 BUS_DMASYNC_POSTREAD);
1064 bus_dmamap_unload(cd->sge_rxmbuf_tag,
1065 rxd->rx_dmamap);
1066 m_freem(rxd->rx_m);
1067 rxd->rx_m = NULL;
1068 }
1069 }
1070 return (0);
1071 }
1072
1073 /*
1074 * Initialize an RX descriptor and attach an MBUF cluster.
1075 */
1076 static int
1077 sge_newbuf(struct sge_softc *sc, int prod)
1078 {
1079 struct mbuf *m;
1080 struct sge_desc *desc;
1081 struct sge_chain_data *cd;
1082 struct sge_rxdesc *rxd;
1083 bus_dma_segment_t segs[1];
1084 bus_dmamap_t map;
1085 int error, nsegs;
1086
1087 SGE_LOCK_ASSERT(sc);
1088
1089 cd = &sc->sge_cdata;
1090 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1091 if (m == NULL)
1092 return (ENOBUFS);
1093 m->m_len = m->m_pkthdr.len = MCLBYTES;
1094 m_adj(m, SGE_RX_BUF_ALIGN);
1095 error = bus_dmamap_load_mbuf_sg(cd->sge_rxmbuf_tag,
1096 cd->sge_rx_spare_map, m, segs, &nsegs, 0);
1097 if (error != 0) {
1098 m_freem(m);
1099 return (error);
1100 }
1101 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1102 rxd = &cd->sge_rxdesc[prod];
1103 if (rxd->rx_m != NULL) {
1104 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1105 BUS_DMASYNC_POSTREAD);
1106 bus_dmamap_unload(cd->sge_rxmbuf_tag, rxd->rx_dmamap);
1107 }
1108 map = rxd->rx_dmamap;
1109 rxd->rx_dmamap = cd->sge_rx_spare_map;
1110 cd->sge_rx_spare_map = map;
1111 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1112 BUS_DMASYNC_PREREAD);
1113 rxd->rx_m = m;
1114
1115 desc = &sc->sge_ldata.sge_rx_ring[prod];
1116 desc->sge_sts_size = 0;
1117 desc->sge_ptr = htole32(SGE_ADDR_LO(segs[0].ds_addr));
1118 desc->sge_flags = htole32(segs[0].ds_len);
1119 if (prod == SGE_RX_RING_CNT - 1)
1120 desc->sge_flags |= htole32(RING_END);
1121 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR | RDC_IP_CSUM |
1122 RDC_TCP_CSUM | RDC_UDP_CSUM);
1123 return (0);
1124 }
1125
1126 static __inline void
1127 sge_discard_rxbuf(struct sge_softc *sc, int index)
1128 {
1129 struct sge_desc *desc;
1130
1131 desc = &sc->sge_ldata.sge_rx_ring[index];
1132 desc->sge_sts_size = 0;
1133 desc->sge_flags = htole32(MCLBYTES - SGE_RX_BUF_ALIGN);
1134 if (index == SGE_RX_RING_CNT - 1)
1135 desc->sge_flags |= htole32(RING_END);
1136 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR | RDC_IP_CSUM |
1137 RDC_TCP_CSUM | RDC_UDP_CSUM);
1138 }
1139
1140 /*
1141 * A frame has been uploaded: pass the resulting mbuf chain up to
1142 * the higher level protocols.
1143 */
1144 static void
1145 sge_rxeof(struct sge_softc *sc)
1146 {
1147 struct ifnet *ifp;
1148 struct mbuf *m;
1149 struct sge_chain_data *cd;
1150 struct sge_desc *cur_rx;
1151 uint32_t rxinfo, rxstat;
1152 int cons, prog;
1153
1154 SGE_LOCK_ASSERT(sc);
1155
1156 ifp = sc->sge_ifp;
1157 cd = &sc->sge_cdata;
1158
1159 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1160 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1161 cons = cd->sge_rx_cons;
1162 for (prog = 0; prog < SGE_RX_RING_CNT; prog++,
1163 SGE_INC(cons, SGE_RX_RING_CNT)) {
1164 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1165 break;
1166 cur_rx = &sc->sge_ldata.sge_rx_ring[cons];
1167 rxinfo = le32toh(cur_rx->sge_cmdsts);
1168 if ((rxinfo & RDC_OWN) != 0)
1169 break;
1170 rxstat = le32toh(cur_rx->sge_sts_size);
1171 if ((rxstat & RDS_CRCOK) == 0 || SGE_RX_ERROR(rxstat) != 0 ||
1172 SGE_RX_NSEGS(rxstat) != 1) {
1173 /* XXX We don't support multi-segment frames yet. */
1174 #ifdef SGE_SHOW_ERRORS
1175 device_printf(sc->sge_dev, "Rx error : 0x%b\n", rxstat,
1176 RX_ERR_BITS);
1177 #endif
1178 sge_discard_rxbuf(sc, cons);
1179 ifp->if_ierrors++;
1180 continue;
1181 }
1182 m = cd->sge_rxdesc[cons].rx_m;
1183 if (sge_newbuf(sc, cons) != 0) {
1184 sge_discard_rxbuf(sc, cons);
1185 ifp->if_iqdrops++;
1186 continue;
1187 }
1188 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1189 if ((rxinfo & RDC_IP_CSUM) != 0 &&
1190 (rxinfo & RDC_IP_CSUM_OK) != 0)
1191 m->m_pkthdr.csum_flags |=
1192 CSUM_IP_CHECKED | CSUM_IP_VALID;
1193 if (((rxinfo & RDC_TCP_CSUM) != 0 &&
1194 (rxinfo & RDC_TCP_CSUM_OK) != 0) ||
1195 ((rxinfo & RDC_UDP_CSUM) != 0 &&
1196 (rxinfo & RDC_UDP_CSUM_OK) != 0)) {
1197 m->m_pkthdr.csum_flags |=
1198 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1199 m->m_pkthdr.csum_data = 0xffff;
1200 }
1201 }
1202 /* Check for VLAN tagged frame. */
1203 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1204 (rxstat & RDS_VLAN) != 0) {
1205 m->m_pkthdr.ether_vtag = rxinfo & RDC_VLAN_MASK;
1206 m->m_flags |= M_VLANTAG;
1207 }
1208 /*
1209 * Account for 10bytes auto padding which is used
1210 * to align IP header on 32bit boundary. Also note,
1211 * CRC bytes is automatically removed by the
1212 * hardware.
1213 */
1214 m->m_data += SGE_RX_PAD_BYTES;
1215 m->m_pkthdr.len = m->m_len = SGE_RX_BYTES(rxstat) -
1216 SGE_RX_PAD_BYTES;
1217 m->m_pkthdr.rcvif = ifp;
1218 ifp->if_ipackets++;
1219 SGE_UNLOCK(sc);
1220 (*ifp->if_input)(ifp, m);
1221 SGE_LOCK(sc);
1222 }
1223
1224 if (prog > 0) {
1225 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1227 cd->sge_rx_cons = cons;
1228 }
1229 }
1230
1231 /*
1232 * A frame was downloaded to the chip. It's safe for us to clean up
1233 * the list buffers.
1234 */
1235 static void
1236 sge_txeof(struct sge_softc *sc)
1237 {
1238 struct ifnet *ifp;
1239 struct sge_list_data *ld;
1240 struct sge_chain_data *cd;
1241 struct sge_txdesc *txd;
1242 uint32_t txstat;
1243 int cons, nsegs, prod;
1244
1245 SGE_LOCK_ASSERT(sc);
1246
1247 ifp = sc->sge_ifp;
1248 ld = &sc->sge_ldata;
1249 cd = &sc->sge_cdata;
1250
1251 if (cd->sge_tx_cnt == 0)
1252 return;
1253 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
1254 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1255 cons = cd->sge_tx_cons;
1256 prod = cd->sge_tx_prod;
1257 for (; cons != prod;) {
1258 txstat = le32toh(ld->sge_tx_ring[cons].sge_cmdsts);
1259 if ((txstat & TDC_OWN) != 0)
1260 break;
1261 /*
1262 * Only the first descriptor of multi-descriptor transmission
1263 * is updated by controller. Driver should skip entire
1264 * chained buffers for the transmitted frame. In other words
1265 * TDC_OWN bit is valid only at the first descriptor of a
1266 * multi-descriptor transmission.
1267 */
1268 if (SGE_TX_ERROR(txstat) != 0) {
1269 #ifdef SGE_SHOW_ERRORS
1270 device_printf(sc->sge_dev, "Tx error : 0x%b\n",
1271 txstat, TX_ERR_BITS);
1272 #endif
1273 ifp->if_oerrors++;
1274 } else {
1275 #ifdef notyet
1276 ifp->if_collisions += (txstat & 0xFFFF) - 1;
1277 #endif
1278 ifp->if_opackets++;
1279 }
1280 txd = &cd->sge_txdesc[cons];
1281 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1282 ld->sge_tx_ring[cons].sge_cmdsts = 0;
1283 SGE_INC(cons, SGE_TX_RING_CNT);
1284 }
1285 /* Reclaim transmitted mbuf. */
1286 KASSERT(txd->tx_m != NULL,
1287 ("%s: freeing NULL mbuf\n", __func__));
1288 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1289 BUS_DMASYNC_POSTWRITE);
1290 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1291 m_freem(txd->tx_m);
1292 txd->tx_m = NULL;
1293 cd->sge_tx_cnt -= txd->tx_ndesc;
1294 KASSERT(cd->sge_tx_cnt >= 0,
1295 ("%s: Active Tx desc counter was garbled\n", __func__));
1296 txd->tx_ndesc = 0;
1297 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1298 }
1299 cd->sge_tx_cons = cons;
1300 if (cd->sge_tx_cnt == 0)
1301 sc->sge_timer = 0;
1302 }
1303
1304 static void
1305 sge_tick(void *arg)
1306 {
1307 struct sge_softc *sc;
1308 struct mii_data *mii;
1309 struct ifnet *ifp;
1310
1311 sc = arg;
1312 SGE_LOCK_ASSERT(sc);
1313
1314 ifp = sc->sge_ifp;
1315 mii = device_get_softc(sc->sge_miibus);
1316 mii_tick(mii);
1317 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1318 sge_miibus_statchg(sc->sge_dev);
1319 if ((sc->sge_flags & SGE_FLAG_LINK) != 0 &&
1320 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1321 sge_start_locked(ifp);
1322 }
1323 /*
1324 * Reclaim transmitted frames here as we do not request
1325 * Tx completion interrupt for every queued frames to
1326 * reduce excessive interrupts.
1327 */
1328 sge_txeof(sc);
1329 sge_watchdog(sc);
1330 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1331 }
1332
1333 static void
1334 sge_intr(void *arg)
1335 {
1336 struct sge_softc *sc;
1337 struct ifnet *ifp;
1338 uint32_t status;
1339
1340 sc = arg;
1341 SGE_LOCK(sc);
1342 ifp = sc->sge_ifp;
1343
1344 status = CSR_READ_4(sc, IntrStatus);
1345 if (status == 0xFFFFFFFF || (status & SGE_INTRS) == 0) {
1346 /* Not ours. */
1347 SGE_UNLOCK(sc);
1348 return;
1349 }
1350 /* Acknowledge interrupts. */
1351 CSR_WRITE_4(sc, IntrStatus, status);
1352 /* Disable further interrupts. */
1353 CSR_WRITE_4(sc, IntrMask, 0);
1354 /*
1355 * It seems the controller supports some kind of interrupt
1356 * moderation mechanism but we still don't know how to
1357 * enable that. To reduce number of generated interrupts
1358 * under load we check pending interrupts in a loop. This
1359 * will increase number of register access and is not correct
1360 * way to handle interrupt moderation but there seems to be
1361 * no other way at this time.
1362 */
1363 for (;;) {
1364 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1365 break;
1366 if ((status & (INTR_RX_DONE | INTR_RX_IDLE)) != 0) {
1367 sge_rxeof(sc);
1368 /* Wakeup Rx MAC. */
1369 if ((status & INTR_RX_IDLE) != 0)
1370 CSR_WRITE_4(sc, RX_CTL,
1371 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1372 }
1373 if ((status & (INTR_TX_DONE | INTR_TX_IDLE)) != 0)
1374 sge_txeof(sc);
1375 status = CSR_READ_4(sc, IntrStatus);
1376 if ((status & SGE_INTRS) == 0)
1377 break;
1378 /* Acknowledge interrupts. */
1379 CSR_WRITE_4(sc, IntrStatus, status);
1380 }
1381 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1382 /* Re-enable interrupts */
1383 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1384 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1385 sge_start_locked(ifp);
1386 }
1387 SGE_UNLOCK(sc);
1388 }
1389
1390 /*
1391 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1392 * pointers to the fragment pointers.
1393 */
1394 static int
1395 sge_encap(struct sge_softc *sc, struct mbuf **m_head)
1396 {
1397 struct mbuf *m;
1398 struct sge_desc *desc;
1399 struct sge_txdesc *txd;
1400 bus_dma_segment_t txsegs[SGE_MAXTXSEGS];
1401 uint32_t cflags, mss;
1402 int error, i, nsegs, prod, si;
1403
1404 SGE_LOCK_ASSERT(sc);
1405
1406 si = prod = sc->sge_cdata.sge_tx_prod;
1407 txd = &sc->sge_cdata.sge_txdesc[prod];
1408 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1409 struct ether_header *eh;
1410 struct ip *ip;
1411 struct tcphdr *tcp;
1412 uint32_t ip_off, poff;
1413
1414 if (M_WRITABLE(*m_head) == 0) {
1415 /* Get a writable copy. */
1416 m = m_dup(*m_head, M_DONTWAIT);
1417 m_freem(*m_head);
1418 if (m == NULL) {
1419 *m_head = NULL;
1420 return (ENOBUFS);
1421 }
1422 *m_head = m;
1423 }
1424 ip_off = sizeof(struct ether_header);
1425 m = m_pullup(*m_head, ip_off);
1426 if (m == NULL) {
1427 *m_head = NULL;
1428 return (ENOBUFS);
1429 }
1430 eh = mtod(m, struct ether_header *);
1431 /* Check the existence of VLAN tag. */
1432 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1433 ip_off = sizeof(struct ether_vlan_header);
1434 m = m_pullup(m, ip_off);
1435 if (m == NULL) {
1436 *m_head = NULL;
1437 return (ENOBUFS);
1438 }
1439 }
1440 m = m_pullup(m, ip_off + sizeof(struct ip));
1441 if (m == NULL) {
1442 *m_head = NULL;
1443 return (ENOBUFS);
1444 }
1445 ip = (struct ip *)(mtod(m, char *) + ip_off);
1446 poff = ip_off + (ip->ip_hl << 2);
1447 m = m_pullup(m, poff + sizeof(struct tcphdr));
1448 if (m == NULL) {
1449 *m_head = NULL;
1450 return (ENOBUFS);
1451 }
1452 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1453 m = m_pullup(m, poff + (tcp->th_off << 2));
1454 if (m == NULL) {
1455 *m_head = NULL;
1456 return (ENOBUFS);
1457 }
1458 /*
1459 * Reset IP checksum and recompute TCP pseudo
1460 * checksum that NDIS specification requires.
1461 */
1462 ip->ip_sum = 0;
1463 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1464 htons(IPPROTO_TCP));
1465 *m_head = m;
1466 }
1467
1468 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1469 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1470 if (error == EFBIG) {
1471 m = m_collapse(*m_head, M_DONTWAIT, SGE_MAXTXSEGS);
1472 if (m == NULL) {
1473 m_freem(*m_head);
1474 *m_head = NULL;
1475 return (ENOBUFS);
1476 }
1477 *m_head = m;
1478 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1479 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1480 if (error != 0) {
1481 m_freem(*m_head);
1482 *m_head = NULL;
1483 return (error);
1484 }
1485 } else if (error != 0)
1486 return (error);
1487
1488 KASSERT(nsegs != 0, ("zero segment returned"));
1489 /* Check descriptor overrun. */
1490 if (sc->sge_cdata.sge_tx_cnt + nsegs >= SGE_TX_RING_CNT) {
1491 bus_dmamap_unload(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap);
1492 return (ENOBUFS);
1493 }
1494 bus_dmamap_sync(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap,
1495 BUS_DMASYNC_PREWRITE);
1496
1497 m = *m_head;
1498 cflags = 0;
1499 mss = 0;
1500 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1501 cflags |= TDC_LS;
1502 mss = (uint32_t)m->m_pkthdr.tso_segsz;
1503 mss <<= 16;
1504 } else {
1505 if (m->m_pkthdr.csum_flags & CSUM_IP)
1506 cflags |= TDC_IP_CSUM;
1507 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1508 cflags |= TDC_TCP_CSUM;
1509 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1510 cflags |= TDC_UDP_CSUM;
1511 }
1512 for (i = 0; i < nsegs; i++) {
1513 desc = &sc->sge_ldata.sge_tx_ring[prod];
1514 if (i == 0) {
1515 desc->sge_sts_size = htole32(m->m_pkthdr.len | mss);
1516 desc->sge_cmdsts = 0;
1517 } else {
1518 desc->sge_sts_size = 0;
1519 desc->sge_cmdsts = htole32(TDC_OWN);
1520 }
1521 desc->sge_ptr = htole32(SGE_ADDR_LO(txsegs[i].ds_addr));
1522 desc->sge_flags = htole32(txsegs[i].ds_len);
1523 if (prod == SGE_TX_RING_CNT - 1)
1524 desc->sge_flags |= htole32(RING_END);
1525 sc->sge_cdata.sge_tx_cnt++;
1526 SGE_INC(prod, SGE_TX_RING_CNT);
1527 }
1528 /* Update producer index. */
1529 sc->sge_cdata.sge_tx_prod = prod;
1530
1531 desc = &sc->sge_ldata.sge_tx_ring[si];
1532 /* Configure VLAN. */
1533 if((m->m_flags & M_VLANTAG) != 0) {
1534 cflags |= m->m_pkthdr.ether_vtag;
1535 desc->sge_sts_size |= htole32(TDS_INS_VLAN);
1536 }
1537 desc->sge_cmdsts |= htole32(TDC_DEF | TDC_CRC | TDC_PAD | cflags);
1538 #if 1
1539 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1540 desc->sge_cmdsts |= htole32(TDC_BST);
1541 #else
1542 if ((sc->sge_flags & SGE_FLAG_FDX) == 0) {
1543 desc->sge_cmdsts |= htole32(TDC_COL | TDC_CRS | TDC_BKF);
1544 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1545 desc->sge_cmdsts |= htole32(TDC_EXT | TDC_BST);
1546 }
1547 #endif
1548 /* Request interrupt and give ownership to controller. */
1549 desc->sge_cmdsts |= htole32(TDC_OWN | TDC_INTR);
1550 txd->tx_m = m;
1551 txd->tx_ndesc = nsegs;
1552 return (0);
1553 }
1554
1555 static void
1556 sge_start(struct ifnet *ifp)
1557 {
1558 struct sge_softc *sc;
1559
1560 sc = ifp->if_softc;
1561 SGE_LOCK(sc);
1562 sge_start_locked(ifp);
1563 SGE_UNLOCK(sc);
1564 }
1565
1566 static void
1567 sge_start_locked(struct ifnet *ifp)
1568 {
1569 struct sge_softc *sc;
1570 struct mbuf *m_head;
1571 int queued = 0;
1572
1573 sc = ifp->if_softc;
1574 SGE_LOCK_ASSERT(sc);
1575
1576 if ((sc->sge_flags & SGE_FLAG_LINK) == 0 ||
1577 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1578 IFF_DRV_RUNNING)
1579 return;
1580
1581 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1582 if (sc->sge_cdata.sge_tx_cnt > (SGE_TX_RING_CNT -
1583 SGE_MAXTXSEGS)) {
1584 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1585 break;
1586 }
1587 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1588 if (m_head == NULL)
1589 break;
1590 if (sge_encap(sc, &m_head)) {
1591 if (m_head == NULL)
1592 break;
1593 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1594 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1595 break;
1596 }
1597 queued++;
1598 /*
1599 * If there's a BPF listener, bounce a copy of this frame
1600 * to him.
1601 */
1602 BPF_MTAP(ifp, m_head);
1603 }
1604
1605 if (queued > 0) {
1606 bus_dmamap_sync(sc->sge_cdata.sge_tx_tag,
1607 sc->sge_cdata.sge_tx_dmamap,
1608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1609 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);
1610 sc->sge_timer = 5;
1611 }
1612 }
1613
1614 static void
1615 sge_init(void *arg)
1616 {
1617 struct sge_softc *sc;
1618
1619 sc = arg;
1620 SGE_LOCK(sc);
1621 sge_init_locked(sc);
1622 SGE_UNLOCK(sc);
1623 }
1624
1625 static void
1626 sge_init_locked(struct sge_softc *sc)
1627 {
1628 struct ifnet *ifp;
1629 struct mii_data *mii;
1630 uint16_t rxfilt;
1631 int i;
1632
1633 SGE_LOCK_ASSERT(sc);
1634 ifp = sc->sge_ifp;
1635 mii = device_get_softc(sc->sge_miibus);
1636 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1637 return;
1638 /*
1639 * Cancel pending I/O and free all RX/TX buffers.
1640 */
1641 sge_stop(sc);
1642 sge_reset(sc);
1643
1644 /* Init circular RX list. */
1645 if (sge_list_rx_init(sc) == ENOBUFS) {
1646 device_printf(sc->sge_dev, "no memory for Rx buffers\n");
1647 sge_stop(sc);
1648 return;
1649 }
1650 /* Init TX descriptors. */
1651 sge_list_tx_init(sc);
1652 /*
1653 * Load the address of the RX and TX lists.
1654 */
1655 CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));
1656 CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));
1657
1658 CSR_WRITE_4(sc, TxMacControl, 0x60);
1659 CSR_WRITE_4(sc, RxWakeOnLan, 0);
1660 CSR_WRITE_4(sc, RxWakeOnLanData, 0);
1661 /* Allow receiving VLAN frames. */
1662 CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
1663 SGE_RX_PAD_BYTES);
1664
1665 for (i = 0; i < ETHER_ADDR_LEN; i++)
1666 CSR_WRITE_1(sc, RxMacAddr + i, IF_LLADDR(ifp)[i]);
1667 /* Configure RX MAC. */
1668 rxfilt = RXMAC_STRIP_FCS | RXMAC_PAD_ENB;
1669 CSR_WRITE_2(sc, RxMacControl, rxfilt);
1670 sge_rxfilter(sc);
1671 sge_setvlan(sc);
1672
1673 /* Initialize default speed/duplex information. */
1674 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0)
1675 sc->sge_flags |= SGE_FLAG_SPEED_1000;
1676 sc->sge_flags |= SGE_FLAG_FDX;
1677 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0)
1678 CSR_WRITE_4(sc, StationControl, 0x04008001);
1679 else
1680 CSR_WRITE_4(sc, StationControl, 0x04000001);
1681 /*
1682 * XXX Try to mitigate interrupts.
1683 */
1684 CSR_WRITE_4(sc, IntrControl, 0x08880000);
1685 #ifdef notyet
1686 if (sc->sge_intrcontrol != 0)
1687 CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);
1688 if (sc->sge_intrtimer != 0)
1689 CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);
1690 #endif
1691
1692 /*
1693 * Clear and enable interrupts.
1694 */
1695 CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);
1696 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1697
1698 /* Enable receiver and transmitter. */
1699 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);
1700 CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1701
1702 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1703 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1704
1705 sc->sge_flags &= ~SGE_FLAG_LINK;
1706 mii_mediachg(mii);
1707 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1708 }
1709
1710 /*
1711 * Set media options.
1712 */
1713 static int
1714 sge_ifmedia_upd(struct ifnet *ifp)
1715 {
1716 struct sge_softc *sc;
1717 struct mii_data *mii;
1718 int error;
1719
1720 sc = ifp->if_softc;
1721 SGE_LOCK(sc);
1722 mii = device_get_softc(sc->sge_miibus);
1723 if (mii->mii_instance) {
1724 struct mii_softc *miisc;
1725 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1726 mii_phy_reset(miisc);
1727 }
1728 error = mii_mediachg(mii);
1729 SGE_UNLOCK(sc);
1730
1731 return (error);
1732 }
1733
1734 /*
1735 * Report current media status.
1736 */
1737 static void
1738 sge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1739 {
1740 struct sge_softc *sc;
1741 struct mii_data *mii;
1742
1743 sc = ifp->if_softc;
1744 SGE_LOCK(sc);
1745 mii = device_get_softc(sc->sge_miibus);
1746 if ((ifp->if_flags & IFF_UP) == 0) {
1747 SGE_UNLOCK(sc);
1748 return;
1749 }
1750 mii_pollstat(mii);
1751 SGE_UNLOCK(sc);
1752 ifmr->ifm_active = mii->mii_media_active;
1753 ifmr->ifm_status = mii->mii_media_status;
1754 }
1755
1756 static int
1757 sge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1758 {
1759 struct sge_softc *sc;
1760 struct ifreq *ifr;
1761 struct mii_data *mii;
1762 int error = 0, mask, reinit;
1763
1764 sc = ifp->if_softc;
1765 ifr = (struct ifreq *)data;
1766
1767 switch(command) {
1768 case SIOCSIFFLAGS:
1769 SGE_LOCK(sc);
1770 if ((ifp->if_flags & IFF_UP) != 0) {
1771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1772 ((ifp->if_flags ^ sc->sge_if_flags) &
1773 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1774 sge_rxfilter(sc);
1775 else
1776 sge_init_locked(sc);
1777 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1778 sge_stop(sc);
1779 sc->sge_if_flags = ifp->if_flags;
1780 SGE_UNLOCK(sc);
1781 break;
1782 case SIOCSIFCAP:
1783 SGE_LOCK(sc);
1784 reinit = 0;
1785 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1786 if ((mask & IFCAP_TXCSUM) != 0 &&
1787 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1788 ifp->if_capenable ^= IFCAP_TXCSUM;
1789 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1790 ifp->if_hwassist |= SGE_CSUM_FEATURES;
1791 else
1792 ifp->if_hwassist &= ~SGE_CSUM_FEATURES;
1793 }
1794 if ((mask & IFCAP_RXCSUM) != 0 &&
1795 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1796 ifp->if_capenable ^= IFCAP_RXCSUM;
1797 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1798 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1799 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1800 if ((mask & IFCAP_TSO4) != 0 &&
1801 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1802 ifp->if_capenable ^= IFCAP_TSO4;
1803 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1804 ifp->if_hwassist |= CSUM_TSO;
1805 else
1806 ifp->if_hwassist &= ~CSUM_TSO;
1807 }
1808 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1809 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1810 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1811 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1812 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1813 /*
1814 * Due to unknown reason, toggling VLAN hardware
1815 * tagging require interface reinitialization.
1816 */
1817 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1818 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1819 ifp->if_capenable &=
1820 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1821 reinit = 1;
1822 }
1823 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1825 sge_init_locked(sc);
1826 }
1827 SGE_UNLOCK(sc);
1828 VLAN_CAPABILITIES(ifp);
1829 break;
1830 case SIOCADDMULTI:
1831 case SIOCDELMULTI:
1832 SGE_LOCK(sc);
1833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1834 sge_rxfilter(sc);
1835 SGE_UNLOCK(sc);
1836 break;
1837 case SIOCGIFMEDIA:
1838 case SIOCSIFMEDIA:
1839 mii = device_get_softc(sc->sge_miibus);
1840 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1841 break;
1842 default:
1843 error = ether_ioctl(ifp, command, data);
1844 break;
1845 }
1846
1847 return (error);
1848 }
1849
1850 static void
1851 sge_watchdog(struct sge_softc *sc)
1852 {
1853 struct ifnet *ifp;
1854
1855 SGE_LOCK_ASSERT(sc);
1856 if (sc->sge_timer == 0 || --sc->sge_timer > 0)
1857 return;
1858
1859 ifp = sc->sge_ifp;
1860 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1861 if (1 || bootverbose)
1862 device_printf(sc->sge_dev,
1863 "watchdog timeout (lost link)\n");
1864 ifp->if_oerrors++;
1865 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1866 sge_init_locked(sc);
1867 return;
1868 }
1869 device_printf(sc->sge_dev, "watchdog timeout\n");
1870 ifp->if_oerrors++;
1871
1872 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1873 sge_init_locked(sc);
1874 if (!IFQ_DRV_IS_EMPTY(&sc->sge_ifp->if_snd))
1875 sge_start_locked(ifp);
1876 }
1877
1878 /*
1879 * Stop the adapter and free any mbufs allocated to the
1880 * RX and TX lists.
1881 */
1882 static void
1883 sge_stop(struct sge_softc *sc)
1884 {
1885 struct ifnet *ifp;
1886
1887 ifp = sc->sge_ifp;
1888
1889 SGE_LOCK_ASSERT(sc);
1890
1891 sc->sge_timer = 0;
1892 callout_stop(&sc->sge_stat_ch);
1893 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1894
1895 CSR_WRITE_4(sc, IntrMask, 0);
1896 CSR_READ_4(sc, IntrMask);
1897 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1898 /* Stop TX/RX MAC. */
1899 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
1900 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
1901 /* XXX Can we assume active DMA cycles gone? */
1902 DELAY(2000);
1903 CSR_WRITE_4(sc, IntrMask, 0);
1904 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1905
1906 sc->sge_flags &= ~SGE_FLAG_LINK;
1907 sge_list_rx_free(sc);
1908 sge_list_tx_free(sc);
1909 }
Cache object: c0705cf09c4f5eba6c538334d75c19f8
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