FreeBSD/Linux Kernel Cross Reference
sys/dev/siis/siis.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 /* ATA register defines */
32 #define ATA_DATA 0 /* (RW) data */
33
34 #define ATA_FEATURE 1 /* (W) feature */
35 #define ATA_F_DMA 0x01 /* enable DMA */
36 #define ATA_F_OVL 0x02 /* enable overlap */
37
38 #define ATA_COUNT 2 /* (W) sector count */
39
40 #define ATA_SECTOR 3 /* (RW) sector # */
41 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
42 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
43 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
44 #define ATA_D_LBA 0x40 /* use LBA addressing */
45 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
46
47 #define ATA_COMMAND 7 /* (W) command */
48
49 #define ATA_ERROR 8 /* (R) error */
50 #define ATA_E_ILI 0x01 /* illegal length */
51 #define ATA_E_NM 0x02 /* no media */
52 #define ATA_E_ABORT 0x04 /* command aborted */
53 #define ATA_E_MCR 0x08 /* media change request */
54 #define ATA_E_IDNF 0x10 /* ID not found */
55 #define ATA_E_MC 0x20 /* media changed */
56 #define ATA_E_UNC 0x40 /* uncorrectable data */
57 #define ATA_E_ICRC 0x80 /* UDMA crc error */
58 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
59
60 #define ATA_IREASON 9 /* (R) interrupt reason */
61 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
62 #define ATA_I_IN 0x02 /* read (1) | write (0) */
63 #define ATA_I_RELEASE 0x04 /* released bus (1) */
64 #define ATA_I_TAGMASK 0xf8 /* tag mask */
65
66 #define ATA_STATUS 10 /* (R) status */
67 #define ATA_ALTSTAT 11 /* (R) alternate status */
68 #define ATA_S_ERROR 0x01 /* error */
69 #define ATA_S_INDEX 0x02 /* index */
70 #define ATA_S_CORR 0x04 /* data corrected */
71 #define ATA_S_DRQ 0x08 /* data request */
72 #define ATA_S_DSC 0x10 /* drive seek completed */
73 #define ATA_S_SERVICE 0x10 /* drive needs service */
74 #define ATA_S_DWF 0x20 /* drive write fault */
75 #define ATA_S_DMA 0x20 /* DMA ready */
76 #define ATA_S_READY 0x40 /* drive ready */
77 #define ATA_S_BUSY 0x80 /* busy */
78
79 #define ATA_CONTROL 12 /* (W) control */
80 #define ATA_A_IDS 0x02 /* disable interrupts */
81 #define ATA_A_RESET 0x04 /* RESET controller */
82 #define ATA_A_4BIT 0x08 /* 4 head bits */
83 #define ATA_A_HOB 0x80 /* High Order Byte enable */
84
85 /* SATA register defines */
86 #define ATA_SSTATUS 13
87 #define ATA_SS_DET_MASK 0x0000000f
88 #define ATA_SS_DET_NO_DEVICE 0x00000000
89 #define ATA_SS_DET_DEV_PRESENT 0x00000001
90 #define ATA_SS_DET_PHY_ONLINE 0x00000003
91 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
92
93 #define ATA_SS_SPD_MASK 0x000000f0
94 #define ATA_SS_SPD_NO_SPEED 0x00000000
95 #define ATA_SS_SPD_GEN1 0x00000010
96 #define ATA_SS_SPD_GEN2 0x00000020
97 #define ATA_SS_SPD_GEN3 0x00000030
98
99 #define ATA_SS_IPM_MASK 0x00000f00
100 #define ATA_SS_IPM_NO_DEVICE 0x00000000
101 #define ATA_SS_IPM_ACTIVE 0x00000100
102 #define ATA_SS_IPM_PARTIAL 0x00000200
103 #define ATA_SS_IPM_SLUMBER 0x00000600
104
105 #define ATA_SERROR 14
106 #define ATA_SE_DATA_CORRECTED 0x00000001
107 #define ATA_SE_COMM_CORRECTED 0x00000002
108 #define ATA_SE_DATA_ERR 0x00000100
109 #define ATA_SE_COMM_ERR 0x00000200
110 #define ATA_SE_PROT_ERR 0x00000400
111 #define ATA_SE_HOST_ERR 0x00000800
112 #define ATA_SE_PHY_CHANGED 0x00010000
113 #define ATA_SE_PHY_IERROR 0x00020000
114 #define ATA_SE_COMM_WAKE 0x00040000
115 #define ATA_SE_DECODE_ERR 0x00080000
116 #define ATA_SE_PARITY_ERR 0x00100000
117 #define ATA_SE_CRC_ERR 0x00200000
118 #define ATA_SE_HANDSHAKE_ERR 0x00400000
119 #define ATA_SE_LINKSEQ_ERR 0x00800000
120 #define ATA_SE_TRANSPORT_ERR 0x01000000
121 #define ATA_SE_UNKNOWN_FIS 0x02000000
122
123 #define ATA_SCONTROL 15
124 #define ATA_SC_DET_MASK 0x0000000f
125 #define ATA_SC_DET_IDLE 0x00000000
126 #define ATA_SC_DET_RESET 0x00000001
127 #define ATA_SC_DET_DISABLE 0x00000004
128
129 #define ATA_SC_SPD_MASK 0x000000f0
130 #define ATA_SC_SPD_NO_SPEED 0x00000000
131 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
132 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
133 #define ATA_SC_SPD_SPEED_GEN3 0x00000030
134
135 #define ATA_SC_IPM_MASK 0x00000f00
136 #define ATA_SC_IPM_NONE 0x00000000
137 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
138 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
139
140 #define ATA_SACTIVE 16
141
142 /*
143 * Global registers
144 */
145 #define SIIS_GCTL 0x0040 /* Global Control */
146 #define SIIS_GCTL_GRESET 0x80000000 /* Global Reset */
147 #define SIIS_GCTL_MSIACK 0x40000000 /* MSI Ack */
148 #define SIIS_GCTL_I2C_IE 0x20000000 /* I2C int enable */
149 #define SIIS_GCTL_300CAP 0x01000000 /* 3Gb/s capable (R) */
150 #define SIIS_GCTL_PIE(n) (1 << (n)) /* Port int enable */
151 #define SIIS_IS 0x0044 /* Interrupt Status */
152 #define SIIS_IS_I2C 0x20000000 /* I2C Int Status */
153 #define SIIS_IS_PORT(n) (1 << (n)) /* Port interrupt stat */
154 #define SIIS_PHYCONF 0x0048 /* PHY Configuration */
155 #define SIIS_BIST_CTL 0x0050
156 #define SIIS_BIST_PATTERN 0x0054 /* 32 bit pattern */
157 #define SIIS_BIST_STATUS 0x0058
158 #define SIIS_I2C_CTL 0x0060
159 #define SIIS_I2C_STS 0x0064
160 #define SIIS_I2C_SADDR 0x0068
161 #define SIIS_I2C_DATA 0x006C
162 #define SIIS_FLASH_ADDR 0x0070
163 #define SIIS_GPIO 0x0074
164
165 /*
166 * Port registers
167 */
168
169 #define SIIS_P_LRAM 0x0000
170 #define SIIS_P_LRAM_SLOT(i) (SIIS_P_LRAM + i * 128)
171 #define SIIS_P_PMPSTS(i) (0x0F80 + i * 8)
172 #define SIIS_P_PMPQACT(i) (0x0F80 + i * 8 + 4)
173 #define SIIS_P_STS 0x1000
174 #define SIIS_P_CTLSET 0x1000
175 #define SIIS_P_CTLCLR 0x1004
176 #define SIIS_P_CTL_READY 0x80000000
177 #define SIIS_P_CTL_OOBB 0x02000000
178 #define SIIS_P_CTL_ACT 0x001F0000
179 #define SIIS_P_CTL_ACT_SHIFT 16
180 #define SIIS_P_CTL_LED_ON 0x00008000
181 #define SIIS_P_CTL_AIA 0x00004000
182 #define SIIS_P_CTL_PME 0x00002000
183 #define SIIS_P_CTL_IA 0x00001000
184 #define SIIS_P_CTL_IR 0x00000800
185 #define SIIS_P_CTL_32BIT 0x00000400
186 #define SIIS_P_CTL_SCR_DIS 0x00000200
187 #define SIIS_P_CTL_CONT_DIS 0x00000100
188 #define SIIS_P_CTL_TBIST 0x00000080
189 #define SIIS_P_CTL_RESUME 0x00000040
190 #define SIIS_P_CTL_PLENGTH 0x00000020
191 #define SIIS_P_CTL_LED_DIS 0x00000010
192 #define SIIS_P_CTL_INT_NCOR 0x00000008
193 #define SIIS_P_CTL_PORT_INIT 0x00000004
194 #define SIIS_P_CTL_DEV_RESET 0x00000002
195 #define SIIS_P_CTL_PORT_RESET 0x00000001
196 #define SIIS_P_IS 0x1008
197 #define SIIS_P_IX_SDBN 0x00000800
198 #define SIIS_P_IX_HS_ET 0x00000400
199 #define SIIS_P_IX_CRC_ET 0x00000200
200 #define SIIS_P_IX_8_10_ET 0x00000100
201 #define SIIS_P_IX_DEX 0x00000080
202 #define SIIS_P_IX_UNRECFIS 0x00000040
203 #define SIIS_P_IX_COMWAKE 0x00000020
204 #define SIIS_P_IX_PHYRDYCHG 0x00000010
205 #define SIIS_P_IX_PMCHG 0x00000008
206 #define SIIS_P_IX_READY 0x00000004
207 #define SIIS_P_IX_COMMERR 0x00000002
208 #define SIIS_P_IX_COMMCOMP 0x00000001
209 #define SIIS_P_IX_ENABLED SIIS_P_IX_COMMCOMP | SIIS_P_IX_COMMERR | \
210 SIIS_P_IX_PHYRDYCHG | SIIS_P_IX_SDBN
211 #define SIIS_P_IESET 0x1010
212 #define SIIS_P_IECLR 0x1014
213 #define SIIS_P_CACTU 0x101C
214 #define SIIS_P_CMDEFIFO 0x1020
215 #define SIIS_P_CMDERR 0x1024
216 #define SIIS_P_CMDERR_DEV 1
217 #define SIIS_P_CMDERR_SDB 2
218 #define SIIS_P_CMDERR_DATAFIS 3
219 #define SIIS_P_CMDERR_SENDFIS 4
220 #define SIIS_P_CMDERR_INCSTATE 5
221 #define SIIS_P_CMDERR_DIRECTION 6
222 #define SIIS_P_CMDERR_UNDERRUN 7
223 #define SIIS_P_CMDERR_OVERRUN 8
224 #define SIIS_P_CMDERR_LLOVERRUN 9
225 #define SIIS_P_CMDERR_PPE 11
226 #define SIIS_P_CMDERR_SGTALIGN 16
227 #define SIIS_P_CMDERR_PCITASGT 17
228 #define SIIS_P_CMDERR_OCIMASGT 18
229 #define SIIS_P_CMDERR_PCIPESGT 19
230 #define SIIS_P_CMDERR_PRBALIGN 24
231 #define SIIS_P_CMDERR_PCITAPRB 25
232 #define SIIS_P_CMDERR_PCIMAPRB 26
233 #define SIIS_P_CMDERR_PCIPEPRB 27
234 #define SIIS_P_CMDERR_PCITADATA 33
235 #define SIIS_P_CMDERR_PCIMADATA 34
236 #define SIIS_P_CMDERR_PCIPEDATA 35
237 #define SIIS_P_CMDERR_SERVICE 36
238 #define SIIS_P_FISCFG 0x1028
239 #define SIIS_P_PCIEFIFOTH 0x102C
240 #define SIIS_P_8_10_DEC_ERR 0x1040
241 #define SIIS_P_CRC_ERR 0x1044
242 #define SIIS_P_HS_ERR 0x1048
243 #define SIIS_P_PHYCFG 0x1050
244 #define SIIS_P_SS 0x1800
245 #define SIIS_P_SS_ATTN 0x80000000
246 #define SIIS_P_CACTL(i) (0x1C00 + i * 8)
247 #define SIIS_P_CACTH(i) (0x1C00 + i * 8 + 4)
248 #define SIIS_P_CTX 0x1E04
249 #define SIIS_P_CTX_SLOT 0x0000001F
250 #define SIIS_P_CTX_SLOT_SHIFT 0
251 #define SIIS_P_CTX_PMP 0x000001E0
252 #define SIIS_P_CTX_PMP_SHIFT 5
253
254 #define SIIS_P_SCTL 0x1F00
255 #define SIIS_P_SSTS 0x1F04
256 #define SIIS_P_SERR 0x1F08
257 #define SIIS_P_SACT 0x1F0C
258 #define SIIS_P_SNTF 0x1F10
259
260 #define SIIS_MAX_PORTS 4
261 #define SIIS_MAX_SLOTS 31
262
263 #define SIIS_OFFSET 0x100
264 #define SIIS_STEP 0x80
265
266 /* Pessimistic prognosis on number of required S/G entries */
267 #define SIIS_SG_ENTRIES (roundup(btoc(maxphys), 4) + 1)
268 /* Port Request Block + S/G entries. 128byte aligned. */
269 #define SIIS_PRB_SIZE (32 + 16 + SIIS_SG_ENTRIES * 16)
270 /* Total main work area. */
271 #define SIIS_WORK_SIZE (SIIS_PRB_SIZE * SIIS_MAX_SLOTS)
272
273 struct siis_dma_prd {
274 u_int64_t dba;
275 u_int32_t dbc;
276 u_int32_t control;
277 #define SIIS_PRD_TRM 0x80000000
278 #define SIIS_PRD_LNK 0x40000000
279 #define SIIS_PRD_DRD 0x20000000
280 #define SIIS_PRD_XCF 0x10000000
281 } __packed;
282
283 struct siis_cmd_ata {
284 struct siis_dma_prd prd[2];
285 } __packed;
286
287 struct siis_cmd_atapi {
288 u_int8_t ccb[16];
289 struct siis_dma_prd prd[1];
290 } __packed;
291
292 struct siis_cmd {
293 u_int16_t control;
294 #define SIIS_PRB_PROTOCOL_OVERRIDE 0x0001
295 #define SIIS_PRB_RETRANSMIT 0x0002
296 #define SIIS_PRB_EXTERNAL_COMMAND 0x0004
297 #define SIIS_PRB_RECEIVE 0x0008
298 #define SIIS_PRB_PACKET_READ 0x0010
299 #define SIIS_PRB_PACKET_WRITE 0x0020
300 #define SIIS_PRB_INTERRUPT_MASK 0x0040
301 #define SIIS_PRB_SOFT_RESET 0x0080
302 u_int16_t protocol_override;
303 #define SIIS_PRB_PROTO_PACKET 0x0001
304 #define SIIS_PRB_PROTO_TCQ 0x0002
305 #define SIIS_PRB_PROTO_NCQ 0x0004
306 #define SIIS_PRB_PROTO_READ 0x0008
307 #define SIIS_PRB_PROTO_WRITE 0x0010
308 #define SIIS_PRB_PROTO_TRANSPARENT 0x0020
309 u_int32_t transfer_count;
310 u_int8_t fis[24];
311 union {
312 struct siis_cmd_ata ata;
313 struct siis_cmd_atapi atapi;
314 } u;
315 } __packed;
316
317 /* misc defines */
318 #define ATA_IRQ_RID 0
319 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
320
321 struct ata_dmaslot {
322 bus_dmamap_t data_map; /* data DMA map */
323 int nsegs; /* Number of segs loaded */
324 };
325
326 /* structure holding DMA related information */
327 struct ata_dma {
328 bus_dma_tag_t work_tag; /* workspace DMA tag */
329 bus_dmamap_t work_map; /* workspace DMA map */
330 uint8_t *work; /* workspace */
331 bus_addr_t work_bus; /* bus address of work */
332 bus_dma_tag_t data_tag; /* data DMA tag */
333 };
334
335 enum siis_slot_states {
336 SIIS_SLOT_EMPTY,
337 SIIS_SLOT_LOADING,
338 SIIS_SLOT_RUNNING,
339 SIIS_SLOT_WAITING
340 };
341
342 struct siis_slot {
343 device_t dev; /* Device handle */
344 u_int8_t slot; /* Number of this slot */
345 enum siis_slot_states state; /* Slot state */
346 u_int prb_offset; /* PRB offset */
347 union ccb *ccb; /* CCB occupying slot */
348 struct ata_dmaslot dma; /* DMA data of this slot */
349 struct callout timeout; /* Execution timeout */
350 };
351
352 struct siis_device {
353 int revision;
354 int mode;
355 u_int bytecount;
356 u_int atapi;
357 u_int tags;
358 u_int caps;
359 };
360
361 /* structure describing an ATA channel */
362 struct siis_channel {
363 device_t dev; /* Device handle */
364 int unit; /* Physical channel */
365 struct resource *r_mem; /* Memory of this channel */
366 struct resource *r_irq; /* Interrupt of this channel */
367 void *ih; /* Interrupt handle */
368 struct ata_dma dma; /* DMA data */
369 struct cam_sim *sim;
370 struct cam_path *path;
371 struct cdev *led; /* Activity led led(4) cdev. */
372 int quirks;
373 int pm_level; /* power management level */
374
375 struct siis_slot slot[SIIS_MAX_SLOTS];
376 union ccb *hold[SIIS_MAX_SLOTS];
377 struct mtx mtx; /* state lock */
378 int devices; /* What is present */
379 int pm_present; /* PM presence reported */
380 uint32_t oslots; /* Occupied slots */
381 uint32_t rslots; /* Running slots */
382 uint32_t aslots; /* Slots with atomic commands */
383 uint32_t eslots; /* Slots in error */
384 uint32_t toslots; /* Slots in timeout */
385 int numrslots; /* Number of running slots */
386 int numtslots[SIIS_MAX_SLOTS]; /* Number of tagged slots */
387 int numhslots; /* Number of held slots */
388 int recoverycmd; /* Our READ LOG active */
389 int fatalerr; /* Fatal error happened */
390 int recovery; /* Some slots are in error */
391 union ccb *frozen; /* Frozen command */
392
393 struct siis_device user[16]; /* User-specified settings */
394 struct siis_device curr[16]; /* Current settings */
395 };
396
397 /* structure describing a SIIS controller */
398 struct siis_controller {
399 device_t dev;
400 int r_grid;
401 struct resource *r_gmem;
402 int r_rid;
403 struct resource *r_mem;
404 struct rman sc_iomem;
405 struct siis_controller_irq {
406 struct resource *r_irq;
407 void *handle;
408 int r_irq_rid;
409 } irq;
410 int quirks;
411 int channels;
412 uint32_t gctl;
413 struct {
414 void (*function)(void *);
415 void *argument;
416 } interrupt[SIIS_MAX_PORTS];
417 };
418
419 enum siis_err_type {
420 SIIS_ERR_NONE, /* No error */
421 SIIS_ERR_INVALID, /* Error detected by us before submitting. */
422 SIIS_ERR_INNOCENT, /* Innocent victim. */
423 SIIS_ERR_TFE, /* Task File Error. */
424 SIIS_ERR_SATA, /* SATA error. */
425 SIIS_ERR_TIMEOUT, /* Command execution timeout. */
426 SIIS_ERR_NCQ, /* NCQ command error. CCB should be put on hold
427 * until READ LOG executed to reveal error. */
428 };
429
430 /* macros to hide busspace uglyness */
431 #define ATA_INB(res, offset) \
432 bus_read_1((res), (offset))
433 #define ATA_INW(res, offset) \
434 bus_read_2((res), (offset))
435 #define ATA_INL(res, offset) \
436 bus_read_4((res), (offset))
437 #define ATA_INSW(res, offset, addr, count) \
438 bus_read_multi_2((res), (offset), (addr), (count))
439 #define ATA_INSW_STRM(res, offset, addr, count) \
440 bus_read_multi_stream_2((res), (offset), (addr), (count))
441 #define ATA_INSL(res, offset, addr, count) \
442 bus_read_multi_4((res), (offset), (addr), (count))
443 #define ATA_INSL_STRM(res, offset, addr, count) \
444 bus_read_multi_stream_4((res), (offset), (addr), (count))
445 #define ATA_OUTB(res, offset, value) \
446 bus_write_1((res), (offset), (value))
447 #define ATA_OUTW(res, offset, value) \
448 bus_write_2((res), (offset), (value))
449 #define ATA_OUTL(res, offset, value) \
450 bus_write_4((res), (offset), (value))
451 #define ATA_OUTSW(res, offset, addr, count) \
452 bus_write_multi_2((res), (offset), (addr), (count))
453 #define ATA_OUTSW_STRM(res, offset, addr, count) \
454 bus_write_multi_stream_2((res), (offset), (addr), (count))
455 #define ATA_OUTSL(res, offset, addr, count) \
456 bus_write_multi_4((res), (offset), (addr), (count))
457 #define ATA_OUTSL_STRM(res, offset, addr, count) \
458 bus_write_multi_stream_4((res), (offset), (addr), (count))
Cache object: fe20d45e7a547ed3ed07b82d0dae9e30
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