FreeBSD/Linux Kernel Cross Reference
sys/dev/sis/if_sis.c
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
5 * Copyright (c) 1997, 1998, 1999
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
41 * available from http://www.sis.com.tw.
42 *
43 * This driver also supports the NatSemi DP83815. Datasheets are
44 * available from http://www.national.com.
45 *
46 * Written by Bill Paul <wpaul@ee.columbia.edu>
47 * Electrical Engineering Department
48 * Columbia University, New York City
49 */
50 /*
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
58 *
59 * The only downside to this chipset is that RX descriptors must be
60 * longword aligned.
61 */
62
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
65 #endif
66
67 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/bus.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
72 #include <sys/lock.h>
73 #include <sys/malloc.h>
74 #include <sys/mbuf.h>
75 #include <sys/module.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
79
80 #include <net/if.h>
81 #include <net/if_var.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
87 #include <net/if_vlan_var.h>
88
89 #include <net/bpf.h>
90
91 #include <machine/bus.h>
92 #include <machine/resource.h>
93 #include <sys/rman.h>
94
95 #include <dev/mii/mii.h>
96 #include <dev/mii/mii_bitbang.h>
97 #include <dev/mii/miivar.h>
98
99 #include <dev/pci/pcireg.h>
100 #include <dev/pci/pcivar.h>
101
102 #define SIS_USEIOSPACE
103
104 #include <dev/sis/if_sisreg.h>
105
106 MODULE_DEPEND(sis, pci, 1, 1, 1);
107 MODULE_DEPEND(sis, ether, 1, 1, 1);
108 MODULE_DEPEND(sis, miibus, 1, 1, 1);
109
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
112
113 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
114 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
115 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
116
117 /*
118 * register space access macros
119 */
120 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
121
122 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
123
124 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
125
126 #define CSR_BARRIER(sc, reg, length, flags) \
127 bus_barrier(sc->sis_res[0], reg, length, flags)
128
129 /*
130 * Various supported device vendors/types and their names.
131 */
132 static const struct sis_type sis_devs[] = {
133 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
134 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
135 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
136 { 0, 0, NULL }
137 };
138
139 static int sis_detach(device_t);
140 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
141 static int sis_dma_alloc(struct sis_softc *);
142 static void sis_dma_free(struct sis_softc *);
143 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
144 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
145 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
146 #ifndef __NO_STRICT_ALIGNMENT
147 static __inline void sis_fixup_rx(struct mbuf *);
148 #endif
149 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150 static int sis_ifmedia_upd(struct ifnet *);
151 static void sis_init(void *);
152 static void sis_initl(struct sis_softc *);
153 static void sis_intr(void *);
154 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
155 static uint32_t sis_mii_bitbang_read(device_t);
156 static void sis_mii_bitbang_write(device_t, uint32_t);
157 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
158 static int sis_resume(device_t);
159 static int sis_rxeof(struct sis_softc *);
160 static void sis_rxfilter(struct sis_softc *);
161 static void sis_rxfilter_ns(struct sis_softc *);
162 static void sis_rxfilter_sis(struct sis_softc *);
163 static void sis_start(struct ifnet *);
164 static void sis_startl(struct ifnet *);
165 static void sis_stop(struct sis_softc *);
166 static int sis_suspend(device_t);
167 static void sis_add_sysctls(struct sis_softc *);
168 static void sis_watchdog(struct sis_softc *);
169 static void sis_wol(struct sis_softc *);
170
171 /*
172 * MII bit-bang glue
173 */
174 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
175 sis_mii_bitbang_read,
176 sis_mii_bitbang_write,
177 {
178 SIS_MII_DATA, /* MII_BIT_MDO */
179 SIS_MII_DATA, /* MII_BIT_MDI */
180 SIS_MII_CLK, /* MII_BIT_MDC */
181 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
182 0, /* MII_BIT_DIR_PHY_HOST */
183 }
184 };
185
186 static struct resource_spec sis_res_spec[] = {
187 #ifdef SIS_USEIOSPACE
188 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
189 #else
190 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
191 #endif
192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
193 { -1, 0 }
194 };
195
196 #define SIS_SETBIT(sc, reg, x) \
197 CSR_WRITE_4(sc, reg, \
198 CSR_READ_4(sc, reg) | (x))
199
200 #define SIS_CLRBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, \
202 CSR_READ_4(sc, reg) & ~(x))
203
204 #define SIO_SET(x) \
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206
207 #define SIO_CLR(x) \
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
209
210 /*
211 * Routine to reverse the bits in a word. Stolen almost
212 * verbatim from /usr/games/fortune.
213 */
214 static uint16_t
215 sis_reverse(uint16_t n)
216 {
217 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
218 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
219 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
220 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
221
222 return (n);
223 }
224
225 static void
226 sis_delay(struct sis_softc *sc)
227 {
228 int idx;
229
230 for (idx = (300 / 33) + 1; idx > 0; idx--)
231 CSR_READ_4(sc, SIS_CSR);
232 }
233
234 static void
235 sis_eeprom_idle(struct sis_softc *sc)
236 {
237 int i;
238
239 SIO_SET(SIS_EECTL_CSEL);
240 sis_delay(sc);
241 SIO_SET(SIS_EECTL_CLK);
242 sis_delay(sc);
243
244 for (i = 0; i < 25; i++) {
245 SIO_CLR(SIS_EECTL_CLK);
246 sis_delay(sc);
247 SIO_SET(SIS_EECTL_CLK);
248 sis_delay(sc);
249 }
250
251 SIO_CLR(SIS_EECTL_CLK);
252 sis_delay(sc);
253 SIO_CLR(SIS_EECTL_CSEL);
254 sis_delay(sc);
255 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
256 }
257
258 /*
259 * Send a read command and address to the EEPROM, check for ACK.
260 */
261 static void
262 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
263 {
264 int d, i;
265
266 d = addr | SIS_EECMD_READ;
267
268 /*
269 * Feed in each bit and stobe the clock.
270 */
271 for (i = 0x400; i; i >>= 1) {
272 if (d & i) {
273 SIO_SET(SIS_EECTL_DIN);
274 } else {
275 SIO_CLR(SIS_EECTL_DIN);
276 }
277 sis_delay(sc);
278 SIO_SET(SIS_EECTL_CLK);
279 sis_delay(sc);
280 SIO_CLR(SIS_EECTL_CLK);
281 sis_delay(sc);
282 }
283 }
284
285 /*
286 * Read a word of data stored in the EEPROM at address 'addr.'
287 */
288 static void
289 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
290 {
291 int i;
292 uint16_t word = 0;
293
294 /* Force EEPROM to idle state. */
295 sis_eeprom_idle(sc);
296
297 /* Enter EEPROM access mode. */
298 sis_delay(sc);
299 SIO_CLR(SIS_EECTL_CLK);
300 sis_delay(sc);
301 SIO_SET(SIS_EECTL_CSEL);
302 sis_delay(sc);
303
304 /*
305 * Send address of word we want to read.
306 */
307 sis_eeprom_putbyte(sc, addr);
308
309 /*
310 * Start reading bits from EEPROM.
311 */
312 for (i = 0x8000; i; i >>= 1) {
313 SIO_SET(SIS_EECTL_CLK);
314 sis_delay(sc);
315 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
316 word |= i;
317 sis_delay(sc);
318 SIO_CLR(SIS_EECTL_CLK);
319 sis_delay(sc);
320 }
321
322 /* Turn off EEPROM access mode. */
323 sis_eeprom_idle(sc);
324
325 *dest = word;
326 }
327
328 /*
329 * Read a sequence of words from the EEPROM.
330 */
331 static void
332 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
333 {
334 int i;
335 uint16_t word = 0, *ptr;
336
337 for (i = 0; i < cnt; i++) {
338 sis_eeprom_getword(sc, off + i, &word);
339 ptr = (uint16_t *)(dest + (i * 2));
340 if (swap)
341 *ptr = ntohs(word);
342 else
343 *ptr = word;
344 }
345 }
346
347 #if defined(__i386__) || defined(__amd64__)
348 static device_t
349 sis_find_bridge(device_t dev)
350 {
351 devclass_t pci_devclass;
352 device_t *pci_devices;
353 int pci_count = 0;
354 device_t *pci_children;
355 int pci_childcount = 0;
356 device_t *busp, *childp;
357 device_t child = NULL;
358 int i, j;
359
360 if ((pci_devclass = devclass_find("pci")) == NULL)
361 return (NULL);
362
363 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
364
365 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
366 if (device_get_children(*busp, &pci_children, &pci_childcount))
367 continue;
368 for (j = 0, childp = pci_children;
369 j < pci_childcount; j++, childp++) {
370 if (pci_get_vendor(*childp) == SIS_VENDORID &&
371 pci_get_device(*childp) == 0x0008) {
372 child = *childp;
373 free(pci_children, M_TEMP);
374 goto done;
375 }
376 }
377 free(pci_children, M_TEMP);
378 }
379
380 done:
381 free(pci_devices, M_TEMP);
382 return (child);
383 }
384
385 static void
386 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
387 {
388 device_t bridge;
389 uint8_t reg;
390 int i;
391 bus_space_tag_t btag;
392
393 bridge = sis_find_bridge(dev);
394 if (bridge == NULL)
395 return;
396 reg = pci_read_config(bridge, 0x48, 1);
397 pci_write_config(bridge, 0x48, reg|0x40, 1);
398
399 /* XXX */
400 #if defined(__amd64__) || defined(__i386__)
401 btag = X86_BUS_SPACE_IO;
402 #endif
403
404 for (i = 0; i < cnt; i++) {
405 bus_space_write_1(btag, 0x0, 0x70, i + off);
406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
407 }
408
409 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
410 }
411
412 static void
413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
414 {
415 uint32_t filtsave, csrsave;
416
417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
418 csrsave = CSR_READ_4(sc, SIS_CSR);
419
420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
421 CSR_WRITE_4(sc, SIS_CSR, 0);
422
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
424
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
431
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
433 CSR_WRITE_4(sc, SIS_CSR, csrsave);
434 }
435 #endif
436
437 /*
438 * Read the MII serial port for the MII bit-bang module.
439 */
440 static uint32_t
441 sis_mii_bitbang_read(device_t dev)
442 {
443 struct sis_softc *sc;
444 uint32_t val;
445
446 sc = device_get_softc(dev);
447
448 val = CSR_READ_4(sc, SIS_EECTL);
449 CSR_BARRIER(sc, SIS_EECTL, 4,
450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
451 return (val);
452 }
453
454 /*
455 * Write the MII serial port for the MII bit-bang module.
456 */
457 static void
458 sis_mii_bitbang_write(device_t dev, uint32_t val)
459 {
460 struct sis_softc *sc;
461
462 sc = device_get_softc(dev);
463
464 CSR_WRITE_4(sc, SIS_EECTL, val);
465 CSR_BARRIER(sc, SIS_EECTL, 4,
466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
467 }
468
469 static int
470 sis_miibus_readreg(device_t dev, int phy, int reg)
471 {
472 struct sis_softc *sc;
473
474 sc = device_get_softc(dev);
475
476 if (sc->sis_type == SIS_TYPE_83815) {
477 if (phy != 0)
478 return (0);
479 /*
480 * The NatSemi chip can take a while after
481 * a reset to come ready, during which the BMSR
482 * returns a value of 0. This is *never* supposed
483 * to happen: some of the BMSR bits are meant to
484 * be hardwired in the on position, and this can
485 * confuse the miibus code a bit during the probe
486 * and attach phase. So we make an effort to check
487 * for this condition and wait for it to clear.
488 */
489 if (!CSR_READ_4(sc, NS_BMSR))
490 DELAY(1000);
491 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
492 }
493
494 /*
495 * Chipsets < SIS_635 seem not to be able to read/write
496 * through mdio. Use the enhanced PHY access register
497 * again for them.
498 */
499 if (sc->sis_type == SIS_TYPE_900 &&
500 sc->sis_rev < SIS_REV_635) {
501 int i, val = 0;
502
503 if (phy != 0)
504 return (0);
505
506 CSR_WRITE_4(sc, SIS_PHYCTL,
507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
508 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
509
510 for (i = 0; i < SIS_TIMEOUT; i++) {
511 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
512 break;
513 }
514
515 if (i == SIS_TIMEOUT) {
516 device_printf(sc->sis_dev,
517 "PHY failed to come ready\n");
518 return (0);
519 }
520
521 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
522
523 if (val == 0xFFFF)
524 return (0);
525
526 return (val);
527 } else
528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
529 reg));
530 }
531
532 static int
533 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
534 {
535 struct sis_softc *sc;
536
537 sc = device_get_softc(dev);
538
539 if (sc->sis_type == SIS_TYPE_83815) {
540 if (phy != 0)
541 return (0);
542 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
543 return (0);
544 }
545
546 /*
547 * Chipsets < SIS_635 seem not to be able to read/write
548 * through mdio. Use the enhanced PHY access register
549 * again for them.
550 */
551 if (sc->sis_type == SIS_TYPE_900 &&
552 sc->sis_rev < SIS_REV_635) {
553 int i;
554
555 if (phy != 0)
556 return (0);
557
558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
559 (reg << 6) | SIS_PHYOP_WRITE);
560 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
561
562 for (i = 0; i < SIS_TIMEOUT; i++) {
563 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
564 break;
565 }
566
567 if (i == SIS_TIMEOUT)
568 device_printf(sc->sis_dev,
569 "PHY failed to come ready\n");
570 } else
571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
572 data);
573 return (0);
574 }
575
576 static void
577 sis_miibus_statchg(device_t dev)
578 {
579 struct sis_softc *sc;
580 struct mii_data *mii;
581 struct ifnet *ifp;
582 uint32_t reg;
583
584 sc = device_get_softc(dev);
585 SIS_LOCK_ASSERT(sc);
586
587 mii = device_get_softc(sc->sis_miibus);
588 ifp = sc->sis_ifp;
589 if (mii == NULL || ifp == NULL ||
590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
591 return;
592
593 sc->sis_flags &= ~SIS_FLAG_LINK;
594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
595 (IFM_ACTIVE | IFM_AVALID)) {
596 switch (IFM_SUBTYPE(mii->mii_media_active)) {
597 case IFM_10_T:
598 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
599 sc->sis_flags |= SIS_FLAG_LINK;
600 break;
601 case IFM_100_TX:
602 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
603 sc->sis_flags |= SIS_FLAG_LINK;
604 break;
605 default:
606 break;
607 }
608 }
609
610 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
611 /*
612 * Stopping MACs seem to reset SIS_TX_LISTPTR and
613 * SIS_RX_LISTPTR which in turn requires resetting
614 * TX/RX buffers. So just don't do anything for
615 * lost link.
616 */
617 return;
618 }
619
620 /* Set full/half duplex mode. */
621 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
622 SIS_SETBIT(sc, SIS_TX_CFG,
623 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
624 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
625 } else {
626 SIS_CLRBIT(sc, SIS_TX_CFG,
627 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
628 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
629 }
630
631 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
632 /*
633 * MPII03.D: Half Duplex Excessive Collisions.
634 * Also page 49 in 83816 manual
635 */
636 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
637 }
638
639 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
640 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
641 /*
642 * Short Cable Receive Errors (MP21.E)
643 */
644 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
645 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
646 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
647 DELAY(100);
648 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
649 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
650 device_printf(sc->sis_dev,
651 "Applying short cable fix (reg=%x)\n", reg);
652 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
653 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
654 }
655 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
656 }
657 /* Enable TX/RX MACs. */
658 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
659 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
660 }
661
662 static uint32_t
663 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
664 {
665 uint32_t crc;
666
667 /* Compute CRC for the address value. */
668 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
669
670 /*
671 * return the filter bit position
672 *
673 * The NatSemi chip has a 512-bit filter, which is
674 * different than the SiS, so we special-case it.
675 */
676 if (sc->sis_type == SIS_TYPE_83815)
677 return (crc >> 23);
678 else if (sc->sis_rev >= SIS_REV_635 ||
679 sc->sis_rev == SIS_REV_900B)
680 return (crc >> 24);
681 else
682 return (crc >> 25);
683 }
684
685 static void
686 sis_rxfilter(struct sis_softc *sc)
687 {
688
689 SIS_LOCK_ASSERT(sc);
690
691 if (sc->sis_type == SIS_TYPE_83815)
692 sis_rxfilter_ns(sc);
693 else
694 sis_rxfilter_sis(sc);
695 }
696
697 static u_int
698 sis_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
699 {
700 struct sis_softc *sc = arg;
701 uint32_t h;
702 int bit, index;
703
704 h = sis_mchash(sc, LLADDR(sdl));
705 index = h >> 3;
706 bit = h & 0x1F;
707 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
708 if (bit > 0xF)
709 bit -= 0x10;
710 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
711
712 return (1);
713 }
714
715 static void
716 sis_rxfilter_ns(struct sis_softc *sc)
717 {
718 struct ifnet *ifp;
719 uint32_t i, filter;
720
721 ifp = sc->sis_ifp;
722 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
723 if (filter & SIS_RXFILTCTL_ENABLE) {
724 /*
725 * Filter should be disabled to program other bits.
726 */
727 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
728 CSR_READ_4(sc, SIS_RXFILT_CTL);
729 }
730 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
731 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
732 SIS_RXFILTCTL_ALLMULTI);
733
734 if (ifp->if_flags & IFF_BROADCAST)
735 filter |= SIS_RXFILTCTL_BROAD;
736 /*
737 * For the NatSemi chip, we have to explicitly enable the
738 * reception of ARP frames, as well as turn on the 'perfect
739 * match' filter where we store the station address, otherwise
740 * we won't receive unicasts meant for this host.
741 */
742 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
743
744 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
745 filter |= SIS_RXFILTCTL_ALLMULTI;
746 if (ifp->if_flags & IFF_PROMISC)
747 filter |= SIS_RXFILTCTL_ALLPHYS;
748 } else {
749 /*
750 * We have to explicitly enable the multicast hash table
751 * on the NatSemi chip if we want to use it, which we do.
752 */
753 filter |= NS_RXFILTCTL_MCHASH;
754
755 /* first, zot all the existing hash bits */
756 for (i = 0; i < 32; i++) {
757 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
758 (i * 2));
759 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
760 }
761
762 if_foreach_llmaddr(ifp, sis_write_maddr, sc);
763 }
764
765 /* Turn the receive filter on */
766 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
767 CSR_READ_4(sc, SIS_RXFILT_CTL);
768 }
769
770 struct sis_hash_maddr_ctx {
771 struct sis_softc *sc;
772 uint16_t hashes[16];
773 };
774
775 static u_int
776 sis_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
777 {
778 struct sis_hash_maddr_ctx *ctx = arg;
779 uint32_t h;
780
781 h = sis_mchash(ctx->sc, LLADDR(sdl));
782 ctx->hashes[h >> 4] |= 1 << (h & 0xf);
783
784 return (1);
785 }
786
787 static void
788 sis_rxfilter_sis(struct sis_softc *sc)
789 {
790 struct ifnet *ifp;
791 struct sis_hash_maddr_ctx ctx;
792 uint32_t filter, i, n;
793
794 ifp = sc->sis_ifp;
795
796 /* hash table size */
797 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
798 n = 16;
799 else
800 n = 8;
801
802 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
803 if (filter & SIS_RXFILTCTL_ENABLE) {
804 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
805 CSR_READ_4(sc, SIS_RXFILT_CTL);
806 }
807 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
808 SIS_RXFILTCTL_ALLMULTI);
809 if (ifp->if_flags & IFF_BROADCAST)
810 filter |= SIS_RXFILTCTL_BROAD;
811
812 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
813 filter |= SIS_RXFILTCTL_ALLMULTI;
814 if (ifp->if_flags & IFF_PROMISC)
815 filter |= SIS_RXFILTCTL_ALLPHYS;
816 for (i = 0; i < n; i++)
817 ctx.hashes[i] = ~0;
818 } else {
819 for (i = 0; i < n; i++)
820 ctx.hashes[i] = 0;
821 ctx.sc = sc;
822 if (if_foreach_llmaddr(ifp, sis_hash_maddr, &ctx) > n) {
823 filter |= SIS_RXFILTCTL_ALLMULTI;
824 for (i = 0; i < n; i++)
825 ctx.hashes[i] = ~0;
826 }
827 }
828
829 for (i = 0; i < n; i++) {
830 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
831 CSR_WRITE_4(sc, SIS_RXFILT_DATA, ctx.hashes[i]);
832 }
833
834 /* Turn the receive filter on */
835 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
836 CSR_READ_4(sc, SIS_RXFILT_CTL);
837 }
838
839 static void
840 sis_reset(struct sis_softc *sc)
841 {
842 int i;
843
844 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
845
846 for (i = 0; i < SIS_TIMEOUT; i++) {
847 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
848 break;
849 }
850
851 if (i == SIS_TIMEOUT)
852 device_printf(sc->sis_dev, "reset never completed\n");
853
854 /* Wait a little while for the chip to get its brains in order. */
855 DELAY(1000);
856
857 /*
858 * If this is a NetSemi chip, make sure to clear
859 * PME mode.
860 */
861 if (sc->sis_type == SIS_TYPE_83815) {
862 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
863 CSR_WRITE_4(sc, NS_CLKRUN, 0);
864 } else {
865 /* Disable WOL functions. */
866 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
867 }
868 }
869
870 /*
871 * Probe for an SiS chip. Check the PCI vendor and device
872 * IDs against our list and return a device name if we find a match.
873 */
874 static int
875 sis_probe(device_t dev)
876 {
877 const struct sis_type *t;
878
879 t = sis_devs;
880
881 while (t->sis_name != NULL) {
882 if ((pci_get_vendor(dev) == t->sis_vid) &&
883 (pci_get_device(dev) == t->sis_did)) {
884 device_set_desc(dev, t->sis_name);
885 return (BUS_PROBE_DEFAULT);
886 }
887 t++;
888 }
889
890 return (ENXIO);
891 }
892
893 /*
894 * Attach the interface. Allocate softc structures, do ifmedia
895 * setup and ethernet/BPF attach.
896 */
897 static int
898 sis_attach(device_t dev)
899 {
900 u_char eaddr[ETHER_ADDR_LEN];
901 struct sis_softc *sc;
902 struct ifnet *ifp;
903 int error = 0, pmc;
904
905 sc = device_get_softc(dev);
906
907 sc->sis_dev = dev;
908
909 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
910 MTX_DEF);
911 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
912
913 if (pci_get_device(dev) == SIS_DEVICEID_900)
914 sc->sis_type = SIS_TYPE_900;
915 if (pci_get_device(dev) == SIS_DEVICEID_7016)
916 sc->sis_type = SIS_TYPE_7016;
917 if (pci_get_vendor(dev) == NS_VENDORID)
918 sc->sis_type = SIS_TYPE_83815;
919
920 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
921 /*
922 * Map control/status registers.
923 */
924 pci_enable_busmaster(dev);
925
926 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
927 if (error) {
928 device_printf(dev, "couldn't allocate resources\n");
929 goto fail;
930 }
931
932 /* Reset the adapter. */
933 sis_reset(sc);
934
935 if (sc->sis_type == SIS_TYPE_900 &&
936 (sc->sis_rev == SIS_REV_635 ||
937 sc->sis_rev == SIS_REV_900B)) {
938 SIO_SET(SIS_CFG_RND_CNT);
939 SIO_SET(SIS_CFG_PERR_DETECT);
940 }
941
942 /*
943 * Get station address from the EEPROM.
944 */
945 switch (pci_get_vendor(dev)) {
946 case NS_VENDORID:
947 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
948
949 /* We can't update the device description, so spew */
950 if (sc->sis_srr == NS_SRR_15C)
951 device_printf(dev, "Silicon Revision: DP83815C\n");
952 else if (sc->sis_srr == NS_SRR_15D)
953 device_printf(dev, "Silicon Revision: DP83815D\n");
954 else if (sc->sis_srr == NS_SRR_16A)
955 device_printf(dev, "Silicon Revision: DP83816A\n");
956 else
957 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
958
959 /*
960 * Reading the MAC address out of the EEPROM on
961 * the NatSemi chip takes a bit more work than
962 * you'd expect. The address spans 4 16-bit words,
963 * with the first word containing only a single bit.
964 * You have to shift everything over one bit to
965 * get it aligned properly. Also, the bits are
966 * stored backwards (the LSB is really the MSB,
967 * and so on) so you have to reverse them in order
968 * to get the MAC address into the form we want.
969 * Why? Who the hell knows.
970 */
971 {
972 uint16_t tmp[4];
973
974 sis_read_eeprom(sc, (caddr_t)&tmp,
975 NS_EE_NODEADDR, 4, 0);
976
977 /* Shift everything over one bit. */
978 tmp[3] = tmp[3] >> 1;
979 tmp[3] |= tmp[2] << 15;
980 tmp[2] = tmp[2] >> 1;
981 tmp[2] |= tmp[1] << 15;
982 tmp[1] = tmp[1] >> 1;
983 tmp[1] |= tmp[0] << 15;
984
985 /* Now reverse all the bits. */
986 tmp[3] = sis_reverse(tmp[3]);
987 tmp[2] = sis_reverse(tmp[2]);
988 tmp[1] = sis_reverse(tmp[1]);
989
990 eaddr[0] = (tmp[1] >> 0) & 0xFF;
991 eaddr[1] = (tmp[1] >> 8) & 0xFF;
992 eaddr[2] = (tmp[2] >> 0) & 0xFF;
993 eaddr[3] = (tmp[2] >> 8) & 0xFF;
994 eaddr[4] = (tmp[3] >> 0) & 0xFF;
995 eaddr[5] = (tmp[3] >> 8) & 0xFF;
996 }
997 break;
998 case SIS_VENDORID:
999 default:
1000 #if defined(__i386__) || defined(__amd64__)
1001 /*
1002 * If this is a SiS 630E chipset with an embedded
1003 * SiS 900 controller, we have to read the MAC address
1004 * from the APC CMOS RAM. Our method for doing this
1005 * is very ugly since we have to reach out and grab
1006 * ahold of hardware for which we cannot properly
1007 * allocate resources. This code is only compiled on
1008 * the i386 architecture since the SiS 630E chipset
1009 * is for x86 motherboards only. Note that there are
1010 * a lot of magic numbers in this hack. These are
1011 * taken from SiS's Linux driver. I'd like to replace
1012 * them with proper symbolic definitions, but that
1013 * requires some datasheets that I don't have access
1014 * to at the moment.
1015 */
1016 if (sc->sis_rev == SIS_REV_630S ||
1017 sc->sis_rev == SIS_REV_630E ||
1018 sc->sis_rev == SIS_REV_630EA1)
1019 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1020
1021 else if (sc->sis_rev == SIS_REV_635 ||
1022 sc->sis_rev == SIS_REV_630ET)
1023 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1024 else if (sc->sis_rev == SIS_REV_96x) {
1025 /* Allow to read EEPROM from LAN. It is shared
1026 * between a 1394 controller and the NIC and each
1027 * time we access it, we need to set SIS_EECMD_REQ.
1028 */
1029 SIO_SET(SIS_EECMD_REQ);
1030 for (int waittime = 0; waittime < SIS_TIMEOUT;
1031 waittime++) {
1032 /* Force EEPROM to idle state. */
1033 sis_eeprom_idle(sc);
1034 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1035 sis_read_eeprom(sc, (caddr_t)&eaddr,
1036 SIS_EE_NODEADDR, 3, 0);
1037 break;
1038 }
1039 DELAY(1);
1040 }
1041 /*
1042 * Set SIS_EECTL_CLK to high, so a other master
1043 * can operate on the i2c bus.
1044 */
1045 SIO_SET(SIS_EECTL_CLK);
1046 /* Refuse EEPROM access by LAN */
1047 SIO_SET(SIS_EECMD_DONE);
1048 } else
1049 #endif
1050 sis_read_eeprom(sc, (caddr_t)&eaddr,
1051 SIS_EE_NODEADDR, 3, 0);
1052 break;
1053 }
1054
1055 sis_add_sysctls(sc);
1056
1057 /* Allocate DMA'able memory. */
1058 if ((error = sis_dma_alloc(sc)) != 0)
1059 goto fail;
1060
1061 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1062 if (ifp == NULL) {
1063 device_printf(dev, "can not if_alloc()\n");
1064 error = ENOSPC;
1065 goto fail;
1066 }
1067 ifp->if_softc = sc;
1068 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1070 ifp->if_ioctl = sis_ioctl;
1071 ifp->if_start = sis_start;
1072 ifp->if_init = sis_init;
1073 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1074 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1075 IFQ_SET_READY(&ifp->if_snd);
1076
1077 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1078 if (sc->sis_type == SIS_TYPE_83815)
1079 ifp->if_capabilities |= IFCAP_WOL;
1080 else
1081 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1082 ifp->if_capenable = ifp->if_capabilities;
1083 }
1084
1085 /*
1086 * Do MII setup.
1087 */
1088 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1089 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1090 if (error != 0) {
1091 device_printf(dev, "attaching PHYs failed\n");
1092 goto fail;
1093 }
1094
1095 /*
1096 * Call MI attach routine.
1097 */
1098 ether_ifattach(ifp, eaddr);
1099
1100 /*
1101 * Tell the upper layer(s) we support long frames.
1102 */
1103 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1104 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1105 ifp->if_capenable = ifp->if_capabilities;
1106 #ifdef DEVICE_POLLING
1107 ifp->if_capabilities |= IFCAP_POLLING;
1108 #endif
1109
1110 /* Hook interrupt last to avoid having to lock softc */
1111 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1112 NULL, sis_intr, sc, &sc->sis_intrhand);
1113
1114 if (error) {
1115 device_printf(dev, "couldn't set up irq\n");
1116 ether_ifdetach(ifp);
1117 goto fail;
1118 }
1119
1120 fail:
1121 if (error)
1122 sis_detach(dev);
1123
1124 return (error);
1125 }
1126
1127 /*
1128 * Shutdown hardware and free up resources. This can be called any
1129 * time after the mutex has been initialized. It is called in both
1130 * the error case in attach and the normal detach case so it needs
1131 * to be careful about only freeing resources that have actually been
1132 * allocated.
1133 */
1134 static int
1135 sis_detach(device_t dev)
1136 {
1137 struct sis_softc *sc;
1138 struct ifnet *ifp;
1139
1140 sc = device_get_softc(dev);
1141 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1142 ifp = sc->sis_ifp;
1143
1144 #ifdef DEVICE_POLLING
1145 if (ifp->if_capenable & IFCAP_POLLING)
1146 ether_poll_deregister(ifp);
1147 #endif
1148
1149 /* These should only be active if attach succeeded. */
1150 if (device_is_attached(dev)) {
1151 SIS_LOCK(sc);
1152 sis_stop(sc);
1153 SIS_UNLOCK(sc);
1154 callout_drain(&sc->sis_stat_ch);
1155 ether_ifdetach(ifp);
1156 }
1157 if (sc->sis_miibus)
1158 device_delete_child(dev, sc->sis_miibus);
1159 bus_generic_detach(dev);
1160
1161 if (sc->sis_intrhand)
1162 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1163 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1164
1165 if (ifp)
1166 if_free(ifp);
1167
1168 sis_dma_free(sc);
1169
1170 mtx_destroy(&sc->sis_mtx);
1171
1172 return (0);
1173 }
1174
1175 struct sis_dmamap_arg {
1176 bus_addr_t sis_busaddr;
1177 };
1178
1179 static void
1180 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1181 {
1182 struct sis_dmamap_arg *ctx;
1183
1184 if (error != 0)
1185 return;
1186
1187 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1188
1189 ctx = (struct sis_dmamap_arg *)arg;
1190 ctx->sis_busaddr = segs[0].ds_addr;
1191 }
1192
1193 static int
1194 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1195 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1196 bus_addr_t *paddr, const char *msg)
1197 {
1198 struct sis_dmamap_arg ctx;
1199 int error;
1200
1201 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1202 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1203 maxsize, 0, NULL, NULL, tag);
1204 if (error != 0) {
1205 device_printf(sc->sis_dev,
1206 "could not create %s dma tag\n", msg);
1207 return (ENOMEM);
1208 }
1209 /* Allocate DMA'able memory for ring. */
1210 error = bus_dmamem_alloc(*tag, (void **)ring,
1211 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1212 if (error != 0) {
1213 device_printf(sc->sis_dev,
1214 "could not allocate DMA'able memory for %s\n", msg);
1215 return (ENOMEM);
1216 }
1217 /* Load the address of the ring. */
1218 ctx.sis_busaddr = 0;
1219 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1220 &ctx, BUS_DMA_NOWAIT);
1221 if (error != 0) {
1222 device_printf(sc->sis_dev,
1223 "could not load DMA'able memory for %s\n", msg);
1224 return (ENOMEM);
1225 }
1226 *paddr = ctx.sis_busaddr;
1227 return (0);
1228 }
1229
1230 static int
1231 sis_dma_alloc(struct sis_softc *sc)
1232 {
1233 struct sis_rxdesc *rxd;
1234 struct sis_txdesc *txd;
1235 int error, i;
1236
1237 /* Allocate the parent bus DMA tag appropriate for PCI. */
1238 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1239 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1240 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1241 0, NULL, NULL, &sc->sis_parent_tag);
1242 if (error != 0) {
1243 device_printf(sc->sis_dev,
1244 "could not allocate parent dma tag\n");
1245 return (ENOMEM);
1246 }
1247
1248 /* Create RX ring. */
1249 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1250 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1251 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1252 if (error)
1253 return (error);
1254
1255 /* Create TX ring. */
1256 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1257 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1258 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1259 if (error)
1260 return (error);
1261
1262 /* Create tag for RX mbufs. */
1263 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1264 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1265 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1266 if (error) {
1267 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1268 return (error);
1269 }
1270
1271 /* Create tag for TX mbufs. */
1272 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1273 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1274 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1275 &sc->sis_tx_tag);
1276 if (error) {
1277 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1278 return (error);
1279 }
1280
1281 /* Create DMA maps for RX buffers. */
1282 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1283 if (error) {
1284 device_printf(sc->sis_dev,
1285 "can't create spare DMA map for RX\n");
1286 return (error);
1287 }
1288 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1289 rxd = &sc->sis_rxdesc[i];
1290 rxd->rx_m = NULL;
1291 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1292 if (error) {
1293 device_printf(sc->sis_dev,
1294 "can't create DMA map for RX\n");
1295 return (error);
1296 }
1297 }
1298
1299 /* Create DMA maps for TX buffers. */
1300 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1301 txd = &sc->sis_txdesc[i];
1302 txd->tx_m = NULL;
1303 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1304 if (error) {
1305 device_printf(sc->sis_dev,
1306 "can't create DMA map for TX\n");
1307 return (error);
1308 }
1309 }
1310
1311 return (0);
1312 }
1313
1314 static void
1315 sis_dma_free(struct sis_softc *sc)
1316 {
1317 struct sis_rxdesc *rxd;
1318 struct sis_txdesc *txd;
1319 int i;
1320
1321 /* Destroy DMA maps for RX buffers. */
1322 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1323 rxd = &sc->sis_rxdesc[i];
1324 if (rxd->rx_dmamap)
1325 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1326 }
1327 if (sc->sis_rx_sparemap)
1328 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1329
1330 /* Destroy DMA maps for TX buffers. */
1331 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1332 txd = &sc->sis_txdesc[i];
1333 if (txd->tx_dmamap)
1334 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1335 }
1336
1337 if (sc->sis_rx_tag)
1338 bus_dma_tag_destroy(sc->sis_rx_tag);
1339 if (sc->sis_tx_tag)
1340 bus_dma_tag_destroy(sc->sis_tx_tag);
1341
1342 /* Destroy RX ring. */
1343 if (sc->sis_rx_paddr)
1344 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1345 if (sc->sis_rx_list)
1346 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1347 sc->sis_rx_list_map);
1348
1349 if (sc->sis_rx_list_tag)
1350 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1351
1352 /* Destroy TX ring. */
1353 if (sc->sis_tx_paddr)
1354 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1355
1356 if (sc->sis_tx_list)
1357 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1358 sc->sis_tx_list_map);
1359
1360 if (sc->sis_tx_list_tag)
1361 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1362
1363 /* Destroy the parent tag. */
1364 if (sc->sis_parent_tag)
1365 bus_dma_tag_destroy(sc->sis_parent_tag);
1366 }
1367
1368 /*
1369 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1370 * we arrange the descriptors in a closed ring, so that the last descriptor
1371 * points back to the first.
1372 */
1373 static int
1374 sis_ring_init(struct sis_softc *sc)
1375 {
1376 struct sis_rxdesc *rxd;
1377 struct sis_txdesc *txd;
1378 bus_addr_t next;
1379 int error, i;
1380
1381 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1382 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1383 txd = &sc->sis_txdesc[i];
1384 txd->tx_m = NULL;
1385 if (i == SIS_TX_LIST_CNT - 1)
1386 next = SIS_TX_RING_ADDR(sc, 0);
1387 else
1388 next = SIS_TX_RING_ADDR(sc, i + 1);
1389 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1390 }
1391 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1392 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1394
1395 sc->sis_rx_cons = 0;
1396 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1397 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1398 rxd = &sc->sis_rxdesc[i];
1399 rxd->rx_desc = &sc->sis_rx_list[i];
1400 if (i == SIS_RX_LIST_CNT - 1)
1401 next = SIS_RX_RING_ADDR(sc, 0);
1402 else
1403 next = SIS_RX_RING_ADDR(sc, i + 1);
1404 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1405 error = sis_newbuf(sc, rxd);
1406 if (error)
1407 return (error);
1408 }
1409 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1410 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1411
1412 return (0);
1413 }
1414
1415 /*
1416 * Initialize an RX descriptor and attach an MBUF cluster.
1417 */
1418 static int
1419 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1420 {
1421 struct mbuf *m;
1422 bus_dma_segment_t segs[1];
1423 bus_dmamap_t map;
1424 int nsegs;
1425
1426 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1427 if (m == NULL)
1428 return (ENOBUFS);
1429 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1430 #ifndef __NO_STRICT_ALIGNMENT
1431 m_adj(m, SIS_RX_BUF_ALIGN);
1432 #endif
1433
1434 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1435 segs, &nsegs, 0) != 0) {
1436 m_freem(m);
1437 return (ENOBUFS);
1438 }
1439 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1440
1441 if (rxd->rx_m != NULL) {
1442 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1443 BUS_DMASYNC_POSTREAD);
1444 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1445 }
1446 map = rxd->rx_dmamap;
1447 rxd->rx_dmamap = sc->sis_rx_sparemap;
1448 sc->sis_rx_sparemap = map;
1449 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1450 rxd->rx_m = m;
1451 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1452 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1453 return (0);
1454 }
1455
1456 static __inline void
1457 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1458 {
1459
1460 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1461 }
1462
1463 #ifndef __NO_STRICT_ALIGNMENT
1464 static __inline void
1465 sis_fixup_rx(struct mbuf *m)
1466 {
1467 uint16_t *src, *dst;
1468 int i;
1469
1470 src = mtod(m, uint16_t *);
1471 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1472
1473 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1474 *dst++ = *src++;
1475
1476 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1477 }
1478 #endif
1479
1480 /*
1481 * A frame has been uploaded: pass the resulting mbuf chain up to
1482 * the higher level protocols.
1483 */
1484 static int
1485 sis_rxeof(struct sis_softc *sc)
1486 {
1487 struct mbuf *m;
1488 struct ifnet *ifp;
1489 struct sis_rxdesc *rxd;
1490 struct sis_desc *cur_rx;
1491 int prog, rx_cons, rx_npkts = 0, total_len;
1492 uint32_t rxstat;
1493
1494 SIS_LOCK_ASSERT(sc);
1495
1496 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1497 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1498
1499 rx_cons = sc->sis_rx_cons;
1500 ifp = sc->sis_ifp;
1501
1502 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1503 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1504 #ifdef DEVICE_POLLING
1505 if (ifp->if_capenable & IFCAP_POLLING) {
1506 if (sc->rxcycles <= 0)
1507 break;
1508 sc->rxcycles--;
1509 }
1510 #endif
1511 cur_rx = &sc->sis_rx_list[rx_cons];
1512 rxstat = le32toh(cur_rx->sis_cmdsts);
1513 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1514 break;
1515 rxd = &sc->sis_rxdesc[rx_cons];
1516
1517 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1518 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1519 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1520 ETHER_CRC_LEN))
1521 rxstat &= ~SIS_RXSTAT_GIANT;
1522 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1523 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1524 if (rxstat & SIS_RXSTAT_COLL)
1525 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1526 sis_discard_rxbuf(rxd);
1527 continue;
1528 }
1529
1530 /* Add a new receive buffer to the ring. */
1531 m = rxd->rx_m;
1532 if (sis_newbuf(sc, rxd) != 0) {
1533 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1534 sis_discard_rxbuf(rxd);
1535 continue;
1536 }
1537
1538 /* No errors; receive the packet. */
1539 m->m_pkthdr.len = m->m_len = total_len;
1540 #ifndef __NO_STRICT_ALIGNMENT
1541 /*
1542 * On architectures without alignment problems we try to
1543 * allocate a new buffer for the receive ring, and pass up
1544 * the one where the packet is already, saving the expensive
1545 * copy operation.
1546 */
1547 sis_fixup_rx(m);
1548 #endif
1549 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1550 m->m_pkthdr.rcvif = ifp;
1551
1552 SIS_UNLOCK(sc);
1553 (*ifp->if_input)(ifp, m);
1554 SIS_LOCK(sc);
1555 rx_npkts++;
1556 }
1557
1558 if (prog > 0) {
1559 sc->sis_rx_cons = rx_cons;
1560 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1561 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1562 }
1563
1564 return (rx_npkts);
1565 }
1566
1567 /*
1568 * A frame was downloaded to the chip. It's safe for us to clean up
1569 * the list buffers.
1570 */
1571
1572 static void
1573 sis_txeof(struct sis_softc *sc)
1574 {
1575 struct ifnet *ifp;
1576 struct sis_desc *cur_tx;
1577 struct sis_txdesc *txd;
1578 uint32_t cons, txstat;
1579
1580 SIS_LOCK_ASSERT(sc);
1581
1582 cons = sc->sis_tx_cons;
1583 if (cons == sc->sis_tx_prod)
1584 return;
1585
1586 ifp = sc->sis_ifp;
1587 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1588 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1589
1590 /*
1591 * Go through our tx list and free mbufs for those
1592 * frames that have been transmitted.
1593 */
1594 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1595 cur_tx = &sc->sis_tx_list[cons];
1596 txstat = le32toh(cur_tx->sis_cmdsts);
1597 if ((txstat & SIS_CMDSTS_OWN) != 0)
1598 break;
1599 txd = &sc->sis_txdesc[cons];
1600 if (txd->tx_m != NULL) {
1601 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1602 BUS_DMASYNC_POSTWRITE);
1603 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1604 m_freem(txd->tx_m);
1605 txd->tx_m = NULL;
1606 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1607 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1608 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1609 (txstat & SIS_TXSTAT_COLLCNT) >> 16);
1610 } else {
1611 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1612 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1613 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1614 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1615 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1616 }
1617 }
1618 sc->sis_tx_cnt--;
1619 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1620 }
1621 sc->sis_tx_cons = cons;
1622 if (sc->sis_tx_cnt == 0)
1623 sc->sis_watchdog_timer = 0;
1624 }
1625
1626 static void
1627 sis_tick(void *xsc)
1628 {
1629 struct sis_softc *sc;
1630 struct mii_data *mii;
1631
1632 sc = xsc;
1633 SIS_LOCK_ASSERT(sc);
1634
1635 mii = device_get_softc(sc->sis_miibus);
1636 mii_tick(mii);
1637 sis_watchdog(sc);
1638 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1639 sis_miibus_statchg(sc->sis_dev);
1640 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1641 }
1642
1643 #ifdef DEVICE_POLLING
1644 static poll_handler_t sis_poll;
1645
1646 static int
1647 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1648 {
1649 struct sis_softc *sc = ifp->if_softc;
1650 int rx_npkts = 0;
1651
1652 SIS_LOCK(sc);
1653 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1654 SIS_UNLOCK(sc);
1655 return (rx_npkts);
1656 }
1657
1658 /*
1659 * On the sis, reading the status register also clears it.
1660 * So before returning to intr mode we must make sure that all
1661 * possible pending sources of interrupts have been served.
1662 * In practice this means run to completion the *eof routines,
1663 * and then call the interrupt routine
1664 */
1665 sc->rxcycles = count;
1666 rx_npkts = sis_rxeof(sc);
1667 sis_txeof(sc);
1668 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1669 sis_startl(ifp);
1670
1671 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1672 uint32_t status;
1673
1674 /* Reading the ISR register clears all interrupts. */
1675 status = CSR_READ_4(sc, SIS_ISR);
1676
1677 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1678 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1679
1680 if (status & (SIS_ISR_RX_IDLE))
1681 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1682
1683 if (status & SIS_ISR_SYSERR) {
1684 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1685 sis_initl(sc);
1686 }
1687 }
1688
1689 SIS_UNLOCK(sc);
1690 return (rx_npkts);
1691 }
1692 #endif /* DEVICE_POLLING */
1693
1694 static void
1695 sis_intr(void *arg)
1696 {
1697 struct sis_softc *sc;
1698 struct ifnet *ifp;
1699 uint32_t status;
1700
1701 sc = arg;
1702 ifp = sc->sis_ifp;
1703
1704 SIS_LOCK(sc);
1705 #ifdef DEVICE_POLLING
1706 if (ifp->if_capenable & IFCAP_POLLING) {
1707 SIS_UNLOCK(sc);
1708 return;
1709 }
1710 #endif
1711
1712 /* Reading the ISR register clears all interrupts. */
1713 status = CSR_READ_4(sc, SIS_ISR);
1714 if ((status & SIS_INTRS) == 0) {
1715 /* Not ours. */
1716 SIS_UNLOCK(sc);
1717 return;
1718 }
1719
1720 /* Disable interrupts. */
1721 CSR_WRITE_4(sc, SIS_IER, 0);
1722
1723 for (;(status & SIS_INTRS) != 0;) {
1724 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1725 break;
1726 if (status &
1727 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1728 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1729 sis_txeof(sc);
1730
1731 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1732 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1733 sis_rxeof(sc);
1734
1735 if (status & SIS_ISR_RX_OFLOW)
1736 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1737
1738 if (status & (SIS_ISR_RX_IDLE))
1739 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1740
1741 if (status & SIS_ISR_SYSERR) {
1742 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1743 sis_initl(sc);
1744 SIS_UNLOCK(sc);
1745 return;
1746 }
1747 status = CSR_READ_4(sc, SIS_ISR);
1748 }
1749
1750 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1751 /* Re-enable interrupts. */
1752 CSR_WRITE_4(sc, SIS_IER, 1);
1753
1754 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1755 sis_startl(ifp);
1756 }
1757
1758 SIS_UNLOCK(sc);
1759 }
1760
1761 /*
1762 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1763 * pointers to the fragment pointers.
1764 */
1765 static int
1766 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1767 {
1768 struct mbuf *m;
1769 struct sis_txdesc *txd;
1770 struct sis_desc *f;
1771 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1772 bus_dmamap_t map;
1773 int error, i, frag, nsegs, prod;
1774 int padlen;
1775
1776 prod = sc->sis_tx_prod;
1777 txd = &sc->sis_txdesc[prod];
1778 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1779 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1780 m = *m_head;
1781 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1782 if (M_WRITABLE(m) == 0) {
1783 /* Get a writable copy. */
1784 m = m_dup(*m_head, M_NOWAIT);
1785 m_freem(*m_head);
1786 if (m == NULL) {
1787 *m_head = NULL;
1788 return (ENOBUFS);
1789 }
1790 *m_head = m;
1791 }
1792 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1793 m = m_defrag(m, M_NOWAIT);
1794 if (m == NULL) {
1795 m_freem(*m_head);
1796 *m_head = NULL;
1797 return (ENOBUFS);
1798 }
1799 }
1800 /*
1801 * Manually pad short frames, and zero the pad space
1802 * to avoid leaking data.
1803 */
1804 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1805 m->m_pkthdr.len += padlen;
1806 m->m_len = m->m_pkthdr.len;
1807 *m_head = m;
1808 }
1809 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1810 *m_head, segs, &nsegs, 0);
1811 if (error == EFBIG) {
1812 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1813 if (m == NULL) {
1814 m_freem(*m_head);
1815 *m_head = NULL;
1816 return (ENOBUFS);
1817 }
1818 *m_head = m;
1819 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1820 *m_head, segs, &nsegs, 0);
1821 if (error != 0) {
1822 m_freem(*m_head);
1823 *m_head = NULL;
1824 return (error);
1825 }
1826 } else if (error != 0)
1827 return (error);
1828
1829 /* Check for descriptor overruns. */
1830 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1831 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1832 return (ENOBUFS);
1833 }
1834
1835 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1836
1837 frag = prod;
1838 for (i = 0; i < nsegs; i++) {
1839 f = &sc->sis_tx_list[prod];
1840 if (i == 0)
1841 f->sis_cmdsts = htole32(segs[i].ds_len |
1842 SIS_CMDSTS_MORE);
1843 else
1844 f->sis_cmdsts = htole32(segs[i].ds_len |
1845 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1846 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1847 SIS_INC(prod, SIS_TX_LIST_CNT);
1848 sc->sis_tx_cnt++;
1849 }
1850
1851 /* Update producer index. */
1852 sc->sis_tx_prod = prod;
1853
1854 /* Remove MORE flag on the last descriptor. */
1855 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1856 f = &sc->sis_tx_list[prod];
1857 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1858
1859 /* Lastly transfer ownership of packet to the controller. */
1860 f = &sc->sis_tx_list[frag];
1861 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1862
1863 /* Swap the last and the first dmamaps. */
1864 map = txd->tx_dmamap;
1865 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1866 sc->sis_txdesc[prod].tx_dmamap = map;
1867 sc->sis_txdesc[prod].tx_m = *m_head;
1868
1869 return (0);
1870 }
1871
1872 static void
1873 sis_start(struct ifnet *ifp)
1874 {
1875 struct sis_softc *sc;
1876
1877 sc = ifp->if_softc;
1878 SIS_LOCK(sc);
1879 sis_startl(ifp);
1880 SIS_UNLOCK(sc);
1881 }
1882
1883 static void
1884 sis_startl(struct ifnet *ifp)
1885 {
1886 struct sis_softc *sc;
1887 struct mbuf *m_head;
1888 int queued;
1889
1890 sc = ifp->if_softc;
1891
1892 SIS_LOCK_ASSERT(sc);
1893
1894 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1895 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1896 return;
1897
1898 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1899 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1900 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1901 if (m_head == NULL)
1902 break;
1903
1904 if (sis_encap(sc, &m_head) != 0) {
1905 if (m_head == NULL)
1906 break;
1907 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1908 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1909 break;
1910 }
1911
1912 queued++;
1913
1914 /*
1915 * If there's a BPF listener, bounce a copy of this frame
1916 * to him.
1917 */
1918 BPF_MTAP(ifp, m_head);
1919 }
1920
1921 if (queued) {
1922 /* Transmit */
1923 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1925 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1926
1927 /*
1928 * Set a timeout in case the chip goes out to lunch.
1929 */
1930 sc->sis_watchdog_timer = 5;
1931 }
1932 }
1933
1934 static void
1935 sis_init(void *xsc)
1936 {
1937 struct sis_softc *sc = xsc;
1938
1939 SIS_LOCK(sc);
1940 sis_initl(sc);
1941 SIS_UNLOCK(sc);
1942 }
1943
1944 static void
1945 sis_initl(struct sis_softc *sc)
1946 {
1947 struct ifnet *ifp = sc->sis_ifp;
1948 struct mii_data *mii;
1949 uint8_t *eaddr;
1950
1951 SIS_LOCK_ASSERT(sc);
1952
1953 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1954 return;
1955
1956 /*
1957 * Cancel pending I/O and free all RX/TX buffers.
1958 */
1959 sis_stop(sc);
1960 /*
1961 * Reset the chip to a known state.
1962 */
1963 sis_reset(sc);
1964 #ifdef notyet
1965 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1966 /*
1967 * Configure 400usec of interrupt holdoff. This is based
1968 * on empirical tests on a Soekris 4801.
1969 */
1970 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1971 }
1972 #endif
1973
1974 mii = device_get_softc(sc->sis_miibus);
1975
1976 /* Set MAC address */
1977 eaddr = IF_LLADDR(sc->sis_ifp);
1978 if (sc->sis_type == SIS_TYPE_83815) {
1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1981 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1982 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1983 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1984 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1985 } else {
1986 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1987 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1988 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1989 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1990 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1991 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1992 }
1993
1994 /* Init circular TX/RX lists. */
1995 if (sis_ring_init(sc) != 0) {
1996 device_printf(sc->sis_dev,
1997 "initialization failed: no memory for rx buffers\n");
1998 sis_stop(sc);
1999 return;
2000 }
2001
2002 if (sc->sis_type == SIS_TYPE_83815) {
2003 if (sc->sis_manual_pad != 0)
2004 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
2005 else
2006 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2007 }
2008
2009 /*
2010 * Short Cable Receive Errors (MP21.E)
2011 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2012 * recommends the following register settings "for optimum
2013 * performance." for rev 15C. Set this also for 15D parts as
2014 * they require it in practice.
2015 */
2016 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2017 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2018 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2019 /* set val for c2 */
2020 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2021 /* load/kill c2 */
2022 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2023 /* rais SD off, from 4 to c */
2024 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2025 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2026 }
2027
2028 sis_rxfilter(sc);
2029
2030 /*
2031 * Load the address of the RX and TX lists.
2032 */
2033 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2034 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2035
2036 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2037 * the PCI bus. When this bit is set, the Max DMA Burst Size
2038 * for TX/RX DMA should be no larger than 16 double words.
2039 */
2040 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2041 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2042 } else {
2043 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2044 }
2045
2046 /* Accept Long Packets for VLAN support */
2047 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2048
2049 /*
2050 * Assume 100Mbps link, actual MAC configuration is done
2051 * after getting a valid link.
2052 */
2053 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2054
2055 /*
2056 * Enable interrupts.
2057 */
2058 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2059 #ifdef DEVICE_POLLING
2060 /*
2061 * ... only enable interrupts if we are not polling, make sure
2062 * they are off otherwise.
2063 */
2064 if (ifp->if_capenable & IFCAP_POLLING)
2065 CSR_WRITE_4(sc, SIS_IER, 0);
2066 else
2067 #endif
2068 CSR_WRITE_4(sc, SIS_IER, 1);
2069
2070 /* Clear MAC disable. */
2071 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2072
2073 sc->sis_flags &= ~SIS_FLAG_LINK;
2074 mii_mediachg(mii);
2075
2076 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2078
2079 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2080 }
2081
2082 /*
2083 * Set media options.
2084 */
2085 static int
2086 sis_ifmedia_upd(struct ifnet *ifp)
2087 {
2088 struct sis_softc *sc;
2089 struct mii_data *mii;
2090 struct mii_softc *miisc;
2091 int error;
2092
2093 sc = ifp->if_softc;
2094
2095 SIS_LOCK(sc);
2096 mii = device_get_softc(sc->sis_miibus);
2097 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2098 PHY_RESET(miisc);
2099 error = mii_mediachg(mii);
2100 SIS_UNLOCK(sc);
2101
2102 return (error);
2103 }
2104
2105 /*
2106 * Report current media status.
2107 */
2108 static void
2109 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2110 {
2111 struct sis_softc *sc;
2112 struct mii_data *mii;
2113
2114 sc = ifp->if_softc;
2115
2116 SIS_LOCK(sc);
2117 mii = device_get_softc(sc->sis_miibus);
2118 mii_pollstat(mii);
2119 ifmr->ifm_active = mii->mii_media_active;
2120 ifmr->ifm_status = mii->mii_media_status;
2121 SIS_UNLOCK(sc);
2122 }
2123
2124 static int
2125 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2126 {
2127 struct sis_softc *sc = ifp->if_softc;
2128 struct ifreq *ifr = (struct ifreq *) data;
2129 struct mii_data *mii;
2130 int error = 0, mask;
2131
2132 switch (command) {
2133 case SIOCSIFFLAGS:
2134 SIS_LOCK(sc);
2135 if (ifp->if_flags & IFF_UP) {
2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2137 ((ifp->if_flags ^ sc->sis_if_flags) &
2138 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2139 sis_rxfilter(sc);
2140 else
2141 sis_initl(sc);
2142 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2143 sis_stop(sc);
2144 sc->sis_if_flags = ifp->if_flags;
2145 SIS_UNLOCK(sc);
2146 break;
2147 case SIOCADDMULTI:
2148 case SIOCDELMULTI:
2149 SIS_LOCK(sc);
2150 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2151 sis_rxfilter(sc);
2152 SIS_UNLOCK(sc);
2153 break;
2154 case SIOCGIFMEDIA:
2155 case SIOCSIFMEDIA:
2156 mii = device_get_softc(sc->sis_miibus);
2157 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2158 break;
2159 case SIOCSIFCAP:
2160 SIS_LOCK(sc);
2161 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2162 #ifdef DEVICE_POLLING
2163 if ((mask & IFCAP_POLLING) != 0 &&
2164 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2165 ifp->if_capenable ^= IFCAP_POLLING;
2166 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2167 error = ether_poll_register(sis_poll, ifp);
2168 if (error != 0) {
2169 SIS_UNLOCK(sc);
2170 break;
2171 }
2172 /* Disable interrupts. */
2173 CSR_WRITE_4(sc, SIS_IER, 0);
2174 } else {
2175 error = ether_poll_deregister(ifp);
2176 /* Enable interrupts. */
2177 CSR_WRITE_4(sc, SIS_IER, 1);
2178 }
2179 }
2180 #endif /* DEVICE_POLLING */
2181 if ((mask & IFCAP_WOL) != 0 &&
2182 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2183 if ((mask & IFCAP_WOL_UCAST) != 0)
2184 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2185 if ((mask & IFCAP_WOL_MCAST) != 0)
2186 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2187 if ((mask & IFCAP_WOL_MAGIC) != 0)
2188 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2189 }
2190 SIS_UNLOCK(sc);
2191 break;
2192 default:
2193 error = ether_ioctl(ifp, command, data);
2194 break;
2195 }
2196
2197 return (error);
2198 }
2199
2200 static void
2201 sis_watchdog(struct sis_softc *sc)
2202 {
2203
2204 SIS_LOCK_ASSERT(sc);
2205
2206 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2207 return;
2208
2209 device_printf(sc->sis_dev, "watchdog timeout\n");
2210 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
2211
2212 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2213 sis_initl(sc);
2214
2215 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2216 sis_startl(sc->sis_ifp);
2217 }
2218
2219 /*
2220 * Stop the adapter and free any mbufs allocated to the
2221 * RX and TX lists.
2222 */
2223 static void
2224 sis_stop(struct sis_softc *sc)
2225 {
2226 struct ifnet *ifp;
2227 struct sis_rxdesc *rxd;
2228 struct sis_txdesc *txd;
2229 int i;
2230
2231 SIS_LOCK_ASSERT(sc);
2232
2233 ifp = sc->sis_ifp;
2234 sc->sis_watchdog_timer = 0;
2235
2236 callout_stop(&sc->sis_stat_ch);
2237
2238 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2239 CSR_WRITE_4(sc, SIS_IER, 0);
2240 CSR_WRITE_4(sc, SIS_IMR, 0);
2241 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2242 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2243 DELAY(1000);
2244 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2245 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2246
2247 sc->sis_flags &= ~SIS_FLAG_LINK;
2248
2249 /*
2250 * Free data in the RX lists.
2251 */
2252 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2253 rxd = &sc->sis_rxdesc[i];
2254 if (rxd->rx_m != NULL) {
2255 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2256 BUS_DMASYNC_POSTREAD);
2257 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2258 m_freem(rxd->rx_m);
2259 rxd->rx_m = NULL;
2260 }
2261 }
2262
2263 /*
2264 * Free the TX list buffers.
2265 */
2266 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2267 txd = &sc->sis_txdesc[i];
2268 if (txd->tx_m != NULL) {
2269 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2270 BUS_DMASYNC_POSTWRITE);
2271 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2272 m_freem(txd->tx_m);
2273 txd->tx_m = NULL;
2274 }
2275 }
2276 }
2277
2278 /*
2279 * Stop all chip I/O so that the kernel's probe routines don't
2280 * get confused by errant DMAs when rebooting.
2281 */
2282 static int
2283 sis_shutdown(device_t dev)
2284 {
2285
2286 return (sis_suspend(dev));
2287 }
2288
2289 static int
2290 sis_suspend(device_t dev)
2291 {
2292 struct sis_softc *sc;
2293
2294 sc = device_get_softc(dev);
2295 SIS_LOCK(sc);
2296 sis_stop(sc);
2297 sis_wol(sc);
2298 SIS_UNLOCK(sc);
2299 return (0);
2300 }
2301
2302 static int
2303 sis_resume(device_t dev)
2304 {
2305 struct sis_softc *sc;
2306 struct ifnet *ifp;
2307
2308 sc = device_get_softc(dev);
2309 SIS_LOCK(sc);
2310 ifp = sc->sis_ifp;
2311 if ((ifp->if_flags & IFF_UP) != 0) {
2312 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2313 sis_initl(sc);
2314 }
2315 SIS_UNLOCK(sc);
2316 return (0);
2317 }
2318
2319 static void
2320 sis_wol(struct sis_softc *sc)
2321 {
2322 struct ifnet *ifp;
2323 uint32_t val;
2324 uint16_t pmstat;
2325 int pmc;
2326
2327 ifp = sc->sis_ifp;
2328 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2329 return;
2330
2331 if (sc->sis_type == SIS_TYPE_83815) {
2332 /* Reset RXDP. */
2333 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2334
2335 /* Configure WOL events. */
2336 CSR_READ_4(sc, NS_WCSR);
2337 val = 0;
2338 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2339 val |= NS_WCSR_WAKE_UCAST;
2340 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2341 val |= NS_WCSR_WAKE_MCAST;
2342 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2343 val |= NS_WCSR_WAKE_MAGIC;
2344 CSR_WRITE_4(sc, NS_WCSR, val);
2345 /* Enable PME and clear PMESTS. */
2346 val = CSR_READ_4(sc, NS_CLKRUN);
2347 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2348 CSR_WRITE_4(sc, NS_CLKRUN, val);
2349 /* Enable silent RX mode. */
2350 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2351 } else {
2352 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2353 return;
2354 val = 0;
2355 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2356 val |= SIS_PWRMAN_WOL_MAGIC;
2357 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2358 /* Request PME. */
2359 pmstat = pci_read_config(sc->sis_dev,
2360 pmc + PCIR_POWER_STATUS, 2);
2361 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2362 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2363 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2364 pci_write_config(sc->sis_dev,
2365 pmc + PCIR_POWER_STATUS, pmstat, 2);
2366 }
2367 }
2368
2369 static void
2370 sis_add_sysctls(struct sis_softc *sc)
2371 {
2372 struct sysctl_ctx_list *ctx;
2373 struct sysctl_oid_list *children;
2374
2375 ctx = device_get_sysctl_ctx(sc->sis_dev);
2376 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2377
2378 /*
2379 * Unlike most other controllers, NS DP83815/DP83816 controllers
2380 * seem to pad with 0xFF when it encounter short frames. According
2381 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2382 * on will have driver pad manully but it's disabled by default
2383 * because it will consume extra CPU cycles for short frames.
2384 */
2385 sc->sis_manual_pad = 0;
2386 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2387 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
2388 }
2389
2390 static device_method_t sis_methods[] = {
2391 /* Device interface */
2392 DEVMETHOD(device_probe, sis_probe),
2393 DEVMETHOD(device_attach, sis_attach),
2394 DEVMETHOD(device_detach, sis_detach),
2395 DEVMETHOD(device_shutdown, sis_shutdown),
2396 DEVMETHOD(device_suspend, sis_suspend),
2397 DEVMETHOD(device_resume, sis_resume),
2398
2399 /* MII interface */
2400 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2401 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2402 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2403
2404 DEVMETHOD_END
2405 };
2406
2407 static driver_t sis_driver = {
2408 "sis",
2409 sis_methods,
2410 sizeof(struct sis_softc)
2411 };
2412
2413 DRIVER_MODULE(sis, pci, sis_driver, 0, 0);
2414 DRIVER_MODULE(miibus, sis, miibus_driver, 0, 0);
Cache object: dbf8032a2c21adfd426b5aa14641c877
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