The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sis/if_sis.c

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    1 /*-
    2  * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
    3  * Copyright (c) 1997, 1998, 1999
    4  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: releng/10.0/sys/dev/sis/if_sis.c 248456 2013-03-18 04:46:17Z yongari $");
   36 
   37 /*
   38  * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
   39  * available from http://www.sis.com.tw.
   40  *
   41  * This driver also supports the NatSemi DP83815. Datasheets are
   42  * available from http://www.national.com.
   43  *
   44  * Written by Bill Paul <wpaul@ee.columbia.edu>
   45  * Electrical Engineering Department
   46  * Columbia University, New York City
   47  */
   48 /*
   49  * The SiS 900 is a fairly simple chip. It uses bus master DMA with
   50  * simple TX and RX descriptors of 3 longwords in size. The receiver
   51  * has a single perfect filter entry for the station address and a
   52  * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
   53  * transceiver while the 7016 requires an external transceiver chip.
   54  * Both chips offer the standard bit-bang MII interface as well as
   55  * an enchanced PHY interface which simplifies accessing MII registers.
   56  *
   57  * The only downside to this chipset is that RX descriptors must be
   58  * longword aligned.
   59  */
   60 
   61 #ifdef HAVE_KERNEL_OPTION_HEADERS
   62 #include "opt_device_polling.h"
   63 #endif
   64 
   65 #include <sys/param.h>
   66 #include <sys/systm.h>
   67 #include <sys/bus.h>
   68 #include <sys/endian.h>
   69 #include <sys/kernel.h>
   70 #include <sys/lock.h>
   71 #include <sys/malloc.h>
   72 #include <sys/mbuf.h>
   73 #include <sys/module.h>
   74 #include <sys/socket.h>
   75 #include <sys/sockio.h>
   76 #include <sys/sysctl.h>
   77 
   78 #include <net/if.h>
   79 #include <net/if_arp.h>
   80 #include <net/ethernet.h>
   81 #include <net/if_dl.h>
   82 #include <net/if_media.h>
   83 #include <net/if_types.h>
   84 #include <net/if_vlan_var.h>
   85 
   86 #include <net/bpf.h>
   87 
   88 #include <machine/bus.h>
   89 #include <machine/resource.h>
   90 #include <sys/rman.h>
   91 
   92 #include <dev/mii/mii.h>
   93 #include <dev/mii/mii_bitbang.h>
   94 #include <dev/mii/miivar.h>
   95 
   96 #include <dev/pci/pcireg.h>
   97 #include <dev/pci/pcivar.h>
   98 
   99 #define SIS_USEIOSPACE
  100 
  101 #include <dev/sis/if_sisreg.h>
  102 
  103 MODULE_DEPEND(sis, pci, 1, 1, 1);
  104 MODULE_DEPEND(sis, ether, 1, 1, 1);
  105 MODULE_DEPEND(sis, miibus, 1, 1, 1);
  106 
  107 /* "device miibus" required.  See GENERIC if you get errors here. */
  108 #include "miibus_if.h"
  109 
  110 #define SIS_LOCK(_sc)           mtx_lock(&(_sc)->sis_mtx)
  111 #define SIS_UNLOCK(_sc)         mtx_unlock(&(_sc)->sis_mtx)
  112 #define SIS_LOCK_ASSERT(_sc)    mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
  113 
  114 /*
  115  * register space access macros
  116  */
  117 #define CSR_WRITE_4(sc, reg, val)       bus_write_4(sc->sis_res[0], reg, val)
  118 
  119 #define CSR_READ_4(sc, reg)             bus_read_4(sc->sis_res[0], reg)
  120 
  121 #define CSR_READ_2(sc, reg)             bus_read_2(sc->sis_res[0], reg)
  122 
  123 #define CSR_BARRIER(sc, reg, length, flags)                             \
  124         bus_barrier(sc->sis_res[0], reg, length, flags)
  125 
  126 /*
  127  * Various supported device vendors/types and their names.
  128  */
  129 static const struct sis_type sis_devs[] = {
  130         { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
  131         { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
  132         { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
  133         { 0, 0, NULL }
  134 };
  135 
  136 static int sis_detach(device_t);
  137 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
  138 static int sis_dma_alloc(struct sis_softc *);
  139 static void sis_dma_free(struct sis_softc *);
  140 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
  141     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
  142 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
  143 #ifndef __NO_STRICT_ALIGNMENT
  144 static __inline void sis_fixup_rx(struct mbuf *);
  145 #endif
  146 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  147 static int sis_ifmedia_upd(struct ifnet *);
  148 static void sis_init(void *);
  149 static void sis_initl(struct sis_softc *);
  150 static void sis_intr(void *);
  151 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
  152 static uint32_t sis_mii_bitbang_read(device_t);
  153 static void sis_mii_bitbang_write(device_t, uint32_t);
  154 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
  155 static int sis_resume(device_t);
  156 static int sis_rxeof(struct sis_softc *);
  157 static void sis_rxfilter(struct sis_softc *);
  158 static void sis_rxfilter_ns(struct sis_softc *);
  159 static void sis_rxfilter_sis(struct sis_softc *);
  160 static void sis_start(struct ifnet *);
  161 static void sis_startl(struct ifnet *);
  162 static void sis_stop(struct sis_softc *);
  163 static int sis_suspend(device_t);
  164 static void sis_add_sysctls(struct sis_softc *);
  165 static void sis_watchdog(struct sis_softc *);
  166 static void sis_wol(struct sis_softc *);
  167 
  168 /*
  169  * MII bit-bang glue
  170  */
  171 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
  172         sis_mii_bitbang_read,
  173         sis_mii_bitbang_write,
  174         {
  175                 SIS_MII_DATA,           /* MII_BIT_MDO */
  176                 SIS_MII_DATA,           /* MII_BIT_MDI */
  177                 SIS_MII_CLK,            /* MII_BIT_MDC */
  178                 SIS_MII_DIR,            /* MII_BIT_DIR_HOST_PHY */
  179                 0,                      /* MII_BIT_DIR_PHY_HOST */
  180         }
  181 };
  182 
  183 static struct resource_spec sis_res_spec[] = {
  184 #ifdef SIS_USEIOSPACE
  185         { SYS_RES_IOPORT,       SIS_PCI_LOIO,   RF_ACTIVE},
  186 #else
  187         { SYS_RES_MEMORY,       SIS_PCI_LOMEM,  RF_ACTIVE},
  188 #endif
  189         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE},
  190         { -1, 0 }
  191 };
  192 
  193 #define SIS_SETBIT(sc, reg, x)                          \
  194         CSR_WRITE_4(sc, reg,                            \
  195                 CSR_READ_4(sc, reg) | (x))
  196 
  197 #define SIS_CLRBIT(sc, reg, x)                          \
  198         CSR_WRITE_4(sc, reg,                            \
  199                 CSR_READ_4(sc, reg) & ~(x))
  200 
  201 #define SIO_SET(x)                                      \
  202         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
  203 
  204 #define SIO_CLR(x)                                      \
  205         CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
  206 
  207 /*
  208  * Routine to reverse the bits in a word. Stolen almost
  209  * verbatim from /usr/games/fortune.
  210  */
  211 static uint16_t
  212 sis_reverse(uint16_t n)
  213 {
  214         n = ((n >>  1) & 0x5555) | ((n <<  1) & 0xaaaa);
  215         n = ((n >>  2) & 0x3333) | ((n <<  2) & 0xcccc);
  216         n = ((n >>  4) & 0x0f0f) | ((n <<  4) & 0xf0f0);
  217         n = ((n >>  8) & 0x00ff) | ((n <<  8) & 0xff00);
  218 
  219         return (n);
  220 }
  221 
  222 static void
  223 sis_delay(struct sis_softc *sc)
  224 {
  225         int                     idx;
  226 
  227         for (idx = (300 / 33) + 1; idx > 0; idx--)
  228                 CSR_READ_4(sc, SIS_CSR);
  229 }
  230 
  231 static void
  232 sis_eeprom_idle(struct sis_softc *sc)
  233 {
  234         int             i;
  235 
  236         SIO_SET(SIS_EECTL_CSEL);
  237         sis_delay(sc);
  238         SIO_SET(SIS_EECTL_CLK);
  239         sis_delay(sc);
  240 
  241         for (i = 0; i < 25; i++) {
  242                 SIO_CLR(SIS_EECTL_CLK);
  243                 sis_delay(sc);
  244                 SIO_SET(SIS_EECTL_CLK);
  245                 sis_delay(sc);
  246         }
  247 
  248         SIO_CLR(SIS_EECTL_CLK);
  249         sis_delay(sc);
  250         SIO_CLR(SIS_EECTL_CSEL);
  251         sis_delay(sc);
  252         CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
  253 }
  254 
  255 /*
  256  * Send a read command and address to the EEPROM, check for ACK.
  257  */
  258 static void
  259 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
  260 {
  261         int             d, i;
  262 
  263         d = addr | SIS_EECMD_READ;
  264 
  265         /*
  266          * Feed in each bit and stobe the clock.
  267          */
  268         for (i = 0x400; i; i >>= 1) {
  269                 if (d & i) {
  270                         SIO_SET(SIS_EECTL_DIN);
  271                 } else {
  272                         SIO_CLR(SIS_EECTL_DIN);
  273                 }
  274                 sis_delay(sc);
  275                 SIO_SET(SIS_EECTL_CLK);
  276                 sis_delay(sc);
  277                 SIO_CLR(SIS_EECTL_CLK);
  278                 sis_delay(sc);
  279         }
  280 }
  281 
  282 /*
  283  * Read a word of data stored in the EEPROM at address 'addr.'
  284  */
  285 static void
  286 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
  287 {
  288         int             i;
  289         uint16_t        word = 0;
  290 
  291         /* Force EEPROM to idle state. */
  292         sis_eeprom_idle(sc);
  293 
  294         /* Enter EEPROM access mode. */
  295         sis_delay(sc);
  296         SIO_CLR(SIS_EECTL_CLK);
  297         sis_delay(sc);
  298         SIO_SET(SIS_EECTL_CSEL);
  299         sis_delay(sc);
  300 
  301         /*
  302          * Send address of word we want to read.
  303          */
  304         sis_eeprom_putbyte(sc, addr);
  305 
  306         /*
  307          * Start reading bits from EEPROM.
  308          */
  309         for (i = 0x8000; i; i >>= 1) {
  310                 SIO_SET(SIS_EECTL_CLK);
  311                 sis_delay(sc);
  312                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
  313                         word |= i;
  314                 sis_delay(sc);
  315                 SIO_CLR(SIS_EECTL_CLK);
  316                 sis_delay(sc);
  317         }
  318 
  319         /* Turn off EEPROM access mode. */
  320         sis_eeprom_idle(sc);
  321 
  322         *dest = word;
  323 }
  324 
  325 /*
  326  * Read a sequence of words from the EEPROM.
  327  */
  328 static void
  329 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
  330 {
  331         int                     i;
  332         uint16_t                word = 0, *ptr;
  333 
  334         for (i = 0; i < cnt; i++) {
  335                 sis_eeprom_getword(sc, off + i, &word);
  336                 ptr = (uint16_t *)(dest + (i * 2));
  337                 if (swap)
  338                         *ptr = ntohs(word);
  339                 else
  340                         *ptr = word;
  341         }
  342 }
  343 
  344 #if defined(__i386__) || defined(__amd64__)
  345 static device_t
  346 sis_find_bridge(device_t dev)
  347 {
  348         devclass_t              pci_devclass;
  349         device_t                *pci_devices;
  350         int                     pci_count = 0;
  351         device_t                *pci_children;
  352         int                     pci_childcount = 0;
  353         device_t                *busp, *childp;
  354         device_t                child = NULL;
  355         int                     i, j;
  356 
  357         if ((pci_devclass = devclass_find("pci")) == NULL)
  358                 return (NULL);
  359 
  360         devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
  361 
  362         for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
  363                 if (device_get_children(*busp, &pci_children, &pci_childcount))
  364                         continue;
  365                 for (j = 0, childp = pci_children;
  366                     j < pci_childcount; j++, childp++) {
  367                         if (pci_get_vendor(*childp) == SIS_VENDORID &&
  368                             pci_get_device(*childp) == 0x0008) {
  369                                 child = *childp;
  370                                 free(pci_children, M_TEMP);
  371                                 goto done;
  372                         }
  373                 }
  374                 free(pci_children, M_TEMP);
  375         }
  376 
  377 done:
  378         free(pci_devices, M_TEMP);
  379         return (child);
  380 }
  381 
  382 static void
  383 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
  384 {
  385         device_t                bridge;
  386         uint8_t                 reg;
  387         int                     i;
  388         bus_space_tag_t         btag;
  389 
  390         bridge = sis_find_bridge(dev);
  391         if (bridge == NULL)
  392                 return;
  393         reg = pci_read_config(bridge, 0x48, 1);
  394         pci_write_config(bridge, 0x48, reg|0x40, 1);
  395 
  396         /* XXX */
  397 #if defined(__amd64__) || defined(__i386__)
  398         btag = X86_BUS_SPACE_IO;
  399 #endif
  400 
  401         for (i = 0; i < cnt; i++) {
  402                 bus_space_write_1(btag, 0x0, 0x70, i + off);
  403                 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
  404         }
  405 
  406         pci_write_config(bridge, 0x48, reg & ~0x40, 1);
  407 }
  408 
  409 static void
  410 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
  411 {
  412         uint32_t                filtsave, csrsave;
  413 
  414         filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
  415         csrsave = CSR_READ_4(sc, SIS_CSR);
  416 
  417         CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
  418         CSR_WRITE_4(sc, SIS_CSR, 0);
  419 
  420         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
  421 
  422         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
  423         ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  424         CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
  425         ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  426         CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
  427         ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
  428 
  429         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
  430         CSR_WRITE_4(sc, SIS_CSR, csrsave);
  431 }
  432 #endif
  433 
  434 /*
  435  * Read the MII serial port for the MII bit-bang module.
  436  */
  437 static uint32_t
  438 sis_mii_bitbang_read(device_t dev)
  439 {
  440         struct sis_softc        *sc;
  441         uint32_t                val;
  442 
  443         sc = device_get_softc(dev);
  444 
  445         val = CSR_READ_4(sc, SIS_EECTL);
  446         CSR_BARRIER(sc, SIS_EECTL, 4,
  447             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
  448         return (val);
  449 }
  450 
  451 /*
  452  * Write the MII serial port for the MII bit-bang module.
  453  */
  454 static void
  455 sis_mii_bitbang_write(device_t dev, uint32_t val)
  456 {
  457         struct sis_softc        *sc;
  458 
  459         sc = device_get_softc(dev);
  460 
  461         CSR_WRITE_4(sc, SIS_EECTL, val);
  462         CSR_BARRIER(sc, SIS_EECTL, 4,
  463             BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
  464 }
  465 
  466 static int
  467 sis_miibus_readreg(device_t dev, int phy, int reg)
  468 {
  469         struct sis_softc        *sc;
  470 
  471         sc = device_get_softc(dev);
  472 
  473         if (sc->sis_type == SIS_TYPE_83815) {
  474                 if (phy != 0)
  475                         return (0);
  476                 /*
  477                  * The NatSemi chip can take a while after
  478                  * a reset to come ready, during which the BMSR
  479                  * returns a value of 0. This is *never* supposed
  480                  * to happen: some of the BMSR bits are meant to
  481                  * be hardwired in the on position, and this can
  482                  * confuse the miibus code a bit during the probe
  483                  * and attach phase. So we make an effort to check
  484                  * for this condition and wait for it to clear.
  485                  */
  486                 if (!CSR_READ_4(sc, NS_BMSR))
  487                         DELAY(1000);
  488                 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
  489         }
  490 
  491         /*
  492          * Chipsets < SIS_635 seem not to be able to read/write
  493          * through mdio. Use the enhanced PHY access register
  494          * again for them.
  495          */
  496         if (sc->sis_type == SIS_TYPE_900 &&
  497             sc->sis_rev < SIS_REV_635) {
  498                 int i, val = 0;
  499 
  500                 if (phy != 0)
  501                         return (0);
  502 
  503                 CSR_WRITE_4(sc, SIS_PHYCTL,
  504                     (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
  505                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  506 
  507                 for (i = 0; i < SIS_TIMEOUT; i++) {
  508                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  509                                 break;
  510                 }
  511 
  512                 if (i == SIS_TIMEOUT) {
  513                         device_printf(sc->sis_dev,
  514                             "PHY failed to come ready\n");
  515                         return (0);
  516                 }
  517 
  518                 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
  519 
  520                 if (val == 0xFFFF)
  521                         return (0);
  522 
  523                 return (val);
  524         } else
  525                 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
  526                     reg));
  527 }
  528 
  529 static int
  530 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
  531 {
  532         struct sis_softc        *sc;
  533 
  534         sc = device_get_softc(dev);
  535 
  536         if (sc->sis_type == SIS_TYPE_83815) {
  537                 if (phy != 0)
  538                         return (0);
  539                 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
  540                 return (0);
  541         }
  542 
  543         /*
  544          * Chipsets < SIS_635 seem not to be able to read/write
  545          * through mdio. Use the enhanced PHY access register
  546          * again for them.
  547          */
  548         if (sc->sis_type == SIS_TYPE_900 &&
  549             sc->sis_rev < SIS_REV_635) {
  550                 int i;
  551 
  552                 if (phy != 0)
  553                         return (0);
  554 
  555                 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
  556                     (reg << 6) | SIS_PHYOP_WRITE);
  557                 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
  558 
  559                 for (i = 0; i < SIS_TIMEOUT; i++) {
  560                         if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
  561                                 break;
  562                 }
  563 
  564                 if (i == SIS_TIMEOUT)
  565                         device_printf(sc->sis_dev,
  566                             "PHY failed to come ready\n");
  567         } else
  568                 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
  569                     data);
  570         return (0);
  571 }
  572 
  573 static void
  574 sis_miibus_statchg(device_t dev)
  575 {
  576         struct sis_softc        *sc;
  577         struct mii_data         *mii;
  578         struct ifnet            *ifp;
  579         uint32_t                reg;
  580 
  581         sc = device_get_softc(dev);
  582         SIS_LOCK_ASSERT(sc);
  583 
  584         mii = device_get_softc(sc->sis_miibus);
  585         ifp = sc->sis_ifp;
  586         if (mii == NULL || ifp == NULL ||
  587             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
  588                 return;
  589 
  590         sc->sis_flags &= ~SIS_FLAG_LINK;
  591         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
  592             (IFM_ACTIVE | IFM_AVALID)) {
  593                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  594                 case IFM_10_T:
  595                         CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
  596                         sc->sis_flags |= SIS_FLAG_LINK;
  597                         break;
  598                 case IFM_100_TX:
  599                         CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
  600                         sc->sis_flags |= SIS_FLAG_LINK;
  601                         break;
  602                 default:
  603                         break;
  604                 }
  605         }
  606 
  607         if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
  608                 /*
  609                  * Stopping MACs seem to reset SIS_TX_LISTPTR and
  610                  * SIS_RX_LISTPTR which in turn requires resetting
  611                  * TX/RX buffers.  So just don't do anything for
  612                  * lost link.
  613                  */
  614                 return;
  615         }
  616 
  617         /* Set full/half duplex mode. */
  618         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
  619                 SIS_SETBIT(sc, SIS_TX_CFG,
  620                     (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
  621                 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
  622         } else {
  623                 SIS_CLRBIT(sc, SIS_TX_CFG,
  624                     (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
  625                 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
  626         }
  627 
  628         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
  629                 /*
  630                  * MPII03.D: Half Duplex Excessive Collisions.
  631                  * Also page 49 in 83816 manual
  632                  */
  633                 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
  634         }
  635 
  636         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
  637             IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
  638                 /*
  639                  * Short Cable Receive Errors (MP21.E)
  640                  */
  641                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
  642                 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
  643                 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
  644                 DELAY(100);
  645                 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
  646                 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
  647                         device_printf(sc->sis_dev,
  648                             "Applying short cable fix (reg=%x)\n", reg);
  649                         CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
  650                         SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
  651                 }
  652                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
  653         }
  654         /* Enable TX/RX MACs. */
  655         SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
  656         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
  657 }
  658 
  659 static uint32_t
  660 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
  661 {
  662         uint32_t                crc;
  663 
  664         /* Compute CRC for the address value. */
  665         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
  666 
  667         /*
  668          * return the filter bit position
  669          *
  670          * The NatSemi chip has a 512-bit filter, which is
  671          * different than the SiS, so we special-case it.
  672          */
  673         if (sc->sis_type == SIS_TYPE_83815)
  674                 return (crc >> 23);
  675         else if (sc->sis_rev >= SIS_REV_635 ||
  676             sc->sis_rev == SIS_REV_900B)
  677                 return (crc >> 24);
  678         else
  679                 return (crc >> 25);
  680 }
  681 
  682 static void
  683 sis_rxfilter(struct sis_softc *sc)
  684 {
  685 
  686         SIS_LOCK_ASSERT(sc);
  687 
  688         if (sc->sis_type == SIS_TYPE_83815)
  689                 sis_rxfilter_ns(sc);
  690         else
  691                 sis_rxfilter_sis(sc);
  692 }
  693 
  694 static void
  695 sis_rxfilter_ns(struct sis_softc *sc)
  696 {
  697         struct ifnet            *ifp;
  698         struct ifmultiaddr      *ifma;
  699         uint32_t                h, i, filter;
  700         int                     bit, index;
  701 
  702         ifp = sc->sis_ifp;
  703         filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
  704         if (filter & SIS_RXFILTCTL_ENABLE) {
  705                 /*
  706                  * Filter should be disabled to program other bits.
  707                  */
  708                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
  709                 CSR_READ_4(sc, SIS_RXFILT_CTL);
  710         }
  711         filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
  712             NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
  713             SIS_RXFILTCTL_ALLMULTI);
  714 
  715         if (ifp->if_flags & IFF_BROADCAST)
  716                 filter |= SIS_RXFILTCTL_BROAD;
  717         /*
  718          * For the NatSemi chip, we have to explicitly enable the
  719          * reception of ARP frames, as well as turn on the 'perfect
  720          * match' filter where we store the station address, otherwise
  721          * we won't receive unicasts meant for this host.
  722          */
  723         filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
  724 
  725         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
  726                 filter |= SIS_RXFILTCTL_ALLMULTI;
  727                 if (ifp->if_flags & IFF_PROMISC)
  728                         filter |= SIS_RXFILTCTL_ALLPHYS;
  729         } else {
  730                 /*
  731                  * We have to explicitly enable the multicast hash table
  732                  * on the NatSemi chip if we want to use it, which we do.
  733                  */
  734                 filter |= NS_RXFILTCTL_MCHASH;
  735 
  736                 /* first, zot all the existing hash bits */
  737                 for (i = 0; i < 32; i++) {
  738                         CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
  739                             (i * 2));
  740                         CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
  741                 }
  742 
  743                 if_maddr_rlock(ifp);
  744                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  745                         if (ifma->ifma_addr->sa_family != AF_LINK)
  746                                 continue;
  747                         h = sis_mchash(sc,
  748                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  749                         index = h >> 3;
  750                         bit = h & 0x1F;
  751                         CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
  752                             index);
  753                         if (bit > 0xF)
  754                                 bit -= 0x10;
  755                         SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
  756                 }
  757                 if_maddr_runlock(ifp);
  758         }
  759 
  760         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
  761         CSR_READ_4(sc, SIS_RXFILT_CTL);
  762 }
  763 
  764 static void
  765 sis_rxfilter_sis(struct sis_softc *sc)
  766 {
  767         struct ifnet            *ifp;
  768         struct ifmultiaddr      *ifma;
  769         uint32_t                filter, h, i, n;
  770         uint16_t                hashes[16];
  771 
  772         ifp = sc->sis_ifp;
  773 
  774         /* hash table size */
  775         if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
  776                 n = 16;
  777         else
  778                 n = 8;
  779 
  780         filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
  781         if (filter & SIS_RXFILTCTL_ENABLE) {
  782                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL);
  783                 CSR_READ_4(sc, SIS_RXFILT_CTL);
  784         }
  785         filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
  786             SIS_RXFILTCTL_ALLMULTI);
  787         if (ifp->if_flags & IFF_BROADCAST)
  788                 filter |= SIS_RXFILTCTL_BROAD;
  789 
  790         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
  791                 filter |= SIS_RXFILTCTL_ALLMULTI;
  792                 if (ifp->if_flags & IFF_PROMISC)
  793                         filter |= SIS_RXFILTCTL_ALLPHYS;
  794                 for (i = 0; i < n; i++)
  795                         hashes[i] = ~0;
  796         } else {
  797                 for (i = 0; i < n; i++)
  798                         hashes[i] = 0;
  799                 i = 0;
  800                 if_maddr_rlock(ifp);
  801                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
  802                         if (ifma->ifma_addr->sa_family != AF_LINK)
  803                         continue;
  804                         h = sis_mchash(sc,
  805                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
  806                         hashes[h >> 4] |= 1 << (h & 0xf);
  807                         i++;
  808                 }
  809                 if_maddr_runlock(ifp);
  810                 if (i > n) {
  811                         filter |= SIS_RXFILTCTL_ALLMULTI;
  812                         for (i = 0; i < n; i++)
  813                                 hashes[i] = ~0;
  814                 }
  815         }
  816 
  817         for (i = 0; i < n; i++) {
  818                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
  819                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
  820         }
  821 
  822         CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
  823         CSR_READ_4(sc, SIS_RXFILT_CTL);
  824 }
  825 
  826 static void
  827 sis_reset(struct sis_softc *sc)
  828 {
  829         int             i;
  830 
  831         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
  832 
  833         for (i = 0; i < SIS_TIMEOUT; i++) {
  834                 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
  835                         break;
  836         }
  837 
  838         if (i == SIS_TIMEOUT)
  839                 device_printf(sc->sis_dev, "reset never completed\n");
  840 
  841         /* Wait a little while for the chip to get its brains in order. */
  842         DELAY(1000);
  843 
  844         /*
  845          * If this is a NetSemi chip, make sure to clear
  846          * PME mode.
  847          */
  848         if (sc->sis_type == SIS_TYPE_83815) {
  849                 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
  850                 CSR_WRITE_4(sc, NS_CLKRUN, 0);
  851         } else {
  852                 /* Disable WOL functions. */
  853                 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
  854         }
  855 }
  856 
  857 /*
  858  * Probe for an SiS chip. Check the PCI vendor and device
  859  * IDs against our list and return a device name if we find a match.
  860  */
  861 static int
  862 sis_probe(device_t dev)
  863 {
  864         const struct sis_type   *t;
  865 
  866         t = sis_devs;
  867 
  868         while (t->sis_name != NULL) {
  869                 if ((pci_get_vendor(dev) == t->sis_vid) &&
  870                     (pci_get_device(dev) == t->sis_did)) {
  871                         device_set_desc(dev, t->sis_name);
  872                         return (BUS_PROBE_DEFAULT);
  873                 }
  874                 t++;
  875         }
  876 
  877         return (ENXIO);
  878 }
  879 
  880 /*
  881  * Attach the interface. Allocate softc structures, do ifmedia
  882  * setup and ethernet/BPF attach.
  883  */
  884 static int
  885 sis_attach(device_t dev)
  886 {
  887         u_char                  eaddr[ETHER_ADDR_LEN];
  888         struct sis_softc        *sc;
  889         struct ifnet            *ifp;
  890         int                     error = 0, pmc, waittime = 0;
  891 
  892         waittime = 0;
  893         sc = device_get_softc(dev);
  894 
  895         sc->sis_dev = dev;
  896 
  897         mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  898             MTX_DEF);
  899         callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
  900 
  901         if (pci_get_device(dev) == SIS_DEVICEID_900)
  902                 sc->sis_type = SIS_TYPE_900;
  903         if (pci_get_device(dev) == SIS_DEVICEID_7016)
  904                 sc->sis_type = SIS_TYPE_7016;
  905         if (pci_get_vendor(dev) == NS_VENDORID)
  906                 sc->sis_type = SIS_TYPE_83815;
  907 
  908         sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
  909         /*
  910          * Map control/status registers.
  911          */
  912         pci_enable_busmaster(dev);
  913 
  914         error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
  915         if (error) {
  916                 device_printf(dev, "couldn't allocate resources\n");
  917                 goto fail;
  918         }
  919 
  920         /* Reset the adapter. */
  921         sis_reset(sc);
  922 
  923         if (sc->sis_type == SIS_TYPE_900 &&
  924             (sc->sis_rev == SIS_REV_635 ||
  925             sc->sis_rev == SIS_REV_900B)) {
  926                 SIO_SET(SIS_CFG_RND_CNT);
  927                 SIO_SET(SIS_CFG_PERR_DETECT);
  928         }
  929 
  930         /*
  931          * Get station address from the EEPROM.
  932          */
  933         switch (pci_get_vendor(dev)) {
  934         case NS_VENDORID:
  935                 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
  936 
  937                 /* We can't update the device description, so spew */
  938                 if (sc->sis_srr == NS_SRR_15C)
  939                         device_printf(dev, "Silicon Revision: DP83815C\n");
  940                 else if (sc->sis_srr == NS_SRR_15D)
  941                         device_printf(dev, "Silicon Revision: DP83815D\n");
  942                 else if (sc->sis_srr == NS_SRR_16A)
  943                         device_printf(dev, "Silicon Revision: DP83816A\n");
  944                 else
  945                         device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
  946 
  947                 /*
  948                  * Reading the MAC address out of the EEPROM on
  949                  * the NatSemi chip takes a bit more work than
  950                  * you'd expect. The address spans 4 16-bit words,
  951                  * with the first word containing only a single bit.
  952                  * You have to shift everything over one bit to
  953                  * get it aligned properly. Also, the bits are
  954                  * stored backwards (the LSB is really the MSB,
  955                  * and so on) so you have to reverse them in order
  956                  * to get the MAC address into the form we want.
  957                  * Why? Who the hell knows.
  958                  */
  959                 {
  960                         uint16_t                tmp[4];
  961 
  962                         sis_read_eeprom(sc, (caddr_t)&tmp,
  963                             NS_EE_NODEADDR, 4, 0);
  964 
  965                         /* Shift everything over one bit. */
  966                         tmp[3] = tmp[3] >> 1;
  967                         tmp[3] |= tmp[2] << 15;
  968                         tmp[2] = tmp[2] >> 1;
  969                         tmp[2] |= tmp[1] << 15;
  970                         tmp[1] = tmp[1] >> 1;
  971                         tmp[1] |= tmp[0] << 15;
  972 
  973                         /* Now reverse all the bits. */
  974                         tmp[3] = sis_reverse(tmp[3]);
  975                         tmp[2] = sis_reverse(tmp[2]);
  976                         tmp[1] = sis_reverse(tmp[1]);
  977 
  978                         eaddr[0] = (tmp[1] >> 0) & 0xFF;
  979                         eaddr[1] = (tmp[1] >> 8) & 0xFF;
  980                         eaddr[2] = (tmp[2] >> 0) & 0xFF;
  981                         eaddr[3] = (tmp[2] >> 8) & 0xFF;
  982                         eaddr[4] = (tmp[3] >> 0) & 0xFF;
  983                         eaddr[5] = (tmp[3] >> 8) & 0xFF;
  984                 }
  985                 break;
  986         case SIS_VENDORID:
  987         default:
  988 #if defined(__i386__) || defined(__amd64__)
  989                 /*
  990                  * If this is a SiS 630E chipset with an embedded
  991                  * SiS 900 controller, we have to read the MAC address
  992                  * from the APC CMOS RAM. Our method for doing this
  993                  * is very ugly since we have to reach out and grab
  994                  * ahold of hardware for which we cannot properly
  995                  * allocate resources. This code is only compiled on
  996                  * the i386 architecture since the SiS 630E chipset
  997                  * is for x86 motherboards only. Note that there are
  998                  * a lot of magic numbers in this hack. These are
  999                  * taken from SiS's Linux driver. I'd like to replace
 1000                  * them with proper symbolic definitions, but that
 1001                  * requires some datasheets that I don't have access
 1002                  * to at the moment.
 1003                  */
 1004                 if (sc->sis_rev == SIS_REV_630S ||
 1005                     sc->sis_rev == SIS_REV_630E ||
 1006                     sc->sis_rev == SIS_REV_630EA1)
 1007                         sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
 1008 
 1009                 else if (sc->sis_rev == SIS_REV_635 ||
 1010                          sc->sis_rev == SIS_REV_630ET)
 1011                         sis_read_mac(sc, dev, (caddr_t)&eaddr);
 1012                 else if (sc->sis_rev == SIS_REV_96x) {
 1013                         /* Allow to read EEPROM from LAN. It is shared
 1014                          * between a 1394 controller and the NIC and each
 1015                          * time we access it, we need to set SIS_EECMD_REQ.
 1016                          */
 1017                         SIO_SET(SIS_EECMD_REQ);
 1018                         for (waittime = 0; waittime < SIS_TIMEOUT;
 1019                             waittime++) {
 1020                                 /* Force EEPROM to idle state. */
 1021                                 sis_eeprom_idle(sc);
 1022                                 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
 1023                                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1024                                             SIS_EE_NODEADDR, 3, 0);
 1025                                         break;
 1026                                 }
 1027                                 DELAY(1);
 1028                         }
 1029                         /*
 1030                          * Set SIS_EECTL_CLK to high, so a other master
 1031                          * can operate on the i2c bus.
 1032                          */
 1033                         SIO_SET(SIS_EECTL_CLK);
 1034                         /* Refuse EEPROM access by LAN */
 1035                         SIO_SET(SIS_EECMD_DONE);
 1036                 } else
 1037 #endif
 1038                         sis_read_eeprom(sc, (caddr_t)&eaddr,
 1039                             SIS_EE_NODEADDR, 3, 0);
 1040                 break;
 1041         }
 1042 
 1043         sis_add_sysctls(sc);
 1044 
 1045         /* Allocate DMA'able memory. */
 1046         if ((error = sis_dma_alloc(sc)) != 0)
 1047                 goto fail;
 1048 
 1049         ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
 1050         if (ifp == NULL) {
 1051                 device_printf(dev, "can not if_alloc()\n");
 1052                 error = ENOSPC;
 1053                 goto fail;
 1054         }
 1055         ifp->if_softc = sc;
 1056         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 1057         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 1058         ifp->if_ioctl = sis_ioctl;
 1059         ifp->if_start = sis_start;
 1060         ifp->if_init = sis_init;
 1061         IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
 1062         ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
 1063         IFQ_SET_READY(&ifp->if_snd);
 1064 
 1065         if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
 1066                 if (sc->sis_type == SIS_TYPE_83815)
 1067                         ifp->if_capabilities |= IFCAP_WOL;
 1068                 else
 1069                         ifp->if_capabilities |= IFCAP_WOL_MAGIC;
 1070                 ifp->if_capenable = ifp->if_capabilities;
 1071         }
 1072 
 1073         /*
 1074          * Do MII setup.
 1075          */
 1076         error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
 1077             sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
 1078         if (error != 0) {
 1079                 device_printf(dev, "attaching PHYs failed\n");
 1080                 goto fail;
 1081         }
 1082 
 1083         /*
 1084          * Call MI attach routine.
 1085          */
 1086         ether_ifattach(ifp, eaddr);
 1087 
 1088         /*
 1089          * Tell the upper layer(s) we support long frames.
 1090          */
 1091         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 1092         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 1093         ifp->if_capenable = ifp->if_capabilities;
 1094 #ifdef DEVICE_POLLING
 1095         ifp->if_capabilities |= IFCAP_POLLING;
 1096 #endif
 1097 
 1098         /* Hook interrupt last to avoid having to lock softc */
 1099         error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
 1100             NULL, sis_intr, sc, &sc->sis_intrhand);
 1101 
 1102         if (error) {
 1103                 device_printf(dev, "couldn't set up irq\n");
 1104                 ether_ifdetach(ifp);
 1105                 goto fail;
 1106         }
 1107 
 1108 fail:
 1109         if (error)
 1110                 sis_detach(dev);
 1111 
 1112         return (error);
 1113 }
 1114 
 1115 /*
 1116  * Shutdown hardware and free up resources. This can be called any
 1117  * time after the mutex has been initialized. It is called in both
 1118  * the error case in attach and the normal detach case so it needs
 1119  * to be careful about only freeing resources that have actually been
 1120  * allocated.
 1121  */
 1122 static int
 1123 sis_detach(device_t dev)
 1124 {
 1125         struct sis_softc        *sc;
 1126         struct ifnet            *ifp;
 1127 
 1128         sc = device_get_softc(dev);
 1129         KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
 1130         ifp = sc->sis_ifp;
 1131 
 1132 #ifdef DEVICE_POLLING
 1133         if (ifp->if_capenable & IFCAP_POLLING)
 1134                 ether_poll_deregister(ifp);
 1135 #endif
 1136 
 1137         /* These should only be active if attach succeeded. */
 1138         if (device_is_attached(dev)) {
 1139                 SIS_LOCK(sc);
 1140                 sis_stop(sc);
 1141                 SIS_UNLOCK(sc);
 1142                 callout_drain(&sc->sis_stat_ch);
 1143                 ether_ifdetach(ifp);
 1144         }
 1145         if (sc->sis_miibus)
 1146                 device_delete_child(dev, sc->sis_miibus);
 1147         bus_generic_detach(dev);
 1148 
 1149         if (sc->sis_intrhand)
 1150                 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
 1151         bus_release_resources(dev, sis_res_spec, sc->sis_res);
 1152 
 1153         if (ifp)
 1154                 if_free(ifp);
 1155 
 1156         sis_dma_free(sc);
 1157 
 1158         mtx_destroy(&sc->sis_mtx);
 1159 
 1160         return (0);
 1161 }
 1162 
 1163 struct sis_dmamap_arg {
 1164         bus_addr_t      sis_busaddr;
 1165 };
 1166 
 1167 static void
 1168 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 1169 {
 1170         struct sis_dmamap_arg   *ctx;
 1171 
 1172         if (error != 0)
 1173                 return;
 1174 
 1175         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 1176 
 1177         ctx = (struct sis_dmamap_arg *)arg;
 1178         ctx->sis_busaddr = segs[0].ds_addr;
 1179 }
 1180 
 1181 static int
 1182 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
 1183     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
 1184     bus_addr_t *paddr, const char *msg)
 1185 {
 1186         struct sis_dmamap_arg   ctx;
 1187         int                     error;
 1188 
 1189         error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
 1190             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
 1191             maxsize, 0, NULL, NULL, tag);
 1192         if (error != 0) {
 1193                 device_printf(sc->sis_dev,
 1194                     "could not create %s dma tag\n", msg);
 1195                 return (ENOMEM);
 1196         }
 1197         /* Allocate DMA'able memory for ring. */
 1198         error = bus_dmamem_alloc(*tag, (void **)ring,
 1199             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
 1200         if (error != 0) {
 1201                 device_printf(sc->sis_dev,
 1202                     "could not allocate DMA'able memory for %s\n", msg);
 1203                 return (ENOMEM);
 1204         }
 1205         /* Load the address of the ring. */
 1206         ctx.sis_busaddr = 0;
 1207         error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
 1208             &ctx, BUS_DMA_NOWAIT);
 1209         if (error != 0) {
 1210                 device_printf(sc->sis_dev,
 1211                     "could not load DMA'able memory for %s\n", msg);
 1212                 return (ENOMEM);
 1213         }
 1214         *paddr = ctx.sis_busaddr;
 1215         return (0);
 1216 }
 1217 
 1218 static int
 1219 sis_dma_alloc(struct sis_softc *sc)
 1220 {
 1221         struct sis_rxdesc       *rxd;
 1222         struct sis_txdesc       *txd;
 1223         int                     error, i;
 1224 
 1225         /* Allocate the parent bus DMA tag appropriate for PCI. */
 1226         error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
 1227             1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
 1228             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
 1229             0, NULL, NULL, &sc->sis_parent_tag);
 1230         if (error != 0) {
 1231                 device_printf(sc->sis_dev,
 1232                     "could not allocate parent dma tag\n");
 1233                 return (ENOMEM);
 1234         }
 1235 
 1236         /* Create RX ring. */
 1237         error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
 1238             &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
 1239             &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
 1240         if (error)
 1241                 return (error);
 1242 
 1243         /* Create TX ring. */
 1244         error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
 1245             &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
 1246             &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
 1247         if (error)
 1248                 return (error);
 1249 
 1250         /* Create tag for RX mbufs. */
 1251         error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
 1252             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
 1253             MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
 1254         if (error) {
 1255                 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
 1256                 return (error);
 1257         }
 1258 
 1259         /* Create tag for TX mbufs. */
 1260         error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
 1261             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 1262             MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
 1263             &sc->sis_tx_tag);
 1264         if (error) {
 1265                 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
 1266                 return (error);
 1267         }
 1268 
 1269         /* Create DMA maps for RX buffers. */
 1270         error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
 1271         if (error) {
 1272                 device_printf(sc->sis_dev,
 1273                     "can't create spare DMA map for RX\n");
 1274                 return (error);
 1275         }
 1276         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 1277                 rxd = &sc->sis_rxdesc[i];
 1278                 rxd->rx_m = NULL;
 1279                 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
 1280                 if (error) {
 1281                         device_printf(sc->sis_dev,
 1282                             "can't create DMA map for RX\n");
 1283                         return (error);
 1284                 }
 1285         }
 1286 
 1287         /* Create DMA maps for TX buffers. */
 1288         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 1289                 txd = &sc->sis_txdesc[i];
 1290                 txd->tx_m = NULL;
 1291                 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
 1292                 if (error) {
 1293                         device_printf(sc->sis_dev,
 1294                             "can't create DMA map for TX\n");
 1295                         return (error);
 1296                 }
 1297         }
 1298 
 1299         return (0);
 1300 }
 1301 
 1302 static void
 1303 sis_dma_free(struct sis_softc *sc)
 1304 {
 1305         struct sis_rxdesc       *rxd;
 1306         struct sis_txdesc       *txd;
 1307         int                     i;
 1308 
 1309         /* Destroy DMA maps for RX buffers. */
 1310         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 1311                 rxd = &sc->sis_rxdesc[i];
 1312                 if (rxd->rx_dmamap)
 1313                         bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
 1314         }
 1315         if (sc->sis_rx_sparemap)
 1316                 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
 1317 
 1318         /* Destroy DMA maps for TX buffers. */
 1319         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 1320                 txd = &sc->sis_txdesc[i];
 1321                 if (txd->tx_dmamap)
 1322                         bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
 1323         }
 1324 
 1325         if (sc->sis_rx_tag)
 1326                 bus_dma_tag_destroy(sc->sis_rx_tag);
 1327         if (sc->sis_tx_tag)
 1328                 bus_dma_tag_destroy(sc->sis_tx_tag);
 1329 
 1330         /* Destroy RX ring. */
 1331         if (sc->sis_rx_list_map)
 1332                 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
 1333         if (sc->sis_rx_list_map && sc->sis_rx_list)
 1334                 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
 1335                     sc->sis_rx_list_map);
 1336 
 1337         if (sc->sis_rx_list_tag)
 1338                 bus_dma_tag_destroy(sc->sis_rx_list_tag);
 1339 
 1340         /* Destroy TX ring. */
 1341         if (sc->sis_tx_list_map)
 1342                 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
 1343 
 1344         if (sc->sis_tx_list_map && sc->sis_tx_list)
 1345                 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
 1346                     sc->sis_tx_list_map);
 1347 
 1348         if (sc->sis_tx_list_tag)
 1349                 bus_dma_tag_destroy(sc->sis_tx_list_tag);
 1350 
 1351         /* Destroy the parent tag. */
 1352         if (sc->sis_parent_tag)
 1353                 bus_dma_tag_destroy(sc->sis_parent_tag);
 1354 }
 1355 
 1356 /*
 1357  * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
 1358  * we arrange the descriptors in a closed ring, so that the last descriptor
 1359  * points back to the first.
 1360  */
 1361 static int
 1362 sis_ring_init(struct sis_softc *sc)
 1363 {
 1364         struct sis_rxdesc       *rxd;
 1365         struct sis_txdesc       *txd;
 1366         bus_addr_t              next;
 1367         int                     error, i;
 1368 
 1369         bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
 1370         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 1371                 txd = &sc->sis_txdesc[i];
 1372                 txd->tx_m = NULL;
 1373                 if (i == SIS_TX_LIST_CNT - 1)
 1374                         next = SIS_TX_RING_ADDR(sc, 0);
 1375                 else
 1376                         next = SIS_TX_RING_ADDR(sc, i + 1);
 1377                 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
 1378         }
 1379         sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
 1380         bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
 1381             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1382 
 1383         sc->sis_rx_cons = 0;
 1384         bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
 1385         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 1386                 rxd = &sc->sis_rxdesc[i];
 1387                 rxd->rx_desc = &sc->sis_rx_list[i];
 1388                 if (i == SIS_RX_LIST_CNT - 1)
 1389                         next = SIS_RX_RING_ADDR(sc, 0);
 1390                 else
 1391                         next = SIS_RX_RING_ADDR(sc, i + 1);
 1392                 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
 1393                 error = sis_newbuf(sc, rxd);
 1394                 if (error)
 1395                         return (error);
 1396         }
 1397         bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
 1398             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1399 
 1400         return (0);
 1401 }
 1402 
 1403 /*
 1404  * Initialize an RX descriptor and attach an MBUF cluster.
 1405  */
 1406 static int
 1407 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
 1408 {
 1409         struct mbuf             *m;
 1410         bus_dma_segment_t       segs[1];
 1411         bus_dmamap_t            map;
 1412         int nsegs;
 1413 
 1414         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 1415         if (m == NULL)
 1416                 return (ENOBUFS);
 1417         m->m_len = m->m_pkthdr.len = SIS_RXLEN;
 1418 #ifndef __NO_STRICT_ALIGNMENT
 1419         m_adj(m, SIS_RX_BUF_ALIGN);
 1420 #endif
 1421 
 1422         if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
 1423             segs, &nsegs, 0) != 0) {
 1424                 m_freem(m);
 1425                 return (ENOBUFS);
 1426         }
 1427         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 1428 
 1429         if (rxd->rx_m != NULL) {
 1430                 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
 1431                     BUS_DMASYNC_POSTREAD);
 1432                 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
 1433         }
 1434         map = rxd->rx_dmamap;
 1435         rxd->rx_dmamap = sc->sis_rx_sparemap;
 1436         sc->sis_rx_sparemap = map;
 1437         bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
 1438         rxd->rx_m = m;
 1439         rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
 1440         rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
 1441         return (0);
 1442 }
 1443 
 1444 static __inline void
 1445 sis_discard_rxbuf(struct sis_rxdesc *rxd)
 1446 {
 1447 
 1448         rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
 1449 }
 1450 
 1451 #ifndef __NO_STRICT_ALIGNMENT
 1452 static __inline void
 1453 sis_fixup_rx(struct mbuf *m)
 1454 {
 1455         uint16_t                *src, *dst;
 1456         int                     i;
 1457 
 1458         src = mtod(m, uint16_t *);
 1459         dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
 1460 
 1461         for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
 1462                 *dst++ = *src++;
 1463 
 1464         m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
 1465 }
 1466 #endif
 1467 
 1468 /*
 1469  * A frame has been uploaded: pass the resulting mbuf chain up to
 1470  * the higher level protocols.
 1471  */
 1472 static int
 1473 sis_rxeof(struct sis_softc *sc)
 1474 {
 1475         struct mbuf             *m;
 1476         struct ifnet            *ifp;
 1477         struct sis_rxdesc       *rxd;
 1478         struct sis_desc         *cur_rx;
 1479         int                     prog, rx_cons, rx_npkts = 0, total_len;
 1480         uint32_t                rxstat;
 1481 
 1482         SIS_LOCK_ASSERT(sc);
 1483 
 1484         bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
 1485             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1486 
 1487         rx_cons = sc->sis_rx_cons;
 1488         ifp = sc->sis_ifp;
 1489 
 1490         for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
 1491             SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
 1492 #ifdef DEVICE_POLLING
 1493                 if (ifp->if_capenable & IFCAP_POLLING) {
 1494                         if (sc->rxcycles <= 0)
 1495                                 break;
 1496                         sc->rxcycles--;
 1497                 }
 1498 #endif
 1499                 cur_rx = &sc->sis_rx_list[rx_cons];
 1500                 rxstat = le32toh(cur_rx->sis_cmdsts);
 1501                 if ((rxstat & SIS_CMDSTS_OWN) == 0)
 1502                         break;
 1503                 rxd = &sc->sis_rxdesc[rx_cons];
 1504 
 1505                 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
 1506                 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
 1507                     total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
 1508                     ETHER_CRC_LEN))
 1509                         rxstat &= ~SIS_RXSTAT_GIANT;
 1510                 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
 1511                         ifp->if_ierrors++;
 1512                         if (rxstat & SIS_RXSTAT_COLL)
 1513                                 ifp->if_collisions++;
 1514                         sis_discard_rxbuf(rxd);
 1515                         continue;
 1516                 }
 1517 
 1518                 /* Add a new receive buffer to the ring. */
 1519                 m = rxd->rx_m;
 1520                 if (sis_newbuf(sc, rxd) != 0) {
 1521                         ifp->if_iqdrops++;
 1522                         sis_discard_rxbuf(rxd);
 1523                         continue;
 1524                 }
 1525 
 1526                 /* No errors; receive the packet. */
 1527                 m->m_pkthdr.len = m->m_len = total_len;
 1528 #ifndef __NO_STRICT_ALIGNMENT
 1529                 /*
 1530                  * On architectures without alignment problems we try to
 1531                  * allocate a new buffer for the receive ring, and pass up
 1532                  * the one where the packet is already, saving the expensive
 1533                  * copy operation.
 1534                  */
 1535                 sis_fixup_rx(m);
 1536 #endif
 1537                 ifp->if_ipackets++;
 1538                 m->m_pkthdr.rcvif = ifp;
 1539 
 1540                 SIS_UNLOCK(sc);
 1541                 (*ifp->if_input)(ifp, m);
 1542                 SIS_LOCK(sc);
 1543                 rx_npkts++;
 1544         }
 1545 
 1546         if (prog > 0) {
 1547                 sc->sis_rx_cons = rx_cons;
 1548                 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
 1549                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1550         }
 1551 
 1552         return (rx_npkts);
 1553 }
 1554 
 1555 /*
 1556  * A frame was downloaded to the chip. It's safe for us to clean up
 1557  * the list buffers.
 1558  */
 1559 
 1560 static void
 1561 sis_txeof(struct sis_softc *sc)
 1562 {
 1563         struct ifnet            *ifp;
 1564         struct sis_desc         *cur_tx;
 1565         struct sis_txdesc       *txd;
 1566         uint32_t                cons, txstat;
 1567 
 1568         SIS_LOCK_ASSERT(sc);
 1569 
 1570         cons = sc->sis_tx_cons;
 1571         if (cons == sc->sis_tx_prod)
 1572                 return;
 1573 
 1574         ifp = sc->sis_ifp;
 1575         bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
 1576             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1577 
 1578         /*
 1579          * Go through our tx list and free mbufs for those
 1580          * frames that have been transmitted.
 1581          */
 1582         for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
 1583                 cur_tx = &sc->sis_tx_list[cons];
 1584                 txstat = le32toh(cur_tx->sis_cmdsts);
 1585                 if ((txstat & SIS_CMDSTS_OWN) != 0)
 1586                         break;
 1587                 txd = &sc->sis_txdesc[cons];
 1588                 if (txd->tx_m != NULL) {
 1589                         bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
 1590                             BUS_DMASYNC_POSTWRITE);
 1591                         bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
 1592                         m_freem(txd->tx_m);
 1593                         txd->tx_m = NULL;
 1594                         if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
 1595                                 ifp->if_opackets++;
 1596                                 ifp->if_collisions +=
 1597                                     (txstat & SIS_TXSTAT_COLLCNT) >> 16;
 1598                         } else {
 1599                                 ifp->if_oerrors++;
 1600                                 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
 1601                                         ifp->if_collisions++;
 1602                                 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
 1603                                         ifp->if_collisions++;
 1604                         }
 1605                 }
 1606                 sc->sis_tx_cnt--;
 1607                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1608         }
 1609         sc->sis_tx_cons = cons;
 1610         if (sc->sis_tx_cnt == 0)
 1611                 sc->sis_watchdog_timer = 0;
 1612 }
 1613 
 1614 static void
 1615 sis_tick(void *xsc)
 1616 {
 1617         struct sis_softc        *sc;
 1618         struct mii_data         *mii;
 1619         struct ifnet            *ifp;
 1620 
 1621         sc = xsc;
 1622         SIS_LOCK_ASSERT(sc);
 1623         ifp = sc->sis_ifp;
 1624 
 1625         mii = device_get_softc(sc->sis_miibus);
 1626         mii_tick(mii);
 1627         sis_watchdog(sc);
 1628         if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
 1629                 sis_miibus_statchg(sc->sis_dev);
 1630         callout_reset(&sc->sis_stat_ch, hz,  sis_tick, sc);
 1631 }
 1632 
 1633 #ifdef DEVICE_POLLING
 1634 static poll_handler_t sis_poll;
 1635 
 1636 static int
 1637 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1638 {
 1639         struct  sis_softc *sc = ifp->if_softc;
 1640         int rx_npkts = 0;
 1641 
 1642         SIS_LOCK(sc);
 1643         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 1644                 SIS_UNLOCK(sc);
 1645                 return (rx_npkts);
 1646         }
 1647 
 1648         /*
 1649          * On the sis, reading the status register also clears it.
 1650          * So before returning to intr mode we must make sure that all
 1651          * possible pending sources of interrupts have been served.
 1652          * In practice this means run to completion the *eof routines,
 1653          * and then call the interrupt routine
 1654          */
 1655         sc->rxcycles = count;
 1656         rx_npkts = sis_rxeof(sc);
 1657         sis_txeof(sc);
 1658         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1659                 sis_startl(ifp);
 1660 
 1661         if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
 1662                 uint32_t        status;
 1663 
 1664                 /* Reading the ISR register clears all interrupts. */
 1665                 status = CSR_READ_4(sc, SIS_ISR);
 1666 
 1667                 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
 1668                         ifp->if_ierrors++;
 1669 
 1670                 if (status & (SIS_ISR_RX_IDLE))
 1671                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1672 
 1673                 if (status & SIS_ISR_SYSERR) {
 1674                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1675                         sis_initl(sc);
 1676                 }
 1677         }
 1678 
 1679         SIS_UNLOCK(sc);
 1680         return (rx_npkts);
 1681 }
 1682 #endif /* DEVICE_POLLING */
 1683 
 1684 static void
 1685 sis_intr(void *arg)
 1686 {
 1687         struct sis_softc        *sc;
 1688         struct ifnet            *ifp;
 1689         uint32_t                status;
 1690 
 1691         sc = arg;
 1692         ifp = sc->sis_ifp;
 1693 
 1694         SIS_LOCK(sc);
 1695 #ifdef DEVICE_POLLING
 1696         if (ifp->if_capenable & IFCAP_POLLING) {
 1697                 SIS_UNLOCK(sc);
 1698                 return;
 1699         }
 1700 #endif
 1701 
 1702         /* Reading the ISR register clears all interrupts. */
 1703         status = CSR_READ_4(sc, SIS_ISR);
 1704         if ((status & SIS_INTRS) == 0) {
 1705                 /* Not ours. */
 1706                 SIS_UNLOCK(sc);
 1707                 return;
 1708         }
 1709 
 1710         /* Disable interrupts. */
 1711         CSR_WRITE_4(sc, SIS_IER, 0);
 1712 
 1713         for (;(status & SIS_INTRS) != 0;) {
 1714                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 1715                         break;
 1716                 if (status &
 1717                     (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
 1718                     SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
 1719                         sis_txeof(sc);
 1720 
 1721                 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
 1722                     SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
 1723                         sis_rxeof(sc);
 1724 
 1725                 if (status & SIS_ISR_RX_OFLOW)
 1726                         ifp->if_ierrors++;
 1727 
 1728                 if (status & (SIS_ISR_RX_IDLE))
 1729                         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 1730 
 1731                 if (status & SIS_ISR_SYSERR) {
 1732                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1733                         sis_initl(sc);
 1734                         SIS_UNLOCK(sc);
 1735                         return;
 1736                 }
 1737                 status = CSR_READ_4(sc, SIS_ISR);
 1738         }
 1739 
 1740         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 1741                 /* Re-enable interrupts. */
 1742                 CSR_WRITE_4(sc, SIS_IER, 1);
 1743 
 1744                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1745                         sis_startl(ifp);
 1746         }
 1747 
 1748         SIS_UNLOCK(sc);
 1749 }
 1750 
 1751 /*
 1752  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1753  * pointers to the fragment pointers.
 1754  */
 1755 static int
 1756 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
 1757 {
 1758         struct mbuf             *m;
 1759         struct sis_txdesc       *txd;
 1760         struct sis_desc         *f;
 1761         bus_dma_segment_t       segs[SIS_MAXTXSEGS];
 1762         bus_dmamap_t            map;
 1763         int                     error, i, frag, nsegs, prod;
 1764         int                     padlen;
 1765 
 1766         prod = sc->sis_tx_prod;
 1767         txd = &sc->sis_txdesc[prod];
 1768         if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
 1769             (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
 1770                 m = *m_head;
 1771                 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
 1772                 if (M_WRITABLE(m) == 0) {
 1773                         /* Get a writable copy. */
 1774                         m = m_dup(*m_head, M_NOWAIT);
 1775                         m_freem(*m_head);
 1776                         if (m == NULL) {
 1777                                 *m_head = NULL;
 1778                                 return (ENOBUFS);
 1779                         }
 1780                         *m_head = m;
 1781                 }
 1782                 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
 1783                         m = m_defrag(m, M_NOWAIT);
 1784                         if (m == NULL) {
 1785                                 m_freem(*m_head);
 1786                                 *m_head = NULL;
 1787                                 return (ENOBUFS);
 1788                         }
 1789                 }
 1790                 /*
 1791                  * Manually pad short frames, and zero the pad space
 1792                  * to avoid leaking data.
 1793                  */
 1794                 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
 1795                 m->m_pkthdr.len += padlen;
 1796                 m->m_len = m->m_pkthdr.len;
 1797                 *m_head = m;
 1798         }
 1799         error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
 1800             *m_head, segs, &nsegs, 0);
 1801         if (error == EFBIG) {
 1802                 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
 1803                 if (m == NULL) {
 1804                         m_freem(*m_head);
 1805                         *m_head = NULL;
 1806                         return (ENOBUFS);
 1807                 }
 1808                 *m_head = m;
 1809                 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
 1810                     *m_head, segs, &nsegs, 0);
 1811                 if (error != 0) {
 1812                         m_freem(*m_head);
 1813                         *m_head = NULL;
 1814                         return (error);
 1815                 }
 1816         } else if (error != 0)
 1817                 return (error);
 1818 
 1819         /* Check for descriptor overruns. */
 1820         if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
 1821                 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
 1822                 return (ENOBUFS);
 1823         }
 1824 
 1825         bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
 1826 
 1827         frag = prod;
 1828         for (i = 0; i < nsegs; i++) {
 1829                 f = &sc->sis_tx_list[prod];
 1830                 if (i == 0)
 1831                         f->sis_cmdsts = htole32(segs[i].ds_len |
 1832                             SIS_CMDSTS_MORE);
 1833                 else
 1834                         f->sis_cmdsts = htole32(segs[i].ds_len |
 1835                             SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
 1836                 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
 1837                 SIS_INC(prod, SIS_TX_LIST_CNT);
 1838                 sc->sis_tx_cnt++;
 1839         }
 1840 
 1841         /* Update producer index. */
 1842         sc->sis_tx_prod = prod;
 1843 
 1844         /* Remove MORE flag on the last descriptor. */
 1845         prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
 1846         f = &sc->sis_tx_list[prod];
 1847         f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
 1848 
 1849         /* Lastly transfer ownership of packet to the controller. */
 1850         f = &sc->sis_tx_list[frag];
 1851         f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
 1852 
 1853         /* Swap the last and the first dmamaps. */
 1854         map = txd->tx_dmamap;
 1855         txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
 1856         sc->sis_txdesc[prod].tx_dmamap = map;
 1857         sc->sis_txdesc[prod].tx_m = *m_head;
 1858 
 1859         return (0);
 1860 }
 1861 
 1862 static void
 1863 sis_start(struct ifnet *ifp)
 1864 {
 1865         struct sis_softc        *sc;
 1866 
 1867         sc = ifp->if_softc;
 1868         SIS_LOCK(sc);
 1869         sis_startl(ifp);
 1870         SIS_UNLOCK(sc);
 1871 }
 1872 
 1873 static void
 1874 sis_startl(struct ifnet *ifp)
 1875 {
 1876         struct sis_softc        *sc;
 1877         struct mbuf             *m_head;
 1878         int                     queued;
 1879 
 1880         sc = ifp->if_softc;
 1881 
 1882         SIS_LOCK_ASSERT(sc);
 1883 
 1884         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 1885             IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
 1886                 return;
 1887 
 1888         for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
 1889             sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
 1890                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 1891                 if (m_head == NULL)
 1892                         break;
 1893 
 1894                 if (sis_encap(sc, &m_head) != 0) {
 1895                         if (m_head == NULL)
 1896                                 break;
 1897                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 1898                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1899                         break;
 1900                 }
 1901 
 1902                 queued++;
 1903 
 1904                 /*
 1905                  * If there's a BPF listener, bounce a copy of this frame
 1906                  * to him.
 1907                  */
 1908                 BPF_MTAP(ifp, m_head);
 1909         }
 1910 
 1911         if (queued) {
 1912                 /* Transmit */
 1913                 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
 1914                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1915                 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
 1916 
 1917                 /*
 1918                  * Set a timeout in case the chip goes out to lunch.
 1919                  */
 1920                 sc->sis_watchdog_timer = 5;
 1921         }
 1922 }
 1923 
 1924 static void
 1925 sis_init(void *xsc)
 1926 {
 1927         struct sis_softc        *sc = xsc;
 1928 
 1929         SIS_LOCK(sc);
 1930         sis_initl(sc);
 1931         SIS_UNLOCK(sc);
 1932 }
 1933 
 1934 static void
 1935 sis_initl(struct sis_softc *sc)
 1936 {
 1937         struct ifnet            *ifp = sc->sis_ifp;
 1938         struct mii_data         *mii;
 1939         uint8_t                 *eaddr;
 1940 
 1941         SIS_LOCK_ASSERT(sc);
 1942 
 1943         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 1944                 return;
 1945 
 1946         /*
 1947          * Cancel pending I/O and free all RX/TX buffers.
 1948          */
 1949         sis_stop(sc);
 1950         /*
 1951          * Reset the chip to a known state.
 1952          */
 1953         sis_reset(sc);
 1954 #ifdef notyet
 1955         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
 1956                 /*
 1957                  * Configure 400usec of interrupt holdoff.  This is based
 1958                  * on emperical tests on a Soekris 4801.
 1959                  */
 1960                 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
 1961         }
 1962 #endif
 1963 
 1964         mii = device_get_softc(sc->sis_miibus);
 1965 
 1966         /* Set MAC address */
 1967         eaddr = IF_LLADDR(sc->sis_ifp);
 1968         if (sc->sis_type == SIS_TYPE_83815) {
 1969                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
 1970                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
 1971                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
 1972                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
 1973                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
 1974                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
 1975         } else {
 1976                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
 1977                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
 1978                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
 1979                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
 1980                 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
 1981                 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
 1982         }
 1983 
 1984         /* Init circular TX/RX lists. */
 1985         if (sis_ring_init(sc) != 0) {
 1986                 device_printf(sc->sis_dev,
 1987                     "initialization failed: no memory for rx buffers\n");
 1988                 sis_stop(sc);
 1989                 return;
 1990         }
 1991 
 1992         if (sc->sis_type == SIS_TYPE_83815) {
 1993                 if (sc->sis_manual_pad != 0)
 1994                         sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
 1995                 else
 1996                         sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
 1997         }
 1998 
 1999         /*
 2000          * Short Cable Receive Errors (MP21.E)
 2001          * also: Page 78 of the DP83815 data sheet (september 2002 version)
 2002          * recommends the following register settings "for optimum
 2003          * performance." for rev 15C.  Set this also for 15D parts as
 2004          * they require it in practice.
 2005          */
 2006         if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
 2007                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
 2008                 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
 2009                 /* set val for c2 */
 2010                 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
 2011                 /* load/kill c2 */
 2012                 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
 2013                 /* rais SD off, from 4 to c */
 2014                 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
 2015                 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
 2016         }
 2017 
 2018         sis_rxfilter(sc);
 2019         /* Turn the receive filter on */
 2020         SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
 2021 
 2022         /*
 2023          * Load the address of the RX and TX lists.
 2024          */
 2025         CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
 2026         CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
 2027 
 2028         /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
 2029          * the PCI bus. When this bit is set, the Max DMA Burst Size
 2030          * for TX/RX DMA should be no larger than 16 double words.
 2031          */
 2032         if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
 2033                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
 2034         } else {
 2035                 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
 2036         }
 2037 
 2038         /* Accept Long Packets for VLAN support */
 2039         SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
 2040 
 2041         /*
 2042          * Assume 100Mbps link, actual MAC configuration is done
 2043          * after getting a valid link.
 2044          */
 2045         CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
 2046 
 2047         /*
 2048          * Enable interrupts.
 2049          */
 2050         CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
 2051 #ifdef DEVICE_POLLING
 2052         /*
 2053          * ... only enable interrupts if we are not polling, make sure
 2054          * they are off otherwise.
 2055          */
 2056         if (ifp->if_capenable & IFCAP_POLLING)
 2057                 CSR_WRITE_4(sc, SIS_IER, 0);
 2058         else
 2059 #endif
 2060         CSR_WRITE_4(sc, SIS_IER, 1);
 2061 
 2062         /* Clear MAC disable. */
 2063         SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
 2064 
 2065         sc->sis_flags &= ~SIS_FLAG_LINK;
 2066         mii_mediachg(mii);
 2067 
 2068         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 2069         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 2070 
 2071         callout_reset(&sc->sis_stat_ch, hz,  sis_tick, sc);
 2072 }
 2073 
 2074 /*
 2075  * Set media options.
 2076  */
 2077 static int
 2078 sis_ifmedia_upd(struct ifnet *ifp)
 2079 {
 2080         struct sis_softc        *sc;
 2081         struct mii_data         *mii;
 2082         struct mii_softc        *miisc;
 2083         int                     error;
 2084 
 2085         sc = ifp->if_softc;
 2086 
 2087         SIS_LOCK(sc);
 2088         mii = device_get_softc(sc->sis_miibus);
 2089         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 2090                 PHY_RESET(miisc);
 2091         error = mii_mediachg(mii);
 2092         SIS_UNLOCK(sc);
 2093 
 2094         return (error);
 2095 }
 2096 
 2097 /*
 2098  * Report current media status.
 2099  */
 2100 static void
 2101 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 2102 {
 2103         struct sis_softc        *sc;
 2104         struct mii_data         *mii;
 2105 
 2106         sc = ifp->if_softc;
 2107 
 2108         SIS_LOCK(sc);
 2109         mii = device_get_softc(sc->sis_miibus);
 2110         mii_pollstat(mii);
 2111         ifmr->ifm_active = mii->mii_media_active;
 2112         ifmr->ifm_status = mii->mii_media_status;
 2113         SIS_UNLOCK(sc);
 2114 }
 2115 
 2116 static int
 2117 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 2118 {
 2119         struct sis_softc        *sc = ifp->if_softc;
 2120         struct ifreq            *ifr = (struct ifreq *) data;
 2121         struct mii_data         *mii;
 2122         int                     error = 0, mask;
 2123 
 2124         switch (command) {
 2125         case SIOCSIFFLAGS:
 2126                 SIS_LOCK(sc);
 2127                 if (ifp->if_flags & IFF_UP) {
 2128                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
 2129                             ((ifp->if_flags ^ sc->sis_if_flags) &
 2130                             (IFF_PROMISC | IFF_ALLMULTI)) != 0)
 2131                                 sis_rxfilter(sc);
 2132                         else
 2133                                 sis_initl(sc);
 2134                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 2135                         sis_stop(sc);
 2136                 sc->sis_if_flags = ifp->if_flags;
 2137                 SIS_UNLOCK(sc);
 2138                 break;
 2139         case SIOCADDMULTI:
 2140         case SIOCDELMULTI:
 2141                 SIS_LOCK(sc);
 2142                 sis_rxfilter(sc);
 2143                 SIS_UNLOCK(sc);
 2144                 break;
 2145         case SIOCGIFMEDIA:
 2146         case SIOCSIFMEDIA:
 2147                 mii = device_get_softc(sc->sis_miibus);
 2148                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 2149                 break;
 2150         case SIOCSIFCAP:
 2151                 SIS_LOCK(sc);
 2152                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 2153 #ifdef DEVICE_POLLING
 2154                 if ((mask & IFCAP_POLLING) != 0 &&
 2155                     (IFCAP_POLLING & ifp->if_capabilities) != 0) {
 2156                         ifp->if_capenable ^= IFCAP_POLLING;
 2157                         if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
 2158                                 error = ether_poll_register(sis_poll, ifp);
 2159                                 if (error != 0) {
 2160                                         SIS_UNLOCK(sc);
 2161                                         break;
 2162                                 }
 2163                                 /* Disable interrupts. */
 2164                                 CSR_WRITE_4(sc, SIS_IER, 0);
 2165                         } else {
 2166                                 error = ether_poll_deregister(ifp);
 2167                                 /* Enable interrupts. */
 2168                                 CSR_WRITE_4(sc, SIS_IER, 1);
 2169                         }
 2170                 }
 2171 #endif /* DEVICE_POLLING */
 2172                 if ((mask & IFCAP_WOL) != 0 &&
 2173                     (ifp->if_capabilities & IFCAP_WOL) != 0) {
 2174                         if ((mask & IFCAP_WOL_UCAST) != 0)
 2175                                 ifp->if_capenable ^= IFCAP_WOL_UCAST;
 2176                         if ((mask & IFCAP_WOL_MCAST) != 0)
 2177                                 ifp->if_capenable ^= IFCAP_WOL_MCAST;
 2178                         if ((mask & IFCAP_WOL_MAGIC) != 0)
 2179                                 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
 2180                 }
 2181                 SIS_UNLOCK(sc);
 2182                 break;
 2183         default:
 2184                 error = ether_ioctl(ifp, command, data);
 2185                 break;
 2186         }
 2187 
 2188         return (error);
 2189 }
 2190 
 2191 static void
 2192 sis_watchdog(struct sis_softc *sc)
 2193 {
 2194 
 2195         SIS_LOCK_ASSERT(sc);
 2196 
 2197         if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
 2198                 return;
 2199 
 2200         device_printf(sc->sis_dev, "watchdog timeout\n");
 2201         sc->sis_ifp->if_oerrors++;
 2202 
 2203         sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 2204         sis_initl(sc);
 2205 
 2206         if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
 2207                 sis_startl(sc->sis_ifp);
 2208 }
 2209 
 2210 /*
 2211  * Stop the adapter and free any mbufs allocated to the
 2212  * RX and TX lists.
 2213  */
 2214 static void
 2215 sis_stop(struct sis_softc *sc)
 2216 {
 2217         struct ifnet *ifp;
 2218         struct sis_rxdesc *rxd;
 2219         struct sis_txdesc *txd;
 2220         int i;
 2221 
 2222         SIS_LOCK_ASSERT(sc);
 2223 
 2224         ifp = sc->sis_ifp;
 2225         sc->sis_watchdog_timer = 0;
 2226 
 2227         callout_stop(&sc->sis_stat_ch);
 2228 
 2229         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 2230         CSR_WRITE_4(sc, SIS_IER, 0);
 2231         CSR_WRITE_4(sc, SIS_IMR, 0);
 2232         CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
 2233         SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
 2234         DELAY(1000);
 2235         CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
 2236         CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
 2237 
 2238         sc->sis_flags &= ~SIS_FLAG_LINK;
 2239 
 2240         /*
 2241          * Free data in the RX lists.
 2242          */
 2243         for (i = 0; i < SIS_RX_LIST_CNT; i++) {
 2244                 rxd = &sc->sis_rxdesc[i];
 2245                 if (rxd->rx_m != NULL) {
 2246                         bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
 2247                             BUS_DMASYNC_POSTREAD);
 2248                         bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
 2249                         m_freem(rxd->rx_m);
 2250                         rxd->rx_m = NULL;
 2251                 }
 2252         }
 2253 
 2254         /*
 2255          * Free the TX list buffers.
 2256          */
 2257         for (i = 0; i < SIS_TX_LIST_CNT; i++) {
 2258                 txd = &sc->sis_txdesc[i];
 2259                 if (txd->tx_m != NULL) {
 2260                         bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
 2261                             BUS_DMASYNC_POSTWRITE);
 2262                         bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
 2263                         m_freem(txd->tx_m);
 2264                         txd->tx_m = NULL;
 2265                 }
 2266         }
 2267 }
 2268 
 2269 /*
 2270  * Stop all chip I/O so that the kernel's probe routines don't
 2271  * get confused by errant DMAs when rebooting.
 2272  */
 2273 static int
 2274 sis_shutdown(device_t dev)
 2275 {
 2276 
 2277         return (sis_suspend(dev));
 2278 }
 2279 
 2280 static int
 2281 sis_suspend(device_t dev)
 2282 {
 2283         struct sis_softc        *sc;
 2284 
 2285         sc = device_get_softc(dev);
 2286         SIS_LOCK(sc);
 2287         sis_stop(sc);
 2288         sis_wol(sc);
 2289         SIS_UNLOCK(sc);
 2290         return (0);
 2291 }
 2292 
 2293 static int
 2294 sis_resume(device_t dev)
 2295 {
 2296         struct sis_softc        *sc;
 2297         struct ifnet            *ifp;
 2298 
 2299         sc = device_get_softc(dev);
 2300         SIS_LOCK(sc);
 2301         ifp = sc->sis_ifp;
 2302         if ((ifp->if_flags & IFF_UP) != 0) {
 2303                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 2304                 sis_initl(sc);
 2305         }
 2306         SIS_UNLOCK(sc);
 2307         return (0);
 2308 }
 2309 
 2310 static void
 2311 sis_wol(struct sis_softc *sc)
 2312 {
 2313         struct ifnet            *ifp;
 2314         uint32_t                val;
 2315         uint16_t                pmstat;
 2316         int                     pmc;
 2317 
 2318         ifp = sc->sis_ifp;
 2319         if ((ifp->if_capenable & IFCAP_WOL) == 0)
 2320                 return;
 2321 
 2322         if (sc->sis_type == SIS_TYPE_83815) {
 2323                 /* Reset RXDP. */
 2324                 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
 2325 
 2326                 /* Configure WOL events. */
 2327                 CSR_READ_4(sc, NS_WCSR);
 2328                 val = 0;
 2329                 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
 2330                         val |= NS_WCSR_WAKE_UCAST;
 2331                 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
 2332                         val |= NS_WCSR_WAKE_MCAST;
 2333                 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 2334                         val |= NS_WCSR_WAKE_MAGIC;
 2335                 CSR_WRITE_4(sc, NS_WCSR, val);
 2336                 /* Enable PME and clear PMESTS. */
 2337                 val = CSR_READ_4(sc, NS_CLKRUN);
 2338                 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
 2339                 CSR_WRITE_4(sc, NS_CLKRUN, val);
 2340                 /* Enable silent RX mode. */
 2341                 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
 2342         } else {
 2343                 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
 2344                         return;
 2345                 val = 0;
 2346                 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 2347                         val |= SIS_PWRMAN_WOL_MAGIC;
 2348                 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
 2349                 /* Request PME. */
 2350                 pmstat = pci_read_config(sc->sis_dev,
 2351                     pmc + PCIR_POWER_STATUS, 2);
 2352                 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
 2353                 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 2354                         pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
 2355                 pci_write_config(sc->sis_dev,
 2356                     pmc + PCIR_POWER_STATUS, pmstat, 2);
 2357         }
 2358 }
 2359 
 2360 static void
 2361 sis_add_sysctls(struct sis_softc *sc)
 2362 {
 2363         struct sysctl_ctx_list *ctx;
 2364         struct sysctl_oid_list *children;
 2365         char tn[32];
 2366         int unit;
 2367 
 2368         ctx = device_get_sysctl_ctx(sc->sis_dev);
 2369         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
 2370 
 2371         unit = device_get_unit(sc->sis_dev);
 2372         /*
 2373          * Unlike most other controllers, NS DP83815/DP83816 controllers
 2374          * seem to pad with 0xFF when it encounter short frames.  According
 2375          * to RFC 1042 the pad bytes should be 0x00.  Turning this tunable
 2376          * on will have driver pad manully but it's disabled by default
 2377          * because it will consume extra CPU cycles for short frames.
 2378          */
 2379         sc->sis_manual_pad = 0;
 2380         snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit);
 2381         TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad);
 2382         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
 2383             CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames");
 2384 }
 2385 
 2386 static device_method_t sis_methods[] = {
 2387         /* Device interface */
 2388         DEVMETHOD(device_probe,         sis_probe),
 2389         DEVMETHOD(device_attach,        sis_attach),
 2390         DEVMETHOD(device_detach,        sis_detach),
 2391         DEVMETHOD(device_shutdown,      sis_shutdown),
 2392         DEVMETHOD(device_suspend,       sis_suspend),
 2393         DEVMETHOD(device_resume,        sis_resume),
 2394 
 2395         /* MII interface */
 2396         DEVMETHOD(miibus_readreg,       sis_miibus_readreg),
 2397         DEVMETHOD(miibus_writereg,      sis_miibus_writereg),
 2398         DEVMETHOD(miibus_statchg,       sis_miibus_statchg),
 2399 
 2400         DEVMETHOD_END
 2401 };
 2402 
 2403 static driver_t sis_driver = {
 2404         "sis",
 2405         sis_methods,
 2406         sizeof(struct sis_softc)
 2407 };
 2408 
 2409 static devclass_t sis_devclass;
 2410 
 2411 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
 2412 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);

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