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sys/dev/sis/if_sis.c
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1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #ifdef HAVE_KERNEL_OPTION_HEADERS 62 #include "opt_device_polling.h" 63 #endif 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/bus.h> 68 #include <sys/endian.h> 69 #include <sys/kernel.h> 70 #include <sys/lock.h> 71 #include <sys/malloc.h> 72 #include <sys/mbuf.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 #include <sys/sockio.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/bus.h> 91 #include <sys/rman.h> 92 93 #include <dev/mii/mii.h> 94 #include <dev/mii/mii_bitbang.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #define SIS_USEIOSPACE 101 102 #include <dev/sis/if_sisreg.h> 103 104 MODULE_DEPEND(sis, pci, 1, 1, 1); 105 MODULE_DEPEND(sis, ether, 1, 1, 1); 106 MODULE_DEPEND(sis, miibus, 1, 1, 1); 107 108 /* "device miibus" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 112 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 113 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 114 115 /* 116 * register space access macros 117 */ 118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 119 120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 121 122 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 123 124 #define CSR_BARRIER(sc, reg, length, flags) \ 125 bus_barrier(sc->sis_res[0], reg, length, flags) 126 127 /* 128 * Various supported device vendors/types and their names. 129 */ 130 static const struct sis_type const sis_devs[] = { 131 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 132 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 133 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 134 { 0, 0, NULL } 135 }; 136 137 static int sis_detach(device_t); 138 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 139 static int sis_dma_alloc(struct sis_softc *); 140 static void sis_dma_free(struct sis_softc *); 141 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 142 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 143 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 144 #ifndef __NO_STRICT_ALIGNMENT 145 static __inline void sis_fixup_rx(struct mbuf *); 146 #endif 147 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 static int sis_ifmedia_upd(struct ifnet *); 149 static void sis_init(void *); 150 static void sis_initl(struct sis_softc *); 151 static void sis_intr(void *); 152 static int sis_ioctl(struct ifnet *, u_long, caddr_t); 153 static uint32_t sis_mii_bitbang_read(device_t); 154 static void sis_mii_bitbang_write(device_t, uint32_t); 155 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 156 static int sis_resume(device_t); 157 static void sis_rxeof(struct sis_softc *); 158 static void sis_rxfilter(struct sis_softc *); 159 static void sis_rxfilter_ns(struct sis_softc *); 160 static void sis_rxfilter_sis(struct sis_softc *); 161 static void sis_start(struct ifnet *); 162 static void sis_startl(struct ifnet *); 163 static void sis_stop(struct sis_softc *); 164 static int sis_suspend(device_t); 165 static void sis_add_sysctls(struct sis_softc *); 166 static void sis_watchdog(struct sis_softc *); 167 static void sis_wol(struct sis_softc *); 168 169 /* 170 * MII bit-bang glue 171 */ 172 static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 173 sis_mii_bitbang_read, 174 sis_mii_bitbang_write, 175 { 176 SIS_MII_DATA, /* MII_BIT_MDO */ 177 SIS_MII_DATA, /* MII_BIT_MDI */ 178 SIS_MII_CLK, /* MII_BIT_MDC */ 179 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 180 0, /* MII_BIT_DIR_PHY_HOST */ 181 } 182 }; 183 184 static struct resource_spec sis_res_spec[] = { 185 #ifdef SIS_USEIOSPACE 186 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 187 #else 188 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 189 #endif 190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 191 { -1, 0 } 192 }; 193 194 #define SIS_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, \ 196 CSR_READ_4(sc, reg) | (x)) 197 198 #define SIS_CLRBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) & ~(x)) 201 202 #define SIO_SET(x) \ 203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 204 205 #define SIO_CLR(x) \ 206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 207 208 /* 209 * Routine to reverse the bits in a word. Stolen almost 210 * verbatim from /usr/games/fortune. 211 */ 212 static uint16_t 213 sis_reverse(uint16_t n) 214 { 215 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 216 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 217 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 218 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 219 220 return (n); 221 } 222 223 static void 224 sis_delay(struct sis_softc *sc) 225 { 226 int idx; 227 228 for (idx = (300 / 33) + 1; idx > 0; idx--) 229 CSR_READ_4(sc, SIS_CSR); 230 } 231 232 static void 233 sis_eeprom_idle(struct sis_softc *sc) 234 { 235 int i; 236 237 SIO_SET(SIS_EECTL_CSEL); 238 sis_delay(sc); 239 SIO_SET(SIS_EECTL_CLK); 240 sis_delay(sc); 241 242 for (i = 0; i < 25; i++) { 243 SIO_CLR(SIS_EECTL_CLK); 244 sis_delay(sc); 245 SIO_SET(SIS_EECTL_CLK); 246 sis_delay(sc); 247 } 248 249 SIO_CLR(SIS_EECTL_CLK); 250 sis_delay(sc); 251 SIO_CLR(SIS_EECTL_CSEL); 252 sis_delay(sc); 253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 254 } 255 256 /* 257 * Send a read command and address to the EEPROM, check for ACK. 258 */ 259 static void 260 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 261 { 262 int d, i; 263 264 d = addr | SIS_EECMD_READ; 265 266 /* 267 * Feed in each bit and stobe the clock. 268 */ 269 for (i = 0x400; i; i >>= 1) { 270 if (d & i) { 271 SIO_SET(SIS_EECTL_DIN); 272 } else { 273 SIO_CLR(SIS_EECTL_DIN); 274 } 275 sis_delay(sc); 276 SIO_SET(SIS_EECTL_CLK); 277 sis_delay(sc); 278 SIO_CLR(SIS_EECTL_CLK); 279 sis_delay(sc); 280 } 281 } 282 283 /* 284 * Read a word of data stored in the EEPROM at address 'addr.' 285 */ 286 static void 287 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 288 { 289 int i; 290 uint16_t word = 0; 291 292 /* Force EEPROM to idle state. */ 293 sis_eeprom_idle(sc); 294 295 /* Enter EEPROM access mode. */ 296 sis_delay(sc); 297 SIO_CLR(SIS_EECTL_CLK); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CSEL); 300 sis_delay(sc); 301 302 /* 303 * Send address of word we want to read. 304 */ 305 sis_eeprom_putbyte(sc, addr); 306 307 /* 308 * Start reading bits from EEPROM. 309 */ 310 for (i = 0x8000; i; i >>= 1) { 311 SIO_SET(SIS_EECTL_CLK); 312 sis_delay(sc); 313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 314 word |= i; 315 sis_delay(sc); 316 SIO_CLR(SIS_EECTL_CLK); 317 sis_delay(sc); 318 } 319 320 /* Turn off EEPROM access mode. */ 321 sis_eeprom_idle(sc); 322 323 *dest = word; 324 } 325 326 /* 327 * Read a sequence of words from the EEPROM. 328 */ 329 static void 330 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 331 { 332 int i; 333 uint16_t word = 0, *ptr; 334 335 for (i = 0; i < cnt; i++) { 336 sis_eeprom_getword(sc, off + i, &word); 337 ptr = (uint16_t *)(dest + (i * 2)); 338 if (swap) 339 *ptr = ntohs(word); 340 else 341 *ptr = word; 342 } 343 } 344 345 #if defined(__i386__) || defined(__amd64__) 346 static device_t 347 sis_find_bridge(device_t dev) 348 { 349 devclass_t pci_devclass; 350 device_t *pci_devices; 351 int pci_count = 0; 352 device_t *pci_children; 353 int pci_childcount = 0; 354 device_t *busp, *childp; 355 device_t child = NULL; 356 int i, j; 357 358 if ((pci_devclass = devclass_find("pci")) == NULL) 359 return (NULL); 360 361 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 362 363 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 364 if (device_get_children(*busp, &pci_children, &pci_childcount)) 365 continue; 366 for (j = 0, childp = pci_children; 367 j < pci_childcount; j++, childp++) { 368 if (pci_get_vendor(*childp) == SIS_VENDORID && 369 pci_get_device(*childp) == 0x0008) { 370 child = *childp; 371 free(pci_children, M_TEMP); 372 goto done; 373 } 374 } 375 free(pci_children, M_TEMP); 376 } 377 378 done: 379 free(pci_devices, M_TEMP); 380 return (child); 381 } 382 383 static void 384 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 385 { 386 device_t bridge; 387 uint8_t reg; 388 int i; 389 bus_space_tag_t btag; 390 391 bridge = sis_find_bridge(dev); 392 if (bridge == NULL) 393 return; 394 reg = pci_read_config(bridge, 0x48, 1); 395 pci_write_config(bridge, 0x48, reg|0x40, 1); 396 397 /* XXX */ 398 #if defined(__i386__) 399 btag = I386_BUS_SPACE_IO; 400 #elif defined(__amd64__) 401 btag = AMD64_BUS_SPACE_IO; 402 #endif 403 404 for (i = 0; i < cnt; i++) { 405 bus_space_write_1(btag, 0x0, 0x70, i + off); 406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 407 } 408 409 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 410 } 411 412 static void 413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 414 { 415 uint32_t filtsave, csrsave; 416 417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 418 csrsave = CSR_READ_4(sc, SIS_CSR); 419 420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 421 CSR_WRITE_4(sc, SIS_CSR, 0); 422 423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 424 425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 431 432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 433 CSR_WRITE_4(sc, SIS_CSR, csrsave); 434 } 435 #endif 436 437 /* 438 * Read the MII serial port for the MII bit-bang module. 439 */ 440 static uint32_t 441 sis_mii_bitbang_read(device_t dev) 442 { 443 struct sis_softc *sc; 444 uint32_t val; 445 446 sc = device_get_softc(dev); 447 448 val = CSR_READ_4(sc, SIS_EECTL); 449 CSR_BARRIER(sc, SIS_EECTL, 4, 450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 451 return (val); 452 } 453 454 /* 455 * Write the MII serial port for the MII bit-bang module. 456 */ 457 static void 458 sis_mii_bitbang_write(device_t dev, uint32_t val) 459 { 460 struct sis_softc *sc; 461 462 sc = device_get_softc(dev); 463 464 CSR_WRITE_4(sc, SIS_EECTL, val); 465 CSR_BARRIER(sc, SIS_EECTL, 4, 466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 467 } 468 469 static int 470 sis_miibus_readreg(device_t dev, int phy, int reg) 471 { 472 struct sis_softc *sc; 473 474 sc = device_get_softc(dev); 475 476 if (sc->sis_type == SIS_TYPE_83815) { 477 if (phy != 0) 478 return (0); 479 /* 480 * The NatSemi chip can take a while after 481 * a reset to come ready, during which the BMSR 482 * returns a value of 0. This is *never* supposed 483 * to happen: some of the BMSR bits are meant to 484 * be hardwired in the on position, and this can 485 * confuse the miibus code a bit during the probe 486 * and attach phase. So we make an effort to check 487 * for this condition and wait for it to clear. 488 */ 489 if (!CSR_READ_4(sc, NS_BMSR)) 490 DELAY(1000); 491 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 492 } 493 494 /* 495 * Chipsets < SIS_635 seem not to be able to read/write 496 * through mdio. Use the enhanced PHY access register 497 * again for them. 498 */ 499 if (sc->sis_type == SIS_TYPE_900 && 500 sc->sis_rev < SIS_REV_635) { 501 int i, val = 0; 502 503 if (phy != 0) 504 return (0); 505 506 CSR_WRITE_4(sc, SIS_PHYCTL, 507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 508 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 509 510 for (i = 0; i < SIS_TIMEOUT; i++) { 511 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 512 break; 513 } 514 515 if (i == SIS_TIMEOUT) { 516 device_printf(sc->sis_dev, 517 "PHY failed to come ready\n"); 518 return (0); 519 } 520 521 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 522 523 if (val == 0xFFFF) 524 return (0); 525 526 return (val); 527 } else 528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 529 reg)); 530 } 531 532 static int 533 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 534 { 535 struct sis_softc *sc; 536 537 sc = device_get_softc(dev); 538 539 if (sc->sis_type == SIS_TYPE_83815) { 540 if (phy != 0) 541 return (0); 542 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 543 return (0); 544 } 545 546 /* 547 * Chipsets < SIS_635 seem not to be able to read/write 548 * through mdio. Use the enhanced PHY access register 549 * again for them. 550 */ 551 if (sc->sis_type == SIS_TYPE_900 && 552 sc->sis_rev < SIS_REV_635) { 553 int i; 554 555 if (phy != 0) 556 return (0); 557 558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 559 (reg << 6) | SIS_PHYOP_WRITE); 560 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 561 562 for (i = 0; i < SIS_TIMEOUT; i++) { 563 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 564 break; 565 } 566 567 if (i == SIS_TIMEOUT) 568 device_printf(sc->sis_dev, 569 "PHY failed to come ready\n"); 570 } else 571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 572 data); 573 return (0); 574 } 575 576 static void 577 sis_miibus_statchg(device_t dev) 578 { 579 struct sis_softc *sc; 580 struct mii_data *mii; 581 struct ifnet *ifp; 582 uint32_t reg; 583 584 sc = device_get_softc(dev); 585 SIS_LOCK_ASSERT(sc); 586 587 mii = device_get_softc(sc->sis_miibus); 588 ifp = sc->sis_ifp; 589 if (mii == NULL || ifp == NULL || 590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 591 return; 592 593 sc->sis_flags &= ~SIS_FLAG_LINK; 594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 595 (IFM_ACTIVE | IFM_AVALID)) { 596 switch (IFM_SUBTYPE(mii->mii_media_active)) { 597 case IFM_10_T: 598 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 599 sc->sis_flags |= SIS_FLAG_LINK; 600 break; 601 case IFM_100_TX: 602 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 603 sc->sis_flags |= SIS_FLAG_LINK; 604 break; 605 default: 606 break; 607 } 608 } 609 610 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 611 /* 612 * Stopping MACs seem to reset SIS_TX_LISTPTR and 613 * SIS_RX_LISTPTR which in turn requires resetting 614 * TX/RX buffers. So just don't do anything for 615 * lost link. 616 */ 617 return; 618 } 619 620 /* Set full/half duplex mode. */ 621 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 622 SIS_SETBIT(sc, SIS_TX_CFG, 623 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 624 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 625 } else { 626 SIS_CLRBIT(sc, SIS_TX_CFG, 627 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 628 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 629 } 630 631 if (sc->sis_type == SIS_TYPE_83816) { 632 /* 633 * MPII03.D: Half Duplex Excessive Collisions. 634 * Also page 49 in 83816 manual 635 */ 636 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 637 } 638 639 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 640 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 641 /* 642 * Short Cable Receive Errors (MP21.E) 643 */ 644 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 645 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 646 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 647 DELAY(100); 648 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 649 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 650 device_printf(sc->sis_dev, 651 "Applying short cable fix (reg=%x)\n", reg); 652 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 653 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 654 } 655 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 656 } 657 /* Enable TX/RX MACs. */ 658 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 659 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 660 } 661 662 static uint32_t 663 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 664 { 665 uint32_t crc; 666 667 /* Compute CRC for the address value. */ 668 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 669 670 /* 671 * return the filter bit position 672 * 673 * The NatSemi chip has a 512-bit filter, which is 674 * different than the SiS, so we special-case it. 675 */ 676 if (sc->sis_type == SIS_TYPE_83815) 677 return (crc >> 23); 678 else if (sc->sis_rev >= SIS_REV_635 || 679 sc->sis_rev == SIS_REV_900B) 680 return (crc >> 24); 681 else 682 return (crc >> 25); 683 } 684 685 static void 686 sis_rxfilter(struct sis_softc *sc) 687 { 688 689 SIS_LOCK_ASSERT(sc); 690 691 if (sc->sis_type == SIS_TYPE_83815) 692 sis_rxfilter_ns(sc); 693 else 694 sis_rxfilter_sis(sc); 695 } 696 697 static void 698 sis_rxfilter_ns(struct sis_softc *sc) 699 { 700 struct ifnet *ifp; 701 struct ifmultiaddr *ifma; 702 uint32_t h, i, filter; 703 int bit, index; 704 705 ifp = sc->sis_ifp; 706 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 707 if (filter & SIS_RXFILTCTL_ENABLE) { 708 /* 709 * Filter should be disabled to program other bits. 710 */ 711 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 712 CSR_READ_4(sc, SIS_RXFILT_CTL); 713 } 714 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 715 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 716 SIS_RXFILTCTL_ALLMULTI); 717 718 if (ifp->if_flags & IFF_BROADCAST) 719 filter |= SIS_RXFILTCTL_BROAD; 720 /* 721 * For the NatSemi chip, we have to explicitly enable the 722 * reception of ARP frames, as well as turn on the 'perfect 723 * match' filter where we store the station address, otherwise 724 * we won't receive unicasts meant for this host. 725 */ 726 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 727 728 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 729 filter |= SIS_RXFILTCTL_ALLMULTI; 730 if (ifp->if_flags & IFF_PROMISC) 731 filter |= SIS_RXFILTCTL_ALLPHYS; 732 } else { 733 /* 734 * We have to explicitly enable the multicast hash table 735 * on the NatSemi chip if we want to use it, which we do. 736 */ 737 filter |= NS_RXFILTCTL_MCHASH; 738 739 /* first, zot all the existing hash bits */ 740 for (i = 0; i < 32; i++) { 741 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 742 (i * 2)); 743 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 744 } 745 746 IF_ADDR_LOCK(ifp); 747 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 748 if (ifma->ifma_addr->sa_family != AF_LINK) 749 continue; 750 h = sis_mchash(sc, 751 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 752 index = h >> 3; 753 bit = h & 0x1F; 754 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 755 index); 756 if (bit > 0xF) 757 bit -= 0x10; 758 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 759 } 760 IF_ADDR_UNLOCK(ifp); 761 } 762 763 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 764 CSR_READ_4(sc, SIS_RXFILT_CTL); 765 } 766 767 static void 768 sis_rxfilter_sis(struct sis_softc *sc) 769 { 770 struct ifnet *ifp; 771 struct ifmultiaddr *ifma; 772 uint32_t filter, h, i, n; 773 uint16_t hashes[16]; 774 775 ifp = sc->sis_ifp; 776 777 /* hash table size */ 778 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 779 n = 16; 780 else 781 n = 8; 782 783 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 784 if (filter & SIS_RXFILTCTL_ENABLE) { 785 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL); 786 CSR_READ_4(sc, SIS_RXFILT_CTL); 787 } 788 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 789 SIS_RXFILTCTL_ALLMULTI); 790 if (ifp->if_flags & IFF_BROADCAST) 791 filter |= SIS_RXFILTCTL_BROAD; 792 793 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 794 filter |= SIS_RXFILTCTL_ALLMULTI; 795 if (ifp->if_flags & IFF_PROMISC) 796 filter |= SIS_RXFILTCTL_ALLPHYS; 797 for (i = 0; i < n; i++) 798 hashes[i] = ~0; 799 } else { 800 for (i = 0; i < n; i++) 801 hashes[i] = 0; 802 i = 0; 803 IF_ADDR_LOCK(ifp); 804 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 805 if (ifma->ifma_addr->sa_family != AF_LINK) 806 continue; 807 h = sis_mchash(sc, 808 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 809 hashes[h >> 4] |= 1 << (h & 0xf); 810 i++; 811 } 812 IF_ADDR_UNLOCK(ifp); 813 if (i > n) { 814 filter |= SIS_RXFILTCTL_ALLMULTI; 815 for (i = 0; i < n; i++) 816 hashes[i] = ~0; 817 } 818 } 819 820 for (i = 0; i < n; i++) { 821 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 822 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 823 } 824 825 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 826 CSR_READ_4(sc, SIS_RXFILT_CTL); 827 } 828 829 static void 830 sis_reset(struct sis_softc *sc) 831 { 832 int i; 833 834 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 835 836 for (i = 0; i < SIS_TIMEOUT; i++) { 837 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 838 break; 839 } 840 841 if (i == SIS_TIMEOUT) 842 device_printf(sc->sis_dev, "reset never completed\n"); 843 844 /* Wait a little while for the chip to get its brains in order. */ 845 DELAY(1000); 846 847 /* 848 * If this is a NetSemi chip, make sure to clear 849 * PME mode. 850 */ 851 if (sc->sis_type == SIS_TYPE_83815) { 852 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 853 CSR_WRITE_4(sc, NS_CLKRUN, 0); 854 } else { 855 /* Disable WOL functions. */ 856 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 857 } 858 } 859 860 /* 861 * Probe for an SiS chip. Check the PCI vendor and device 862 * IDs against our list and return a device name if we find a match. 863 */ 864 static int 865 sis_probe(device_t dev) 866 { 867 const struct sis_type *t; 868 869 t = sis_devs; 870 871 while (t->sis_name != NULL) { 872 if ((pci_get_vendor(dev) == t->sis_vid) && 873 (pci_get_device(dev) == t->sis_did)) { 874 device_set_desc(dev, t->sis_name); 875 return (BUS_PROBE_DEFAULT); 876 } 877 t++; 878 } 879 880 return (ENXIO); 881 } 882 883 /* 884 * Attach the interface. Allocate softc structures, do ifmedia 885 * setup and ethernet/BPF attach. 886 */ 887 static int 888 sis_attach(device_t dev) 889 { 890 u_char eaddr[ETHER_ADDR_LEN]; 891 struct sis_softc *sc; 892 struct ifnet *ifp; 893 int error = 0, pmc, waittime = 0; 894 895 waittime = 0; 896 sc = device_get_softc(dev); 897 898 sc->sis_dev = dev; 899 900 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 901 MTX_DEF); 902 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 903 904 if (pci_get_device(dev) == SIS_DEVICEID_900) 905 sc->sis_type = SIS_TYPE_900; 906 if (pci_get_device(dev) == SIS_DEVICEID_7016) 907 sc->sis_type = SIS_TYPE_7016; 908 if (pci_get_vendor(dev) == NS_VENDORID) 909 sc->sis_type = SIS_TYPE_83815; 910 911 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 912 /* 913 * Map control/status registers. 914 */ 915 pci_enable_busmaster(dev); 916 917 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 918 if (error) { 919 device_printf(dev, "couldn't allocate resources\n"); 920 goto fail; 921 } 922 923 /* Reset the adapter. */ 924 sis_reset(sc); 925 926 if (sc->sis_type == SIS_TYPE_900 && 927 (sc->sis_rev == SIS_REV_635 || 928 sc->sis_rev == SIS_REV_900B)) { 929 SIO_SET(SIS_CFG_RND_CNT); 930 SIO_SET(SIS_CFG_PERR_DETECT); 931 } 932 933 /* 934 * Get station address from the EEPROM. 935 */ 936 switch (pci_get_vendor(dev)) { 937 case NS_VENDORID: 938 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 939 940 /* We can't update the device description, so spew */ 941 if (sc->sis_srr == NS_SRR_15C) 942 device_printf(dev, "Silicon Revision: DP83815C\n"); 943 else if (sc->sis_srr == NS_SRR_15D) 944 device_printf(dev, "Silicon Revision: DP83815D\n"); 945 else if (sc->sis_srr == NS_SRR_16A) 946 device_printf(dev, "Silicon Revision: DP83816A\n"); 947 else 948 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 949 950 /* 951 * Reading the MAC address out of the EEPROM on 952 * the NatSemi chip takes a bit more work than 953 * you'd expect. The address spans 4 16-bit words, 954 * with the first word containing only a single bit. 955 * You have to shift everything over one bit to 956 * get it aligned properly. Also, the bits are 957 * stored backwards (the LSB is really the MSB, 958 * and so on) so you have to reverse them in order 959 * to get the MAC address into the form we want. 960 * Why? Who the hell knows. 961 */ 962 { 963 uint16_t tmp[4]; 964 965 sis_read_eeprom(sc, (caddr_t)&tmp, 966 NS_EE_NODEADDR, 4, 0); 967 968 /* Shift everything over one bit. */ 969 tmp[3] = tmp[3] >> 1; 970 tmp[3] |= tmp[2] << 15; 971 tmp[2] = tmp[2] >> 1; 972 tmp[2] |= tmp[1] << 15; 973 tmp[1] = tmp[1] >> 1; 974 tmp[1] |= tmp[0] << 15; 975 976 /* Now reverse all the bits. */ 977 tmp[3] = sis_reverse(tmp[3]); 978 tmp[2] = sis_reverse(tmp[2]); 979 tmp[1] = sis_reverse(tmp[1]); 980 981 eaddr[0] = (tmp[1] >> 0) & 0xFF; 982 eaddr[1] = (tmp[1] >> 8) & 0xFF; 983 eaddr[2] = (tmp[2] >> 0) & 0xFF; 984 eaddr[3] = (tmp[2] >> 8) & 0xFF; 985 eaddr[4] = (tmp[3] >> 0) & 0xFF; 986 eaddr[5] = (tmp[3] >> 8) & 0xFF; 987 } 988 break; 989 case SIS_VENDORID: 990 default: 991 #if defined(__i386__) || defined(__amd64__) 992 /* 993 * If this is a SiS 630E chipset with an embedded 994 * SiS 900 controller, we have to read the MAC address 995 * from the APC CMOS RAM. Our method for doing this 996 * is very ugly since we have to reach out and grab 997 * ahold of hardware for which we cannot properly 998 * allocate resources. This code is only compiled on 999 * the i386 architecture since the SiS 630E chipset 1000 * is for x86 motherboards only. Note that there are 1001 * a lot of magic numbers in this hack. These are 1002 * taken from SiS's Linux driver. I'd like to replace 1003 * them with proper symbolic definitions, but that 1004 * requires some datasheets that I don't have access 1005 * to at the moment. 1006 */ 1007 if (sc->sis_rev == SIS_REV_630S || 1008 sc->sis_rev == SIS_REV_630E || 1009 sc->sis_rev == SIS_REV_630EA1) 1010 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1011 1012 else if (sc->sis_rev == SIS_REV_635 || 1013 sc->sis_rev == SIS_REV_630ET) 1014 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1015 else if (sc->sis_rev == SIS_REV_96x) { 1016 /* Allow to read EEPROM from LAN. It is shared 1017 * between a 1394 controller and the NIC and each 1018 * time we access it, we need to set SIS_EECMD_REQ. 1019 */ 1020 SIO_SET(SIS_EECMD_REQ); 1021 for (waittime = 0; waittime < SIS_TIMEOUT; 1022 waittime++) { 1023 /* Force EEPROM to idle state. */ 1024 sis_eeprom_idle(sc); 1025 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1026 sis_read_eeprom(sc, (caddr_t)&eaddr, 1027 SIS_EE_NODEADDR, 3, 0); 1028 break; 1029 } 1030 DELAY(1); 1031 } 1032 /* 1033 * Set SIS_EECTL_CLK to high, so a other master 1034 * can operate on the i2c bus. 1035 */ 1036 SIO_SET(SIS_EECTL_CLK); 1037 /* Refuse EEPROM access by LAN */ 1038 SIO_SET(SIS_EECMD_DONE); 1039 } else 1040 #endif 1041 sis_read_eeprom(sc, (caddr_t)&eaddr, 1042 SIS_EE_NODEADDR, 3, 0); 1043 break; 1044 } 1045 1046 sis_add_sysctls(sc); 1047 1048 /* Allocate DMA'able memory. */ 1049 if ((error = sis_dma_alloc(sc)) != 0) 1050 goto fail; 1051 1052 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1053 if (ifp == NULL) { 1054 device_printf(dev, "can not if_alloc()\n"); 1055 error = ENOSPC; 1056 goto fail; 1057 } 1058 ifp->if_softc = sc; 1059 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1060 ifp->if_mtu = ETHERMTU; 1061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1062 ifp->if_ioctl = sis_ioctl; 1063 ifp->if_start = sis_start; 1064 ifp->if_init = sis_init; 1065 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1066 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1067 IFQ_SET_READY(&ifp->if_snd); 1068 1069 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1070 if (sc->sis_type == SIS_TYPE_83815) 1071 ifp->if_capabilities |= IFCAP_WOL; 1072 else 1073 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1074 ifp->if_capenable = ifp->if_capabilities; 1075 } 1076 1077 /* 1078 * Do MII setup. 1079 */ 1080 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1081 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1082 if (error != 0) { 1083 device_printf(dev, "attaching PHYs failed\n"); 1084 goto fail; 1085 } 1086 1087 /* 1088 * Call MI attach routine. 1089 */ 1090 ether_ifattach(ifp, eaddr); 1091 1092 /* 1093 * Tell the upper layer(s) we support long frames. 1094 */ 1095 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1096 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1097 ifp->if_capenable = ifp->if_capabilities; 1098 #ifdef DEVICE_POLLING 1099 ifp->if_capabilities |= IFCAP_POLLING; 1100 #endif 1101 1102 /* Hook interrupt last to avoid having to lock softc */ 1103 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1104 NULL, sis_intr, sc, &sc->sis_intrhand); 1105 1106 if (error) { 1107 device_printf(dev, "couldn't set up irq\n"); 1108 ether_ifdetach(ifp); 1109 goto fail; 1110 } 1111 1112 fail: 1113 if (error) 1114 sis_detach(dev); 1115 1116 return (error); 1117 } 1118 1119 /* 1120 * Shutdown hardware and free up resources. This can be called any 1121 * time after the mutex has been initialized. It is called in both 1122 * the error case in attach and the normal detach case so it needs 1123 * to be careful about only freeing resources that have actually been 1124 * allocated. 1125 */ 1126 static int 1127 sis_detach(device_t dev) 1128 { 1129 struct sis_softc *sc; 1130 struct ifnet *ifp; 1131 1132 sc = device_get_softc(dev); 1133 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1134 ifp = sc->sis_ifp; 1135 1136 #ifdef DEVICE_POLLING 1137 if (ifp->if_capenable & IFCAP_POLLING) 1138 ether_poll_deregister(ifp); 1139 #endif 1140 1141 /* These should only be active if attach succeeded. */ 1142 if (device_is_attached(dev)) { 1143 SIS_LOCK(sc); 1144 sis_stop(sc); 1145 SIS_UNLOCK(sc); 1146 callout_drain(&sc->sis_stat_ch); 1147 ether_ifdetach(ifp); 1148 } 1149 if (sc->sis_miibus) 1150 device_delete_child(dev, sc->sis_miibus); 1151 bus_generic_detach(dev); 1152 1153 if (sc->sis_intrhand) 1154 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1155 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1156 1157 if (ifp) 1158 if_free(ifp); 1159 1160 sis_dma_free(sc); 1161 1162 mtx_destroy(&sc->sis_mtx); 1163 1164 return (0); 1165 } 1166 1167 struct sis_dmamap_arg { 1168 bus_addr_t sis_busaddr; 1169 }; 1170 1171 static void 1172 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1173 { 1174 struct sis_dmamap_arg *ctx; 1175 1176 if (error != 0) 1177 return; 1178 1179 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1180 1181 ctx = (struct sis_dmamap_arg *)arg; 1182 ctx->sis_busaddr = segs[0].ds_addr; 1183 } 1184 1185 static int 1186 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1187 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1188 bus_addr_t *paddr, const char *msg) 1189 { 1190 struct sis_dmamap_arg ctx; 1191 int error; 1192 1193 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1194 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1195 maxsize, 0, NULL, NULL, tag); 1196 if (error != 0) { 1197 device_printf(sc->sis_dev, 1198 "could not create %s dma tag\n", msg); 1199 return (ENOMEM); 1200 } 1201 /* Allocate DMA'able memory for ring. */ 1202 error = bus_dmamem_alloc(*tag, (void **)ring, 1203 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1204 if (error != 0) { 1205 device_printf(sc->sis_dev, 1206 "could not allocate DMA'able memory for %s\n", msg); 1207 return (ENOMEM); 1208 } 1209 /* Load the address of the ring. */ 1210 ctx.sis_busaddr = 0; 1211 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1212 &ctx, BUS_DMA_NOWAIT); 1213 if (error != 0) { 1214 device_printf(sc->sis_dev, 1215 "could not load DMA'able memory for %s\n", msg); 1216 return (ENOMEM); 1217 } 1218 *paddr = ctx.sis_busaddr; 1219 return (0); 1220 } 1221 1222 static int 1223 sis_dma_alloc(struct sis_softc *sc) 1224 { 1225 struct sis_rxdesc *rxd; 1226 struct sis_txdesc *txd; 1227 int error, i; 1228 1229 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1230 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1231 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1232 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1233 0, NULL, NULL, &sc->sis_parent_tag); 1234 if (error != 0) { 1235 device_printf(sc->sis_dev, 1236 "could not allocate parent dma tag\n"); 1237 return (ENOMEM); 1238 } 1239 1240 /* Create RX ring. */ 1241 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1242 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1243 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1244 if (error) 1245 return (error); 1246 1247 /* Create TX ring. */ 1248 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1249 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1250 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1251 if (error) 1252 return (error); 1253 1254 /* Create tag for RX mbufs. */ 1255 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1256 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1257 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1258 if (error) { 1259 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1260 return (error); 1261 } 1262 1263 /* Create tag for TX mbufs. */ 1264 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1266 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1267 &sc->sis_tx_tag); 1268 if (error) { 1269 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1270 return (error); 1271 } 1272 1273 /* Create DMA maps for RX buffers. */ 1274 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1275 if (error) { 1276 device_printf(sc->sis_dev, 1277 "can't create spare DMA map for RX\n"); 1278 return (error); 1279 } 1280 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1281 rxd = &sc->sis_rxdesc[i]; 1282 rxd->rx_m = NULL; 1283 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1284 if (error) { 1285 device_printf(sc->sis_dev, 1286 "can't create DMA map for RX\n"); 1287 return (error); 1288 } 1289 } 1290 1291 /* Create DMA maps for TX buffers. */ 1292 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1293 txd = &sc->sis_txdesc[i]; 1294 txd->tx_m = NULL; 1295 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1296 if (error) { 1297 device_printf(sc->sis_dev, 1298 "can't create DMA map for TX\n"); 1299 return (error); 1300 } 1301 } 1302 1303 return (0); 1304 } 1305 1306 static void 1307 sis_dma_free(struct sis_softc *sc) 1308 { 1309 struct sis_rxdesc *rxd; 1310 struct sis_txdesc *txd; 1311 int i; 1312 1313 /* Destroy DMA maps for RX buffers. */ 1314 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1315 rxd = &sc->sis_rxdesc[i]; 1316 if (rxd->rx_dmamap) 1317 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1318 } 1319 if (sc->sis_rx_sparemap) 1320 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1321 1322 /* Destroy DMA maps for TX buffers. */ 1323 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1324 txd = &sc->sis_txdesc[i]; 1325 if (txd->tx_dmamap) 1326 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1327 } 1328 1329 if (sc->sis_rx_tag) 1330 bus_dma_tag_destroy(sc->sis_rx_tag); 1331 if (sc->sis_tx_tag) 1332 bus_dma_tag_destroy(sc->sis_tx_tag); 1333 1334 /* Destroy RX ring. */ 1335 if (sc->sis_rx_list_map) 1336 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1337 if (sc->sis_rx_list_map && sc->sis_rx_list) 1338 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1339 sc->sis_rx_list_map); 1340 1341 if (sc->sis_rx_list_tag) 1342 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1343 1344 /* Destroy TX ring. */ 1345 if (sc->sis_tx_list_map) 1346 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1347 1348 if (sc->sis_tx_list_map && sc->sis_tx_list) 1349 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1350 sc->sis_tx_list_map); 1351 1352 if (sc->sis_tx_list_tag) 1353 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1354 1355 /* Destroy the parent tag. */ 1356 if (sc->sis_parent_tag) 1357 bus_dma_tag_destroy(sc->sis_parent_tag); 1358 } 1359 1360 /* 1361 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1362 * we arrange the descriptors in a closed ring, so that the last descriptor 1363 * points back to the first. 1364 */ 1365 static int 1366 sis_ring_init(struct sis_softc *sc) 1367 { 1368 struct sis_rxdesc *rxd; 1369 struct sis_txdesc *txd; 1370 bus_addr_t next; 1371 int error, i; 1372 1373 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1374 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1375 txd = &sc->sis_txdesc[i]; 1376 txd->tx_m = NULL; 1377 if (i == SIS_TX_LIST_CNT - 1) 1378 next = SIS_TX_RING_ADDR(sc, 0); 1379 else 1380 next = SIS_TX_RING_ADDR(sc, i + 1); 1381 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1382 } 1383 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1384 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1386 1387 sc->sis_rx_cons = 0; 1388 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1389 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1390 rxd = &sc->sis_rxdesc[i]; 1391 rxd->rx_desc = &sc->sis_rx_list[i]; 1392 if (i == SIS_RX_LIST_CNT - 1) 1393 next = SIS_RX_RING_ADDR(sc, 0); 1394 else 1395 next = SIS_RX_RING_ADDR(sc, i + 1); 1396 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1397 error = sis_newbuf(sc, rxd); 1398 if (error) 1399 return (error); 1400 } 1401 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1403 1404 return (0); 1405 } 1406 1407 /* 1408 * Initialize an RX descriptor and attach an MBUF cluster. 1409 */ 1410 static int 1411 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1412 { 1413 struct mbuf *m; 1414 bus_dma_segment_t segs[1]; 1415 bus_dmamap_t map; 1416 int nsegs; 1417 1418 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1419 if (m == NULL) 1420 return (ENOBUFS); 1421 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1422 #ifndef __NO_STRICT_ALIGNMENT 1423 m_adj(m, SIS_RX_BUF_ALIGN); 1424 #endif 1425 1426 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1427 segs, &nsegs, 0) != 0) { 1428 m_freem(m); 1429 return (ENOBUFS); 1430 } 1431 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1432 1433 if (rxd->rx_m != NULL) { 1434 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1435 BUS_DMASYNC_POSTREAD); 1436 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1437 } 1438 map = rxd->rx_dmamap; 1439 rxd->rx_dmamap = sc->sis_rx_sparemap; 1440 sc->sis_rx_sparemap = map; 1441 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1442 rxd->rx_m = m; 1443 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1444 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1445 return (0); 1446 } 1447 1448 static __inline void 1449 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1450 { 1451 1452 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1453 } 1454 1455 #ifndef __NO_STRICT_ALIGNMENT 1456 static __inline void 1457 sis_fixup_rx(struct mbuf *m) 1458 { 1459 uint16_t *src, *dst; 1460 int i; 1461 1462 src = mtod(m, uint16_t *); 1463 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1464 1465 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1466 *dst++ = *src++; 1467 1468 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1469 } 1470 #endif 1471 1472 /* 1473 * A frame has been uploaded: pass the resulting mbuf chain up to 1474 * the higher level protocols. 1475 */ 1476 static void 1477 sis_rxeof(struct sis_softc *sc) 1478 { 1479 struct mbuf *m; 1480 struct ifnet *ifp; 1481 struct sis_rxdesc *rxd; 1482 struct sis_desc *cur_rx; 1483 int prog, rx_cons, total_len; 1484 uint32_t rxstat; 1485 1486 SIS_LOCK_ASSERT(sc); 1487 1488 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1490 1491 rx_cons = sc->sis_rx_cons; 1492 ifp = sc->sis_ifp; 1493 1494 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1495 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1496 #ifdef DEVICE_POLLING 1497 if (ifp->if_capenable & IFCAP_POLLING) { 1498 if (sc->rxcycles <= 0) 1499 break; 1500 sc->rxcycles--; 1501 } 1502 #endif 1503 cur_rx = &sc->sis_rx_list[rx_cons]; 1504 rxstat = le32toh(cur_rx->sis_cmdsts); 1505 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1506 break; 1507 rxd = &sc->sis_rxdesc[rx_cons]; 1508 1509 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1510 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1511 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1512 ETHER_CRC_LEN)) 1513 rxstat &= ~SIS_RXSTAT_GIANT; 1514 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1515 ifp->if_ierrors++; 1516 if (rxstat & SIS_RXSTAT_COLL) 1517 ifp->if_collisions++; 1518 sis_discard_rxbuf(rxd); 1519 continue; 1520 } 1521 1522 /* Add a new receive buffer to the ring. */ 1523 m = rxd->rx_m; 1524 if (sis_newbuf(sc, rxd) != 0) { 1525 ifp->if_iqdrops++; 1526 sis_discard_rxbuf(rxd); 1527 continue; 1528 } 1529 1530 /* No errors; receive the packet. */ 1531 m->m_pkthdr.len = m->m_len = total_len; 1532 #ifndef __NO_STRICT_ALIGNMENT 1533 /* 1534 * On architectures without alignment problems we try to 1535 * allocate a new buffer for the receive ring, and pass up 1536 * the one where the packet is already, saving the expensive 1537 * copy operation. 1538 */ 1539 sis_fixup_rx(m); 1540 #endif 1541 ifp->if_ipackets++; 1542 m->m_pkthdr.rcvif = ifp; 1543 1544 SIS_UNLOCK(sc); 1545 (*ifp->if_input)(ifp, m); 1546 SIS_LOCK(sc); 1547 } 1548 1549 if (prog > 0) { 1550 sc->sis_rx_cons = rx_cons; 1551 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1553 } 1554 1555 } 1556 1557 /* 1558 * A frame was downloaded to the chip. It's safe for us to clean up 1559 * the list buffers. 1560 */ 1561 1562 static void 1563 sis_txeof(struct sis_softc *sc) 1564 { 1565 struct ifnet *ifp; 1566 struct sis_desc *cur_tx; 1567 struct sis_txdesc *txd; 1568 uint32_t cons, txstat; 1569 1570 SIS_LOCK_ASSERT(sc); 1571 1572 cons = sc->sis_tx_cons; 1573 if (cons == sc->sis_tx_prod) 1574 return; 1575 1576 ifp = sc->sis_ifp; 1577 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1578 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1579 1580 /* 1581 * Go through our tx list and free mbufs for those 1582 * frames that have been transmitted. 1583 */ 1584 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1585 cur_tx = &sc->sis_tx_list[cons]; 1586 txstat = le32toh(cur_tx->sis_cmdsts); 1587 if ((txstat & SIS_CMDSTS_OWN) != 0) 1588 break; 1589 txd = &sc->sis_txdesc[cons]; 1590 if (txd->tx_m != NULL) { 1591 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1592 BUS_DMASYNC_POSTWRITE); 1593 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1594 m_freem(txd->tx_m); 1595 txd->tx_m = NULL; 1596 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1597 ifp->if_opackets++; 1598 ifp->if_collisions += 1599 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1600 } else { 1601 ifp->if_oerrors++; 1602 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1603 ifp->if_collisions++; 1604 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1605 ifp->if_collisions++; 1606 } 1607 } 1608 sc->sis_tx_cnt--; 1609 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1610 } 1611 sc->sis_tx_cons = cons; 1612 if (sc->sis_tx_cnt == 0) 1613 sc->sis_watchdog_timer = 0; 1614 } 1615 1616 static void 1617 sis_tick(void *xsc) 1618 { 1619 struct sis_softc *sc; 1620 struct mii_data *mii; 1621 struct ifnet *ifp; 1622 1623 sc = xsc; 1624 SIS_LOCK_ASSERT(sc); 1625 ifp = sc->sis_ifp; 1626 1627 mii = device_get_softc(sc->sis_miibus); 1628 mii_tick(mii); 1629 sis_watchdog(sc); 1630 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1631 sis_miibus_statchg(sc->sis_dev); 1632 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1633 } 1634 1635 #ifdef DEVICE_POLLING 1636 static poll_handler_t sis_poll; 1637 1638 static void 1639 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1640 { 1641 struct sis_softc *sc = ifp->if_softc; 1642 1643 SIS_LOCK(sc); 1644 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1645 SIS_UNLOCK(sc); 1646 return; 1647 } 1648 1649 /* 1650 * On the sis, reading the status register also clears it. 1651 * So before returning to intr mode we must make sure that all 1652 * possible pending sources of interrupts have been served. 1653 * In practice this means run to completion the *eof routines, 1654 * and then call the interrupt routine 1655 */ 1656 sc->rxcycles = count; 1657 sis_rxeof(sc); 1658 sis_txeof(sc); 1659 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1660 sis_startl(ifp); 1661 1662 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1663 uint32_t status; 1664 1665 /* Reading the ISR register clears all interrupts. */ 1666 status = CSR_READ_4(sc, SIS_ISR); 1667 1668 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1669 ifp->if_ierrors++; 1670 1671 if (status & (SIS_ISR_RX_IDLE)) 1672 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1673 1674 if (status & SIS_ISR_SYSERR) { 1675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1676 sis_initl(sc); 1677 } 1678 } 1679 1680 SIS_UNLOCK(sc); 1681 } 1682 #endif /* DEVICE_POLLING */ 1683 1684 static void 1685 sis_intr(void *arg) 1686 { 1687 struct sis_softc *sc; 1688 struct ifnet *ifp; 1689 uint32_t status; 1690 1691 sc = arg; 1692 ifp = sc->sis_ifp; 1693 1694 SIS_LOCK(sc); 1695 #ifdef DEVICE_POLLING 1696 if (ifp->if_capenable & IFCAP_POLLING) { 1697 SIS_UNLOCK(sc); 1698 return; 1699 } 1700 #endif 1701 1702 /* Reading the ISR register clears all interrupts. */ 1703 status = CSR_READ_4(sc, SIS_ISR); 1704 if ((status & SIS_INTRS) == 0) { 1705 /* Not ours. */ 1706 SIS_UNLOCK(sc); 1707 return; 1708 } 1709 1710 /* Disable interrupts. */ 1711 CSR_WRITE_4(sc, SIS_IER, 0); 1712 1713 for (;(status & SIS_INTRS) != 0;) { 1714 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1715 break; 1716 if (status & 1717 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1718 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1719 sis_txeof(sc); 1720 1721 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1722 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1723 sis_rxeof(sc); 1724 1725 if (status & SIS_ISR_RX_OFLOW) 1726 ifp->if_ierrors++; 1727 1728 if (status & (SIS_ISR_RX_IDLE)) 1729 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1730 1731 if (status & SIS_ISR_SYSERR) { 1732 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1733 sis_initl(sc); 1734 SIS_UNLOCK(sc); 1735 return; 1736 } 1737 status = CSR_READ_4(sc, SIS_ISR); 1738 } 1739 1740 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1741 /* Re-enable interrupts. */ 1742 CSR_WRITE_4(sc, SIS_IER, 1); 1743 1744 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1745 sis_startl(ifp); 1746 } 1747 1748 SIS_UNLOCK(sc); 1749 } 1750 1751 /* 1752 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1753 * pointers to the fragment pointers. 1754 */ 1755 static int 1756 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1757 { 1758 struct mbuf *m; 1759 struct sis_txdesc *txd; 1760 struct sis_desc *f; 1761 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1762 bus_dmamap_t map; 1763 int error, i, frag, nsegs, prod; 1764 int padlen; 1765 1766 prod = sc->sis_tx_prod; 1767 txd = &sc->sis_txdesc[prod]; 1768 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1769 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1770 m = *m_head; 1771 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1772 if (M_WRITABLE(m) == 0) { 1773 /* Get a writable copy. */ 1774 m = m_dup(*m_head, M_DONTWAIT); 1775 m_freem(*m_head); 1776 if (m == NULL) { 1777 *m_head = NULL; 1778 return (ENOBUFS); 1779 } 1780 *m_head = m; 1781 } 1782 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1783 m = m_defrag(m, M_DONTWAIT); 1784 if (m == NULL) { 1785 m_freem(*m_head); 1786 *m_head = NULL; 1787 return (ENOBUFS); 1788 } 1789 } 1790 /* 1791 * Manually pad short frames, and zero the pad space 1792 * to avoid leaking data. 1793 */ 1794 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1795 m->m_pkthdr.len += padlen; 1796 m->m_len = m->m_pkthdr.len; 1797 *m_head = m; 1798 } 1799 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1800 *m_head, segs, &nsegs, 0); 1801 if (error == EFBIG) { 1802 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS); 1803 if (m == NULL) { 1804 m_freem(*m_head); 1805 *m_head = NULL; 1806 return (ENOBUFS); 1807 } 1808 *m_head = m; 1809 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1810 *m_head, segs, &nsegs, 0); 1811 if (error != 0) { 1812 m_freem(*m_head); 1813 *m_head = NULL; 1814 return (error); 1815 } 1816 } else if (error != 0) 1817 return (error); 1818 1819 /* Check for descriptor overruns. */ 1820 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1821 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1822 return (ENOBUFS); 1823 } 1824 1825 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1826 1827 frag = prod; 1828 for (i = 0; i < nsegs; i++) { 1829 f = &sc->sis_tx_list[prod]; 1830 if (i == 0) 1831 f->sis_cmdsts = htole32(segs[i].ds_len | 1832 SIS_CMDSTS_MORE); 1833 else 1834 f->sis_cmdsts = htole32(segs[i].ds_len | 1835 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1836 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1837 SIS_INC(prod, SIS_TX_LIST_CNT); 1838 sc->sis_tx_cnt++; 1839 } 1840 1841 /* Update producer index. */ 1842 sc->sis_tx_prod = prod; 1843 1844 /* Remove MORE flag on the last descriptor. */ 1845 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1846 f = &sc->sis_tx_list[prod]; 1847 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1848 1849 /* Lastly transfer ownership of packet to the controller. */ 1850 f = &sc->sis_tx_list[frag]; 1851 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1852 1853 /* Swap the last and the first dmamaps. */ 1854 map = txd->tx_dmamap; 1855 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1856 sc->sis_txdesc[prod].tx_dmamap = map; 1857 sc->sis_txdesc[prod].tx_m = *m_head; 1858 1859 return (0); 1860 } 1861 1862 static void 1863 sis_start(struct ifnet *ifp) 1864 { 1865 struct sis_softc *sc; 1866 1867 sc = ifp->if_softc; 1868 SIS_LOCK(sc); 1869 sis_startl(ifp); 1870 SIS_UNLOCK(sc); 1871 } 1872 1873 static void 1874 sis_startl(struct ifnet *ifp) 1875 { 1876 struct sis_softc *sc; 1877 struct mbuf *m_head; 1878 int queued; 1879 1880 sc = ifp->if_softc; 1881 1882 SIS_LOCK_ASSERT(sc); 1883 1884 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1885 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1886 return; 1887 1888 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1889 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1890 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1891 if (m_head == NULL) 1892 break; 1893 1894 if (sis_encap(sc, &m_head) != 0) { 1895 if (m_head == NULL) 1896 break; 1897 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1898 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1899 break; 1900 } 1901 1902 queued++; 1903 1904 /* 1905 * If there's a BPF listener, bounce a copy of this frame 1906 * to him. 1907 */ 1908 BPF_MTAP(ifp, m_head); 1909 } 1910 1911 if (queued) { 1912 /* Transmit */ 1913 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1915 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1916 1917 /* 1918 * Set a timeout in case the chip goes out to lunch. 1919 */ 1920 sc->sis_watchdog_timer = 5; 1921 } 1922 } 1923 1924 static void 1925 sis_init(void *xsc) 1926 { 1927 struct sis_softc *sc = xsc; 1928 1929 SIS_LOCK(sc); 1930 sis_initl(sc); 1931 SIS_UNLOCK(sc); 1932 } 1933 1934 static void 1935 sis_initl(struct sis_softc *sc) 1936 { 1937 struct ifnet *ifp = sc->sis_ifp; 1938 struct mii_data *mii; 1939 uint8_t *eaddr; 1940 1941 SIS_LOCK_ASSERT(sc); 1942 1943 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1944 return; 1945 1946 /* 1947 * Cancel pending I/O and free all RX/TX buffers. 1948 */ 1949 sis_stop(sc); 1950 /* 1951 * Reset the chip to a known state. 1952 */ 1953 sis_reset(sc); 1954 #ifdef notyet 1955 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1956 /* 1957 * Configure 400usec of interrupt holdoff. This is based 1958 * on emperical tests on a Soekris 4801. 1959 */ 1960 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1961 } 1962 #endif 1963 1964 mii = device_get_softc(sc->sis_miibus); 1965 1966 /* Set MAC address */ 1967 eaddr = IF_LLADDR(sc->sis_ifp); 1968 if (sc->sis_type == SIS_TYPE_83815) { 1969 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1970 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1971 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1972 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1973 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1974 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1975 } else { 1976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1982 } 1983 1984 /* Init circular TX/RX lists. */ 1985 if (sis_ring_init(sc) != 0) { 1986 device_printf(sc->sis_dev, 1987 "initialization failed: no memory for rx buffers\n"); 1988 sis_stop(sc); 1989 return; 1990 } 1991 1992 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) { 1993 if (sc->sis_manual_pad != 0) 1994 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 1995 else 1996 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 1997 } 1998 1999 /* 2000 * Short Cable Receive Errors (MP21.E) 2001 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2002 * recommends the following register settings "for optimum 2003 * performance." for rev 15C. Set this also for 15D parts as 2004 * they require it in practice. 2005 */ 2006 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2007 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2008 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2009 /* set val for c2 */ 2010 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2011 /* load/kill c2 */ 2012 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2013 /* rais SD off, from 4 to c */ 2014 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2015 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2016 } 2017 2018 sis_rxfilter(sc); 2019 /* Turn the receive filter on */ 2020 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2021 2022 /* 2023 * Load the address of the RX and TX lists. 2024 */ 2025 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2026 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2027 2028 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2029 * the PCI bus. When this bit is set, the Max DMA Burst Size 2030 * for TX/RX DMA should be no larger than 16 double words. 2031 */ 2032 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2033 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2034 } else { 2035 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2036 } 2037 2038 /* Accept Long Packets for VLAN support */ 2039 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2040 2041 /* 2042 * Assume 100Mbps link, actual MAC configuration is done 2043 * after getting a valid link. 2044 */ 2045 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2046 2047 /* 2048 * Enable interrupts. 2049 */ 2050 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2051 #ifdef DEVICE_POLLING 2052 /* 2053 * ... only enable interrupts if we are not polling, make sure 2054 * they are off otherwise. 2055 */ 2056 if (ifp->if_capenable & IFCAP_POLLING) 2057 CSR_WRITE_4(sc, SIS_IER, 0); 2058 else 2059 #endif 2060 CSR_WRITE_4(sc, SIS_IER, 1); 2061 2062 /* Clear MAC disable. */ 2063 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2064 2065 sc->sis_flags &= ~SIS_FLAG_LINK; 2066 mii_mediachg(mii); 2067 2068 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2069 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2070 2071 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2072 } 2073 2074 /* 2075 * Set media options. 2076 */ 2077 static int 2078 sis_ifmedia_upd(struct ifnet *ifp) 2079 { 2080 struct sis_softc *sc; 2081 struct mii_data *mii; 2082 struct mii_softc *miisc; 2083 int error; 2084 2085 sc = ifp->if_softc; 2086 2087 SIS_LOCK(sc); 2088 mii = device_get_softc(sc->sis_miibus); 2089 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2090 mii_phy_reset(miisc); 2091 error = mii_mediachg(mii); 2092 SIS_UNLOCK(sc); 2093 2094 return (error); 2095 } 2096 2097 /* 2098 * Report current media status. 2099 */ 2100 static void 2101 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2102 { 2103 struct sis_softc *sc; 2104 struct mii_data *mii; 2105 2106 sc = ifp->if_softc; 2107 2108 SIS_LOCK(sc); 2109 mii = device_get_softc(sc->sis_miibus); 2110 mii_pollstat(mii); 2111 ifmr->ifm_active = mii->mii_media_active; 2112 ifmr->ifm_status = mii->mii_media_status; 2113 SIS_UNLOCK(sc); 2114 } 2115 2116 static int 2117 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2118 { 2119 struct sis_softc *sc = ifp->if_softc; 2120 struct ifreq *ifr = (struct ifreq *) data; 2121 struct mii_data *mii; 2122 int error = 0, mask; 2123 2124 switch (command) { 2125 case SIOCSIFFLAGS: 2126 SIS_LOCK(sc); 2127 if (ifp->if_flags & IFF_UP) { 2128 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2129 ((ifp->if_flags ^ sc->sis_if_flags) & 2130 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2131 sis_rxfilter(sc); 2132 else 2133 sis_initl(sc); 2134 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2135 sis_stop(sc); 2136 sc->sis_if_flags = ifp->if_flags; 2137 SIS_UNLOCK(sc); 2138 break; 2139 case SIOCADDMULTI: 2140 case SIOCDELMULTI: 2141 SIS_LOCK(sc); 2142 sis_rxfilter(sc); 2143 SIS_UNLOCK(sc); 2144 break; 2145 case SIOCGIFMEDIA: 2146 case SIOCSIFMEDIA: 2147 mii = device_get_softc(sc->sis_miibus); 2148 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2149 break; 2150 case SIOCSIFCAP: 2151 SIS_LOCK(sc); 2152 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2153 #ifdef DEVICE_POLLING 2154 if ((mask & IFCAP_POLLING) != 0 && 2155 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2156 ifp->if_capenable ^= IFCAP_POLLING; 2157 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2158 error = ether_poll_register(sis_poll, ifp); 2159 if (error != 0) { 2160 SIS_UNLOCK(sc); 2161 break; 2162 } 2163 /* Disable interrupts. */ 2164 CSR_WRITE_4(sc, SIS_IER, 0); 2165 } else { 2166 error = ether_poll_deregister(ifp); 2167 /* Enable interrupts. */ 2168 CSR_WRITE_4(sc, SIS_IER, 1); 2169 } 2170 } 2171 #endif /* DEVICE_POLLING */ 2172 if ((mask & IFCAP_WOL) != 0 && 2173 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2174 if ((mask & IFCAP_WOL_UCAST) != 0) 2175 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2176 if ((mask & IFCAP_WOL_MCAST) != 0) 2177 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2178 if ((mask & IFCAP_WOL_MAGIC) != 0) 2179 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2180 } 2181 SIS_UNLOCK(sc); 2182 break; 2183 default: 2184 error = ether_ioctl(ifp, command, data); 2185 break; 2186 } 2187 2188 return (error); 2189 } 2190 2191 static void 2192 sis_watchdog(struct sis_softc *sc) 2193 { 2194 2195 SIS_LOCK_ASSERT(sc); 2196 2197 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2198 return; 2199 2200 device_printf(sc->sis_dev, "watchdog timeout\n"); 2201 sc->sis_ifp->if_oerrors++; 2202 2203 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2204 sis_initl(sc); 2205 2206 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2207 sis_startl(sc->sis_ifp); 2208 } 2209 2210 /* 2211 * Stop the adapter and free any mbufs allocated to the 2212 * RX and TX lists. 2213 */ 2214 static void 2215 sis_stop(struct sis_softc *sc) 2216 { 2217 struct ifnet *ifp; 2218 struct sis_rxdesc *rxd; 2219 struct sis_txdesc *txd; 2220 int i; 2221 2222 SIS_LOCK_ASSERT(sc); 2223 2224 ifp = sc->sis_ifp; 2225 sc->sis_watchdog_timer = 0; 2226 2227 callout_stop(&sc->sis_stat_ch); 2228 2229 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2230 CSR_WRITE_4(sc, SIS_IER, 0); 2231 CSR_WRITE_4(sc, SIS_IMR, 0); 2232 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2233 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2234 DELAY(1000); 2235 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2236 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2237 2238 sc->sis_flags &= ~SIS_FLAG_LINK; 2239 2240 /* 2241 * Free data in the RX lists. 2242 */ 2243 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2244 rxd = &sc->sis_rxdesc[i]; 2245 if (rxd->rx_m != NULL) { 2246 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2247 BUS_DMASYNC_POSTREAD); 2248 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2249 m_freem(rxd->rx_m); 2250 rxd->rx_m = NULL; 2251 } 2252 } 2253 2254 /* 2255 * Free the TX list buffers. 2256 */ 2257 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2258 txd = &sc->sis_txdesc[i]; 2259 if (txd->tx_m != NULL) { 2260 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2261 BUS_DMASYNC_POSTWRITE); 2262 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2263 m_freem(txd->tx_m); 2264 txd->tx_m = NULL; 2265 } 2266 } 2267 } 2268 2269 /* 2270 * Stop all chip I/O so that the kernel's probe routines don't 2271 * get confused by errant DMAs when rebooting. 2272 */ 2273 static int 2274 sis_shutdown(device_t dev) 2275 { 2276 2277 return (sis_suspend(dev)); 2278 } 2279 2280 static int 2281 sis_suspend(device_t dev) 2282 { 2283 struct sis_softc *sc; 2284 2285 sc = device_get_softc(dev); 2286 SIS_LOCK(sc); 2287 sis_stop(sc); 2288 sis_wol(sc); 2289 SIS_UNLOCK(sc); 2290 return (0); 2291 } 2292 2293 static int 2294 sis_resume(device_t dev) 2295 { 2296 struct sis_softc *sc; 2297 struct ifnet *ifp; 2298 2299 sc = device_get_softc(dev); 2300 SIS_LOCK(sc); 2301 ifp = sc->sis_ifp; 2302 if ((ifp->if_flags & IFF_UP) != 0) { 2303 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2304 sis_initl(sc); 2305 } 2306 SIS_UNLOCK(sc); 2307 return (0); 2308 } 2309 2310 static void 2311 sis_wol(struct sis_softc *sc) 2312 { 2313 struct ifnet *ifp; 2314 uint32_t val; 2315 uint16_t pmstat; 2316 int pmc; 2317 2318 ifp = sc->sis_ifp; 2319 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2320 return; 2321 2322 if (sc->sis_type == SIS_TYPE_83815) { 2323 /* Reset RXDP. */ 2324 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2325 2326 /* Configure WOL events. */ 2327 CSR_READ_4(sc, NS_WCSR); 2328 val = 0; 2329 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2330 val |= NS_WCSR_WAKE_UCAST; 2331 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2332 val |= NS_WCSR_WAKE_MCAST; 2333 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2334 val |= NS_WCSR_WAKE_MAGIC; 2335 CSR_WRITE_4(sc, NS_WCSR, val); 2336 /* Enable PME and clear PMESTS. */ 2337 val = CSR_READ_4(sc, NS_CLKRUN); 2338 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2339 CSR_WRITE_4(sc, NS_CLKRUN, val); 2340 /* Enable silent RX mode. */ 2341 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2342 } else { 2343 if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2344 return; 2345 val = 0; 2346 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2347 val |= SIS_PWRMAN_WOL_MAGIC; 2348 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2349 /* Request PME. */ 2350 pmstat = pci_read_config(sc->sis_dev, 2351 pmc + PCIR_POWER_STATUS, 2); 2352 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2353 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2354 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2355 pci_write_config(sc->sis_dev, 2356 pmc + PCIR_POWER_STATUS, pmstat, 2); 2357 } 2358 } 2359 2360 static void 2361 sis_add_sysctls(struct sis_softc *sc) 2362 { 2363 struct sysctl_ctx_list *ctx; 2364 struct sysctl_oid_list *children; 2365 char tn[32]; 2366 int unit; 2367 2368 ctx = device_get_sysctl_ctx(sc->sis_dev); 2369 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2370 2371 unit = device_get_unit(sc->sis_dev); 2372 /* 2373 * Unlike most other controllers, NS DP83815/DP83816 controllers 2374 * seem to pad with 0xFF when it encounter short frames. According 2375 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2376 * on will have driver pad manully but it's disabled by default 2377 * because it will consume extra CPU cycles for short frames. 2378 */ 2379 sc->sis_manual_pad = 0; 2380 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2381 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2382 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2383 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2384 } 2385 2386 static device_method_t sis_methods[] = { 2387 /* Device interface */ 2388 DEVMETHOD(device_probe, sis_probe), 2389 DEVMETHOD(device_attach, sis_attach), 2390 DEVMETHOD(device_detach, sis_detach), 2391 DEVMETHOD(device_shutdown, sis_shutdown), 2392 DEVMETHOD(device_suspend, sis_suspend), 2393 DEVMETHOD(device_resume, sis_resume), 2394 2395 /* bus interface */ 2396 DEVMETHOD(bus_print_child, bus_generic_print_child), 2397 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2398 2399 /* MII interface */ 2400 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2401 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2402 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2403 2404 { 0, 0 } 2405 }; 2406 2407 static driver_t sis_driver = { 2408 "sis", 2409 sis_methods, 2410 sizeof(struct sis_softc) 2411 }; 2412 2413 static devclass_t sis_devclass; 2414 2415 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2416 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
Cache object: 950656e6ef21979fafb201c726780146
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