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sys/dev/sis/if_sis.c
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1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/9.0/sys/dev/sis/if_sis.c 227277 2011-11-06 21:09:10Z marius $"); 36 37 /* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #ifdef HAVE_KERNEL_OPTION_HEADERS 62 #include "opt_device_polling.h" 63 #endif 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/bus.h> 68 #include <sys/endian.h> 69 #include <sys/kernel.h> 70 #include <sys/lock.h> 71 #include <sys/malloc.h> 72 #include <sys/mbuf.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 #include <sys/sockio.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/mii_bitbang.h> 94 #include <dev/mii/miivar.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 #define SIS_USEIOSPACE 100 101 #include <dev/sis/if_sisreg.h> 102 103 MODULE_DEPEND(sis, pci, 1, 1, 1); 104 MODULE_DEPEND(sis, ether, 1, 1, 1); 105 MODULE_DEPEND(sis, miibus, 1, 1, 1); 106 107 /* "device miibus" required. See GENERIC if you get errors here. */ 108 #include "miibus_if.h" 109 110 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 111 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 112 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 113 114 /* 115 * register space access macros 116 */ 117 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 118 119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 120 121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 122 123 #define CSR_BARRIER(sc, reg, length, flags) \ 124 bus_barrier(sc->sis_res[0], reg, length, flags) 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 static const struct sis_type const sis_devs[] = { 130 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 131 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 132 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 133 { 0, 0, NULL } 134 }; 135 136 static int sis_detach(device_t); 137 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 138 static int sis_dma_alloc(struct sis_softc *); 139 static void sis_dma_free(struct sis_softc *); 140 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 141 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 142 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 143 #ifndef __NO_STRICT_ALIGNMENT 144 static __inline void sis_fixup_rx(struct mbuf *); 145 #endif 146 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 static int sis_ifmedia_upd(struct ifnet *); 148 static void sis_init(void *); 149 static void sis_initl(struct sis_softc *); 150 static void sis_intr(void *); 151 static int sis_ioctl(struct ifnet *, u_long, caddr_t); 152 static uint32_t sis_mii_bitbang_read(device_t); 153 static void sis_mii_bitbang_write(device_t, uint32_t); 154 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 155 static int sis_resume(device_t); 156 static int sis_rxeof(struct sis_softc *); 157 static void sis_rxfilter(struct sis_softc *); 158 static void sis_rxfilter_ns(struct sis_softc *); 159 static void sis_rxfilter_sis(struct sis_softc *); 160 static void sis_start(struct ifnet *); 161 static void sis_startl(struct ifnet *); 162 static void sis_stop(struct sis_softc *); 163 static int sis_suspend(device_t); 164 static void sis_add_sysctls(struct sis_softc *); 165 static void sis_watchdog(struct sis_softc *); 166 static void sis_wol(struct sis_softc *); 167 168 /* 169 * MII bit-bang glue 170 */ 171 static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 172 sis_mii_bitbang_read, 173 sis_mii_bitbang_write, 174 { 175 SIS_MII_DATA, /* MII_BIT_MDO */ 176 SIS_MII_DATA, /* MII_BIT_MDI */ 177 SIS_MII_CLK, /* MII_BIT_MDC */ 178 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 179 0, /* MII_BIT_DIR_PHY_HOST */ 180 } 181 }; 182 183 static struct resource_spec sis_res_spec[] = { 184 #ifdef SIS_USEIOSPACE 185 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 186 #else 187 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 188 #endif 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 190 { -1, 0 } 191 }; 192 193 #define SIS_SETBIT(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, \ 195 CSR_READ_4(sc, reg) | (x)) 196 197 #define SIS_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) & ~(x)) 200 201 #define SIO_SET(x) \ 202 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 203 204 #define SIO_CLR(x) \ 205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 206 207 /* 208 * Routine to reverse the bits in a word. Stolen almost 209 * verbatim from /usr/games/fortune. 210 */ 211 static uint16_t 212 sis_reverse(uint16_t n) 213 { 214 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 215 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 216 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 217 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 218 219 return (n); 220 } 221 222 static void 223 sis_delay(struct sis_softc *sc) 224 { 225 int idx; 226 227 for (idx = (300 / 33) + 1; idx > 0; idx--) 228 CSR_READ_4(sc, SIS_CSR); 229 } 230 231 static void 232 sis_eeprom_idle(struct sis_softc *sc) 233 { 234 int i; 235 236 SIO_SET(SIS_EECTL_CSEL); 237 sis_delay(sc); 238 SIO_SET(SIS_EECTL_CLK); 239 sis_delay(sc); 240 241 for (i = 0; i < 25; i++) { 242 SIO_CLR(SIS_EECTL_CLK); 243 sis_delay(sc); 244 SIO_SET(SIS_EECTL_CLK); 245 sis_delay(sc); 246 } 247 248 SIO_CLR(SIS_EECTL_CLK); 249 sis_delay(sc); 250 SIO_CLR(SIS_EECTL_CSEL); 251 sis_delay(sc); 252 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 253 } 254 255 /* 256 * Send a read command and address to the EEPROM, check for ACK. 257 */ 258 static void 259 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 260 { 261 int d, i; 262 263 d = addr | SIS_EECMD_READ; 264 265 /* 266 * Feed in each bit and stobe the clock. 267 */ 268 for (i = 0x400; i; i >>= 1) { 269 if (d & i) { 270 SIO_SET(SIS_EECTL_DIN); 271 } else { 272 SIO_CLR(SIS_EECTL_DIN); 273 } 274 sis_delay(sc); 275 SIO_SET(SIS_EECTL_CLK); 276 sis_delay(sc); 277 SIO_CLR(SIS_EECTL_CLK); 278 sis_delay(sc); 279 } 280 } 281 282 /* 283 * Read a word of data stored in the EEPROM at address 'addr.' 284 */ 285 static void 286 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 287 { 288 int i; 289 uint16_t word = 0; 290 291 /* Force EEPROM to idle state. */ 292 sis_eeprom_idle(sc); 293 294 /* Enter EEPROM access mode. */ 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 SIO_SET(SIS_EECTL_CSEL); 299 sis_delay(sc); 300 301 /* 302 * Send address of word we want to read. 303 */ 304 sis_eeprom_putbyte(sc, addr); 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 for (i = 0x8000; i; i >>= 1) { 310 SIO_SET(SIS_EECTL_CLK); 311 sis_delay(sc); 312 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 313 word |= i; 314 sis_delay(sc); 315 SIO_CLR(SIS_EECTL_CLK); 316 sis_delay(sc); 317 } 318 319 /* Turn off EEPROM access mode. */ 320 sis_eeprom_idle(sc); 321 322 *dest = word; 323 } 324 325 /* 326 * Read a sequence of words from the EEPROM. 327 */ 328 static void 329 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 330 { 331 int i; 332 uint16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 sis_eeprom_getword(sc, off + i, &word); 336 ptr = (uint16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342 } 343 344 #if defined(__i386__) || defined(__amd64__) 345 static device_t 346 sis_find_bridge(device_t dev) 347 { 348 devclass_t pci_devclass; 349 device_t *pci_devices; 350 int pci_count = 0; 351 device_t *pci_children; 352 int pci_childcount = 0; 353 device_t *busp, *childp; 354 device_t child = NULL; 355 int i, j; 356 357 if ((pci_devclass = devclass_find("pci")) == NULL) 358 return (NULL); 359 360 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 361 362 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 363 if (device_get_children(*busp, &pci_children, &pci_childcount)) 364 continue; 365 for (j = 0, childp = pci_children; 366 j < pci_childcount; j++, childp++) { 367 if (pci_get_vendor(*childp) == SIS_VENDORID && 368 pci_get_device(*childp) == 0x0008) { 369 child = *childp; 370 free(pci_children, M_TEMP); 371 goto done; 372 } 373 } 374 free(pci_children, M_TEMP); 375 } 376 377 done: 378 free(pci_devices, M_TEMP); 379 return (child); 380 } 381 382 static void 383 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 384 { 385 device_t bridge; 386 uint8_t reg; 387 int i; 388 bus_space_tag_t btag; 389 390 bridge = sis_find_bridge(dev); 391 if (bridge == NULL) 392 return; 393 reg = pci_read_config(bridge, 0x48, 1); 394 pci_write_config(bridge, 0x48, reg|0x40, 1); 395 396 /* XXX */ 397 #if defined(__amd64__) || defined(__i386__) 398 btag = X86_BUS_SPACE_IO; 399 #endif 400 401 for (i = 0; i < cnt; i++) { 402 bus_space_write_1(btag, 0x0, 0x70, i + off); 403 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 404 } 405 406 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 407 } 408 409 static void 410 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 411 { 412 uint32_t filtsave, csrsave; 413 414 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 415 csrsave = CSR_READ_4(sc, SIS_CSR); 416 417 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 418 CSR_WRITE_4(sc, SIS_CSR, 0); 419 420 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 421 422 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 423 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 424 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 425 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 427 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 428 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 430 CSR_WRITE_4(sc, SIS_CSR, csrsave); 431 } 432 #endif 433 434 /* 435 * Read the MII serial port for the MII bit-bang module. 436 */ 437 static uint32_t 438 sis_mii_bitbang_read(device_t dev) 439 { 440 struct sis_softc *sc; 441 uint32_t val; 442 443 sc = device_get_softc(dev); 444 445 val = CSR_READ_4(sc, SIS_EECTL); 446 CSR_BARRIER(sc, SIS_EECTL, 4, 447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 448 return (val); 449 } 450 451 /* 452 * Write the MII serial port for the MII bit-bang module. 453 */ 454 static void 455 sis_mii_bitbang_write(device_t dev, uint32_t val) 456 { 457 struct sis_softc *sc; 458 459 sc = device_get_softc(dev); 460 461 CSR_WRITE_4(sc, SIS_EECTL, val); 462 CSR_BARRIER(sc, SIS_EECTL, 4, 463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 464 } 465 466 static int 467 sis_miibus_readreg(device_t dev, int phy, int reg) 468 { 469 struct sis_softc *sc; 470 471 sc = device_get_softc(dev); 472 473 if (sc->sis_type == SIS_TYPE_83815) { 474 if (phy != 0) 475 return (0); 476 /* 477 * The NatSemi chip can take a while after 478 * a reset to come ready, during which the BMSR 479 * returns a value of 0. This is *never* supposed 480 * to happen: some of the BMSR bits are meant to 481 * be hardwired in the on position, and this can 482 * confuse the miibus code a bit during the probe 483 * and attach phase. So we make an effort to check 484 * for this condition and wait for it to clear. 485 */ 486 if (!CSR_READ_4(sc, NS_BMSR)) 487 DELAY(1000); 488 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 489 } 490 491 /* 492 * Chipsets < SIS_635 seem not to be able to read/write 493 * through mdio. Use the enhanced PHY access register 494 * again for them. 495 */ 496 if (sc->sis_type == SIS_TYPE_900 && 497 sc->sis_rev < SIS_REV_635) { 498 int i, val = 0; 499 500 if (phy != 0) 501 return (0); 502 503 CSR_WRITE_4(sc, SIS_PHYCTL, 504 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 505 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 506 507 for (i = 0; i < SIS_TIMEOUT; i++) { 508 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 509 break; 510 } 511 512 if (i == SIS_TIMEOUT) { 513 device_printf(sc->sis_dev, 514 "PHY failed to come ready\n"); 515 return (0); 516 } 517 518 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 519 520 if (val == 0xFFFF) 521 return (0); 522 523 return (val); 524 } else 525 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 526 reg)); 527 } 528 529 static int 530 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 531 { 532 struct sis_softc *sc; 533 534 sc = device_get_softc(dev); 535 536 if (sc->sis_type == SIS_TYPE_83815) { 537 if (phy != 0) 538 return (0); 539 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 540 return (0); 541 } 542 543 /* 544 * Chipsets < SIS_635 seem not to be able to read/write 545 * through mdio. Use the enhanced PHY access register 546 * again for them. 547 */ 548 if (sc->sis_type == SIS_TYPE_900 && 549 sc->sis_rev < SIS_REV_635) { 550 int i; 551 552 if (phy != 0) 553 return (0); 554 555 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 556 (reg << 6) | SIS_PHYOP_WRITE); 557 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 558 559 for (i = 0; i < SIS_TIMEOUT; i++) { 560 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 561 break; 562 } 563 564 if (i == SIS_TIMEOUT) 565 device_printf(sc->sis_dev, 566 "PHY failed to come ready\n"); 567 } else 568 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 569 data); 570 return (0); 571 } 572 573 static void 574 sis_miibus_statchg(device_t dev) 575 { 576 struct sis_softc *sc; 577 struct mii_data *mii; 578 struct ifnet *ifp; 579 uint32_t reg; 580 581 sc = device_get_softc(dev); 582 SIS_LOCK_ASSERT(sc); 583 584 mii = device_get_softc(sc->sis_miibus); 585 ifp = sc->sis_ifp; 586 if (mii == NULL || ifp == NULL || 587 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 588 return; 589 590 sc->sis_flags &= ~SIS_FLAG_LINK; 591 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 592 (IFM_ACTIVE | IFM_AVALID)) { 593 switch (IFM_SUBTYPE(mii->mii_media_active)) { 594 case IFM_10_T: 595 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 596 sc->sis_flags |= SIS_FLAG_LINK; 597 break; 598 case IFM_100_TX: 599 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 600 sc->sis_flags |= SIS_FLAG_LINK; 601 break; 602 default: 603 break; 604 } 605 } 606 607 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 608 /* 609 * Stopping MACs seem to reset SIS_TX_LISTPTR and 610 * SIS_RX_LISTPTR which in turn requires resetting 611 * TX/RX buffers. So just don't do anything for 612 * lost link. 613 */ 614 return; 615 } 616 617 /* Set full/half duplex mode. */ 618 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 619 SIS_SETBIT(sc, SIS_TX_CFG, 620 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 621 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 622 } else { 623 SIS_CLRBIT(sc, SIS_TX_CFG, 624 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 625 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 626 } 627 628 if (sc->sis_type == SIS_TYPE_83816) { 629 /* 630 * MPII03.D: Half Duplex Excessive Collisions. 631 * Also page 49 in 83816 manual 632 */ 633 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 634 } 635 636 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 637 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 638 /* 639 * Short Cable Receive Errors (MP21.E) 640 */ 641 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 642 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 643 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 644 DELAY(100); 645 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 646 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 647 device_printf(sc->sis_dev, 648 "Applying short cable fix (reg=%x)\n", reg); 649 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 650 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 651 } 652 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 653 } 654 /* Enable TX/RX MACs. */ 655 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 657 } 658 659 static uint32_t 660 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 661 { 662 uint32_t crc; 663 664 /* Compute CRC for the address value. */ 665 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 666 667 /* 668 * return the filter bit position 669 * 670 * The NatSemi chip has a 512-bit filter, which is 671 * different than the SiS, so we special-case it. 672 */ 673 if (sc->sis_type == SIS_TYPE_83815) 674 return (crc >> 23); 675 else if (sc->sis_rev >= SIS_REV_635 || 676 sc->sis_rev == SIS_REV_900B) 677 return (crc >> 24); 678 else 679 return (crc >> 25); 680 } 681 682 static void 683 sis_rxfilter(struct sis_softc *sc) 684 { 685 686 SIS_LOCK_ASSERT(sc); 687 688 if (sc->sis_type == SIS_TYPE_83815) 689 sis_rxfilter_ns(sc); 690 else 691 sis_rxfilter_sis(sc); 692 } 693 694 static void 695 sis_rxfilter_ns(struct sis_softc *sc) 696 { 697 struct ifnet *ifp; 698 struct ifmultiaddr *ifma; 699 uint32_t h, i, filter; 700 int bit, index; 701 702 ifp = sc->sis_ifp; 703 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 704 if (filter & SIS_RXFILTCTL_ENABLE) { 705 /* 706 * Filter should be disabled to program other bits. 707 */ 708 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 709 CSR_READ_4(sc, SIS_RXFILT_CTL); 710 } 711 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 712 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 713 SIS_RXFILTCTL_ALLMULTI); 714 715 if (ifp->if_flags & IFF_BROADCAST) 716 filter |= SIS_RXFILTCTL_BROAD; 717 /* 718 * For the NatSemi chip, we have to explicitly enable the 719 * reception of ARP frames, as well as turn on the 'perfect 720 * match' filter where we store the station address, otherwise 721 * we won't receive unicasts meant for this host. 722 */ 723 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 724 725 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 726 filter |= SIS_RXFILTCTL_ALLMULTI; 727 if (ifp->if_flags & IFF_PROMISC) 728 filter |= SIS_RXFILTCTL_ALLPHYS; 729 } else { 730 /* 731 * We have to explicitly enable the multicast hash table 732 * on the NatSemi chip if we want to use it, which we do. 733 */ 734 filter |= NS_RXFILTCTL_MCHASH; 735 736 /* first, zot all the existing hash bits */ 737 for (i = 0; i < 32; i++) { 738 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 739 (i * 2)); 740 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 741 } 742 743 if_maddr_rlock(ifp); 744 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 745 if (ifma->ifma_addr->sa_family != AF_LINK) 746 continue; 747 h = sis_mchash(sc, 748 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 749 index = h >> 3; 750 bit = h & 0x1F; 751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 752 index); 753 if (bit > 0xF) 754 bit -= 0x10; 755 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 756 } 757 if_maddr_runlock(ifp); 758 } 759 760 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 761 CSR_READ_4(sc, SIS_RXFILT_CTL); 762 } 763 764 static void 765 sis_rxfilter_sis(struct sis_softc *sc) 766 { 767 struct ifnet *ifp; 768 struct ifmultiaddr *ifma; 769 uint32_t filter, h, i, n; 770 uint16_t hashes[16]; 771 772 ifp = sc->sis_ifp; 773 774 /* hash table size */ 775 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 776 n = 16; 777 else 778 n = 8; 779 780 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 781 if (filter & SIS_RXFILTCTL_ENABLE) { 782 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL); 783 CSR_READ_4(sc, SIS_RXFILT_CTL); 784 } 785 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 786 SIS_RXFILTCTL_ALLMULTI); 787 if (ifp->if_flags & IFF_BROADCAST) 788 filter |= SIS_RXFILTCTL_BROAD; 789 790 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 791 filter |= SIS_RXFILTCTL_ALLMULTI; 792 if (ifp->if_flags & IFF_PROMISC) 793 filter |= SIS_RXFILTCTL_ALLPHYS; 794 for (i = 0; i < n; i++) 795 hashes[i] = ~0; 796 } else { 797 for (i = 0; i < n; i++) 798 hashes[i] = 0; 799 i = 0; 800 if_maddr_rlock(ifp); 801 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 802 if (ifma->ifma_addr->sa_family != AF_LINK) 803 continue; 804 h = sis_mchash(sc, 805 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 806 hashes[h >> 4] |= 1 << (h & 0xf); 807 i++; 808 } 809 if_maddr_runlock(ifp); 810 if (i > n) { 811 filter |= SIS_RXFILTCTL_ALLMULTI; 812 for (i = 0; i < n; i++) 813 hashes[i] = ~0; 814 } 815 } 816 817 for (i = 0; i < n; i++) { 818 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 819 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 820 } 821 822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 823 CSR_READ_4(sc, SIS_RXFILT_CTL); 824 } 825 826 static void 827 sis_reset(struct sis_softc *sc) 828 { 829 int i; 830 831 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 832 833 for (i = 0; i < SIS_TIMEOUT; i++) { 834 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 835 break; 836 } 837 838 if (i == SIS_TIMEOUT) 839 device_printf(sc->sis_dev, "reset never completed\n"); 840 841 /* Wait a little while for the chip to get its brains in order. */ 842 DELAY(1000); 843 844 /* 845 * If this is a NetSemi chip, make sure to clear 846 * PME mode. 847 */ 848 if (sc->sis_type == SIS_TYPE_83815) { 849 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 850 CSR_WRITE_4(sc, NS_CLKRUN, 0); 851 } else { 852 /* Disable WOL functions. */ 853 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 854 } 855 } 856 857 /* 858 * Probe for an SiS chip. Check the PCI vendor and device 859 * IDs against our list and return a device name if we find a match. 860 */ 861 static int 862 sis_probe(device_t dev) 863 { 864 const struct sis_type *t; 865 866 t = sis_devs; 867 868 while (t->sis_name != NULL) { 869 if ((pci_get_vendor(dev) == t->sis_vid) && 870 (pci_get_device(dev) == t->sis_did)) { 871 device_set_desc(dev, t->sis_name); 872 return (BUS_PROBE_DEFAULT); 873 } 874 t++; 875 } 876 877 return (ENXIO); 878 } 879 880 /* 881 * Attach the interface. Allocate softc structures, do ifmedia 882 * setup and ethernet/BPF attach. 883 */ 884 static int 885 sis_attach(device_t dev) 886 { 887 u_char eaddr[ETHER_ADDR_LEN]; 888 struct sis_softc *sc; 889 struct ifnet *ifp; 890 int error = 0, pmc, waittime = 0; 891 892 waittime = 0; 893 sc = device_get_softc(dev); 894 895 sc->sis_dev = dev; 896 897 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 898 MTX_DEF); 899 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 900 901 if (pci_get_device(dev) == SIS_DEVICEID_900) 902 sc->sis_type = SIS_TYPE_900; 903 if (pci_get_device(dev) == SIS_DEVICEID_7016) 904 sc->sis_type = SIS_TYPE_7016; 905 if (pci_get_vendor(dev) == NS_VENDORID) 906 sc->sis_type = SIS_TYPE_83815; 907 908 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 909 /* 910 * Map control/status registers. 911 */ 912 pci_enable_busmaster(dev); 913 914 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 915 if (error) { 916 device_printf(dev, "couldn't allocate resources\n"); 917 goto fail; 918 } 919 920 /* Reset the adapter. */ 921 sis_reset(sc); 922 923 if (sc->sis_type == SIS_TYPE_900 && 924 (sc->sis_rev == SIS_REV_635 || 925 sc->sis_rev == SIS_REV_900B)) { 926 SIO_SET(SIS_CFG_RND_CNT); 927 SIO_SET(SIS_CFG_PERR_DETECT); 928 } 929 930 /* 931 * Get station address from the EEPROM. 932 */ 933 switch (pci_get_vendor(dev)) { 934 case NS_VENDORID: 935 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 936 937 /* We can't update the device description, so spew */ 938 if (sc->sis_srr == NS_SRR_15C) 939 device_printf(dev, "Silicon Revision: DP83815C\n"); 940 else if (sc->sis_srr == NS_SRR_15D) 941 device_printf(dev, "Silicon Revision: DP83815D\n"); 942 else if (sc->sis_srr == NS_SRR_16A) 943 device_printf(dev, "Silicon Revision: DP83816A\n"); 944 else 945 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 946 947 /* 948 * Reading the MAC address out of the EEPROM on 949 * the NatSemi chip takes a bit more work than 950 * you'd expect. The address spans 4 16-bit words, 951 * with the first word containing only a single bit. 952 * You have to shift everything over one bit to 953 * get it aligned properly. Also, the bits are 954 * stored backwards (the LSB is really the MSB, 955 * and so on) so you have to reverse them in order 956 * to get the MAC address into the form we want. 957 * Why? Who the hell knows. 958 */ 959 { 960 uint16_t tmp[4]; 961 962 sis_read_eeprom(sc, (caddr_t)&tmp, 963 NS_EE_NODEADDR, 4, 0); 964 965 /* Shift everything over one bit. */ 966 tmp[3] = tmp[3] >> 1; 967 tmp[3] |= tmp[2] << 15; 968 tmp[2] = tmp[2] >> 1; 969 tmp[2] |= tmp[1] << 15; 970 tmp[1] = tmp[1] >> 1; 971 tmp[1] |= tmp[0] << 15; 972 973 /* Now reverse all the bits. */ 974 tmp[3] = sis_reverse(tmp[3]); 975 tmp[2] = sis_reverse(tmp[2]); 976 tmp[1] = sis_reverse(tmp[1]); 977 978 eaddr[0] = (tmp[1] >> 0) & 0xFF; 979 eaddr[1] = (tmp[1] >> 8) & 0xFF; 980 eaddr[2] = (tmp[2] >> 0) & 0xFF; 981 eaddr[3] = (tmp[2] >> 8) & 0xFF; 982 eaddr[4] = (tmp[3] >> 0) & 0xFF; 983 eaddr[5] = (tmp[3] >> 8) & 0xFF; 984 } 985 break; 986 case SIS_VENDORID: 987 default: 988 #if defined(__i386__) || defined(__amd64__) 989 /* 990 * If this is a SiS 630E chipset with an embedded 991 * SiS 900 controller, we have to read the MAC address 992 * from the APC CMOS RAM. Our method for doing this 993 * is very ugly since we have to reach out and grab 994 * ahold of hardware for which we cannot properly 995 * allocate resources. This code is only compiled on 996 * the i386 architecture since the SiS 630E chipset 997 * is for x86 motherboards only. Note that there are 998 * a lot of magic numbers in this hack. These are 999 * taken from SiS's Linux driver. I'd like to replace 1000 * them with proper symbolic definitions, but that 1001 * requires some datasheets that I don't have access 1002 * to at the moment. 1003 */ 1004 if (sc->sis_rev == SIS_REV_630S || 1005 sc->sis_rev == SIS_REV_630E || 1006 sc->sis_rev == SIS_REV_630EA1) 1007 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1008 1009 else if (sc->sis_rev == SIS_REV_635 || 1010 sc->sis_rev == SIS_REV_630ET) 1011 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1012 else if (sc->sis_rev == SIS_REV_96x) { 1013 /* Allow to read EEPROM from LAN. It is shared 1014 * between a 1394 controller and the NIC and each 1015 * time we access it, we need to set SIS_EECMD_REQ. 1016 */ 1017 SIO_SET(SIS_EECMD_REQ); 1018 for (waittime = 0; waittime < SIS_TIMEOUT; 1019 waittime++) { 1020 /* Force EEPROM to idle state. */ 1021 sis_eeprom_idle(sc); 1022 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1023 sis_read_eeprom(sc, (caddr_t)&eaddr, 1024 SIS_EE_NODEADDR, 3, 0); 1025 break; 1026 } 1027 DELAY(1); 1028 } 1029 /* 1030 * Set SIS_EECTL_CLK to high, so a other master 1031 * can operate on the i2c bus. 1032 */ 1033 SIO_SET(SIS_EECTL_CLK); 1034 /* Refuse EEPROM access by LAN */ 1035 SIO_SET(SIS_EECMD_DONE); 1036 } else 1037 #endif 1038 sis_read_eeprom(sc, (caddr_t)&eaddr, 1039 SIS_EE_NODEADDR, 3, 0); 1040 break; 1041 } 1042 1043 sis_add_sysctls(sc); 1044 1045 /* Allocate DMA'able memory. */ 1046 if ((error = sis_dma_alloc(sc)) != 0) 1047 goto fail; 1048 1049 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1050 if (ifp == NULL) { 1051 device_printf(dev, "can not if_alloc()\n"); 1052 error = ENOSPC; 1053 goto fail; 1054 } 1055 ifp->if_softc = sc; 1056 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1057 ifp->if_mtu = ETHERMTU; 1058 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1059 ifp->if_ioctl = sis_ioctl; 1060 ifp->if_start = sis_start; 1061 ifp->if_init = sis_init; 1062 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1063 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1064 IFQ_SET_READY(&ifp->if_snd); 1065 1066 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1067 if (sc->sis_type == SIS_TYPE_83815) 1068 ifp->if_capabilities |= IFCAP_WOL; 1069 else 1070 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1071 ifp->if_capenable = ifp->if_capabilities; 1072 } 1073 1074 /* 1075 * Do MII setup. 1076 */ 1077 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1078 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1079 if (error != 0) { 1080 device_printf(dev, "attaching PHYs failed\n"); 1081 goto fail; 1082 } 1083 1084 /* 1085 * Call MI attach routine. 1086 */ 1087 ether_ifattach(ifp, eaddr); 1088 1089 /* 1090 * Tell the upper layer(s) we support long frames. 1091 */ 1092 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1093 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1094 ifp->if_capenable = ifp->if_capabilities; 1095 #ifdef DEVICE_POLLING 1096 ifp->if_capabilities |= IFCAP_POLLING; 1097 #endif 1098 1099 /* Hook interrupt last to avoid having to lock softc */ 1100 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1101 NULL, sis_intr, sc, &sc->sis_intrhand); 1102 1103 if (error) { 1104 device_printf(dev, "couldn't set up irq\n"); 1105 ether_ifdetach(ifp); 1106 goto fail; 1107 } 1108 1109 fail: 1110 if (error) 1111 sis_detach(dev); 1112 1113 return (error); 1114 } 1115 1116 /* 1117 * Shutdown hardware and free up resources. This can be called any 1118 * time after the mutex has been initialized. It is called in both 1119 * the error case in attach and the normal detach case so it needs 1120 * to be careful about only freeing resources that have actually been 1121 * allocated. 1122 */ 1123 static int 1124 sis_detach(device_t dev) 1125 { 1126 struct sis_softc *sc; 1127 struct ifnet *ifp; 1128 1129 sc = device_get_softc(dev); 1130 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1131 ifp = sc->sis_ifp; 1132 1133 #ifdef DEVICE_POLLING 1134 if (ifp->if_capenable & IFCAP_POLLING) 1135 ether_poll_deregister(ifp); 1136 #endif 1137 1138 /* These should only be active if attach succeeded. */ 1139 if (device_is_attached(dev)) { 1140 SIS_LOCK(sc); 1141 sis_stop(sc); 1142 SIS_UNLOCK(sc); 1143 callout_drain(&sc->sis_stat_ch); 1144 ether_ifdetach(ifp); 1145 } 1146 if (sc->sis_miibus) 1147 device_delete_child(dev, sc->sis_miibus); 1148 bus_generic_detach(dev); 1149 1150 if (sc->sis_intrhand) 1151 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1152 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1153 1154 if (ifp) 1155 if_free(ifp); 1156 1157 sis_dma_free(sc); 1158 1159 mtx_destroy(&sc->sis_mtx); 1160 1161 return (0); 1162 } 1163 1164 struct sis_dmamap_arg { 1165 bus_addr_t sis_busaddr; 1166 }; 1167 1168 static void 1169 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1170 { 1171 struct sis_dmamap_arg *ctx; 1172 1173 if (error != 0) 1174 return; 1175 1176 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1177 1178 ctx = (struct sis_dmamap_arg *)arg; 1179 ctx->sis_busaddr = segs[0].ds_addr; 1180 } 1181 1182 static int 1183 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1184 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1185 bus_addr_t *paddr, const char *msg) 1186 { 1187 struct sis_dmamap_arg ctx; 1188 int error; 1189 1190 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1191 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1192 maxsize, 0, NULL, NULL, tag); 1193 if (error != 0) { 1194 device_printf(sc->sis_dev, 1195 "could not create %s dma tag\n", msg); 1196 return (ENOMEM); 1197 } 1198 /* Allocate DMA'able memory for ring. */ 1199 error = bus_dmamem_alloc(*tag, (void **)ring, 1200 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1201 if (error != 0) { 1202 device_printf(sc->sis_dev, 1203 "could not allocate DMA'able memory for %s\n", msg); 1204 return (ENOMEM); 1205 } 1206 /* Load the address of the ring. */ 1207 ctx.sis_busaddr = 0; 1208 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1209 &ctx, BUS_DMA_NOWAIT); 1210 if (error != 0) { 1211 device_printf(sc->sis_dev, 1212 "could not load DMA'able memory for %s\n", msg); 1213 return (ENOMEM); 1214 } 1215 *paddr = ctx.sis_busaddr; 1216 return (0); 1217 } 1218 1219 static int 1220 sis_dma_alloc(struct sis_softc *sc) 1221 { 1222 struct sis_rxdesc *rxd; 1223 struct sis_txdesc *txd; 1224 int error, i; 1225 1226 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1227 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1228 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1229 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1230 0, NULL, NULL, &sc->sis_parent_tag); 1231 if (error != 0) { 1232 device_printf(sc->sis_dev, 1233 "could not allocate parent dma tag\n"); 1234 return (ENOMEM); 1235 } 1236 1237 /* Create RX ring. */ 1238 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1239 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1240 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1241 if (error) 1242 return (error); 1243 1244 /* Create TX ring. */ 1245 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1246 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1247 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1248 if (error) 1249 return (error); 1250 1251 /* Create tag for RX mbufs. */ 1252 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1253 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1254 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1255 if (error) { 1256 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1257 return (error); 1258 } 1259 1260 /* Create tag for TX mbufs. */ 1261 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1262 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1263 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1264 &sc->sis_tx_tag); 1265 if (error) { 1266 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1267 return (error); 1268 } 1269 1270 /* Create DMA maps for RX buffers. */ 1271 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1272 if (error) { 1273 device_printf(sc->sis_dev, 1274 "can't create spare DMA map for RX\n"); 1275 return (error); 1276 } 1277 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1278 rxd = &sc->sis_rxdesc[i]; 1279 rxd->rx_m = NULL; 1280 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1281 if (error) { 1282 device_printf(sc->sis_dev, 1283 "can't create DMA map for RX\n"); 1284 return (error); 1285 } 1286 } 1287 1288 /* Create DMA maps for TX buffers. */ 1289 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1290 txd = &sc->sis_txdesc[i]; 1291 txd->tx_m = NULL; 1292 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1293 if (error) { 1294 device_printf(sc->sis_dev, 1295 "can't create DMA map for TX\n"); 1296 return (error); 1297 } 1298 } 1299 1300 return (0); 1301 } 1302 1303 static void 1304 sis_dma_free(struct sis_softc *sc) 1305 { 1306 struct sis_rxdesc *rxd; 1307 struct sis_txdesc *txd; 1308 int i; 1309 1310 /* Destroy DMA maps for RX buffers. */ 1311 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1312 rxd = &sc->sis_rxdesc[i]; 1313 if (rxd->rx_dmamap) 1314 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1315 } 1316 if (sc->sis_rx_sparemap) 1317 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1318 1319 /* Destroy DMA maps for TX buffers. */ 1320 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1321 txd = &sc->sis_txdesc[i]; 1322 if (txd->tx_dmamap) 1323 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1324 } 1325 1326 if (sc->sis_rx_tag) 1327 bus_dma_tag_destroy(sc->sis_rx_tag); 1328 if (sc->sis_tx_tag) 1329 bus_dma_tag_destroy(sc->sis_tx_tag); 1330 1331 /* Destroy RX ring. */ 1332 if (sc->sis_rx_list_map) 1333 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1334 if (sc->sis_rx_list_map && sc->sis_rx_list) 1335 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1336 sc->sis_rx_list_map); 1337 1338 if (sc->sis_rx_list_tag) 1339 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1340 1341 /* Destroy TX ring. */ 1342 if (sc->sis_tx_list_map) 1343 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1344 1345 if (sc->sis_tx_list_map && sc->sis_tx_list) 1346 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1347 sc->sis_tx_list_map); 1348 1349 if (sc->sis_tx_list_tag) 1350 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1351 1352 /* Destroy the parent tag. */ 1353 if (sc->sis_parent_tag) 1354 bus_dma_tag_destroy(sc->sis_parent_tag); 1355 } 1356 1357 /* 1358 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1359 * we arrange the descriptors in a closed ring, so that the last descriptor 1360 * points back to the first. 1361 */ 1362 static int 1363 sis_ring_init(struct sis_softc *sc) 1364 { 1365 struct sis_rxdesc *rxd; 1366 struct sis_txdesc *txd; 1367 bus_addr_t next; 1368 int error, i; 1369 1370 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1371 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1372 txd = &sc->sis_txdesc[i]; 1373 txd->tx_m = NULL; 1374 if (i == SIS_TX_LIST_CNT - 1) 1375 next = SIS_TX_RING_ADDR(sc, 0); 1376 else 1377 next = SIS_TX_RING_ADDR(sc, i + 1); 1378 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1379 } 1380 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1381 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1383 1384 sc->sis_rx_cons = 0; 1385 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1386 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1387 rxd = &sc->sis_rxdesc[i]; 1388 rxd->rx_desc = &sc->sis_rx_list[i]; 1389 if (i == SIS_RX_LIST_CNT - 1) 1390 next = SIS_RX_RING_ADDR(sc, 0); 1391 else 1392 next = SIS_RX_RING_ADDR(sc, i + 1); 1393 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1394 error = sis_newbuf(sc, rxd); 1395 if (error) 1396 return (error); 1397 } 1398 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1399 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1400 1401 return (0); 1402 } 1403 1404 /* 1405 * Initialize an RX descriptor and attach an MBUF cluster. 1406 */ 1407 static int 1408 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1409 { 1410 struct mbuf *m; 1411 bus_dma_segment_t segs[1]; 1412 bus_dmamap_t map; 1413 int nsegs; 1414 1415 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1416 if (m == NULL) 1417 return (ENOBUFS); 1418 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1419 #ifndef __NO_STRICT_ALIGNMENT 1420 m_adj(m, SIS_RX_BUF_ALIGN); 1421 #endif 1422 1423 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1424 segs, &nsegs, 0) != 0) { 1425 m_freem(m); 1426 return (ENOBUFS); 1427 } 1428 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1429 1430 if (rxd->rx_m != NULL) { 1431 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1432 BUS_DMASYNC_POSTREAD); 1433 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1434 } 1435 map = rxd->rx_dmamap; 1436 rxd->rx_dmamap = sc->sis_rx_sparemap; 1437 sc->sis_rx_sparemap = map; 1438 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1439 rxd->rx_m = m; 1440 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1441 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1442 return (0); 1443 } 1444 1445 static __inline void 1446 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1447 { 1448 1449 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1450 } 1451 1452 #ifndef __NO_STRICT_ALIGNMENT 1453 static __inline void 1454 sis_fixup_rx(struct mbuf *m) 1455 { 1456 uint16_t *src, *dst; 1457 int i; 1458 1459 src = mtod(m, uint16_t *); 1460 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1461 1462 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1463 *dst++ = *src++; 1464 1465 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1466 } 1467 #endif 1468 1469 /* 1470 * A frame has been uploaded: pass the resulting mbuf chain up to 1471 * the higher level protocols. 1472 */ 1473 static int 1474 sis_rxeof(struct sis_softc *sc) 1475 { 1476 struct mbuf *m; 1477 struct ifnet *ifp; 1478 struct sis_rxdesc *rxd; 1479 struct sis_desc *cur_rx; 1480 int prog, rx_cons, rx_npkts = 0, total_len; 1481 uint32_t rxstat; 1482 1483 SIS_LOCK_ASSERT(sc); 1484 1485 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1487 1488 rx_cons = sc->sis_rx_cons; 1489 ifp = sc->sis_ifp; 1490 1491 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1492 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1493 #ifdef DEVICE_POLLING 1494 if (ifp->if_capenable & IFCAP_POLLING) { 1495 if (sc->rxcycles <= 0) 1496 break; 1497 sc->rxcycles--; 1498 } 1499 #endif 1500 cur_rx = &sc->sis_rx_list[rx_cons]; 1501 rxstat = le32toh(cur_rx->sis_cmdsts); 1502 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1503 break; 1504 rxd = &sc->sis_rxdesc[rx_cons]; 1505 1506 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1507 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1508 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1509 ETHER_CRC_LEN)) 1510 rxstat &= ~SIS_RXSTAT_GIANT; 1511 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1512 ifp->if_ierrors++; 1513 if (rxstat & SIS_RXSTAT_COLL) 1514 ifp->if_collisions++; 1515 sis_discard_rxbuf(rxd); 1516 continue; 1517 } 1518 1519 /* Add a new receive buffer to the ring. */ 1520 m = rxd->rx_m; 1521 if (sis_newbuf(sc, rxd) != 0) { 1522 ifp->if_iqdrops++; 1523 sis_discard_rxbuf(rxd); 1524 continue; 1525 } 1526 1527 /* No errors; receive the packet. */ 1528 m->m_pkthdr.len = m->m_len = total_len; 1529 #ifndef __NO_STRICT_ALIGNMENT 1530 /* 1531 * On architectures without alignment problems we try to 1532 * allocate a new buffer for the receive ring, and pass up 1533 * the one where the packet is already, saving the expensive 1534 * copy operation. 1535 */ 1536 sis_fixup_rx(m); 1537 #endif 1538 ifp->if_ipackets++; 1539 m->m_pkthdr.rcvif = ifp; 1540 1541 SIS_UNLOCK(sc); 1542 (*ifp->if_input)(ifp, m); 1543 SIS_LOCK(sc); 1544 rx_npkts++; 1545 } 1546 1547 if (prog > 0) { 1548 sc->sis_rx_cons = rx_cons; 1549 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1551 } 1552 1553 return (rx_npkts); 1554 } 1555 1556 /* 1557 * A frame was downloaded to the chip. It's safe for us to clean up 1558 * the list buffers. 1559 */ 1560 1561 static void 1562 sis_txeof(struct sis_softc *sc) 1563 { 1564 struct ifnet *ifp; 1565 struct sis_desc *cur_tx; 1566 struct sis_txdesc *txd; 1567 uint32_t cons, txstat; 1568 1569 SIS_LOCK_ASSERT(sc); 1570 1571 cons = sc->sis_tx_cons; 1572 if (cons == sc->sis_tx_prod) 1573 return; 1574 1575 ifp = sc->sis_ifp; 1576 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1578 1579 /* 1580 * Go through our tx list and free mbufs for those 1581 * frames that have been transmitted. 1582 */ 1583 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1584 cur_tx = &sc->sis_tx_list[cons]; 1585 txstat = le32toh(cur_tx->sis_cmdsts); 1586 if ((txstat & SIS_CMDSTS_OWN) != 0) 1587 break; 1588 txd = &sc->sis_txdesc[cons]; 1589 if (txd->tx_m != NULL) { 1590 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1591 BUS_DMASYNC_POSTWRITE); 1592 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1593 m_freem(txd->tx_m); 1594 txd->tx_m = NULL; 1595 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1596 ifp->if_opackets++; 1597 ifp->if_collisions += 1598 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1599 } else { 1600 ifp->if_oerrors++; 1601 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1602 ifp->if_collisions++; 1603 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1604 ifp->if_collisions++; 1605 } 1606 } 1607 sc->sis_tx_cnt--; 1608 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1609 } 1610 sc->sis_tx_cons = cons; 1611 if (sc->sis_tx_cnt == 0) 1612 sc->sis_watchdog_timer = 0; 1613 } 1614 1615 static void 1616 sis_tick(void *xsc) 1617 { 1618 struct sis_softc *sc; 1619 struct mii_data *mii; 1620 struct ifnet *ifp; 1621 1622 sc = xsc; 1623 SIS_LOCK_ASSERT(sc); 1624 ifp = sc->sis_ifp; 1625 1626 mii = device_get_softc(sc->sis_miibus); 1627 mii_tick(mii); 1628 sis_watchdog(sc); 1629 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1630 sis_miibus_statchg(sc->sis_dev); 1631 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1632 } 1633 1634 #ifdef DEVICE_POLLING 1635 static poll_handler_t sis_poll; 1636 1637 static int 1638 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1639 { 1640 struct sis_softc *sc = ifp->if_softc; 1641 int rx_npkts = 0; 1642 1643 SIS_LOCK(sc); 1644 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1645 SIS_UNLOCK(sc); 1646 return (rx_npkts); 1647 } 1648 1649 /* 1650 * On the sis, reading the status register also clears it. 1651 * So before returning to intr mode we must make sure that all 1652 * possible pending sources of interrupts have been served. 1653 * In practice this means run to completion the *eof routines, 1654 * and then call the interrupt routine 1655 */ 1656 sc->rxcycles = count; 1657 rx_npkts = sis_rxeof(sc); 1658 sis_txeof(sc); 1659 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1660 sis_startl(ifp); 1661 1662 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1663 uint32_t status; 1664 1665 /* Reading the ISR register clears all interrupts. */ 1666 status = CSR_READ_4(sc, SIS_ISR); 1667 1668 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1669 ifp->if_ierrors++; 1670 1671 if (status & (SIS_ISR_RX_IDLE)) 1672 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1673 1674 if (status & SIS_ISR_SYSERR) { 1675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1676 sis_initl(sc); 1677 } 1678 } 1679 1680 SIS_UNLOCK(sc); 1681 return (rx_npkts); 1682 } 1683 #endif /* DEVICE_POLLING */ 1684 1685 static void 1686 sis_intr(void *arg) 1687 { 1688 struct sis_softc *sc; 1689 struct ifnet *ifp; 1690 uint32_t status; 1691 1692 sc = arg; 1693 ifp = sc->sis_ifp; 1694 1695 SIS_LOCK(sc); 1696 #ifdef DEVICE_POLLING 1697 if (ifp->if_capenable & IFCAP_POLLING) { 1698 SIS_UNLOCK(sc); 1699 return; 1700 } 1701 #endif 1702 1703 /* Reading the ISR register clears all interrupts. */ 1704 status = CSR_READ_4(sc, SIS_ISR); 1705 if ((status & SIS_INTRS) == 0) { 1706 /* Not ours. */ 1707 SIS_UNLOCK(sc); 1708 return; 1709 } 1710 1711 /* Disable interrupts. */ 1712 CSR_WRITE_4(sc, SIS_IER, 0); 1713 1714 for (;(status & SIS_INTRS) != 0;) { 1715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1716 break; 1717 if (status & 1718 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1719 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1720 sis_txeof(sc); 1721 1722 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1723 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1724 sis_rxeof(sc); 1725 1726 if (status & SIS_ISR_RX_OFLOW) 1727 ifp->if_ierrors++; 1728 1729 if (status & (SIS_ISR_RX_IDLE)) 1730 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1731 1732 if (status & SIS_ISR_SYSERR) { 1733 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1734 sis_initl(sc); 1735 SIS_UNLOCK(sc); 1736 return; 1737 } 1738 status = CSR_READ_4(sc, SIS_ISR); 1739 } 1740 1741 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1742 /* Re-enable interrupts. */ 1743 CSR_WRITE_4(sc, SIS_IER, 1); 1744 1745 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1746 sis_startl(ifp); 1747 } 1748 1749 SIS_UNLOCK(sc); 1750 } 1751 1752 /* 1753 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1754 * pointers to the fragment pointers. 1755 */ 1756 static int 1757 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1758 { 1759 struct mbuf *m; 1760 struct sis_txdesc *txd; 1761 struct sis_desc *f; 1762 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1763 bus_dmamap_t map; 1764 int error, i, frag, nsegs, prod; 1765 int padlen; 1766 1767 prod = sc->sis_tx_prod; 1768 txd = &sc->sis_txdesc[prod]; 1769 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1770 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1771 m = *m_head; 1772 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1773 if (M_WRITABLE(m) == 0) { 1774 /* Get a writable copy. */ 1775 m = m_dup(*m_head, M_DONTWAIT); 1776 m_freem(*m_head); 1777 if (m == NULL) { 1778 *m_head = NULL; 1779 return (ENOBUFS); 1780 } 1781 *m_head = m; 1782 } 1783 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1784 m = m_defrag(m, M_DONTWAIT); 1785 if (m == NULL) { 1786 m_freem(*m_head); 1787 *m_head = NULL; 1788 return (ENOBUFS); 1789 } 1790 } 1791 /* 1792 * Manually pad short frames, and zero the pad space 1793 * to avoid leaking data. 1794 */ 1795 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1796 m->m_pkthdr.len += padlen; 1797 m->m_len = m->m_pkthdr.len; 1798 *m_head = m; 1799 } 1800 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1801 *m_head, segs, &nsegs, 0); 1802 if (error == EFBIG) { 1803 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS); 1804 if (m == NULL) { 1805 m_freem(*m_head); 1806 *m_head = NULL; 1807 return (ENOBUFS); 1808 } 1809 *m_head = m; 1810 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1811 *m_head, segs, &nsegs, 0); 1812 if (error != 0) { 1813 m_freem(*m_head); 1814 *m_head = NULL; 1815 return (error); 1816 } 1817 } else if (error != 0) 1818 return (error); 1819 1820 /* Check for descriptor overruns. */ 1821 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1822 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1823 return (ENOBUFS); 1824 } 1825 1826 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1827 1828 frag = prod; 1829 for (i = 0; i < nsegs; i++) { 1830 f = &sc->sis_tx_list[prod]; 1831 if (i == 0) 1832 f->sis_cmdsts = htole32(segs[i].ds_len | 1833 SIS_CMDSTS_MORE); 1834 else 1835 f->sis_cmdsts = htole32(segs[i].ds_len | 1836 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1837 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1838 SIS_INC(prod, SIS_TX_LIST_CNT); 1839 sc->sis_tx_cnt++; 1840 } 1841 1842 /* Update producer index. */ 1843 sc->sis_tx_prod = prod; 1844 1845 /* Remove MORE flag on the last descriptor. */ 1846 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1847 f = &sc->sis_tx_list[prod]; 1848 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1849 1850 /* Lastly transfer ownership of packet to the controller. */ 1851 f = &sc->sis_tx_list[frag]; 1852 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1853 1854 /* Swap the last and the first dmamaps. */ 1855 map = txd->tx_dmamap; 1856 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1857 sc->sis_txdesc[prod].tx_dmamap = map; 1858 sc->sis_txdesc[prod].tx_m = *m_head; 1859 1860 return (0); 1861 } 1862 1863 static void 1864 sis_start(struct ifnet *ifp) 1865 { 1866 struct sis_softc *sc; 1867 1868 sc = ifp->if_softc; 1869 SIS_LOCK(sc); 1870 sis_startl(ifp); 1871 SIS_UNLOCK(sc); 1872 } 1873 1874 static void 1875 sis_startl(struct ifnet *ifp) 1876 { 1877 struct sis_softc *sc; 1878 struct mbuf *m_head; 1879 int queued; 1880 1881 sc = ifp->if_softc; 1882 1883 SIS_LOCK_ASSERT(sc); 1884 1885 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1886 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1887 return; 1888 1889 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1890 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1891 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1892 if (m_head == NULL) 1893 break; 1894 1895 if (sis_encap(sc, &m_head) != 0) { 1896 if (m_head == NULL) 1897 break; 1898 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1899 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1900 break; 1901 } 1902 1903 queued++; 1904 1905 /* 1906 * If there's a BPF listener, bounce a copy of this frame 1907 * to him. 1908 */ 1909 BPF_MTAP(ifp, m_head); 1910 } 1911 1912 if (queued) { 1913 /* Transmit */ 1914 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1916 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1917 1918 /* 1919 * Set a timeout in case the chip goes out to lunch. 1920 */ 1921 sc->sis_watchdog_timer = 5; 1922 } 1923 } 1924 1925 static void 1926 sis_init(void *xsc) 1927 { 1928 struct sis_softc *sc = xsc; 1929 1930 SIS_LOCK(sc); 1931 sis_initl(sc); 1932 SIS_UNLOCK(sc); 1933 } 1934 1935 static void 1936 sis_initl(struct sis_softc *sc) 1937 { 1938 struct ifnet *ifp = sc->sis_ifp; 1939 struct mii_data *mii; 1940 uint8_t *eaddr; 1941 1942 SIS_LOCK_ASSERT(sc); 1943 1944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1945 return; 1946 1947 /* 1948 * Cancel pending I/O and free all RX/TX buffers. 1949 */ 1950 sis_stop(sc); 1951 /* 1952 * Reset the chip to a known state. 1953 */ 1954 sis_reset(sc); 1955 #ifdef notyet 1956 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1957 /* 1958 * Configure 400usec of interrupt holdoff. This is based 1959 * on emperical tests on a Soekris 4801. 1960 */ 1961 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1962 } 1963 #endif 1964 1965 mii = device_get_softc(sc->sis_miibus); 1966 1967 /* Set MAC address */ 1968 eaddr = IF_LLADDR(sc->sis_ifp); 1969 if (sc->sis_type == SIS_TYPE_83815) { 1970 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1971 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1973 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1974 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1975 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1976 } else { 1977 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1978 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1981 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1982 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1983 } 1984 1985 /* Init circular TX/RX lists. */ 1986 if (sis_ring_init(sc) != 0) { 1987 device_printf(sc->sis_dev, 1988 "initialization failed: no memory for rx buffers\n"); 1989 sis_stop(sc); 1990 return; 1991 } 1992 1993 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) { 1994 if (sc->sis_manual_pad != 0) 1995 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 1996 else 1997 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 1998 } 1999 2000 /* 2001 * Short Cable Receive Errors (MP21.E) 2002 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2003 * recommends the following register settings "for optimum 2004 * performance." for rev 15C. Set this also for 15D parts as 2005 * they require it in practice. 2006 */ 2007 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2008 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2009 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2010 /* set val for c2 */ 2011 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2012 /* load/kill c2 */ 2013 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2014 /* rais SD off, from 4 to c */ 2015 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2016 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2017 } 2018 2019 sis_rxfilter(sc); 2020 /* Turn the receive filter on */ 2021 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2022 2023 /* 2024 * Load the address of the RX and TX lists. 2025 */ 2026 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2027 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2028 2029 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2030 * the PCI bus. When this bit is set, the Max DMA Burst Size 2031 * for TX/RX DMA should be no larger than 16 double words. 2032 */ 2033 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2034 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2035 } else { 2036 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2037 } 2038 2039 /* Accept Long Packets for VLAN support */ 2040 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2041 2042 /* 2043 * Assume 100Mbps link, actual MAC configuration is done 2044 * after getting a valid link. 2045 */ 2046 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2047 2048 /* 2049 * Enable interrupts. 2050 */ 2051 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2052 #ifdef DEVICE_POLLING 2053 /* 2054 * ... only enable interrupts if we are not polling, make sure 2055 * they are off otherwise. 2056 */ 2057 if (ifp->if_capenable & IFCAP_POLLING) 2058 CSR_WRITE_4(sc, SIS_IER, 0); 2059 else 2060 #endif 2061 CSR_WRITE_4(sc, SIS_IER, 1); 2062 2063 /* Clear MAC disable. */ 2064 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2065 2066 sc->sis_flags &= ~SIS_FLAG_LINK; 2067 mii_mediachg(mii); 2068 2069 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2070 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2071 2072 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2073 } 2074 2075 /* 2076 * Set media options. 2077 */ 2078 static int 2079 sis_ifmedia_upd(struct ifnet *ifp) 2080 { 2081 struct sis_softc *sc; 2082 struct mii_data *mii; 2083 struct mii_softc *miisc; 2084 int error; 2085 2086 sc = ifp->if_softc; 2087 2088 SIS_LOCK(sc); 2089 mii = device_get_softc(sc->sis_miibus); 2090 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2091 PHY_RESET(miisc); 2092 error = mii_mediachg(mii); 2093 SIS_UNLOCK(sc); 2094 2095 return (error); 2096 } 2097 2098 /* 2099 * Report current media status. 2100 */ 2101 static void 2102 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2103 { 2104 struct sis_softc *sc; 2105 struct mii_data *mii; 2106 2107 sc = ifp->if_softc; 2108 2109 SIS_LOCK(sc); 2110 mii = device_get_softc(sc->sis_miibus); 2111 mii_pollstat(mii); 2112 SIS_UNLOCK(sc); 2113 ifmr->ifm_active = mii->mii_media_active; 2114 ifmr->ifm_status = mii->mii_media_status; 2115 } 2116 2117 static int 2118 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2119 { 2120 struct sis_softc *sc = ifp->if_softc; 2121 struct ifreq *ifr = (struct ifreq *) data; 2122 struct mii_data *mii; 2123 int error = 0, mask; 2124 2125 switch (command) { 2126 case SIOCSIFFLAGS: 2127 SIS_LOCK(sc); 2128 if (ifp->if_flags & IFF_UP) { 2129 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2130 ((ifp->if_flags ^ sc->sis_if_flags) & 2131 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2132 sis_rxfilter(sc); 2133 else 2134 sis_initl(sc); 2135 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2136 sis_stop(sc); 2137 sc->sis_if_flags = ifp->if_flags; 2138 SIS_UNLOCK(sc); 2139 break; 2140 case SIOCADDMULTI: 2141 case SIOCDELMULTI: 2142 SIS_LOCK(sc); 2143 sis_rxfilter(sc); 2144 SIS_UNLOCK(sc); 2145 break; 2146 case SIOCGIFMEDIA: 2147 case SIOCSIFMEDIA: 2148 mii = device_get_softc(sc->sis_miibus); 2149 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2150 break; 2151 case SIOCSIFCAP: 2152 SIS_LOCK(sc); 2153 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2154 #ifdef DEVICE_POLLING 2155 if ((mask & IFCAP_POLLING) != 0 && 2156 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2157 ifp->if_capenable ^= IFCAP_POLLING; 2158 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2159 error = ether_poll_register(sis_poll, ifp); 2160 if (error != 0) { 2161 SIS_UNLOCK(sc); 2162 break; 2163 } 2164 /* Disable interrupts. */ 2165 CSR_WRITE_4(sc, SIS_IER, 0); 2166 } else { 2167 error = ether_poll_deregister(ifp); 2168 /* Enable interrupts. */ 2169 CSR_WRITE_4(sc, SIS_IER, 1); 2170 } 2171 } 2172 #endif /* DEVICE_POLLING */ 2173 if ((mask & IFCAP_WOL) != 0 && 2174 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2175 if ((mask & IFCAP_WOL_UCAST) != 0) 2176 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2177 if ((mask & IFCAP_WOL_MCAST) != 0) 2178 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2179 if ((mask & IFCAP_WOL_MAGIC) != 0) 2180 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2181 } 2182 SIS_UNLOCK(sc); 2183 break; 2184 default: 2185 error = ether_ioctl(ifp, command, data); 2186 break; 2187 } 2188 2189 return (error); 2190 } 2191 2192 static void 2193 sis_watchdog(struct sis_softc *sc) 2194 { 2195 2196 SIS_LOCK_ASSERT(sc); 2197 2198 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2199 return; 2200 2201 device_printf(sc->sis_dev, "watchdog timeout\n"); 2202 sc->sis_ifp->if_oerrors++; 2203 2204 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2205 sis_initl(sc); 2206 2207 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2208 sis_startl(sc->sis_ifp); 2209 } 2210 2211 /* 2212 * Stop the adapter and free any mbufs allocated to the 2213 * RX and TX lists. 2214 */ 2215 static void 2216 sis_stop(struct sis_softc *sc) 2217 { 2218 struct ifnet *ifp; 2219 struct sis_rxdesc *rxd; 2220 struct sis_txdesc *txd; 2221 int i; 2222 2223 SIS_LOCK_ASSERT(sc); 2224 2225 ifp = sc->sis_ifp; 2226 sc->sis_watchdog_timer = 0; 2227 2228 callout_stop(&sc->sis_stat_ch); 2229 2230 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2231 CSR_WRITE_4(sc, SIS_IER, 0); 2232 CSR_WRITE_4(sc, SIS_IMR, 0); 2233 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2234 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2235 DELAY(1000); 2236 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2237 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2238 2239 sc->sis_flags &= ~SIS_FLAG_LINK; 2240 2241 /* 2242 * Free data in the RX lists. 2243 */ 2244 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2245 rxd = &sc->sis_rxdesc[i]; 2246 if (rxd->rx_m != NULL) { 2247 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2248 BUS_DMASYNC_POSTREAD); 2249 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2250 m_freem(rxd->rx_m); 2251 rxd->rx_m = NULL; 2252 } 2253 } 2254 2255 /* 2256 * Free the TX list buffers. 2257 */ 2258 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2259 txd = &sc->sis_txdesc[i]; 2260 if (txd->tx_m != NULL) { 2261 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2262 BUS_DMASYNC_POSTWRITE); 2263 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2264 m_freem(txd->tx_m); 2265 txd->tx_m = NULL; 2266 } 2267 } 2268 } 2269 2270 /* 2271 * Stop all chip I/O so that the kernel's probe routines don't 2272 * get confused by errant DMAs when rebooting. 2273 */ 2274 static int 2275 sis_shutdown(device_t dev) 2276 { 2277 2278 return (sis_suspend(dev)); 2279 } 2280 2281 static int 2282 sis_suspend(device_t dev) 2283 { 2284 struct sis_softc *sc; 2285 2286 sc = device_get_softc(dev); 2287 SIS_LOCK(sc); 2288 sis_stop(sc); 2289 sis_wol(sc); 2290 SIS_UNLOCK(sc); 2291 return (0); 2292 } 2293 2294 static int 2295 sis_resume(device_t dev) 2296 { 2297 struct sis_softc *sc; 2298 struct ifnet *ifp; 2299 2300 sc = device_get_softc(dev); 2301 SIS_LOCK(sc); 2302 ifp = sc->sis_ifp; 2303 if ((ifp->if_flags & IFF_UP) != 0) { 2304 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2305 sis_initl(sc); 2306 } 2307 SIS_UNLOCK(sc); 2308 return (0); 2309 } 2310 2311 static void 2312 sis_wol(struct sis_softc *sc) 2313 { 2314 struct ifnet *ifp; 2315 uint32_t val; 2316 uint16_t pmstat; 2317 int pmc; 2318 2319 ifp = sc->sis_ifp; 2320 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2321 return; 2322 2323 if (sc->sis_type == SIS_TYPE_83815) { 2324 /* Reset RXDP. */ 2325 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2326 2327 /* Configure WOL events. */ 2328 CSR_READ_4(sc, NS_WCSR); 2329 val = 0; 2330 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2331 val |= NS_WCSR_WAKE_UCAST; 2332 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2333 val |= NS_WCSR_WAKE_MCAST; 2334 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2335 val |= NS_WCSR_WAKE_MAGIC; 2336 CSR_WRITE_4(sc, NS_WCSR, val); 2337 /* Enable PME and clear PMESTS. */ 2338 val = CSR_READ_4(sc, NS_CLKRUN); 2339 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2340 CSR_WRITE_4(sc, NS_CLKRUN, val); 2341 /* Enable silent RX mode. */ 2342 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2343 } else { 2344 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2345 return; 2346 val = 0; 2347 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2348 val |= SIS_PWRMAN_WOL_MAGIC; 2349 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2350 /* Request PME. */ 2351 pmstat = pci_read_config(sc->sis_dev, 2352 pmc + PCIR_POWER_STATUS, 2); 2353 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2354 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2355 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2356 pci_write_config(sc->sis_dev, 2357 pmc + PCIR_POWER_STATUS, pmstat, 2); 2358 } 2359 } 2360 2361 static void 2362 sis_add_sysctls(struct sis_softc *sc) 2363 { 2364 struct sysctl_ctx_list *ctx; 2365 struct sysctl_oid_list *children; 2366 char tn[32]; 2367 int unit; 2368 2369 ctx = device_get_sysctl_ctx(sc->sis_dev); 2370 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2371 2372 unit = device_get_unit(sc->sis_dev); 2373 /* 2374 * Unlike most other controllers, NS DP83815/DP83816 controllers 2375 * seem to pad with 0xFF when it encounter short frames. According 2376 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2377 * on will have driver pad manully but it's disabled by default 2378 * because it will consume extra CPU cycles for short frames. 2379 */ 2380 sc->sis_manual_pad = 0; 2381 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2382 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2383 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2384 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2385 } 2386 2387 static device_method_t sis_methods[] = { 2388 /* Device interface */ 2389 DEVMETHOD(device_probe, sis_probe), 2390 DEVMETHOD(device_attach, sis_attach), 2391 DEVMETHOD(device_detach, sis_detach), 2392 DEVMETHOD(device_shutdown, sis_shutdown), 2393 DEVMETHOD(device_suspend, sis_suspend), 2394 DEVMETHOD(device_resume, sis_resume), 2395 2396 /* bus interface */ 2397 DEVMETHOD(bus_print_child, bus_generic_print_child), 2398 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2399 2400 /* MII interface */ 2401 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2402 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2403 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2404 2405 { 0, 0 } 2406 }; 2407 2408 static driver_t sis_driver = { 2409 "sis", 2410 sis_methods, 2411 sizeof(struct sis_softc) 2412 }; 2413 2414 static devclass_t sis_devclass; 2415 2416 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2417 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
Cache object: 2856b117e5a066bd0277026ea2b163d2
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