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sys/dev/sis/if_sis.c
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1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #ifdef HAVE_KERNEL_OPTION_HEADERS 62 #include "opt_device_polling.h" 63 #endif 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/bus.h> 68 #include <sys/endian.h> 69 #include <sys/kernel.h> 70 #include <sys/lock.h> 71 #include <sys/malloc.h> 72 #include <sys/mbuf.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 #include <sys/sockio.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/mii_bitbang.h> 94 #include <dev/mii/miivar.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 99 #define SIS_USEIOSPACE 100 101 #include <dev/sis/if_sisreg.h> 102 103 MODULE_DEPEND(sis, pci, 1, 1, 1); 104 MODULE_DEPEND(sis, ether, 1, 1, 1); 105 MODULE_DEPEND(sis, miibus, 1, 1, 1); 106 107 /* "device miibus" required. See GENERIC if you get errors here. */ 108 #include "miibus_if.h" 109 110 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 111 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 112 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 113 114 /* 115 * register space access macros 116 */ 117 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 118 119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 120 121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 122 123 #define CSR_BARRIER(sc, reg, length, flags) \ 124 bus_barrier(sc->sis_res[0], reg, length, flags) 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 static const struct sis_type sis_devs[] = { 130 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 131 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 132 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 133 { 0, 0, NULL } 134 }; 135 136 static int sis_detach(device_t); 137 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 138 static int sis_dma_alloc(struct sis_softc *); 139 static void sis_dma_free(struct sis_softc *); 140 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 141 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 142 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 143 #ifndef __NO_STRICT_ALIGNMENT 144 static __inline void sis_fixup_rx(struct mbuf *); 145 #endif 146 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 static int sis_ifmedia_upd(struct ifnet *); 148 static void sis_init(void *); 149 static void sis_initl(struct sis_softc *); 150 static void sis_intr(void *); 151 static int sis_ioctl(struct ifnet *, u_long, caddr_t); 152 static uint32_t sis_mii_bitbang_read(device_t); 153 static void sis_mii_bitbang_write(device_t, uint32_t); 154 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 155 static int sis_resume(device_t); 156 static int sis_rxeof(struct sis_softc *); 157 static void sis_rxfilter(struct sis_softc *); 158 static void sis_rxfilter_ns(struct sis_softc *); 159 static void sis_rxfilter_sis(struct sis_softc *); 160 static void sis_start(struct ifnet *); 161 static void sis_startl(struct ifnet *); 162 static void sis_stop(struct sis_softc *); 163 static int sis_suspend(device_t); 164 static void sis_add_sysctls(struct sis_softc *); 165 static void sis_watchdog(struct sis_softc *); 166 static void sis_wol(struct sis_softc *); 167 168 /* 169 * MII bit-bang glue 170 */ 171 static const struct mii_bitbang_ops sis_mii_bitbang_ops = { 172 sis_mii_bitbang_read, 173 sis_mii_bitbang_write, 174 { 175 SIS_MII_DATA, /* MII_BIT_MDO */ 176 SIS_MII_DATA, /* MII_BIT_MDI */ 177 SIS_MII_CLK, /* MII_BIT_MDC */ 178 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 179 0, /* MII_BIT_DIR_PHY_HOST */ 180 } 181 }; 182 183 static struct resource_spec sis_res_spec[] = { 184 #ifdef SIS_USEIOSPACE 185 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 186 #else 187 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 188 #endif 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 190 { -1, 0 } 191 }; 192 193 #define SIS_SETBIT(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, \ 195 CSR_READ_4(sc, reg) | (x)) 196 197 #define SIS_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) & ~(x)) 200 201 #define SIO_SET(x) \ 202 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 203 204 #define SIO_CLR(x) \ 205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 206 207 /* 208 * Routine to reverse the bits in a word. Stolen almost 209 * verbatim from /usr/games/fortune. 210 */ 211 static uint16_t 212 sis_reverse(uint16_t n) 213 { 214 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 215 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 216 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 217 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 218 219 return (n); 220 } 221 222 static void 223 sis_delay(struct sis_softc *sc) 224 { 225 int idx; 226 227 for (idx = (300 / 33) + 1; idx > 0; idx--) 228 CSR_READ_4(sc, SIS_CSR); 229 } 230 231 static void 232 sis_eeprom_idle(struct sis_softc *sc) 233 { 234 int i; 235 236 SIO_SET(SIS_EECTL_CSEL); 237 sis_delay(sc); 238 SIO_SET(SIS_EECTL_CLK); 239 sis_delay(sc); 240 241 for (i = 0; i < 25; i++) { 242 SIO_CLR(SIS_EECTL_CLK); 243 sis_delay(sc); 244 SIO_SET(SIS_EECTL_CLK); 245 sis_delay(sc); 246 } 247 248 SIO_CLR(SIS_EECTL_CLK); 249 sis_delay(sc); 250 SIO_CLR(SIS_EECTL_CSEL); 251 sis_delay(sc); 252 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 253 } 254 255 /* 256 * Send a read command and address to the EEPROM, check for ACK. 257 */ 258 static void 259 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 260 { 261 int d, i; 262 263 d = addr | SIS_EECMD_READ; 264 265 /* 266 * Feed in each bit and stobe the clock. 267 */ 268 for (i = 0x400; i; i >>= 1) { 269 if (d & i) { 270 SIO_SET(SIS_EECTL_DIN); 271 } else { 272 SIO_CLR(SIS_EECTL_DIN); 273 } 274 sis_delay(sc); 275 SIO_SET(SIS_EECTL_CLK); 276 sis_delay(sc); 277 SIO_CLR(SIS_EECTL_CLK); 278 sis_delay(sc); 279 } 280 } 281 282 /* 283 * Read a word of data stored in the EEPROM at address 'addr.' 284 */ 285 static void 286 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 287 { 288 int i; 289 uint16_t word = 0; 290 291 /* Force EEPROM to idle state. */ 292 sis_eeprom_idle(sc); 293 294 /* Enter EEPROM access mode. */ 295 sis_delay(sc); 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 SIO_SET(SIS_EECTL_CSEL); 299 sis_delay(sc); 300 301 /* 302 * Send address of word we want to read. 303 */ 304 sis_eeprom_putbyte(sc, addr); 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 for (i = 0x8000; i; i >>= 1) { 310 SIO_SET(SIS_EECTL_CLK); 311 sis_delay(sc); 312 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 313 word |= i; 314 sis_delay(sc); 315 SIO_CLR(SIS_EECTL_CLK); 316 sis_delay(sc); 317 } 318 319 /* Turn off EEPROM access mode. */ 320 sis_eeprom_idle(sc); 321 322 *dest = word; 323 } 324 325 /* 326 * Read a sequence of words from the EEPROM. 327 */ 328 static void 329 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 330 { 331 int i; 332 uint16_t word = 0, *ptr; 333 334 for (i = 0; i < cnt; i++) { 335 sis_eeprom_getword(sc, off + i, &word); 336 ptr = (uint16_t *)(dest + (i * 2)); 337 if (swap) 338 *ptr = ntohs(word); 339 else 340 *ptr = word; 341 } 342 } 343 344 #if defined(__i386__) || defined(__amd64__) 345 static device_t 346 sis_find_bridge(device_t dev) 347 { 348 devclass_t pci_devclass; 349 device_t *pci_devices; 350 int pci_count = 0; 351 device_t *pci_children; 352 int pci_childcount = 0; 353 device_t *busp, *childp; 354 device_t child = NULL; 355 int i, j; 356 357 if ((pci_devclass = devclass_find("pci")) == NULL) 358 return (NULL); 359 360 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 361 362 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 363 if (device_get_children(*busp, &pci_children, &pci_childcount)) 364 continue; 365 for (j = 0, childp = pci_children; 366 j < pci_childcount; j++, childp++) { 367 if (pci_get_vendor(*childp) == SIS_VENDORID && 368 pci_get_device(*childp) == 0x0008) { 369 child = *childp; 370 free(pci_children, M_TEMP); 371 goto done; 372 } 373 } 374 free(pci_children, M_TEMP); 375 } 376 377 done: 378 free(pci_devices, M_TEMP); 379 return (child); 380 } 381 382 static void 383 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 384 { 385 device_t bridge; 386 uint8_t reg; 387 int i; 388 bus_space_tag_t btag; 389 390 bridge = sis_find_bridge(dev); 391 if (bridge == NULL) 392 return; 393 reg = pci_read_config(bridge, 0x48, 1); 394 pci_write_config(bridge, 0x48, reg|0x40, 1); 395 396 /* XXX */ 397 #if defined(__amd64__) || defined(__i386__) 398 btag = X86_BUS_SPACE_IO; 399 #endif 400 401 for (i = 0; i < cnt; i++) { 402 bus_space_write_1(btag, 0x0, 0x70, i + off); 403 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 404 } 405 406 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 407 } 408 409 static void 410 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 411 { 412 uint32_t filtsave, csrsave; 413 414 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 415 csrsave = CSR_READ_4(sc, SIS_CSR); 416 417 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 418 CSR_WRITE_4(sc, SIS_CSR, 0); 419 420 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 421 422 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 423 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 424 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 425 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 427 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 428 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 430 CSR_WRITE_4(sc, SIS_CSR, csrsave); 431 } 432 #endif 433 434 /* 435 * Read the MII serial port for the MII bit-bang module. 436 */ 437 static uint32_t 438 sis_mii_bitbang_read(device_t dev) 439 { 440 struct sis_softc *sc; 441 uint32_t val; 442 443 sc = device_get_softc(dev); 444 445 val = CSR_READ_4(sc, SIS_EECTL); 446 CSR_BARRIER(sc, SIS_EECTL, 4, 447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 448 return (val); 449 } 450 451 /* 452 * Write the MII serial port for the MII bit-bang module. 453 */ 454 static void 455 sis_mii_bitbang_write(device_t dev, uint32_t val) 456 { 457 struct sis_softc *sc; 458 459 sc = device_get_softc(dev); 460 461 CSR_WRITE_4(sc, SIS_EECTL, val); 462 CSR_BARRIER(sc, SIS_EECTL, 4, 463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 464 } 465 466 static int 467 sis_miibus_readreg(device_t dev, int phy, int reg) 468 { 469 struct sis_softc *sc; 470 471 sc = device_get_softc(dev); 472 473 if (sc->sis_type == SIS_TYPE_83815) { 474 if (phy != 0) 475 return (0); 476 /* 477 * The NatSemi chip can take a while after 478 * a reset to come ready, during which the BMSR 479 * returns a value of 0. This is *never* supposed 480 * to happen: some of the BMSR bits are meant to 481 * be hardwired in the on position, and this can 482 * confuse the miibus code a bit during the probe 483 * and attach phase. So we make an effort to check 484 * for this condition and wait for it to clear. 485 */ 486 if (!CSR_READ_4(sc, NS_BMSR)) 487 DELAY(1000); 488 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 489 } 490 491 /* 492 * Chipsets < SIS_635 seem not to be able to read/write 493 * through mdio. Use the enhanced PHY access register 494 * again for them. 495 */ 496 if (sc->sis_type == SIS_TYPE_900 && 497 sc->sis_rev < SIS_REV_635) { 498 int i, val = 0; 499 500 if (phy != 0) 501 return (0); 502 503 CSR_WRITE_4(sc, SIS_PHYCTL, 504 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 505 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 506 507 for (i = 0; i < SIS_TIMEOUT; i++) { 508 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 509 break; 510 } 511 512 if (i == SIS_TIMEOUT) { 513 device_printf(sc->sis_dev, 514 "PHY failed to come ready\n"); 515 return (0); 516 } 517 518 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 519 520 if (val == 0xFFFF) 521 return (0); 522 523 return (val); 524 } else 525 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 526 reg)); 527 } 528 529 static int 530 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 531 { 532 struct sis_softc *sc; 533 534 sc = device_get_softc(dev); 535 536 if (sc->sis_type == SIS_TYPE_83815) { 537 if (phy != 0) 538 return (0); 539 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 540 return (0); 541 } 542 543 /* 544 * Chipsets < SIS_635 seem not to be able to read/write 545 * through mdio. Use the enhanced PHY access register 546 * again for them. 547 */ 548 if (sc->sis_type == SIS_TYPE_900 && 549 sc->sis_rev < SIS_REV_635) { 550 int i; 551 552 if (phy != 0) 553 return (0); 554 555 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 556 (reg << 6) | SIS_PHYOP_WRITE); 557 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 558 559 for (i = 0; i < SIS_TIMEOUT; i++) { 560 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 561 break; 562 } 563 564 if (i == SIS_TIMEOUT) 565 device_printf(sc->sis_dev, 566 "PHY failed to come ready\n"); 567 } else 568 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg, 569 data); 570 return (0); 571 } 572 573 static void 574 sis_miibus_statchg(device_t dev) 575 { 576 struct sis_softc *sc; 577 struct mii_data *mii; 578 struct ifnet *ifp; 579 uint32_t reg; 580 581 sc = device_get_softc(dev); 582 SIS_LOCK_ASSERT(sc); 583 584 mii = device_get_softc(sc->sis_miibus); 585 ifp = sc->sis_ifp; 586 if (mii == NULL || ifp == NULL || 587 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 588 return; 589 590 sc->sis_flags &= ~SIS_FLAG_LINK; 591 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 592 (IFM_ACTIVE | IFM_AVALID)) { 593 switch (IFM_SUBTYPE(mii->mii_media_active)) { 594 case IFM_10_T: 595 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 596 sc->sis_flags |= SIS_FLAG_LINK; 597 break; 598 case IFM_100_TX: 599 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 600 sc->sis_flags |= SIS_FLAG_LINK; 601 break; 602 default: 603 break; 604 } 605 } 606 607 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 608 /* 609 * Stopping MACs seem to reset SIS_TX_LISTPTR and 610 * SIS_RX_LISTPTR which in turn requires resetting 611 * TX/RX buffers. So just don't do anything for 612 * lost link. 613 */ 614 return; 615 } 616 617 /* Set full/half duplex mode. */ 618 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 619 SIS_SETBIT(sc, SIS_TX_CFG, 620 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 621 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 622 } else { 623 SIS_CLRBIT(sc, SIS_TX_CFG, 624 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 625 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 626 } 627 628 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 629 /* 630 * MPII03.D: Half Duplex Excessive Collisions. 631 * Also page 49 in 83816 manual 632 */ 633 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 634 } 635 636 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 637 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 638 /* 639 * Short Cable Receive Errors (MP21.E) 640 */ 641 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 642 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 643 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 644 DELAY(100); 645 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 646 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 647 device_printf(sc->sis_dev, 648 "Applying short cable fix (reg=%x)\n", reg); 649 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 650 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 651 } 652 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 653 } 654 /* Enable TX/RX MACs. */ 655 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 657 } 658 659 static uint32_t 660 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 661 { 662 uint32_t crc; 663 664 /* Compute CRC for the address value. */ 665 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 666 667 /* 668 * return the filter bit position 669 * 670 * The NatSemi chip has a 512-bit filter, which is 671 * different than the SiS, so we special-case it. 672 */ 673 if (sc->sis_type == SIS_TYPE_83815) 674 return (crc >> 23); 675 else if (sc->sis_rev >= SIS_REV_635 || 676 sc->sis_rev == SIS_REV_900B) 677 return (crc >> 24); 678 else 679 return (crc >> 25); 680 } 681 682 static void 683 sis_rxfilter(struct sis_softc *sc) 684 { 685 686 SIS_LOCK_ASSERT(sc); 687 688 if (sc->sis_type == SIS_TYPE_83815) 689 sis_rxfilter_ns(sc); 690 else 691 sis_rxfilter_sis(sc); 692 } 693 694 static void 695 sis_rxfilter_ns(struct sis_softc *sc) 696 { 697 struct ifnet *ifp; 698 struct ifmultiaddr *ifma; 699 uint32_t h, i, filter; 700 int bit, index; 701 702 ifp = sc->sis_ifp; 703 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 704 if (filter & SIS_RXFILTCTL_ENABLE) { 705 /* 706 * Filter should be disabled to program other bits. 707 */ 708 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 709 CSR_READ_4(sc, SIS_RXFILT_CTL); 710 } 711 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 712 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 713 SIS_RXFILTCTL_ALLMULTI); 714 715 if (ifp->if_flags & IFF_BROADCAST) 716 filter |= SIS_RXFILTCTL_BROAD; 717 /* 718 * For the NatSemi chip, we have to explicitly enable the 719 * reception of ARP frames, as well as turn on the 'perfect 720 * match' filter where we store the station address, otherwise 721 * we won't receive unicasts meant for this host. 722 */ 723 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 724 725 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 726 filter |= SIS_RXFILTCTL_ALLMULTI; 727 if (ifp->if_flags & IFF_PROMISC) 728 filter |= SIS_RXFILTCTL_ALLPHYS; 729 } else { 730 /* 731 * We have to explicitly enable the multicast hash table 732 * on the NatSemi chip if we want to use it, which we do. 733 */ 734 filter |= NS_RXFILTCTL_MCHASH; 735 736 /* first, zot all the existing hash bits */ 737 for (i = 0; i < 32; i++) { 738 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 739 (i * 2)); 740 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 741 } 742 743 if_maddr_rlock(ifp); 744 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 745 if (ifma->ifma_addr->sa_family != AF_LINK) 746 continue; 747 h = sis_mchash(sc, 748 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 749 index = h >> 3; 750 bit = h & 0x1F; 751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 752 index); 753 if (bit > 0xF) 754 bit -= 0x10; 755 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 756 } 757 if_maddr_runlock(ifp); 758 } 759 760 /* Turn the receive filter on */ 761 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 762 CSR_READ_4(sc, SIS_RXFILT_CTL); 763 } 764 765 static void 766 sis_rxfilter_sis(struct sis_softc *sc) 767 { 768 struct ifnet *ifp; 769 struct ifmultiaddr *ifma; 770 uint32_t filter, h, i, n; 771 uint16_t hashes[16]; 772 773 ifp = sc->sis_ifp; 774 775 /* hash table size */ 776 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 777 n = 16; 778 else 779 n = 8; 780 781 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 782 if (filter & SIS_RXFILTCTL_ENABLE) { 783 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 784 CSR_READ_4(sc, SIS_RXFILT_CTL); 785 } 786 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 787 SIS_RXFILTCTL_ALLMULTI); 788 if (ifp->if_flags & IFF_BROADCAST) 789 filter |= SIS_RXFILTCTL_BROAD; 790 791 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 792 filter |= SIS_RXFILTCTL_ALLMULTI; 793 if (ifp->if_flags & IFF_PROMISC) 794 filter |= SIS_RXFILTCTL_ALLPHYS; 795 for (i = 0; i < n; i++) 796 hashes[i] = ~0; 797 } else { 798 for (i = 0; i < n; i++) 799 hashes[i] = 0; 800 i = 0; 801 if_maddr_rlock(ifp); 802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 803 if (ifma->ifma_addr->sa_family != AF_LINK) 804 continue; 805 h = sis_mchash(sc, 806 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 807 hashes[h >> 4] |= 1 << (h & 0xf); 808 i++; 809 } 810 if_maddr_runlock(ifp); 811 if (i > n) { 812 filter |= SIS_RXFILTCTL_ALLMULTI; 813 for (i = 0; i < n; i++) 814 hashes[i] = ~0; 815 } 816 } 817 818 for (i = 0; i < n; i++) { 819 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 820 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 821 } 822 823 /* Turn the receive filter on */ 824 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE); 825 CSR_READ_4(sc, SIS_RXFILT_CTL); 826 } 827 828 static void 829 sis_reset(struct sis_softc *sc) 830 { 831 int i; 832 833 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 834 835 for (i = 0; i < SIS_TIMEOUT; i++) { 836 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 837 break; 838 } 839 840 if (i == SIS_TIMEOUT) 841 device_printf(sc->sis_dev, "reset never completed\n"); 842 843 /* Wait a little while for the chip to get its brains in order. */ 844 DELAY(1000); 845 846 /* 847 * If this is a NetSemi chip, make sure to clear 848 * PME mode. 849 */ 850 if (sc->sis_type == SIS_TYPE_83815) { 851 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 852 CSR_WRITE_4(sc, NS_CLKRUN, 0); 853 } else { 854 /* Disable WOL functions. */ 855 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 856 } 857 } 858 859 /* 860 * Probe for an SiS chip. Check the PCI vendor and device 861 * IDs against our list and return a device name if we find a match. 862 */ 863 static int 864 sis_probe(device_t dev) 865 { 866 const struct sis_type *t; 867 868 t = sis_devs; 869 870 while (t->sis_name != NULL) { 871 if ((pci_get_vendor(dev) == t->sis_vid) && 872 (pci_get_device(dev) == t->sis_did)) { 873 device_set_desc(dev, t->sis_name); 874 return (BUS_PROBE_DEFAULT); 875 } 876 t++; 877 } 878 879 return (ENXIO); 880 } 881 882 /* 883 * Attach the interface. Allocate softc structures, do ifmedia 884 * setup and ethernet/BPF attach. 885 */ 886 static int 887 sis_attach(device_t dev) 888 { 889 u_char eaddr[ETHER_ADDR_LEN]; 890 struct sis_softc *sc; 891 struct ifnet *ifp; 892 int error = 0, pmc, waittime = 0; 893 894 waittime = 0; 895 sc = device_get_softc(dev); 896 897 sc->sis_dev = dev; 898 899 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 900 MTX_DEF); 901 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 902 903 if (pci_get_device(dev) == SIS_DEVICEID_900) 904 sc->sis_type = SIS_TYPE_900; 905 if (pci_get_device(dev) == SIS_DEVICEID_7016) 906 sc->sis_type = SIS_TYPE_7016; 907 if (pci_get_vendor(dev) == NS_VENDORID) 908 sc->sis_type = SIS_TYPE_83815; 909 910 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 911 /* 912 * Map control/status registers. 913 */ 914 pci_enable_busmaster(dev); 915 916 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 917 if (error) { 918 device_printf(dev, "couldn't allocate resources\n"); 919 goto fail; 920 } 921 922 /* Reset the adapter. */ 923 sis_reset(sc); 924 925 if (sc->sis_type == SIS_TYPE_900 && 926 (sc->sis_rev == SIS_REV_635 || 927 sc->sis_rev == SIS_REV_900B)) { 928 SIO_SET(SIS_CFG_RND_CNT); 929 SIO_SET(SIS_CFG_PERR_DETECT); 930 } 931 932 /* 933 * Get station address from the EEPROM. 934 */ 935 switch (pci_get_vendor(dev)) { 936 case NS_VENDORID: 937 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 938 939 /* We can't update the device description, so spew */ 940 if (sc->sis_srr == NS_SRR_15C) 941 device_printf(dev, "Silicon Revision: DP83815C\n"); 942 else if (sc->sis_srr == NS_SRR_15D) 943 device_printf(dev, "Silicon Revision: DP83815D\n"); 944 else if (sc->sis_srr == NS_SRR_16A) 945 device_printf(dev, "Silicon Revision: DP83816A\n"); 946 else 947 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 948 949 /* 950 * Reading the MAC address out of the EEPROM on 951 * the NatSemi chip takes a bit more work than 952 * you'd expect. The address spans 4 16-bit words, 953 * with the first word containing only a single bit. 954 * You have to shift everything over one bit to 955 * get it aligned properly. Also, the bits are 956 * stored backwards (the LSB is really the MSB, 957 * and so on) so you have to reverse them in order 958 * to get the MAC address into the form we want. 959 * Why? Who the hell knows. 960 */ 961 { 962 uint16_t tmp[4]; 963 964 sis_read_eeprom(sc, (caddr_t)&tmp, 965 NS_EE_NODEADDR, 4, 0); 966 967 /* Shift everything over one bit. */ 968 tmp[3] = tmp[3] >> 1; 969 tmp[3] |= tmp[2] << 15; 970 tmp[2] = tmp[2] >> 1; 971 tmp[2] |= tmp[1] << 15; 972 tmp[1] = tmp[1] >> 1; 973 tmp[1] |= tmp[0] << 15; 974 975 /* Now reverse all the bits. */ 976 tmp[3] = sis_reverse(tmp[3]); 977 tmp[2] = sis_reverse(tmp[2]); 978 tmp[1] = sis_reverse(tmp[1]); 979 980 eaddr[0] = (tmp[1] >> 0) & 0xFF; 981 eaddr[1] = (tmp[1] >> 8) & 0xFF; 982 eaddr[2] = (tmp[2] >> 0) & 0xFF; 983 eaddr[3] = (tmp[2] >> 8) & 0xFF; 984 eaddr[4] = (tmp[3] >> 0) & 0xFF; 985 eaddr[5] = (tmp[3] >> 8) & 0xFF; 986 } 987 break; 988 case SIS_VENDORID: 989 default: 990 #if defined(__i386__) || defined(__amd64__) 991 /* 992 * If this is a SiS 630E chipset with an embedded 993 * SiS 900 controller, we have to read the MAC address 994 * from the APC CMOS RAM. Our method for doing this 995 * is very ugly since we have to reach out and grab 996 * ahold of hardware for which we cannot properly 997 * allocate resources. This code is only compiled on 998 * the i386 architecture since the SiS 630E chipset 999 * is for x86 motherboards only. Note that there are 1000 * a lot of magic numbers in this hack. These are 1001 * taken from SiS's Linux driver. I'd like to replace 1002 * them with proper symbolic definitions, but that 1003 * requires some datasheets that I don't have access 1004 * to at the moment. 1005 */ 1006 if (sc->sis_rev == SIS_REV_630S || 1007 sc->sis_rev == SIS_REV_630E || 1008 sc->sis_rev == SIS_REV_630EA1) 1009 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1010 1011 else if (sc->sis_rev == SIS_REV_635 || 1012 sc->sis_rev == SIS_REV_630ET) 1013 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1014 else if (sc->sis_rev == SIS_REV_96x) { 1015 /* Allow to read EEPROM from LAN. It is shared 1016 * between a 1394 controller and the NIC and each 1017 * time we access it, we need to set SIS_EECMD_REQ. 1018 */ 1019 SIO_SET(SIS_EECMD_REQ); 1020 for (waittime = 0; waittime < SIS_TIMEOUT; 1021 waittime++) { 1022 /* Force EEPROM to idle state. */ 1023 sis_eeprom_idle(sc); 1024 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1025 sis_read_eeprom(sc, (caddr_t)&eaddr, 1026 SIS_EE_NODEADDR, 3, 0); 1027 break; 1028 } 1029 DELAY(1); 1030 } 1031 /* 1032 * Set SIS_EECTL_CLK to high, so a other master 1033 * can operate on the i2c bus. 1034 */ 1035 SIO_SET(SIS_EECTL_CLK); 1036 /* Refuse EEPROM access by LAN */ 1037 SIO_SET(SIS_EECMD_DONE); 1038 } else 1039 #endif 1040 sis_read_eeprom(sc, (caddr_t)&eaddr, 1041 SIS_EE_NODEADDR, 3, 0); 1042 break; 1043 } 1044 1045 sis_add_sysctls(sc); 1046 1047 /* Allocate DMA'able memory. */ 1048 if ((error = sis_dma_alloc(sc)) != 0) 1049 goto fail; 1050 1051 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1052 if (ifp == NULL) { 1053 device_printf(dev, "can not if_alloc()\n"); 1054 error = ENOSPC; 1055 goto fail; 1056 } 1057 ifp->if_softc = sc; 1058 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1059 ifp->if_mtu = ETHERMTU; 1060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1061 ifp->if_ioctl = sis_ioctl; 1062 ifp->if_start = sis_start; 1063 ifp->if_init = sis_init; 1064 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1065 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1066 IFQ_SET_READY(&ifp->if_snd); 1067 1068 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1069 if (sc->sis_type == SIS_TYPE_83815) 1070 ifp->if_capabilities |= IFCAP_WOL; 1071 else 1072 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1073 ifp->if_capenable = ifp->if_capabilities; 1074 } 1075 1076 /* 1077 * Do MII setup. 1078 */ 1079 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1080 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1081 if (error != 0) { 1082 device_printf(dev, "attaching PHYs failed\n"); 1083 goto fail; 1084 } 1085 1086 /* 1087 * Call MI attach routine. 1088 */ 1089 ether_ifattach(ifp, eaddr); 1090 1091 /* 1092 * Tell the upper layer(s) we support long frames. 1093 */ 1094 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1095 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1096 ifp->if_capenable = ifp->if_capabilities; 1097 #ifdef DEVICE_POLLING 1098 ifp->if_capabilities |= IFCAP_POLLING; 1099 #endif 1100 1101 /* Hook interrupt last to avoid having to lock softc */ 1102 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1103 NULL, sis_intr, sc, &sc->sis_intrhand); 1104 1105 if (error) { 1106 device_printf(dev, "couldn't set up irq\n"); 1107 ether_ifdetach(ifp); 1108 goto fail; 1109 } 1110 1111 fail: 1112 if (error) 1113 sis_detach(dev); 1114 1115 return (error); 1116 } 1117 1118 /* 1119 * Shutdown hardware and free up resources. This can be called any 1120 * time after the mutex has been initialized. It is called in both 1121 * the error case in attach and the normal detach case so it needs 1122 * to be careful about only freeing resources that have actually been 1123 * allocated. 1124 */ 1125 static int 1126 sis_detach(device_t dev) 1127 { 1128 struct sis_softc *sc; 1129 struct ifnet *ifp; 1130 1131 sc = device_get_softc(dev); 1132 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1133 ifp = sc->sis_ifp; 1134 1135 #ifdef DEVICE_POLLING 1136 if (ifp->if_capenable & IFCAP_POLLING) 1137 ether_poll_deregister(ifp); 1138 #endif 1139 1140 /* These should only be active if attach succeeded. */ 1141 if (device_is_attached(dev)) { 1142 SIS_LOCK(sc); 1143 sis_stop(sc); 1144 SIS_UNLOCK(sc); 1145 callout_drain(&sc->sis_stat_ch); 1146 ether_ifdetach(ifp); 1147 } 1148 if (sc->sis_miibus) 1149 device_delete_child(dev, sc->sis_miibus); 1150 bus_generic_detach(dev); 1151 1152 if (sc->sis_intrhand) 1153 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1154 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1155 1156 if (ifp) 1157 if_free(ifp); 1158 1159 sis_dma_free(sc); 1160 1161 mtx_destroy(&sc->sis_mtx); 1162 1163 return (0); 1164 } 1165 1166 struct sis_dmamap_arg { 1167 bus_addr_t sis_busaddr; 1168 }; 1169 1170 static void 1171 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1172 { 1173 struct sis_dmamap_arg *ctx; 1174 1175 if (error != 0) 1176 return; 1177 1178 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1179 1180 ctx = (struct sis_dmamap_arg *)arg; 1181 ctx->sis_busaddr = segs[0].ds_addr; 1182 } 1183 1184 static int 1185 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1186 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1187 bus_addr_t *paddr, const char *msg) 1188 { 1189 struct sis_dmamap_arg ctx; 1190 int error; 1191 1192 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1193 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1194 maxsize, 0, NULL, NULL, tag); 1195 if (error != 0) { 1196 device_printf(sc->sis_dev, 1197 "could not create %s dma tag\n", msg); 1198 return (ENOMEM); 1199 } 1200 /* Allocate DMA'able memory for ring. */ 1201 error = bus_dmamem_alloc(*tag, (void **)ring, 1202 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1203 if (error != 0) { 1204 device_printf(sc->sis_dev, 1205 "could not allocate DMA'able memory for %s\n", msg); 1206 return (ENOMEM); 1207 } 1208 /* Load the address of the ring. */ 1209 ctx.sis_busaddr = 0; 1210 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1211 &ctx, BUS_DMA_NOWAIT); 1212 if (error != 0) { 1213 device_printf(sc->sis_dev, 1214 "could not load DMA'able memory for %s\n", msg); 1215 return (ENOMEM); 1216 } 1217 *paddr = ctx.sis_busaddr; 1218 return (0); 1219 } 1220 1221 static int 1222 sis_dma_alloc(struct sis_softc *sc) 1223 { 1224 struct sis_rxdesc *rxd; 1225 struct sis_txdesc *txd; 1226 int error, i; 1227 1228 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1229 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1230 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1231 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1232 0, NULL, NULL, &sc->sis_parent_tag); 1233 if (error != 0) { 1234 device_printf(sc->sis_dev, 1235 "could not allocate parent dma tag\n"); 1236 return (ENOMEM); 1237 } 1238 1239 /* Create RX ring. */ 1240 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1241 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1242 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1243 if (error) 1244 return (error); 1245 1246 /* Create TX ring. */ 1247 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1248 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1249 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1250 if (error) 1251 return (error); 1252 1253 /* Create tag for RX mbufs. */ 1254 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1255 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1256 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1257 if (error) { 1258 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1259 return (error); 1260 } 1261 1262 /* Create tag for TX mbufs. */ 1263 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1264 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1265 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1266 &sc->sis_tx_tag); 1267 if (error) { 1268 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1269 return (error); 1270 } 1271 1272 /* Create DMA maps for RX buffers. */ 1273 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1274 if (error) { 1275 device_printf(sc->sis_dev, 1276 "can't create spare DMA map for RX\n"); 1277 return (error); 1278 } 1279 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1280 rxd = &sc->sis_rxdesc[i]; 1281 rxd->rx_m = NULL; 1282 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1283 if (error) { 1284 device_printf(sc->sis_dev, 1285 "can't create DMA map for RX\n"); 1286 return (error); 1287 } 1288 } 1289 1290 /* Create DMA maps for TX buffers. */ 1291 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1292 txd = &sc->sis_txdesc[i]; 1293 txd->tx_m = NULL; 1294 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1295 if (error) { 1296 device_printf(sc->sis_dev, 1297 "can't create DMA map for TX\n"); 1298 return (error); 1299 } 1300 } 1301 1302 return (0); 1303 } 1304 1305 static void 1306 sis_dma_free(struct sis_softc *sc) 1307 { 1308 struct sis_rxdesc *rxd; 1309 struct sis_txdesc *txd; 1310 int i; 1311 1312 /* Destroy DMA maps for RX buffers. */ 1313 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1314 rxd = &sc->sis_rxdesc[i]; 1315 if (rxd->rx_dmamap) 1316 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1317 } 1318 if (sc->sis_rx_sparemap) 1319 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1320 1321 /* Destroy DMA maps for TX buffers. */ 1322 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1323 txd = &sc->sis_txdesc[i]; 1324 if (txd->tx_dmamap) 1325 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1326 } 1327 1328 if (sc->sis_rx_tag) 1329 bus_dma_tag_destroy(sc->sis_rx_tag); 1330 if (sc->sis_tx_tag) 1331 bus_dma_tag_destroy(sc->sis_tx_tag); 1332 1333 /* Destroy RX ring. */ 1334 if (sc->sis_rx_list_map) 1335 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1336 if (sc->sis_rx_list_map && sc->sis_rx_list) 1337 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1338 sc->sis_rx_list_map); 1339 1340 if (sc->sis_rx_list_tag) 1341 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1342 1343 /* Destroy TX ring. */ 1344 if (sc->sis_tx_list_map) 1345 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1346 1347 if (sc->sis_tx_list_map && sc->sis_tx_list) 1348 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1349 sc->sis_tx_list_map); 1350 1351 if (sc->sis_tx_list_tag) 1352 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1353 1354 /* Destroy the parent tag. */ 1355 if (sc->sis_parent_tag) 1356 bus_dma_tag_destroy(sc->sis_parent_tag); 1357 } 1358 1359 /* 1360 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1361 * we arrange the descriptors in a closed ring, so that the last descriptor 1362 * points back to the first. 1363 */ 1364 static int 1365 sis_ring_init(struct sis_softc *sc) 1366 { 1367 struct sis_rxdesc *rxd; 1368 struct sis_txdesc *txd; 1369 bus_addr_t next; 1370 int error, i; 1371 1372 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1373 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1374 txd = &sc->sis_txdesc[i]; 1375 txd->tx_m = NULL; 1376 if (i == SIS_TX_LIST_CNT - 1) 1377 next = SIS_TX_RING_ADDR(sc, 0); 1378 else 1379 next = SIS_TX_RING_ADDR(sc, i + 1); 1380 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1381 } 1382 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1383 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1385 1386 sc->sis_rx_cons = 0; 1387 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1388 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1389 rxd = &sc->sis_rxdesc[i]; 1390 rxd->rx_desc = &sc->sis_rx_list[i]; 1391 if (i == SIS_RX_LIST_CNT - 1) 1392 next = SIS_RX_RING_ADDR(sc, 0); 1393 else 1394 next = SIS_RX_RING_ADDR(sc, i + 1); 1395 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1396 error = sis_newbuf(sc, rxd); 1397 if (error) 1398 return (error); 1399 } 1400 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1402 1403 return (0); 1404 } 1405 1406 /* 1407 * Initialize an RX descriptor and attach an MBUF cluster. 1408 */ 1409 static int 1410 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1411 { 1412 struct mbuf *m; 1413 bus_dma_segment_t segs[1]; 1414 bus_dmamap_t map; 1415 int nsegs; 1416 1417 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1418 if (m == NULL) 1419 return (ENOBUFS); 1420 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1421 #ifndef __NO_STRICT_ALIGNMENT 1422 m_adj(m, SIS_RX_BUF_ALIGN); 1423 #endif 1424 1425 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1426 segs, &nsegs, 0) != 0) { 1427 m_freem(m); 1428 return (ENOBUFS); 1429 } 1430 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1431 1432 if (rxd->rx_m != NULL) { 1433 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1434 BUS_DMASYNC_POSTREAD); 1435 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1436 } 1437 map = rxd->rx_dmamap; 1438 rxd->rx_dmamap = sc->sis_rx_sparemap; 1439 sc->sis_rx_sparemap = map; 1440 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1441 rxd->rx_m = m; 1442 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1443 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1444 return (0); 1445 } 1446 1447 static __inline void 1448 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1449 { 1450 1451 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1452 } 1453 1454 #ifndef __NO_STRICT_ALIGNMENT 1455 static __inline void 1456 sis_fixup_rx(struct mbuf *m) 1457 { 1458 uint16_t *src, *dst; 1459 int i; 1460 1461 src = mtod(m, uint16_t *); 1462 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1463 1464 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1465 *dst++ = *src++; 1466 1467 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1468 } 1469 #endif 1470 1471 /* 1472 * A frame has been uploaded: pass the resulting mbuf chain up to 1473 * the higher level protocols. 1474 */ 1475 static int 1476 sis_rxeof(struct sis_softc *sc) 1477 { 1478 struct mbuf *m; 1479 struct ifnet *ifp; 1480 struct sis_rxdesc *rxd; 1481 struct sis_desc *cur_rx; 1482 int prog, rx_cons, rx_npkts = 0, total_len; 1483 uint32_t rxstat; 1484 1485 SIS_LOCK_ASSERT(sc); 1486 1487 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1488 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1489 1490 rx_cons = sc->sis_rx_cons; 1491 ifp = sc->sis_ifp; 1492 1493 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1494 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1495 #ifdef DEVICE_POLLING 1496 if (ifp->if_capenable & IFCAP_POLLING) { 1497 if (sc->rxcycles <= 0) 1498 break; 1499 sc->rxcycles--; 1500 } 1501 #endif 1502 cur_rx = &sc->sis_rx_list[rx_cons]; 1503 rxstat = le32toh(cur_rx->sis_cmdsts); 1504 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1505 break; 1506 rxd = &sc->sis_rxdesc[rx_cons]; 1507 1508 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1509 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1510 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1511 ETHER_CRC_LEN)) 1512 rxstat &= ~SIS_RXSTAT_GIANT; 1513 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1514 ifp->if_ierrors++; 1515 if (rxstat & SIS_RXSTAT_COLL) 1516 ifp->if_collisions++; 1517 sis_discard_rxbuf(rxd); 1518 continue; 1519 } 1520 1521 /* Add a new receive buffer to the ring. */ 1522 m = rxd->rx_m; 1523 if (sis_newbuf(sc, rxd) != 0) { 1524 ifp->if_iqdrops++; 1525 sis_discard_rxbuf(rxd); 1526 continue; 1527 } 1528 1529 /* No errors; receive the packet. */ 1530 m->m_pkthdr.len = m->m_len = total_len; 1531 #ifndef __NO_STRICT_ALIGNMENT 1532 /* 1533 * On architectures without alignment problems we try to 1534 * allocate a new buffer for the receive ring, and pass up 1535 * the one where the packet is already, saving the expensive 1536 * copy operation. 1537 */ 1538 sis_fixup_rx(m); 1539 #endif 1540 ifp->if_ipackets++; 1541 m->m_pkthdr.rcvif = ifp; 1542 1543 SIS_UNLOCK(sc); 1544 (*ifp->if_input)(ifp, m); 1545 SIS_LOCK(sc); 1546 rx_npkts++; 1547 } 1548 1549 if (prog > 0) { 1550 sc->sis_rx_cons = rx_cons; 1551 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1553 } 1554 1555 return (rx_npkts); 1556 } 1557 1558 /* 1559 * A frame was downloaded to the chip. It's safe for us to clean up 1560 * the list buffers. 1561 */ 1562 1563 static void 1564 sis_txeof(struct sis_softc *sc) 1565 { 1566 struct ifnet *ifp; 1567 struct sis_desc *cur_tx; 1568 struct sis_txdesc *txd; 1569 uint32_t cons, txstat; 1570 1571 SIS_LOCK_ASSERT(sc); 1572 1573 cons = sc->sis_tx_cons; 1574 if (cons == sc->sis_tx_prod) 1575 return; 1576 1577 ifp = sc->sis_ifp; 1578 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1580 1581 /* 1582 * Go through our tx list and free mbufs for those 1583 * frames that have been transmitted. 1584 */ 1585 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1586 cur_tx = &sc->sis_tx_list[cons]; 1587 txstat = le32toh(cur_tx->sis_cmdsts); 1588 if ((txstat & SIS_CMDSTS_OWN) != 0) 1589 break; 1590 txd = &sc->sis_txdesc[cons]; 1591 if (txd->tx_m != NULL) { 1592 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1593 BUS_DMASYNC_POSTWRITE); 1594 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1595 m_freem(txd->tx_m); 1596 txd->tx_m = NULL; 1597 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1598 ifp->if_opackets++; 1599 ifp->if_collisions += 1600 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1601 } else { 1602 ifp->if_oerrors++; 1603 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1604 ifp->if_collisions++; 1605 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1606 ifp->if_collisions++; 1607 } 1608 } 1609 sc->sis_tx_cnt--; 1610 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1611 } 1612 sc->sis_tx_cons = cons; 1613 if (sc->sis_tx_cnt == 0) 1614 sc->sis_watchdog_timer = 0; 1615 } 1616 1617 static void 1618 sis_tick(void *xsc) 1619 { 1620 struct sis_softc *sc; 1621 struct mii_data *mii; 1622 1623 sc = xsc; 1624 SIS_LOCK_ASSERT(sc); 1625 1626 mii = device_get_softc(sc->sis_miibus); 1627 mii_tick(mii); 1628 sis_watchdog(sc); 1629 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1630 sis_miibus_statchg(sc->sis_dev); 1631 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1632 } 1633 1634 #ifdef DEVICE_POLLING 1635 static poll_handler_t sis_poll; 1636 1637 static int 1638 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1639 { 1640 struct sis_softc *sc = ifp->if_softc; 1641 int rx_npkts = 0; 1642 1643 SIS_LOCK(sc); 1644 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1645 SIS_UNLOCK(sc); 1646 return (rx_npkts); 1647 } 1648 1649 /* 1650 * On the sis, reading the status register also clears it. 1651 * So before returning to intr mode we must make sure that all 1652 * possible pending sources of interrupts have been served. 1653 * In practice this means run to completion the *eof routines, 1654 * and then call the interrupt routine 1655 */ 1656 sc->rxcycles = count; 1657 rx_npkts = sis_rxeof(sc); 1658 sis_txeof(sc); 1659 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1660 sis_startl(ifp); 1661 1662 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1663 uint32_t status; 1664 1665 /* Reading the ISR register clears all interrupts. */ 1666 status = CSR_READ_4(sc, SIS_ISR); 1667 1668 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1669 ifp->if_ierrors++; 1670 1671 if (status & (SIS_ISR_RX_IDLE)) 1672 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1673 1674 if (status & SIS_ISR_SYSERR) { 1675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1676 sis_initl(sc); 1677 } 1678 } 1679 1680 SIS_UNLOCK(sc); 1681 return (rx_npkts); 1682 } 1683 #endif /* DEVICE_POLLING */ 1684 1685 static void 1686 sis_intr(void *arg) 1687 { 1688 struct sis_softc *sc; 1689 struct ifnet *ifp; 1690 uint32_t status; 1691 1692 sc = arg; 1693 ifp = sc->sis_ifp; 1694 1695 SIS_LOCK(sc); 1696 #ifdef DEVICE_POLLING 1697 if (ifp->if_capenable & IFCAP_POLLING) { 1698 SIS_UNLOCK(sc); 1699 return; 1700 } 1701 #endif 1702 1703 /* Reading the ISR register clears all interrupts. */ 1704 status = CSR_READ_4(sc, SIS_ISR); 1705 if ((status & SIS_INTRS) == 0) { 1706 /* Not ours. */ 1707 SIS_UNLOCK(sc); 1708 return; 1709 } 1710 1711 /* Disable interrupts. */ 1712 CSR_WRITE_4(sc, SIS_IER, 0); 1713 1714 for (;(status & SIS_INTRS) != 0;) { 1715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1716 break; 1717 if (status & 1718 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1719 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1720 sis_txeof(sc); 1721 1722 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1723 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1724 sis_rxeof(sc); 1725 1726 if (status & SIS_ISR_RX_OFLOW) 1727 ifp->if_ierrors++; 1728 1729 if (status & (SIS_ISR_RX_IDLE)) 1730 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1731 1732 if (status & SIS_ISR_SYSERR) { 1733 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1734 sis_initl(sc); 1735 SIS_UNLOCK(sc); 1736 return; 1737 } 1738 status = CSR_READ_4(sc, SIS_ISR); 1739 } 1740 1741 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1742 /* Re-enable interrupts. */ 1743 CSR_WRITE_4(sc, SIS_IER, 1); 1744 1745 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1746 sis_startl(ifp); 1747 } 1748 1749 SIS_UNLOCK(sc); 1750 } 1751 1752 /* 1753 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1754 * pointers to the fragment pointers. 1755 */ 1756 static int 1757 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1758 { 1759 struct mbuf *m; 1760 struct sis_txdesc *txd; 1761 struct sis_desc *f; 1762 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1763 bus_dmamap_t map; 1764 int error, i, frag, nsegs, prod; 1765 int padlen; 1766 1767 prod = sc->sis_tx_prod; 1768 txd = &sc->sis_txdesc[prod]; 1769 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1770 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1771 m = *m_head; 1772 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1773 if (M_WRITABLE(m) == 0) { 1774 /* Get a writable copy. */ 1775 m = m_dup(*m_head, M_NOWAIT); 1776 m_freem(*m_head); 1777 if (m == NULL) { 1778 *m_head = NULL; 1779 return (ENOBUFS); 1780 } 1781 *m_head = m; 1782 } 1783 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1784 m = m_defrag(m, M_NOWAIT); 1785 if (m == NULL) { 1786 m_freem(*m_head); 1787 *m_head = NULL; 1788 return (ENOBUFS); 1789 } 1790 } 1791 /* 1792 * Manually pad short frames, and zero the pad space 1793 * to avoid leaking data. 1794 */ 1795 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1796 m->m_pkthdr.len += padlen; 1797 m->m_len = m->m_pkthdr.len; 1798 *m_head = m; 1799 } 1800 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1801 *m_head, segs, &nsegs, 0); 1802 if (error == EFBIG) { 1803 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS); 1804 if (m == NULL) { 1805 m_freem(*m_head); 1806 *m_head = NULL; 1807 return (ENOBUFS); 1808 } 1809 *m_head = m; 1810 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1811 *m_head, segs, &nsegs, 0); 1812 if (error != 0) { 1813 m_freem(*m_head); 1814 *m_head = NULL; 1815 return (error); 1816 } 1817 } else if (error != 0) 1818 return (error); 1819 1820 /* Check for descriptor overruns. */ 1821 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1822 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1823 return (ENOBUFS); 1824 } 1825 1826 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1827 1828 frag = prod; 1829 for (i = 0; i < nsegs; i++) { 1830 f = &sc->sis_tx_list[prod]; 1831 if (i == 0) 1832 f->sis_cmdsts = htole32(segs[i].ds_len | 1833 SIS_CMDSTS_MORE); 1834 else 1835 f->sis_cmdsts = htole32(segs[i].ds_len | 1836 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1837 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1838 SIS_INC(prod, SIS_TX_LIST_CNT); 1839 sc->sis_tx_cnt++; 1840 } 1841 1842 /* Update producer index. */ 1843 sc->sis_tx_prod = prod; 1844 1845 /* Remove MORE flag on the last descriptor. */ 1846 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1847 f = &sc->sis_tx_list[prod]; 1848 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1849 1850 /* Lastly transfer ownership of packet to the controller. */ 1851 f = &sc->sis_tx_list[frag]; 1852 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1853 1854 /* Swap the last and the first dmamaps. */ 1855 map = txd->tx_dmamap; 1856 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1857 sc->sis_txdesc[prod].tx_dmamap = map; 1858 sc->sis_txdesc[prod].tx_m = *m_head; 1859 1860 return (0); 1861 } 1862 1863 static void 1864 sis_start(struct ifnet *ifp) 1865 { 1866 struct sis_softc *sc; 1867 1868 sc = ifp->if_softc; 1869 SIS_LOCK(sc); 1870 sis_startl(ifp); 1871 SIS_UNLOCK(sc); 1872 } 1873 1874 static void 1875 sis_startl(struct ifnet *ifp) 1876 { 1877 struct sis_softc *sc; 1878 struct mbuf *m_head; 1879 int queued; 1880 1881 sc = ifp->if_softc; 1882 1883 SIS_LOCK_ASSERT(sc); 1884 1885 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1886 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 1887 return; 1888 1889 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1890 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 1891 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1892 if (m_head == NULL) 1893 break; 1894 1895 if (sis_encap(sc, &m_head) != 0) { 1896 if (m_head == NULL) 1897 break; 1898 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1899 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1900 break; 1901 } 1902 1903 queued++; 1904 1905 /* 1906 * If there's a BPF listener, bounce a copy of this frame 1907 * to him. 1908 */ 1909 BPF_MTAP(ifp, m_head); 1910 } 1911 1912 if (queued) { 1913 /* Transmit */ 1914 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1916 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1917 1918 /* 1919 * Set a timeout in case the chip goes out to lunch. 1920 */ 1921 sc->sis_watchdog_timer = 5; 1922 } 1923 } 1924 1925 static void 1926 sis_init(void *xsc) 1927 { 1928 struct sis_softc *sc = xsc; 1929 1930 SIS_LOCK(sc); 1931 sis_initl(sc); 1932 SIS_UNLOCK(sc); 1933 } 1934 1935 static void 1936 sis_initl(struct sis_softc *sc) 1937 { 1938 struct ifnet *ifp = sc->sis_ifp; 1939 struct mii_data *mii; 1940 uint8_t *eaddr; 1941 1942 SIS_LOCK_ASSERT(sc); 1943 1944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1945 return; 1946 1947 /* 1948 * Cancel pending I/O and free all RX/TX buffers. 1949 */ 1950 sis_stop(sc); 1951 /* 1952 * Reset the chip to a known state. 1953 */ 1954 sis_reset(sc); 1955 #ifdef notyet 1956 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1957 /* 1958 * Configure 400usec of interrupt holdoff. This is based 1959 * on emperical tests on a Soekris 4801. 1960 */ 1961 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1962 } 1963 #endif 1964 1965 mii = device_get_softc(sc->sis_miibus); 1966 1967 /* Set MAC address */ 1968 eaddr = IF_LLADDR(sc->sis_ifp); 1969 if (sc->sis_type == SIS_TYPE_83815) { 1970 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1971 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1973 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1974 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1975 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1976 } else { 1977 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1978 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 1981 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1982 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 1983 } 1984 1985 /* Init circular TX/RX lists. */ 1986 if (sis_ring_init(sc) != 0) { 1987 device_printf(sc->sis_dev, 1988 "initialization failed: no memory for rx buffers\n"); 1989 sis_stop(sc); 1990 return; 1991 } 1992 1993 if (sc->sis_type == SIS_TYPE_83815) { 1994 if (sc->sis_manual_pad != 0) 1995 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 1996 else 1997 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 1998 } 1999 2000 /* 2001 * Short Cable Receive Errors (MP21.E) 2002 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2003 * recommends the following register settings "for optimum 2004 * performance." for rev 15C. Set this also for 15D parts as 2005 * they require it in practice. 2006 */ 2007 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2008 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2009 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2010 /* set val for c2 */ 2011 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2012 /* load/kill c2 */ 2013 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2014 /* rais SD off, from 4 to c */ 2015 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2016 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2017 } 2018 2019 sis_rxfilter(sc); 2020 2021 /* 2022 * Load the address of the RX and TX lists. 2023 */ 2024 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2025 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2026 2027 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2028 * the PCI bus. When this bit is set, the Max DMA Burst Size 2029 * for TX/RX DMA should be no larger than 16 double words. 2030 */ 2031 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2032 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2033 } else { 2034 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2035 } 2036 2037 /* Accept Long Packets for VLAN support */ 2038 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2039 2040 /* 2041 * Assume 100Mbps link, actual MAC configuration is done 2042 * after getting a valid link. 2043 */ 2044 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2045 2046 /* 2047 * Enable interrupts. 2048 */ 2049 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2050 #ifdef DEVICE_POLLING 2051 /* 2052 * ... only enable interrupts if we are not polling, make sure 2053 * they are off otherwise. 2054 */ 2055 if (ifp->if_capenable & IFCAP_POLLING) 2056 CSR_WRITE_4(sc, SIS_IER, 0); 2057 else 2058 #endif 2059 CSR_WRITE_4(sc, SIS_IER, 1); 2060 2061 /* Clear MAC disable. */ 2062 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2063 2064 sc->sis_flags &= ~SIS_FLAG_LINK; 2065 mii_mediachg(mii); 2066 2067 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2068 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2069 2070 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2071 } 2072 2073 /* 2074 * Set media options. 2075 */ 2076 static int 2077 sis_ifmedia_upd(struct ifnet *ifp) 2078 { 2079 struct sis_softc *sc; 2080 struct mii_data *mii; 2081 struct mii_softc *miisc; 2082 int error; 2083 2084 sc = ifp->if_softc; 2085 2086 SIS_LOCK(sc); 2087 mii = device_get_softc(sc->sis_miibus); 2088 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2089 PHY_RESET(miisc); 2090 error = mii_mediachg(mii); 2091 SIS_UNLOCK(sc); 2092 2093 return (error); 2094 } 2095 2096 /* 2097 * Report current media status. 2098 */ 2099 static void 2100 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2101 { 2102 struct sis_softc *sc; 2103 struct mii_data *mii; 2104 2105 sc = ifp->if_softc; 2106 2107 SIS_LOCK(sc); 2108 mii = device_get_softc(sc->sis_miibus); 2109 mii_pollstat(mii); 2110 ifmr->ifm_active = mii->mii_media_active; 2111 ifmr->ifm_status = mii->mii_media_status; 2112 SIS_UNLOCK(sc); 2113 } 2114 2115 static int 2116 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2117 { 2118 struct sis_softc *sc = ifp->if_softc; 2119 struct ifreq *ifr = (struct ifreq *) data; 2120 struct mii_data *mii; 2121 int error = 0, mask; 2122 2123 switch (command) { 2124 case SIOCSIFFLAGS: 2125 SIS_LOCK(sc); 2126 if (ifp->if_flags & IFF_UP) { 2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2128 ((ifp->if_flags ^ sc->sis_if_flags) & 2129 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2130 sis_rxfilter(sc); 2131 else 2132 sis_initl(sc); 2133 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2134 sis_stop(sc); 2135 sc->sis_if_flags = ifp->if_flags; 2136 SIS_UNLOCK(sc); 2137 break; 2138 case SIOCADDMULTI: 2139 case SIOCDELMULTI: 2140 SIS_LOCK(sc); 2141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2142 sis_rxfilter(sc); 2143 SIS_UNLOCK(sc); 2144 break; 2145 case SIOCGIFMEDIA: 2146 case SIOCSIFMEDIA: 2147 mii = device_get_softc(sc->sis_miibus); 2148 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2149 break; 2150 case SIOCSIFCAP: 2151 SIS_LOCK(sc); 2152 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2153 #ifdef DEVICE_POLLING 2154 if ((mask & IFCAP_POLLING) != 0 && 2155 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2156 ifp->if_capenable ^= IFCAP_POLLING; 2157 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2158 error = ether_poll_register(sis_poll, ifp); 2159 if (error != 0) { 2160 SIS_UNLOCK(sc); 2161 break; 2162 } 2163 /* Disable interrupts. */ 2164 CSR_WRITE_4(sc, SIS_IER, 0); 2165 } else { 2166 error = ether_poll_deregister(ifp); 2167 /* Enable interrupts. */ 2168 CSR_WRITE_4(sc, SIS_IER, 1); 2169 } 2170 } 2171 #endif /* DEVICE_POLLING */ 2172 if ((mask & IFCAP_WOL) != 0 && 2173 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2174 if ((mask & IFCAP_WOL_UCAST) != 0) 2175 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2176 if ((mask & IFCAP_WOL_MCAST) != 0) 2177 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2178 if ((mask & IFCAP_WOL_MAGIC) != 0) 2179 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2180 } 2181 SIS_UNLOCK(sc); 2182 break; 2183 default: 2184 error = ether_ioctl(ifp, command, data); 2185 break; 2186 } 2187 2188 return (error); 2189 } 2190 2191 static void 2192 sis_watchdog(struct sis_softc *sc) 2193 { 2194 2195 SIS_LOCK_ASSERT(sc); 2196 2197 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2198 return; 2199 2200 device_printf(sc->sis_dev, "watchdog timeout\n"); 2201 sc->sis_ifp->if_oerrors++; 2202 2203 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2204 sis_initl(sc); 2205 2206 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2207 sis_startl(sc->sis_ifp); 2208 } 2209 2210 /* 2211 * Stop the adapter and free any mbufs allocated to the 2212 * RX and TX lists. 2213 */ 2214 static void 2215 sis_stop(struct sis_softc *sc) 2216 { 2217 struct ifnet *ifp; 2218 struct sis_rxdesc *rxd; 2219 struct sis_txdesc *txd; 2220 int i; 2221 2222 SIS_LOCK_ASSERT(sc); 2223 2224 ifp = sc->sis_ifp; 2225 sc->sis_watchdog_timer = 0; 2226 2227 callout_stop(&sc->sis_stat_ch); 2228 2229 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2230 CSR_WRITE_4(sc, SIS_IER, 0); 2231 CSR_WRITE_4(sc, SIS_IMR, 0); 2232 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2233 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2234 DELAY(1000); 2235 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2236 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2237 2238 sc->sis_flags &= ~SIS_FLAG_LINK; 2239 2240 /* 2241 * Free data in the RX lists. 2242 */ 2243 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2244 rxd = &sc->sis_rxdesc[i]; 2245 if (rxd->rx_m != NULL) { 2246 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2247 BUS_DMASYNC_POSTREAD); 2248 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2249 m_freem(rxd->rx_m); 2250 rxd->rx_m = NULL; 2251 } 2252 } 2253 2254 /* 2255 * Free the TX list buffers. 2256 */ 2257 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2258 txd = &sc->sis_txdesc[i]; 2259 if (txd->tx_m != NULL) { 2260 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2261 BUS_DMASYNC_POSTWRITE); 2262 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2263 m_freem(txd->tx_m); 2264 txd->tx_m = NULL; 2265 } 2266 } 2267 } 2268 2269 /* 2270 * Stop all chip I/O so that the kernel's probe routines don't 2271 * get confused by errant DMAs when rebooting. 2272 */ 2273 static int 2274 sis_shutdown(device_t dev) 2275 { 2276 2277 return (sis_suspend(dev)); 2278 } 2279 2280 static int 2281 sis_suspend(device_t dev) 2282 { 2283 struct sis_softc *sc; 2284 2285 sc = device_get_softc(dev); 2286 SIS_LOCK(sc); 2287 sis_stop(sc); 2288 sis_wol(sc); 2289 SIS_UNLOCK(sc); 2290 return (0); 2291 } 2292 2293 static int 2294 sis_resume(device_t dev) 2295 { 2296 struct sis_softc *sc; 2297 struct ifnet *ifp; 2298 2299 sc = device_get_softc(dev); 2300 SIS_LOCK(sc); 2301 ifp = sc->sis_ifp; 2302 if ((ifp->if_flags & IFF_UP) != 0) { 2303 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2304 sis_initl(sc); 2305 } 2306 SIS_UNLOCK(sc); 2307 return (0); 2308 } 2309 2310 static void 2311 sis_wol(struct sis_softc *sc) 2312 { 2313 struct ifnet *ifp; 2314 uint32_t val; 2315 uint16_t pmstat; 2316 int pmc; 2317 2318 ifp = sc->sis_ifp; 2319 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2320 return; 2321 2322 if (sc->sis_type == SIS_TYPE_83815) { 2323 /* Reset RXDP. */ 2324 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2325 2326 /* Configure WOL events. */ 2327 CSR_READ_4(sc, NS_WCSR); 2328 val = 0; 2329 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2330 val |= NS_WCSR_WAKE_UCAST; 2331 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2332 val |= NS_WCSR_WAKE_MCAST; 2333 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2334 val |= NS_WCSR_WAKE_MAGIC; 2335 CSR_WRITE_4(sc, NS_WCSR, val); 2336 /* Enable PME and clear PMESTS. */ 2337 val = CSR_READ_4(sc, NS_CLKRUN); 2338 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2339 CSR_WRITE_4(sc, NS_CLKRUN, val); 2340 /* Enable silent RX mode. */ 2341 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2342 } else { 2343 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2344 return; 2345 val = 0; 2346 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2347 val |= SIS_PWRMAN_WOL_MAGIC; 2348 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2349 /* Request PME. */ 2350 pmstat = pci_read_config(sc->sis_dev, 2351 pmc + PCIR_POWER_STATUS, 2); 2352 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2353 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2354 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2355 pci_write_config(sc->sis_dev, 2356 pmc + PCIR_POWER_STATUS, pmstat, 2); 2357 } 2358 } 2359 2360 static void 2361 sis_add_sysctls(struct sis_softc *sc) 2362 { 2363 struct sysctl_ctx_list *ctx; 2364 struct sysctl_oid_list *children; 2365 char tn[32]; 2366 int unit; 2367 2368 ctx = device_get_sysctl_ctx(sc->sis_dev); 2369 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2370 2371 unit = device_get_unit(sc->sis_dev); 2372 /* 2373 * Unlike most other controllers, NS DP83815/DP83816 controllers 2374 * seem to pad with 0xFF when it encounter short frames. According 2375 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2376 * on will have driver pad manully but it's disabled by default 2377 * because it will consume extra CPU cycles for short frames. 2378 */ 2379 sc->sis_manual_pad = 0; 2380 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2381 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2382 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2383 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2384 } 2385 2386 static device_method_t sis_methods[] = { 2387 /* Device interface */ 2388 DEVMETHOD(device_probe, sis_probe), 2389 DEVMETHOD(device_attach, sis_attach), 2390 DEVMETHOD(device_detach, sis_detach), 2391 DEVMETHOD(device_shutdown, sis_shutdown), 2392 DEVMETHOD(device_suspend, sis_suspend), 2393 DEVMETHOD(device_resume, sis_resume), 2394 2395 /* MII interface */ 2396 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2397 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2398 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2399 2400 DEVMETHOD_END 2401 }; 2402 2403 static driver_t sis_driver = { 2404 "sis", 2405 sis_methods, 2406 sizeof(struct sis_softc) 2407 }; 2408 2409 static devclass_t sis_devclass; 2410 2411 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2412 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
Cache object: bdee18b1f47bd667e6333f162f7e98ed
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