FreeBSD/Linux Kernel Cross Reference
sys/dev/sis/if_sis.c
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
5 * Copyright (c) 1997, 1998, 1999
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
41 * available from http://www.sis.com.tw.
42 *
43 * This driver also supports the NatSemi DP83815. Datasheets are
44 * available from http://www.national.com.
45 *
46 * Written by Bill Paul <wpaul@ee.columbia.edu>
47 * Electrical Engineering Department
48 * Columbia University, New York City
49 */
50 /*
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
58 *
59 * The only downside to this chipset is that RX descriptors must be
60 * longword aligned.
61 */
62
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
65 #endif
66
67 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/bus.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
72 #include <sys/lock.h>
73 #include <sys/malloc.h>
74 #include <sys/mbuf.h>
75 #include <sys/module.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
79
80 #include <net/if.h>
81 #include <net/if_var.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
87 #include <net/if_vlan_var.h>
88
89 #include <net/bpf.h>
90
91 #include <machine/bus.h>
92 #include <machine/resource.h>
93 #include <sys/rman.h>
94
95 #include <dev/mii/mii.h>
96 #include <dev/mii/mii_bitbang.h>
97 #include <dev/mii/miivar.h>
98
99 #include <dev/pci/pcireg.h>
100 #include <dev/pci/pcivar.h>
101
102 #define SIS_USEIOSPACE
103
104 #include <dev/sis/if_sisreg.h>
105
106 MODULE_DEPEND(sis, pci, 1, 1, 1);
107 MODULE_DEPEND(sis, ether, 1, 1, 1);
108 MODULE_DEPEND(sis, miibus, 1, 1, 1);
109
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
112
113 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
114 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
115 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
116
117 /*
118 * register space access macros
119 */
120 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
121
122 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
123
124 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
125
126 #define CSR_BARRIER(sc, reg, length, flags) \
127 bus_barrier(sc->sis_res[0], reg, length, flags)
128
129 /*
130 * Various supported device vendors/types and their names.
131 */
132 static const struct sis_type sis_devs[] = {
133 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
134 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
135 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
136 { 0, 0, NULL }
137 };
138
139 static int sis_detach(device_t);
140 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
141 static int sis_dma_alloc(struct sis_softc *);
142 static void sis_dma_free(struct sis_softc *);
143 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
144 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
145 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
146 #ifndef __NO_STRICT_ALIGNMENT
147 static __inline void sis_fixup_rx(struct mbuf *);
148 #endif
149 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150 static int sis_ifmedia_upd(struct ifnet *);
151 static void sis_init(void *);
152 static void sis_initl(struct sis_softc *);
153 static void sis_intr(void *);
154 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
155 static uint32_t sis_mii_bitbang_read(device_t);
156 static void sis_mii_bitbang_write(device_t, uint32_t);
157 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
158 static int sis_resume(device_t);
159 static int sis_rxeof(struct sis_softc *);
160 static void sis_rxfilter(struct sis_softc *);
161 static void sis_rxfilter_ns(struct sis_softc *);
162 static void sis_rxfilter_sis(struct sis_softc *);
163 static void sis_start(struct ifnet *);
164 static void sis_startl(struct ifnet *);
165 static void sis_stop(struct sis_softc *);
166 static int sis_suspend(device_t);
167 static void sis_add_sysctls(struct sis_softc *);
168 static void sis_watchdog(struct sis_softc *);
169 static void sis_wol(struct sis_softc *);
170
171 /*
172 * MII bit-bang glue
173 */
174 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
175 sis_mii_bitbang_read,
176 sis_mii_bitbang_write,
177 {
178 SIS_MII_DATA, /* MII_BIT_MDO */
179 SIS_MII_DATA, /* MII_BIT_MDI */
180 SIS_MII_CLK, /* MII_BIT_MDC */
181 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
182 0, /* MII_BIT_DIR_PHY_HOST */
183 }
184 };
185
186 static struct resource_spec sis_res_spec[] = {
187 #ifdef SIS_USEIOSPACE
188 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
189 #else
190 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
191 #endif
192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
193 { -1, 0 }
194 };
195
196 #define SIS_SETBIT(sc, reg, x) \
197 CSR_WRITE_4(sc, reg, \
198 CSR_READ_4(sc, reg) | (x))
199
200 #define SIS_CLRBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, \
202 CSR_READ_4(sc, reg) & ~(x))
203
204 #define SIO_SET(x) \
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206
207 #define SIO_CLR(x) \
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
209
210 /*
211 * Routine to reverse the bits in a word. Stolen almost
212 * verbatim from /usr/games/fortune.
213 */
214 static uint16_t
215 sis_reverse(uint16_t n)
216 {
217 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
218 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
219 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
220 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
221
222 return (n);
223 }
224
225 static void
226 sis_delay(struct sis_softc *sc)
227 {
228 int idx;
229
230 for (idx = (300 / 33) + 1; idx > 0; idx--)
231 CSR_READ_4(sc, SIS_CSR);
232 }
233
234 static void
235 sis_eeprom_idle(struct sis_softc *sc)
236 {
237 int i;
238
239 SIO_SET(SIS_EECTL_CSEL);
240 sis_delay(sc);
241 SIO_SET(SIS_EECTL_CLK);
242 sis_delay(sc);
243
244 for (i = 0; i < 25; i++) {
245 SIO_CLR(SIS_EECTL_CLK);
246 sis_delay(sc);
247 SIO_SET(SIS_EECTL_CLK);
248 sis_delay(sc);
249 }
250
251 SIO_CLR(SIS_EECTL_CLK);
252 sis_delay(sc);
253 SIO_CLR(SIS_EECTL_CSEL);
254 sis_delay(sc);
255 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
256 }
257
258 /*
259 * Send a read command and address to the EEPROM, check for ACK.
260 */
261 static void
262 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
263 {
264 int d, i;
265
266 d = addr | SIS_EECMD_READ;
267
268 /*
269 * Feed in each bit and stobe the clock.
270 */
271 for (i = 0x400; i; i >>= 1) {
272 if (d & i) {
273 SIO_SET(SIS_EECTL_DIN);
274 } else {
275 SIO_CLR(SIS_EECTL_DIN);
276 }
277 sis_delay(sc);
278 SIO_SET(SIS_EECTL_CLK);
279 sis_delay(sc);
280 SIO_CLR(SIS_EECTL_CLK);
281 sis_delay(sc);
282 }
283 }
284
285 /*
286 * Read a word of data stored in the EEPROM at address 'addr.'
287 */
288 static void
289 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
290 {
291 int i;
292 uint16_t word = 0;
293
294 /* Force EEPROM to idle state. */
295 sis_eeprom_idle(sc);
296
297 /* Enter EEPROM access mode. */
298 sis_delay(sc);
299 SIO_CLR(SIS_EECTL_CLK);
300 sis_delay(sc);
301 SIO_SET(SIS_EECTL_CSEL);
302 sis_delay(sc);
303
304 /*
305 * Send address of word we want to read.
306 */
307 sis_eeprom_putbyte(sc, addr);
308
309 /*
310 * Start reading bits from EEPROM.
311 */
312 for (i = 0x8000; i; i >>= 1) {
313 SIO_SET(SIS_EECTL_CLK);
314 sis_delay(sc);
315 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
316 word |= i;
317 sis_delay(sc);
318 SIO_CLR(SIS_EECTL_CLK);
319 sis_delay(sc);
320 }
321
322 /* Turn off EEPROM access mode. */
323 sis_eeprom_idle(sc);
324
325 *dest = word;
326 }
327
328 /*
329 * Read a sequence of words from the EEPROM.
330 */
331 static void
332 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
333 {
334 int i;
335 uint16_t word = 0, *ptr;
336
337 for (i = 0; i < cnt; i++) {
338 sis_eeprom_getword(sc, off + i, &word);
339 ptr = (uint16_t *)(dest + (i * 2));
340 if (swap)
341 *ptr = ntohs(word);
342 else
343 *ptr = word;
344 }
345 }
346
347 #if defined(__i386__) || defined(__amd64__)
348 static device_t
349 sis_find_bridge(device_t dev)
350 {
351 devclass_t pci_devclass;
352 device_t *pci_devices;
353 int pci_count = 0;
354 device_t *pci_children;
355 int pci_childcount = 0;
356 device_t *busp, *childp;
357 device_t child = NULL;
358 int i, j;
359
360 if ((pci_devclass = devclass_find("pci")) == NULL)
361 return (NULL);
362
363 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
364
365 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
366 if (device_get_children(*busp, &pci_children, &pci_childcount))
367 continue;
368 for (j = 0, childp = pci_children;
369 j < pci_childcount; j++, childp++) {
370 if (pci_get_vendor(*childp) == SIS_VENDORID &&
371 pci_get_device(*childp) == 0x0008) {
372 child = *childp;
373 free(pci_children, M_TEMP);
374 goto done;
375 }
376 }
377 free(pci_children, M_TEMP);
378 }
379
380 done:
381 free(pci_devices, M_TEMP);
382 return (child);
383 }
384
385 static void
386 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
387 {
388 device_t bridge;
389 uint8_t reg;
390 int i;
391 bus_space_tag_t btag;
392
393 bridge = sis_find_bridge(dev);
394 if (bridge == NULL)
395 return;
396 reg = pci_read_config(bridge, 0x48, 1);
397 pci_write_config(bridge, 0x48, reg|0x40, 1);
398
399 /* XXX */
400 #if defined(__amd64__) || defined(__i386__)
401 btag = X86_BUS_SPACE_IO;
402 #endif
403
404 for (i = 0; i < cnt; i++) {
405 bus_space_write_1(btag, 0x0, 0x70, i + off);
406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
407 }
408
409 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
410 }
411
412 static void
413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
414 {
415 uint32_t filtsave, csrsave;
416
417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
418 csrsave = CSR_READ_4(sc, SIS_CSR);
419
420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
421 CSR_WRITE_4(sc, SIS_CSR, 0);
422
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
424
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
431
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
433 CSR_WRITE_4(sc, SIS_CSR, csrsave);
434 }
435 #endif
436
437 /*
438 * Read the MII serial port for the MII bit-bang module.
439 */
440 static uint32_t
441 sis_mii_bitbang_read(device_t dev)
442 {
443 struct sis_softc *sc;
444 uint32_t val;
445
446 sc = device_get_softc(dev);
447
448 val = CSR_READ_4(sc, SIS_EECTL);
449 CSR_BARRIER(sc, SIS_EECTL, 4,
450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
451 return (val);
452 }
453
454 /*
455 * Write the MII serial port for the MII bit-bang module.
456 */
457 static void
458 sis_mii_bitbang_write(device_t dev, uint32_t val)
459 {
460 struct sis_softc *sc;
461
462 sc = device_get_softc(dev);
463
464 CSR_WRITE_4(sc, SIS_EECTL, val);
465 CSR_BARRIER(sc, SIS_EECTL, 4,
466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
467 }
468
469 static int
470 sis_miibus_readreg(device_t dev, int phy, int reg)
471 {
472 struct sis_softc *sc;
473
474 sc = device_get_softc(dev);
475
476 if (sc->sis_type == SIS_TYPE_83815) {
477 if (phy != 0)
478 return (0);
479 /*
480 * The NatSemi chip can take a while after
481 * a reset to come ready, during which the BMSR
482 * returns a value of 0. This is *never* supposed
483 * to happen: some of the BMSR bits are meant to
484 * be hardwired in the on position, and this can
485 * confuse the miibus code a bit during the probe
486 * and attach phase. So we make an effort to check
487 * for this condition and wait for it to clear.
488 */
489 if (!CSR_READ_4(sc, NS_BMSR))
490 DELAY(1000);
491 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
492 }
493
494 /*
495 * Chipsets < SIS_635 seem not to be able to read/write
496 * through mdio. Use the enhanced PHY access register
497 * again for them.
498 */
499 if (sc->sis_type == SIS_TYPE_900 &&
500 sc->sis_rev < SIS_REV_635) {
501 int i, val = 0;
502
503 if (phy != 0)
504 return (0);
505
506 CSR_WRITE_4(sc, SIS_PHYCTL,
507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
508 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
509
510 for (i = 0; i < SIS_TIMEOUT; i++) {
511 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
512 break;
513 }
514
515 if (i == SIS_TIMEOUT) {
516 device_printf(sc->sis_dev,
517 "PHY failed to come ready\n");
518 return (0);
519 }
520
521 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
522
523 if (val == 0xFFFF)
524 return (0);
525
526 return (val);
527 } else
528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
529 reg));
530 }
531
532 static int
533 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
534 {
535 struct sis_softc *sc;
536
537 sc = device_get_softc(dev);
538
539 if (sc->sis_type == SIS_TYPE_83815) {
540 if (phy != 0)
541 return (0);
542 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
543 return (0);
544 }
545
546 /*
547 * Chipsets < SIS_635 seem not to be able to read/write
548 * through mdio. Use the enhanced PHY access register
549 * again for them.
550 */
551 if (sc->sis_type == SIS_TYPE_900 &&
552 sc->sis_rev < SIS_REV_635) {
553 int i;
554
555 if (phy != 0)
556 return (0);
557
558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
559 (reg << 6) | SIS_PHYOP_WRITE);
560 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
561
562 for (i = 0; i < SIS_TIMEOUT; i++) {
563 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
564 break;
565 }
566
567 if (i == SIS_TIMEOUT)
568 device_printf(sc->sis_dev,
569 "PHY failed to come ready\n");
570 } else
571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
572 data);
573 return (0);
574 }
575
576 static void
577 sis_miibus_statchg(device_t dev)
578 {
579 struct sis_softc *sc;
580 struct mii_data *mii;
581 struct ifnet *ifp;
582 uint32_t reg;
583
584 sc = device_get_softc(dev);
585 SIS_LOCK_ASSERT(sc);
586
587 mii = device_get_softc(sc->sis_miibus);
588 ifp = sc->sis_ifp;
589 if (mii == NULL || ifp == NULL ||
590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
591 return;
592
593 sc->sis_flags &= ~SIS_FLAG_LINK;
594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
595 (IFM_ACTIVE | IFM_AVALID)) {
596 switch (IFM_SUBTYPE(mii->mii_media_active)) {
597 case IFM_10_T:
598 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
599 sc->sis_flags |= SIS_FLAG_LINK;
600 break;
601 case IFM_100_TX:
602 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
603 sc->sis_flags |= SIS_FLAG_LINK;
604 break;
605 default:
606 break;
607 }
608 }
609
610 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
611 /*
612 * Stopping MACs seem to reset SIS_TX_LISTPTR and
613 * SIS_RX_LISTPTR which in turn requires resetting
614 * TX/RX buffers. So just don't do anything for
615 * lost link.
616 */
617 return;
618 }
619
620 /* Set full/half duplex mode. */
621 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
622 SIS_SETBIT(sc, SIS_TX_CFG,
623 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
624 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
625 } else {
626 SIS_CLRBIT(sc, SIS_TX_CFG,
627 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
628 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
629 }
630
631 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
632 /*
633 * MPII03.D: Half Duplex Excessive Collisions.
634 * Also page 49 in 83816 manual
635 */
636 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
637 }
638
639 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
640 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
641 /*
642 * Short Cable Receive Errors (MP21.E)
643 */
644 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
645 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
646 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
647 DELAY(100);
648 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
649 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
650 device_printf(sc->sis_dev,
651 "Applying short cable fix (reg=%x)\n", reg);
652 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
653 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
654 }
655 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
656 }
657 /* Enable TX/RX MACs. */
658 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
659 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
660 }
661
662 static uint32_t
663 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
664 {
665 uint32_t crc;
666
667 /* Compute CRC for the address value. */
668 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
669
670 /*
671 * return the filter bit position
672 *
673 * The NatSemi chip has a 512-bit filter, which is
674 * different than the SiS, so we special-case it.
675 */
676 if (sc->sis_type == SIS_TYPE_83815)
677 return (crc >> 23);
678 else if (sc->sis_rev >= SIS_REV_635 ||
679 sc->sis_rev == SIS_REV_900B)
680 return (crc >> 24);
681 else
682 return (crc >> 25);
683 }
684
685 static void
686 sis_rxfilter(struct sis_softc *sc)
687 {
688
689 SIS_LOCK_ASSERT(sc);
690
691 if (sc->sis_type == SIS_TYPE_83815)
692 sis_rxfilter_ns(sc);
693 else
694 sis_rxfilter_sis(sc);
695 }
696
697 static u_int
698 sis_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
699 {
700 struct sis_softc *sc = arg;
701 uint32_t h;
702 int bit, index;
703
704 h = sis_mchash(sc, LLADDR(sdl));
705 index = h >> 3;
706 bit = h & 0x1F;
707 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
708 if (bit > 0xF)
709 bit -= 0x10;
710 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
711
712 return (1);
713 }
714
715 static void
716 sis_rxfilter_ns(struct sis_softc *sc)
717 {
718 struct ifnet *ifp;
719 uint32_t i, filter;
720
721 ifp = sc->sis_ifp;
722 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
723 if (filter & SIS_RXFILTCTL_ENABLE) {
724 /*
725 * Filter should be disabled to program other bits.
726 */
727 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
728 CSR_READ_4(sc, SIS_RXFILT_CTL);
729 }
730 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
731 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
732 SIS_RXFILTCTL_ALLMULTI);
733
734 if (ifp->if_flags & IFF_BROADCAST)
735 filter |= SIS_RXFILTCTL_BROAD;
736 /*
737 * For the NatSemi chip, we have to explicitly enable the
738 * reception of ARP frames, as well as turn on the 'perfect
739 * match' filter where we store the station address, otherwise
740 * we won't receive unicasts meant for this host.
741 */
742 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
743
744 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
745 filter |= SIS_RXFILTCTL_ALLMULTI;
746 if (ifp->if_flags & IFF_PROMISC)
747 filter |= SIS_RXFILTCTL_ALLPHYS;
748 } else {
749 /*
750 * We have to explicitly enable the multicast hash table
751 * on the NatSemi chip if we want to use it, which we do.
752 */
753 filter |= NS_RXFILTCTL_MCHASH;
754
755 /* first, zot all the existing hash bits */
756 for (i = 0; i < 32; i++) {
757 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
758 (i * 2));
759 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
760 }
761
762 if_foreach_llmaddr(ifp, sis_write_maddr, sc);
763 }
764
765 /* Turn the receive filter on */
766 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
767 CSR_READ_4(sc, SIS_RXFILT_CTL);
768 }
769
770 struct sis_hash_maddr_ctx {
771 struct sis_softc *sc;
772 uint16_t hashes[16];
773 };
774
775 static u_int
776 sis_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
777 {
778 struct sis_hash_maddr_ctx *ctx = arg;
779 uint32_t h;
780
781 h = sis_mchash(ctx->sc, LLADDR(sdl));
782 ctx->hashes[h >> 4] |= 1 << (h & 0xf);
783
784 return (1);
785 }
786
787 static void
788 sis_rxfilter_sis(struct sis_softc *sc)
789 {
790 struct ifnet *ifp;
791 struct sis_hash_maddr_ctx ctx;
792 uint32_t filter, i, n;
793
794 ifp = sc->sis_ifp;
795
796 /* hash table size */
797 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
798 n = 16;
799 else
800 n = 8;
801
802 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
803 if (filter & SIS_RXFILTCTL_ENABLE) {
804 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
805 CSR_READ_4(sc, SIS_RXFILT_CTL);
806 }
807 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
808 SIS_RXFILTCTL_ALLMULTI);
809 if (ifp->if_flags & IFF_BROADCAST)
810 filter |= SIS_RXFILTCTL_BROAD;
811
812 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
813 filter |= SIS_RXFILTCTL_ALLMULTI;
814 if (ifp->if_flags & IFF_PROMISC)
815 filter |= SIS_RXFILTCTL_ALLPHYS;
816 for (i = 0; i < n; i++)
817 ctx.hashes[i] = ~0;
818 } else {
819 for (i = 0; i < n; i++)
820 ctx.hashes[i] = 0;
821 ctx.sc = sc;
822 if (if_foreach_llmaddr(ifp, sis_hash_maddr, &ctx) > n) {
823 filter |= SIS_RXFILTCTL_ALLMULTI;
824 for (i = 0; i < n; i++)
825 ctx.hashes[i] = ~0;
826 }
827 }
828
829 for (i = 0; i < n; i++) {
830 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
831 CSR_WRITE_4(sc, SIS_RXFILT_DATA, ctx.hashes[i]);
832 }
833
834 /* Turn the receive filter on */
835 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
836 CSR_READ_4(sc, SIS_RXFILT_CTL);
837 }
838
839 static void
840 sis_reset(struct sis_softc *sc)
841 {
842 int i;
843
844 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
845
846 for (i = 0; i < SIS_TIMEOUT; i++) {
847 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
848 break;
849 }
850
851 if (i == SIS_TIMEOUT)
852 device_printf(sc->sis_dev, "reset never completed\n");
853
854 /* Wait a little while for the chip to get its brains in order. */
855 DELAY(1000);
856
857 /*
858 * If this is a NetSemi chip, make sure to clear
859 * PME mode.
860 */
861 if (sc->sis_type == SIS_TYPE_83815) {
862 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
863 CSR_WRITE_4(sc, NS_CLKRUN, 0);
864 } else {
865 /* Disable WOL functions. */
866 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
867 }
868 }
869
870 /*
871 * Probe for an SiS chip. Check the PCI vendor and device
872 * IDs against our list and return a device name if we find a match.
873 */
874 static int
875 sis_probe(device_t dev)
876 {
877 const struct sis_type *t;
878
879 t = sis_devs;
880
881 while (t->sis_name != NULL) {
882 if ((pci_get_vendor(dev) == t->sis_vid) &&
883 (pci_get_device(dev) == t->sis_did)) {
884 device_set_desc(dev, t->sis_name);
885 return (BUS_PROBE_DEFAULT);
886 }
887 t++;
888 }
889
890 return (ENXIO);
891 }
892
893 /*
894 * Attach the interface. Allocate softc structures, do ifmedia
895 * setup and ethernet/BPF attach.
896 */
897 static int
898 sis_attach(device_t dev)
899 {
900 u_char eaddr[ETHER_ADDR_LEN];
901 struct sis_softc *sc;
902 struct ifnet *ifp;
903 int error = 0, pmc, waittime = 0;
904
905 waittime = 0;
906 sc = device_get_softc(dev);
907
908 sc->sis_dev = dev;
909
910 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
911 MTX_DEF);
912 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
913
914 if (pci_get_device(dev) == SIS_DEVICEID_900)
915 sc->sis_type = SIS_TYPE_900;
916 if (pci_get_device(dev) == SIS_DEVICEID_7016)
917 sc->sis_type = SIS_TYPE_7016;
918 if (pci_get_vendor(dev) == NS_VENDORID)
919 sc->sis_type = SIS_TYPE_83815;
920
921 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
922 /*
923 * Map control/status registers.
924 */
925 pci_enable_busmaster(dev);
926
927 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
928 if (error) {
929 device_printf(dev, "couldn't allocate resources\n");
930 goto fail;
931 }
932
933 /* Reset the adapter. */
934 sis_reset(sc);
935
936 if (sc->sis_type == SIS_TYPE_900 &&
937 (sc->sis_rev == SIS_REV_635 ||
938 sc->sis_rev == SIS_REV_900B)) {
939 SIO_SET(SIS_CFG_RND_CNT);
940 SIO_SET(SIS_CFG_PERR_DETECT);
941 }
942
943 /*
944 * Get station address from the EEPROM.
945 */
946 switch (pci_get_vendor(dev)) {
947 case NS_VENDORID:
948 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
949
950 /* We can't update the device description, so spew */
951 if (sc->sis_srr == NS_SRR_15C)
952 device_printf(dev, "Silicon Revision: DP83815C\n");
953 else if (sc->sis_srr == NS_SRR_15D)
954 device_printf(dev, "Silicon Revision: DP83815D\n");
955 else if (sc->sis_srr == NS_SRR_16A)
956 device_printf(dev, "Silicon Revision: DP83816A\n");
957 else
958 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
959
960 /*
961 * Reading the MAC address out of the EEPROM on
962 * the NatSemi chip takes a bit more work than
963 * you'd expect. The address spans 4 16-bit words,
964 * with the first word containing only a single bit.
965 * You have to shift everything over one bit to
966 * get it aligned properly. Also, the bits are
967 * stored backwards (the LSB is really the MSB,
968 * and so on) so you have to reverse them in order
969 * to get the MAC address into the form we want.
970 * Why? Who the hell knows.
971 */
972 {
973 uint16_t tmp[4];
974
975 sis_read_eeprom(sc, (caddr_t)&tmp,
976 NS_EE_NODEADDR, 4, 0);
977
978 /* Shift everything over one bit. */
979 tmp[3] = tmp[3] >> 1;
980 tmp[3] |= tmp[2] << 15;
981 tmp[2] = tmp[2] >> 1;
982 tmp[2] |= tmp[1] << 15;
983 tmp[1] = tmp[1] >> 1;
984 tmp[1] |= tmp[0] << 15;
985
986 /* Now reverse all the bits. */
987 tmp[3] = sis_reverse(tmp[3]);
988 tmp[2] = sis_reverse(tmp[2]);
989 tmp[1] = sis_reverse(tmp[1]);
990
991 eaddr[0] = (tmp[1] >> 0) & 0xFF;
992 eaddr[1] = (tmp[1] >> 8) & 0xFF;
993 eaddr[2] = (tmp[2] >> 0) & 0xFF;
994 eaddr[3] = (tmp[2] >> 8) & 0xFF;
995 eaddr[4] = (tmp[3] >> 0) & 0xFF;
996 eaddr[5] = (tmp[3] >> 8) & 0xFF;
997 }
998 break;
999 case SIS_VENDORID:
1000 default:
1001 #if defined(__i386__) || defined(__amd64__)
1002 /*
1003 * If this is a SiS 630E chipset with an embedded
1004 * SiS 900 controller, we have to read the MAC address
1005 * from the APC CMOS RAM. Our method for doing this
1006 * is very ugly since we have to reach out and grab
1007 * ahold of hardware for which we cannot properly
1008 * allocate resources. This code is only compiled on
1009 * the i386 architecture since the SiS 630E chipset
1010 * is for x86 motherboards only. Note that there are
1011 * a lot of magic numbers in this hack. These are
1012 * taken from SiS's Linux driver. I'd like to replace
1013 * them with proper symbolic definitions, but that
1014 * requires some datasheets that I don't have access
1015 * to at the moment.
1016 */
1017 if (sc->sis_rev == SIS_REV_630S ||
1018 sc->sis_rev == SIS_REV_630E ||
1019 sc->sis_rev == SIS_REV_630EA1)
1020 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1021
1022 else if (sc->sis_rev == SIS_REV_635 ||
1023 sc->sis_rev == SIS_REV_630ET)
1024 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1025 else if (sc->sis_rev == SIS_REV_96x) {
1026 /* Allow to read EEPROM from LAN. It is shared
1027 * between a 1394 controller and the NIC and each
1028 * time we access it, we need to set SIS_EECMD_REQ.
1029 */
1030 SIO_SET(SIS_EECMD_REQ);
1031 for (waittime = 0; waittime < SIS_TIMEOUT;
1032 waittime++) {
1033 /* Force EEPROM to idle state. */
1034 sis_eeprom_idle(sc);
1035 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1036 sis_read_eeprom(sc, (caddr_t)&eaddr,
1037 SIS_EE_NODEADDR, 3, 0);
1038 break;
1039 }
1040 DELAY(1);
1041 }
1042 /*
1043 * Set SIS_EECTL_CLK to high, so a other master
1044 * can operate on the i2c bus.
1045 */
1046 SIO_SET(SIS_EECTL_CLK);
1047 /* Refuse EEPROM access by LAN */
1048 SIO_SET(SIS_EECMD_DONE);
1049 } else
1050 #endif
1051 sis_read_eeprom(sc, (caddr_t)&eaddr,
1052 SIS_EE_NODEADDR, 3, 0);
1053 break;
1054 }
1055
1056 sis_add_sysctls(sc);
1057
1058 /* Allocate DMA'able memory. */
1059 if ((error = sis_dma_alloc(sc)) != 0)
1060 goto fail;
1061
1062 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1063 if (ifp == NULL) {
1064 device_printf(dev, "can not if_alloc()\n");
1065 error = ENOSPC;
1066 goto fail;
1067 }
1068 ifp->if_softc = sc;
1069 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1070 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1071 ifp->if_ioctl = sis_ioctl;
1072 ifp->if_start = sis_start;
1073 ifp->if_init = sis_init;
1074 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1075 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1076 IFQ_SET_READY(&ifp->if_snd);
1077
1078 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1079 if (sc->sis_type == SIS_TYPE_83815)
1080 ifp->if_capabilities |= IFCAP_WOL;
1081 else
1082 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1083 ifp->if_capenable = ifp->if_capabilities;
1084 }
1085
1086 /*
1087 * Do MII setup.
1088 */
1089 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1090 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1091 if (error != 0) {
1092 device_printf(dev, "attaching PHYs failed\n");
1093 goto fail;
1094 }
1095
1096 /*
1097 * Call MI attach routine.
1098 */
1099 ether_ifattach(ifp, eaddr);
1100
1101 /*
1102 * Tell the upper layer(s) we support long frames.
1103 */
1104 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1105 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1106 ifp->if_capenable = ifp->if_capabilities;
1107 #ifdef DEVICE_POLLING
1108 ifp->if_capabilities |= IFCAP_POLLING;
1109 #endif
1110
1111 /* Hook interrupt last to avoid having to lock softc */
1112 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1113 NULL, sis_intr, sc, &sc->sis_intrhand);
1114
1115 if (error) {
1116 device_printf(dev, "couldn't set up irq\n");
1117 ether_ifdetach(ifp);
1118 goto fail;
1119 }
1120
1121 fail:
1122 if (error)
1123 sis_detach(dev);
1124
1125 return (error);
1126 }
1127
1128 /*
1129 * Shutdown hardware and free up resources. This can be called any
1130 * time after the mutex has been initialized. It is called in both
1131 * the error case in attach and the normal detach case so it needs
1132 * to be careful about only freeing resources that have actually been
1133 * allocated.
1134 */
1135 static int
1136 sis_detach(device_t dev)
1137 {
1138 struct sis_softc *sc;
1139 struct ifnet *ifp;
1140
1141 sc = device_get_softc(dev);
1142 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1143 ifp = sc->sis_ifp;
1144
1145 #ifdef DEVICE_POLLING
1146 if (ifp->if_capenable & IFCAP_POLLING)
1147 ether_poll_deregister(ifp);
1148 #endif
1149
1150 /* These should only be active if attach succeeded. */
1151 if (device_is_attached(dev)) {
1152 SIS_LOCK(sc);
1153 sis_stop(sc);
1154 SIS_UNLOCK(sc);
1155 callout_drain(&sc->sis_stat_ch);
1156 ether_ifdetach(ifp);
1157 }
1158 if (sc->sis_miibus)
1159 device_delete_child(dev, sc->sis_miibus);
1160 bus_generic_detach(dev);
1161
1162 if (sc->sis_intrhand)
1163 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1164 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1165
1166 if (ifp)
1167 if_free(ifp);
1168
1169 sis_dma_free(sc);
1170
1171 mtx_destroy(&sc->sis_mtx);
1172
1173 return (0);
1174 }
1175
1176 struct sis_dmamap_arg {
1177 bus_addr_t sis_busaddr;
1178 };
1179
1180 static void
1181 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1182 {
1183 struct sis_dmamap_arg *ctx;
1184
1185 if (error != 0)
1186 return;
1187
1188 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1189
1190 ctx = (struct sis_dmamap_arg *)arg;
1191 ctx->sis_busaddr = segs[0].ds_addr;
1192 }
1193
1194 static int
1195 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1196 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1197 bus_addr_t *paddr, const char *msg)
1198 {
1199 struct sis_dmamap_arg ctx;
1200 int error;
1201
1202 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1203 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1204 maxsize, 0, NULL, NULL, tag);
1205 if (error != 0) {
1206 device_printf(sc->sis_dev,
1207 "could not create %s dma tag\n", msg);
1208 return (ENOMEM);
1209 }
1210 /* Allocate DMA'able memory for ring. */
1211 error = bus_dmamem_alloc(*tag, (void **)ring,
1212 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1213 if (error != 0) {
1214 device_printf(sc->sis_dev,
1215 "could not allocate DMA'able memory for %s\n", msg);
1216 return (ENOMEM);
1217 }
1218 /* Load the address of the ring. */
1219 ctx.sis_busaddr = 0;
1220 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1221 &ctx, BUS_DMA_NOWAIT);
1222 if (error != 0) {
1223 device_printf(sc->sis_dev,
1224 "could not load DMA'able memory for %s\n", msg);
1225 return (ENOMEM);
1226 }
1227 *paddr = ctx.sis_busaddr;
1228 return (0);
1229 }
1230
1231 static int
1232 sis_dma_alloc(struct sis_softc *sc)
1233 {
1234 struct sis_rxdesc *rxd;
1235 struct sis_txdesc *txd;
1236 int error, i;
1237
1238 /* Allocate the parent bus DMA tag appropriate for PCI. */
1239 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1240 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1241 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1242 0, NULL, NULL, &sc->sis_parent_tag);
1243 if (error != 0) {
1244 device_printf(sc->sis_dev,
1245 "could not allocate parent dma tag\n");
1246 return (ENOMEM);
1247 }
1248
1249 /* Create RX ring. */
1250 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1251 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1252 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1253 if (error)
1254 return (error);
1255
1256 /* Create TX ring. */
1257 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1258 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1259 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1260 if (error)
1261 return (error);
1262
1263 /* Create tag for RX mbufs. */
1264 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1266 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1267 if (error) {
1268 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1269 return (error);
1270 }
1271
1272 /* Create tag for TX mbufs. */
1273 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1274 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1275 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1276 &sc->sis_tx_tag);
1277 if (error) {
1278 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1279 return (error);
1280 }
1281
1282 /* Create DMA maps for RX buffers. */
1283 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1284 if (error) {
1285 device_printf(sc->sis_dev,
1286 "can't create spare DMA map for RX\n");
1287 return (error);
1288 }
1289 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1290 rxd = &sc->sis_rxdesc[i];
1291 rxd->rx_m = NULL;
1292 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1293 if (error) {
1294 device_printf(sc->sis_dev,
1295 "can't create DMA map for RX\n");
1296 return (error);
1297 }
1298 }
1299
1300 /* Create DMA maps for TX buffers. */
1301 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1302 txd = &sc->sis_txdesc[i];
1303 txd->tx_m = NULL;
1304 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1305 if (error) {
1306 device_printf(sc->sis_dev,
1307 "can't create DMA map for TX\n");
1308 return (error);
1309 }
1310 }
1311
1312 return (0);
1313 }
1314
1315 static void
1316 sis_dma_free(struct sis_softc *sc)
1317 {
1318 struct sis_rxdesc *rxd;
1319 struct sis_txdesc *txd;
1320 int i;
1321
1322 /* Destroy DMA maps for RX buffers. */
1323 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1324 rxd = &sc->sis_rxdesc[i];
1325 if (rxd->rx_dmamap)
1326 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1327 }
1328 if (sc->sis_rx_sparemap)
1329 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1330
1331 /* Destroy DMA maps for TX buffers. */
1332 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1333 txd = &sc->sis_txdesc[i];
1334 if (txd->tx_dmamap)
1335 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1336 }
1337
1338 if (sc->sis_rx_tag)
1339 bus_dma_tag_destroy(sc->sis_rx_tag);
1340 if (sc->sis_tx_tag)
1341 bus_dma_tag_destroy(sc->sis_tx_tag);
1342
1343 /* Destroy RX ring. */
1344 if (sc->sis_rx_paddr)
1345 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1346 if (sc->sis_rx_list)
1347 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1348 sc->sis_rx_list_map);
1349
1350 if (sc->sis_rx_list_tag)
1351 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1352
1353 /* Destroy TX ring. */
1354 if (sc->sis_tx_paddr)
1355 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1356
1357 if (sc->sis_tx_list)
1358 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1359 sc->sis_tx_list_map);
1360
1361 if (sc->sis_tx_list_tag)
1362 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1363
1364 /* Destroy the parent tag. */
1365 if (sc->sis_parent_tag)
1366 bus_dma_tag_destroy(sc->sis_parent_tag);
1367 }
1368
1369 /*
1370 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1371 * we arrange the descriptors in a closed ring, so that the last descriptor
1372 * points back to the first.
1373 */
1374 static int
1375 sis_ring_init(struct sis_softc *sc)
1376 {
1377 struct sis_rxdesc *rxd;
1378 struct sis_txdesc *txd;
1379 bus_addr_t next;
1380 int error, i;
1381
1382 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1383 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1384 txd = &sc->sis_txdesc[i];
1385 txd->tx_m = NULL;
1386 if (i == SIS_TX_LIST_CNT - 1)
1387 next = SIS_TX_RING_ADDR(sc, 0);
1388 else
1389 next = SIS_TX_RING_ADDR(sc, i + 1);
1390 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1391 }
1392 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1393 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1395
1396 sc->sis_rx_cons = 0;
1397 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1398 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1399 rxd = &sc->sis_rxdesc[i];
1400 rxd->rx_desc = &sc->sis_rx_list[i];
1401 if (i == SIS_RX_LIST_CNT - 1)
1402 next = SIS_RX_RING_ADDR(sc, 0);
1403 else
1404 next = SIS_RX_RING_ADDR(sc, i + 1);
1405 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1406 error = sis_newbuf(sc, rxd);
1407 if (error)
1408 return (error);
1409 }
1410 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1411 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1412
1413 return (0);
1414 }
1415
1416 /*
1417 * Initialize an RX descriptor and attach an MBUF cluster.
1418 */
1419 static int
1420 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1421 {
1422 struct mbuf *m;
1423 bus_dma_segment_t segs[1];
1424 bus_dmamap_t map;
1425 int nsegs;
1426
1427 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1428 if (m == NULL)
1429 return (ENOBUFS);
1430 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1431 #ifndef __NO_STRICT_ALIGNMENT
1432 m_adj(m, SIS_RX_BUF_ALIGN);
1433 #endif
1434
1435 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1436 segs, &nsegs, 0) != 0) {
1437 m_freem(m);
1438 return (ENOBUFS);
1439 }
1440 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1441
1442 if (rxd->rx_m != NULL) {
1443 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1444 BUS_DMASYNC_POSTREAD);
1445 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1446 }
1447 map = rxd->rx_dmamap;
1448 rxd->rx_dmamap = sc->sis_rx_sparemap;
1449 sc->sis_rx_sparemap = map;
1450 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1451 rxd->rx_m = m;
1452 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1453 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1454 return (0);
1455 }
1456
1457 static __inline void
1458 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1459 {
1460
1461 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1462 }
1463
1464 #ifndef __NO_STRICT_ALIGNMENT
1465 static __inline void
1466 sis_fixup_rx(struct mbuf *m)
1467 {
1468 uint16_t *src, *dst;
1469 int i;
1470
1471 src = mtod(m, uint16_t *);
1472 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1473
1474 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1475 *dst++ = *src++;
1476
1477 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1478 }
1479 #endif
1480
1481 /*
1482 * A frame has been uploaded: pass the resulting mbuf chain up to
1483 * the higher level protocols.
1484 */
1485 static int
1486 sis_rxeof(struct sis_softc *sc)
1487 {
1488 struct mbuf *m;
1489 struct ifnet *ifp;
1490 struct sis_rxdesc *rxd;
1491 struct sis_desc *cur_rx;
1492 int prog, rx_cons, rx_npkts = 0, total_len;
1493 uint32_t rxstat;
1494
1495 SIS_LOCK_ASSERT(sc);
1496
1497 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1498 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1499
1500 rx_cons = sc->sis_rx_cons;
1501 ifp = sc->sis_ifp;
1502
1503 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1504 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1505 #ifdef DEVICE_POLLING
1506 if (ifp->if_capenable & IFCAP_POLLING) {
1507 if (sc->rxcycles <= 0)
1508 break;
1509 sc->rxcycles--;
1510 }
1511 #endif
1512 cur_rx = &sc->sis_rx_list[rx_cons];
1513 rxstat = le32toh(cur_rx->sis_cmdsts);
1514 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1515 break;
1516 rxd = &sc->sis_rxdesc[rx_cons];
1517
1518 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1519 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1520 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1521 ETHER_CRC_LEN))
1522 rxstat &= ~SIS_RXSTAT_GIANT;
1523 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1524 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1525 if (rxstat & SIS_RXSTAT_COLL)
1526 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1527 sis_discard_rxbuf(rxd);
1528 continue;
1529 }
1530
1531 /* Add a new receive buffer to the ring. */
1532 m = rxd->rx_m;
1533 if (sis_newbuf(sc, rxd) != 0) {
1534 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1535 sis_discard_rxbuf(rxd);
1536 continue;
1537 }
1538
1539 /* No errors; receive the packet. */
1540 m->m_pkthdr.len = m->m_len = total_len;
1541 #ifndef __NO_STRICT_ALIGNMENT
1542 /*
1543 * On architectures without alignment problems we try to
1544 * allocate a new buffer for the receive ring, and pass up
1545 * the one where the packet is already, saving the expensive
1546 * copy operation.
1547 */
1548 sis_fixup_rx(m);
1549 #endif
1550 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1551 m->m_pkthdr.rcvif = ifp;
1552
1553 SIS_UNLOCK(sc);
1554 (*ifp->if_input)(ifp, m);
1555 SIS_LOCK(sc);
1556 rx_npkts++;
1557 }
1558
1559 if (prog > 0) {
1560 sc->sis_rx_cons = rx_cons;
1561 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1563 }
1564
1565 return (rx_npkts);
1566 }
1567
1568 /*
1569 * A frame was downloaded to the chip. It's safe for us to clean up
1570 * the list buffers.
1571 */
1572
1573 static void
1574 sis_txeof(struct sis_softc *sc)
1575 {
1576 struct ifnet *ifp;
1577 struct sis_desc *cur_tx;
1578 struct sis_txdesc *txd;
1579 uint32_t cons, txstat;
1580
1581 SIS_LOCK_ASSERT(sc);
1582
1583 cons = sc->sis_tx_cons;
1584 if (cons == sc->sis_tx_prod)
1585 return;
1586
1587 ifp = sc->sis_ifp;
1588 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1589 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1590
1591 /*
1592 * Go through our tx list and free mbufs for those
1593 * frames that have been transmitted.
1594 */
1595 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1596 cur_tx = &sc->sis_tx_list[cons];
1597 txstat = le32toh(cur_tx->sis_cmdsts);
1598 if ((txstat & SIS_CMDSTS_OWN) != 0)
1599 break;
1600 txd = &sc->sis_txdesc[cons];
1601 if (txd->tx_m != NULL) {
1602 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1603 BUS_DMASYNC_POSTWRITE);
1604 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1605 m_freem(txd->tx_m);
1606 txd->tx_m = NULL;
1607 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1608 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1609 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1610 (txstat & SIS_TXSTAT_COLLCNT) >> 16);
1611 } else {
1612 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1613 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1614 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1615 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1616 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1617 }
1618 }
1619 sc->sis_tx_cnt--;
1620 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1621 }
1622 sc->sis_tx_cons = cons;
1623 if (sc->sis_tx_cnt == 0)
1624 sc->sis_watchdog_timer = 0;
1625 }
1626
1627 static void
1628 sis_tick(void *xsc)
1629 {
1630 struct sis_softc *sc;
1631 struct mii_data *mii;
1632
1633 sc = xsc;
1634 SIS_LOCK_ASSERT(sc);
1635
1636 mii = device_get_softc(sc->sis_miibus);
1637 mii_tick(mii);
1638 sis_watchdog(sc);
1639 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1640 sis_miibus_statchg(sc->sis_dev);
1641 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1642 }
1643
1644 #ifdef DEVICE_POLLING
1645 static poll_handler_t sis_poll;
1646
1647 static int
1648 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1649 {
1650 struct sis_softc *sc = ifp->if_softc;
1651 int rx_npkts = 0;
1652
1653 SIS_LOCK(sc);
1654 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1655 SIS_UNLOCK(sc);
1656 return (rx_npkts);
1657 }
1658
1659 /*
1660 * On the sis, reading the status register also clears it.
1661 * So before returning to intr mode we must make sure that all
1662 * possible pending sources of interrupts have been served.
1663 * In practice this means run to completion the *eof routines,
1664 * and then call the interrupt routine
1665 */
1666 sc->rxcycles = count;
1667 rx_npkts = sis_rxeof(sc);
1668 sis_txeof(sc);
1669 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1670 sis_startl(ifp);
1671
1672 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1673 uint32_t status;
1674
1675 /* Reading the ISR register clears all interrupts. */
1676 status = CSR_READ_4(sc, SIS_ISR);
1677
1678 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1679 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1680
1681 if (status & (SIS_ISR_RX_IDLE))
1682 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1683
1684 if (status & SIS_ISR_SYSERR) {
1685 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1686 sis_initl(sc);
1687 }
1688 }
1689
1690 SIS_UNLOCK(sc);
1691 return (rx_npkts);
1692 }
1693 #endif /* DEVICE_POLLING */
1694
1695 static void
1696 sis_intr(void *arg)
1697 {
1698 struct sis_softc *sc;
1699 struct ifnet *ifp;
1700 uint32_t status;
1701
1702 sc = arg;
1703 ifp = sc->sis_ifp;
1704
1705 SIS_LOCK(sc);
1706 #ifdef DEVICE_POLLING
1707 if (ifp->if_capenable & IFCAP_POLLING) {
1708 SIS_UNLOCK(sc);
1709 return;
1710 }
1711 #endif
1712
1713 /* Reading the ISR register clears all interrupts. */
1714 status = CSR_READ_4(sc, SIS_ISR);
1715 if ((status & SIS_INTRS) == 0) {
1716 /* Not ours. */
1717 SIS_UNLOCK(sc);
1718 return;
1719 }
1720
1721 /* Disable interrupts. */
1722 CSR_WRITE_4(sc, SIS_IER, 0);
1723
1724 for (;(status & SIS_INTRS) != 0;) {
1725 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1726 break;
1727 if (status &
1728 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1729 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1730 sis_txeof(sc);
1731
1732 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1733 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1734 sis_rxeof(sc);
1735
1736 if (status & SIS_ISR_RX_OFLOW)
1737 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1738
1739 if (status & (SIS_ISR_RX_IDLE))
1740 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1741
1742 if (status & SIS_ISR_SYSERR) {
1743 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1744 sis_initl(sc);
1745 SIS_UNLOCK(sc);
1746 return;
1747 }
1748 status = CSR_READ_4(sc, SIS_ISR);
1749 }
1750
1751 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1752 /* Re-enable interrupts. */
1753 CSR_WRITE_4(sc, SIS_IER, 1);
1754
1755 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1756 sis_startl(ifp);
1757 }
1758
1759 SIS_UNLOCK(sc);
1760 }
1761
1762 /*
1763 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1764 * pointers to the fragment pointers.
1765 */
1766 static int
1767 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1768 {
1769 struct mbuf *m;
1770 struct sis_txdesc *txd;
1771 struct sis_desc *f;
1772 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1773 bus_dmamap_t map;
1774 int error, i, frag, nsegs, prod;
1775 int padlen;
1776
1777 prod = sc->sis_tx_prod;
1778 txd = &sc->sis_txdesc[prod];
1779 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1780 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1781 m = *m_head;
1782 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1783 if (M_WRITABLE(m) == 0) {
1784 /* Get a writable copy. */
1785 m = m_dup(*m_head, M_NOWAIT);
1786 m_freem(*m_head);
1787 if (m == NULL) {
1788 *m_head = NULL;
1789 return (ENOBUFS);
1790 }
1791 *m_head = m;
1792 }
1793 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1794 m = m_defrag(m, M_NOWAIT);
1795 if (m == NULL) {
1796 m_freem(*m_head);
1797 *m_head = NULL;
1798 return (ENOBUFS);
1799 }
1800 }
1801 /*
1802 * Manually pad short frames, and zero the pad space
1803 * to avoid leaking data.
1804 */
1805 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1806 m->m_pkthdr.len += padlen;
1807 m->m_len = m->m_pkthdr.len;
1808 *m_head = m;
1809 }
1810 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1811 *m_head, segs, &nsegs, 0);
1812 if (error == EFBIG) {
1813 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1814 if (m == NULL) {
1815 m_freem(*m_head);
1816 *m_head = NULL;
1817 return (ENOBUFS);
1818 }
1819 *m_head = m;
1820 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1821 *m_head, segs, &nsegs, 0);
1822 if (error != 0) {
1823 m_freem(*m_head);
1824 *m_head = NULL;
1825 return (error);
1826 }
1827 } else if (error != 0)
1828 return (error);
1829
1830 /* Check for descriptor overruns. */
1831 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1832 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1833 return (ENOBUFS);
1834 }
1835
1836 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1837
1838 frag = prod;
1839 for (i = 0; i < nsegs; i++) {
1840 f = &sc->sis_tx_list[prod];
1841 if (i == 0)
1842 f->sis_cmdsts = htole32(segs[i].ds_len |
1843 SIS_CMDSTS_MORE);
1844 else
1845 f->sis_cmdsts = htole32(segs[i].ds_len |
1846 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1847 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1848 SIS_INC(prod, SIS_TX_LIST_CNT);
1849 sc->sis_tx_cnt++;
1850 }
1851
1852 /* Update producer index. */
1853 sc->sis_tx_prod = prod;
1854
1855 /* Remove MORE flag on the last descriptor. */
1856 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1857 f = &sc->sis_tx_list[prod];
1858 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1859
1860 /* Lastly transfer ownership of packet to the controller. */
1861 f = &sc->sis_tx_list[frag];
1862 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1863
1864 /* Swap the last and the first dmamaps. */
1865 map = txd->tx_dmamap;
1866 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1867 sc->sis_txdesc[prod].tx_dmamap = map;
1868 sc->sis_txdesc[prod].tx_m = *m_head;
1869
1870 return (0);
1871 }
1872
1873 static void
1874 sis_start(struct ifnet *ifp)
1875 {
1876 struct sis_softc *sc;
1877
1878 sc = ifp->if_softc;
1879 SIS_LOCK(sc);
1880 sis_startl(ifp);
1881 SIS_UNLOCK(sc);
1882 }
1883
1884 static void
1885 sis_startl(struct ifnet *ifp)
1886 {
1887 struct sis_softc *sc;
1888 struct mbuf *m_head;
1889 int queued;
1890
1891 sc = ifp->if_softc;
1892
1893 SIS_LOCK_ASSERT(sc);
1894
1895 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1896 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1897 return;
1898
1899 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1900 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1901 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1902 if (m_head == NULL)
1903 break;
1904
1905 if (sis_encap(sc, &m_head) != 0) {
1906 if (m_head == NULL)
1907 break;
1908 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1909 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1910 break;
1911 }
1912
1913 queued++;
1914
1915 /*
1916 * If there's a BPF listener, bounce a copy of this frame
1917 * to him.
1918 */
1919 BPF_MTAP(ifp, m_head);
1920 }
1921
1922 if (queued) {
1923 /* Transmit */
1924 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1926 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1927
1928 /*
1929 * Set a timeout in case the chip goes out to lunch.
1930 */
1931 sc->sis_watchdog_timer = 5;
1932 }
1933 }
1934
1935 static void
1936 sis_init(void *xsc)
1937 {
1938 struct sis_softc *sc = xsc;
1939
1940 SIS_LOCK(sc);
1941 sis_initl(sc);
1942 SIS_UNLOCK(sc);
1943 }
1944
1945 static void
1946 sis_initl(struct sis_softc *sc)
1947 {
1948 struct ifnet *ifp = sc->sis_ifp;
1949 struct mii_data *mii;
1950 uint8_t *eaddr;
1951
1952 SIS_LOCK_ASSERT(sc);
1953
1954 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1955 return;
1956
1957 /*
1958 * Cancel pending I/O and free all RX/TX buffers.
1959 */
1960 sis_stop(sc);
1961 /*
1962 * Reset the chip to a known state.
1963 */
1964 sis_reset(sc);
1965 #ifdef notyet
1966 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1967 /*
1968 * Configure 400usec of interrupt holdoff. This is based
1969 * on emperical tests on a Soekris 4801.
1970 */
1971 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1972 }
1973 #endif
1974
1975 mii = device_get_softc(sc->sis_miibus);
1976
1977 /* Set MAC address */
1978 eaddr = IF_LLADDR(sc->sis_ifp);
1979 if (sc->sis_type == SIS_TYPE_83815) {
1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1982 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1983 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1984 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1985 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1986 } else {
1987 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1988 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1989 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1990 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1991 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1992 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1993 }
1994
1995 /* Init circular TX/RX lists. */
1996 if (sis_ring_init(sc) != 0) {
1997 device_printf(sc->sis_dev,
1998 "initialization failed: no memory for rx buffers\n");
1999 sis_stop(sc);
2000 return;
2001 }
2002
2003 if (sc->sis_type == SIS_TYPE_83815) {
2004 if (sc->sis_manual_pad != 0)
2005 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
2006 else
2007 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2008 }
2009
2010 /*
2011 * Short Cable Receive Errors (MP21.E)
2012 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2013 * recommends the following register settings "for optimum
2014 * performance." for rev 15C. Set this also for 15D parts as
2015 * they require it in practice.
2016 */
2017 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2018 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2019 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2020 /* set val for c2 */
2021 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2022 /* load/kill c2 */
2023 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2024 /* rais SD off, from 4 to c */
2025 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2026 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2027 }
2028
2029 sis_rxfilter(sc);
2030
2031 /*
2032 * Load the address of the RX and TX lists.
2033 */
2034 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2035 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2036
2037 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2038 * the PCI bus. When this bit is set, the Max DMA Burst Size
2039 * for TX/RX DMA should be no larger than 16 double words.
2040 */
2041 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2042 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2043 } else {
2044 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2045 }
2046
2047 /* Accept Long Packets for VLAN support */
2048 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2049
2050 /*
2051 * Assume 100Mbps link, actual MAC configuration is done
2052 * after getting a valid link.
2053 */
2054 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2055
2056 /*
2057 * Enable interrupts.
2058 */
2059 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2060 #ifdef DEVICE_POLLING
2061 /*
2062 * ... only enable interrupts if we are not polling, make sure
2063 * they are off otherwise.
2064 */
2065 if (ifp->if_capenable & IFCAP_POLLING)
2066 CSR_WRITE_4(sc, SIS_IER, 0);
2067 else
2068 #endif
2069 CSR_WRITE_4(sc, SIS_IER, 1);
2070
2071 /* Clear MAC disable. */
2072 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2073
2074 sc->sis_flags &= ~SIS_FLAG_LINK;
2075 mii_mediachg(mii);
2076
2077 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2078 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2079
2080 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2081 }
2082
2083 /*
2084 * Set media options.
2085 */
2086 static int
2087 sis_ifmedia_upd(struct ifnet *ifp)
2088 {
2089 struct sis_softc *sc;
2090 struct mii_data *mii;
2091 struct mii_softc *miisc;
2092 int error;
2093
2094 sc = ifp->if_softc;
2095
2096 SIS_LOCK(sc);
2097 mii = device_get_softc(sc->sis_miibus);
2098 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2099 PHY_RESET(miisc);
2100 error = mii_mediachg(mii);
2101 SIS_UNLOCK(sc);
2102
2103 return (error);
2104 }
2105
2106 /*
2107 * Report current media status.
2108 */
2109 static void
2110 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2111 {
2112 struct sis_softc *sc;
2113 struct mii_data *mii;
2114
2115 sc = ifp->if_softc;
2116
2117 SIS_LOCK(sc);
2118 mii = device_get_softc(sc->sis_miibus);
2119 mii_pollstat(mii);
2120 ifmr->ifm_active = mii->mii_media_active;
2121 ifmr->ifm_status = mii->mii_media_status;
2122 SIS_UNLOCK(sc);
2123 }
2124
2125 static int
2126 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2127 {
2128 struct sis_softc *sc = ifp->if_softc;
2129 struct ifreq *ifr = (struct ifreq *) data;
2130 struct mii_data *mii;
2131 int error = 0, mask;
2132
2133 switch (command) {
2134 case SIOCSIFFLAGS:
2135 SIS_LOCK(sc);
2136 if (ifp->if_flags & IFF_UP) {
2137 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2138 ((ifp->if_flags ^ sc->sis_if_flags) &
2139 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2140 sis_rxfilter(sc);
2141 else
2142 sis_initl(sc);
2143 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2144 sis_stop(sc);
2145 sc->sis_if_flags = ifp->if_flags;
2146 SIS_UNLOCK(sc);
2147 break;
2148 case SIOCADDMULTI:
2149 case SIOCDELMULTI:
2150 SIS_LOCK(sc);
2151 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2152 sis_rxfilter(sc);
2153 SIS_UNLOCK(sc);
2154 break;
2155 case SIOCGIFMEDIA:
2156 case SIOCSIFMEDIA:
2157 mii = device_get_softc(sc->sis_miibus);
2158 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2159 break;
2160 case SIOCSIFCAP:
2161 SIS_LOCK(sc);
2162 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2163 #ifdef DEVICE_POLLING
2164 if ((mask & IFCAP_POLLING) != 0 &&
2165 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2166 ifp->if_capenable ^= IFCAP_POLLING;
2167 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2168 error = ether_poll_register(sis_poll, ifp);
2169 if (error != 0) {
2170 SIS_UNLOCK(sc);
2171 break;
2172 }
2173 /* Disable interrupts. */
2174 CSR_WRITE_4(sc, SIS_IER, 0);
2175 } else {
2176 error = ether_poll_deregister(ifp);
2177 /* Enable interrupts. */
2178 CSR_WRITE_4(sc, SIS_IER, 1);
2179 }
2180 }
2181 #endif /* DEVICE_POLLING */
2182 if ((mask & IFCAP_WOL) != 0 &&
2183 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2184 if ((mask & IFCAP_WOL_UCAST) != 0)
2185 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2186 if ((mask & IFCAP_WOL_MCAST) != 0)
2187 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2188 if ((mask & IFCAP_WOL_MAGIC) != 0)
2189 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2190 }
2191 SIS_UNLOCK(sc);
2192 break;
2193 default:
2194 error = ether_ioctl(ifp, command, data);
2195 break;
2196 }
2197
2198 return (error);
2199 }
2200
2201 static void
2202 sis_watchdog(struct sis_softc *sc)
2203 {
2204
2205 SIS_LOCK_ASSERT(sc);
2206
2207 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2208 return;
2209
2210 device_printf(sc->sis_dev, "watchdog timeout\n");
2211 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
2212
2213 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2214 sis_initl(sc);
2215
2216 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2217 sis_startl(sc->sis_ifp);
2218 }
2219
2220 /*
2221 * Stop the adapter and free any mbufs allocated to the
2222 * RX and TX lists.
2223 */
2224 static void
2225 sis_stop(struct sis_softc *sc)
2226 {
2227 struct ifnet *ifp;
2228 struct sis_rxdesc *rxd;
2229 struct sis_txdesc *txd;
2230 int i;
2231
2232 SIS_LOCK_ASSERT(sc);
2233
2234 ifp = sc->sis_ifp;
2235 sc->sis_watchdog_timer = 0;
2236
2237 callout_stop(&sc->sis_stat_ch);
2238
2239 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2240 CSR_WRITE_4(sc, SIS_IER, 0);
2241 CSR_WRITE_4(sc, SIS_IMR, 0);
2242 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2243 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2244 DELAY(1000);
2245 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2246 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2247
2248 sc->sis_flags &= ~SIS_FLAG_LINK;
2249
2250 /*
2251 * Free data in the RX lists.
2252 */
2253 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2254 rxd = &sc->sis_rxdesc[i];
2255 if (rxd->rx_m != NULL) {
2256 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2257 BUS_DMASYNC_POSTREAD);
2258 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2259 m_freem(rxd->rx_m);
2260 rxd->rx_m = NULL;
2261 }
2262 }
2263
2264 /*
2265 * Free the TX list buffers.
2266 */
2267 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2268 txd = &sc->sis_txdesc[i];
2269 if (txd->tx_m != NULL) {
2270 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2271 BUS_DMASYNC_POSTWRITE);
2272 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2273 m_freem(txd->tx_m);
2274 txd->tx_m = NULL;
2275 }
2276 }
2277 }
2278
2279 /*
2280 * Stop all chip I/O so that the kernel's probe routines don't
2281 * get confused by errant DMAs when rebooting.
2282 */
2283 static int
2284 sis_shutdown(device_t dev)
2285 {
2286
2287 return (sis_suspend(dev));
2288 }
2289
2290 static int
2291 sis_suspend(device_t dev)
2292 {
2293 struct sis_softc *sc;
2294
2295 sc = device_get_softc(dev);
2296 SIS_LOCK(sc);
2297 sis_stop(sc);
2298 sis_wol(sc);
2299 SIS_UNLOCK(sc);
2300 return (0);
2301 }
2302
2303 static int
2304 sis_resume(device_t dev)
2305 {
2306 struct sis_softc *sc;
2307 struct ifnet *ifp;
2308
2309 sc = device_get_softc(dev);
2310 SIS_LOCK(sc);
2311 ifp = sc->sis_ifp;
2312 if ((ifp->if_flags & IFF_UP) != 0) {
2313 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2314 sis_initl(sc);
2315 }
2316 SIS_UNLOCK(sc);
2317 return (0);
2318 }
2319
2320 static void
2321 sis_wol(struct sis_softc *sc)
2322 {
2323 struct ifnet *ifp;
2324 uint32_t val;
2325 uint16_t pmstat;
2326 int pmc;
2327
2328 ifp = sc->sis_ifp;
2329 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2330 return;
2331
2332 if (sc->sis_type == SIS_TYPE_83815) {
2333 /* Reset RXDP. */
2334 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2335
2336 /* Configure WOL events. */
2337 CSR_READ_4(sc, NS_WCSR);
2338 val = 0;
2339 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2340 val |= NS_WCSR_WAKE_UCAST;
2341 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2342 val |= NS_WCSR_WAKE_MCAST;
2343 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2344 val |= NS_WCSR_WAKE_MAGIC;
2345 CSR_WRITE_4(sc, NS_WCSR, val);
2346 /* Enable PME and clear PMESTS. */
2347 val = CSR_READ_4(sc, NS_CLKRUN);
2348 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2349 CSR_WRITE_4(sc, NS_CLKRUN, val);
2350 /* Enable silent RX mode. */
2351 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2352 } else {
2353 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2354 return;
2355 val = 0;
2356 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2357 val |= SIS_PWRMAN_WOL_MAGIC;
2358 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2359 /* Request PME. */
2360 pmstat = pci_read_config(sc->sis_dev,
2361 pmc + PCIR_POWER_STATUS, 2);
2362 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2363 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2364 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2365 pci_write_config(sc->sis_dev,
2366 pmc + PCIR_POWER_STATUS, pmstat, 2);
2367 }
2368 }
2369
2370 static void
2371 sis_add_sysctls(struct sis_softc *sc)
2372 {
2373 struct sysctl_ctx_list *ctx;
2374 struct sysctl_oid_list *children;
2375 int unit;
2376
2377 ctx = device_get_sysctl_ctx(sc->sis_dev);
2378 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2379
2380 unit = device_get_unit(sc->sis_dev);
2381 /*
2382 * Unlike most other controllers, NS DP83815/DP83816 controllers
2383 * seem to pad with 0xFF when it encounter short frames. According
2384 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2385 * on will have driver pad manully but it's disabled by default
2386 * because it will consume extra CPU cycles for short frames.
2387 */
2388 sc->sis_manual_pad = 0;
2389 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2390 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
2391 }
2392
2393 static device_method_t sis_methods[] = {
2394 /* Device interface */
2395 DEVMETHOD(device_probe, sis_probe),
2396 DEVMETHOD(device_attach, sis_attach),
2397 DEVMETHOD(device_detach, sis_detach),
2398 DEVMETHOD(device_shutdown, sis_shutdown),
2399 DEVMETHOD(device_suspend, sis_suspend),
2400 DEVMETHOD(device_resume, sis_resume),
2401
2402 /* MII interface */
2403 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2404 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2405 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2406
2407 DEVMETHOD_END
2408 };
2409
2410 static driver_t sis_driver = {
2411 "sis",
2412 sis_methods,
2413 sizeof(struct sis_softc)
2414 };
2415
2416 static devclass_t sis_devclass;
2417
2418 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2419 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
Cache object: c8e0a5a099e672bf69de59b39f0f1adf
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