Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sk/if_skreg.h
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1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD$ 37 */ 38 39 /*- 40 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 41 * 42 * Permission to use, copy, modify, and distribute this software for any 43 * purpose with or without fee is hereby granted, provided that the above 44 * copyright notice and this permission notice appear in all copies. 45 * 46 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 47 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 48 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 49 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 50 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 51 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 52 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 53 */ 54 55 /* Values to keep the different chip revisions apart (SK_CHIPVER). */ 56 #define SK_GENESIS 0x0A 57 #define SK_YUKON 0xB0 58 #define SK_YUKON_LITE 0xB1 59 #define SK_YUKON_LP 0xB2 60 #define SK_YUKON_FAMILY(x) ((x) & 0xB0) 61 62 /* Known revisions in SK_CONFIG. */ 63 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 64 #define SK_YUKON_LITE_REV_A1 0x3 65 #define SK_YUKON_LITE_REV_A3 0x7 66 67 /* 68 * SysKonnect PCI vendor ID 69 */ 70 #define VENDORID_SK 0x1148 71 72 /* 73 * Marvell PCI vendor ID 74 */ 75 #define VENDORID_MARVELL 0x11AB 76 77 /* 78 * SK-NET gigabit ethernet device IDs 79 */ 80 #define DEVICEID_SK_V1 0x4300 81 #define DEVICEID_SK_V2 0x4320 82 83 /* 84 * Belkin F5D5005 85 */ 86 #define DEVICEID_BELKIN_5005 0x5005 87 88 /* 89 * 3Com PCI vendor ID 90 */ 91 #define VENDORID_3COM 0x10b7 92 93 /* 94 * 3Com gigabit ethernet device ID 95 */ 96 #define DEVICEID_3COM_3C940 0x1700 97 98 /* 99 * Linksys PCI vendor ID 100 */ 101 #define VENDORID_LINKSYS 0x1737 102 103 /* 104 * Linksys gigabit ethernet device ID 105 */ 106 #define DEVICEID_LINKSYS_EG1032 0x1032 107 108 /* 109 * Linksys gigabit ethernet rev 2 sub-device ID 110 */ 111 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 112 113 /* 114 * D-Link PCI vendor ID 115 */ 116 #define VENDORID_DLINK 0x1186 117 118 /* 119 * D-Link gigabit ethernet device ID 120 */ 121 #define DEVICEID_DLINK_DGE530T_A1 0x4c00 122 #define DEVICEID_DLINK_DGE530T_B1 0x4b01 123 124 /* 125 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 126 * but internally it has a 16K register space. This 16K space is 127 * divided into 128-byte blocks. The first 128 bytes of the I/O 128 * window represent the first block, which is permanently mapped 129 * at the start of the window. The other 127 blocks can be mapped 130 * to the second 128 bytes of the I/O window by setting the desired 131 * block value in the RAP register in block 0. Not all of the 127 132 * blocks are actually used. Most registers are 32 bits wide, but 133 * there are a few 16-bit and 8-bit ones as well. 134 */ 135 136 /* Start of remappable register window. */ 137 #define SK_WIN_BASE 0x0080 138 139 /* Size of a window */ 140 #define SK_WIN_LEN 0x80 141 142 #define SK_WIN_MASK 0x3F80 143 #define SK_REG_MASK 0x7F 144 145 /* Compute the window of a given register (for the RAP register) */ 146 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 147 148 /* Compute the relative offset of a register within the window */ 149 #define SK_REG(reg) ((reg) & SK_REG_MASK) 150 151 #define SK_PORT_A 0 152 #define SK_PORT_B 1 153 154 /* 155 * Compute offset of port-specific register. Since there are two 156 * ports, there are two of some GEnesis modules (e.g. two sets of 157 * DMA queues, two sets of FIFO control registers, etc...). Normally, 158 * the block for port 0 is at offset 0x0 and the block for port 1 is 159 * at offset 0x80 (i.e. the next page over). However for the transmit 160 * BMUs and RAMbuffers, there are two blocks for each port: one for 161 * the sync transmit queue and one for the async queue (which we don't 162 * use). However instead of ordering them like this: 163 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 164 * SysKonnect has instead ordered them like this: 165 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 166 * This means that when referencing the TX BMU and RAMbuffer registers, 167 * we have to double the block offset (0x80 * 2) in order to reach the 168 * second queue. This prevents us from using the same formula 169 * (sk_port * 0x80) to compute the offsets for all of the port-specific 170 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 171 * The simplest thing is to provide an extra argument to these macros: 172 * the 'skip' parameter. The 'skip' value is the number of extra pages 173 * for skip when computing the port0/port1 offsets. For most registers, 174 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 175 */ 176 #define SK_IF_READ_4(sc_if, skip, reg) \ 177 sk_win_read_4(sc_if->sk_softc, reg + \ 178 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 179 #define SK_IF_READ_2(sc_if, skip, reg) \ 180 sk_win_read_2(sc_if->sk_softc, reg + \ 181 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 182 #define SK_IF_READ_1(sc_if, skip, reg) \ 183 sk_win_read_1(sc_if->sk_softc, reg + \ 184 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 185 186 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 187 sk_win_write_4(sc_if->sk_softc, \ 188 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 189 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 190 sk_win_write_2(sc_if->sk_softc, \ 191 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 192 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 193 sk_win_write_1(sc_if->sk_softc, \ 194 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 195 196 /* Block 0 registers, permanently mapped at iobase. */ 197 #define SK_RAP 0x0000 198 #define SK_CSR 0x0004 199 #define SK_LED 0x0006 200 #define SK_ISR 0x0008 /* interrupt source */ 201 #define SK_IMR 0x000C /* interrupt mask */ 202 #define SK_IESR 0x0010 /* interrupt hardware error source */ 203 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 204 #define SK_ISSR 0x0018 /* special interrupt source */ 205 #define SK_XM_IMR0 0x0020 206 #define SK_XM_ISR0 0x0028 207 #define SK_XM_PHYADDR0 0x0030 208 #define SK_XM_PHYDATA0 0x0034 209 #define SK_XM_IMR1 0x0040 210 #define SK_XM_ISR1 0x0048 211 #define SK_XM_PHYADDR1 0x0050 212 #define SK_XM_PHYDATA1 0x0054 213 #define SK_BMU_RX_CSR0 0x0060 214 #define SK_BMU_RX_CSR1 0x0064 215 #define SK_BMU_TXS_CSR0 0x0068 216 #define SK_BMU_TXA_CSR0 0x006C 217 #define SK_BMU_TXS_CSR1 0x0070 218 #define SK_BMU_TXA_CSR1 0x0074 219 220 /* SK_CSR register */ 221 #define SK_CSR_SW_RESET 0x0001 222 #define SK_CSR_SW_UNRESET 0x0002 223 #define SK_CSR_MASTER_RESET 0x0004 224 #define SK_CSR_MASTER_UNRESET 0x0008 225 #define SK_CSR_MASTER_STOP 0x0010 226 #define SK_CSR_MASTER_DONE 0x0020 227 #define SK_CSR_SW_IRQ_CLEAR 0x0040 228 #define SK_CSR_SW_IRQ_SET 0x0080 229 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 230 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 231 232 /* SK_LED register */ 233 #define SK_LED_GREEN_OFF 0x01 234 #define SK_LED_GREEN_ON 0x02 235 236 /* SK_ISR register */ 237 #define SK_ISR_TX2_AS_CHECK 0x00000001 238 #define SK_ISR_TX2_AS_EOF 0x00000002 239 #define SK_ISR_TX2_AS_EOB 0x00000004 240 #define SK_ISR_TX2_S_CHECK 0x00000008 241 #define SK_ISR_TX2_S_EOF 0x00000010 242 #define SK_ISR_TX2_S_EOB 0x00000020 243 #define SK_ISR_TX1_AS_CHECK 0x00000040 244 #define SK_ISR_TX1_AS_EOF 0x00000080 245 #define SK_ISR_TX1_AS_EOB 0x00000100 246 #define SK_ISR_TX1_S_CHECK 0x00000200 247 #define SK_ISR_TX1_S_EOF 0x00000400 248 #define SK_ISR_TX1_S_EOB 0x00000800 249 #define SK_ISR_RX2_CHECK 0x00001000 250 #define SK_ISR_RX2_EOF 0x00002000 251 #define SK_ISR_RX2_EOB 0x00004000 252 #define SK_ISR_RX1_CHECK 0x00008000 253 #define SK_ISR_RX1_EOF 0x00010000 254 #define SK_ISR_RX1_EOB 0x00020000 255 #define SK_ISR_LINK2_OFLOW 0x00040000 256 #define SK_ISR_MAC2 0x00080000 257 #define SK_ISR_LINK1_OFLOW 0x00100000 258 #define SK_ISR_MAC1 0x00200000 259 #define SK_ISR_TIMER 0x00400000 260 #define SK_ISR_EXTERNAL_REG 0x00800000 261 #define SK_ISR_SW 0x01000000 262 #define SK_ISR_I2C_RDY 0x02000000 263 #define SK_ISR_TX2_TIMEO 0x04000000 264 #define SK_ISR_TX1_TIMEO 0x08000000 265 #define SK_ISR_RX2_TIMEO 0x10000000 266 #define SK_ISR_RX1_TIMEO 0x20000000 267 #define SK_ISR_RSVD 0x40000000 268 #define SK_ISR_HWERR 0x80000000 269 270 /* SK_IMR register */ 271 #define SK_IMR_TX2_AS_CHECK 0x00000001 272 #define SK_IMR_TX2_AS_EOF 0x00000002 273 #define SK_IMR_TX2_AS_EOB 0x00000004 274 #define SK_IMR_TX2_S_CHECK 0x00000008 275 #define SK_IMR_TX2_S_EOF 0x00000010 276 #define SK_IMR_TX2_S_EOB 0x00000020 277 #define SK_IMR_TX1_AS_CHECK 0x00000040 278 #define SK_IMR_TX1_AS_EOF 0x00000080 279 #define SK_IMR_TX1_AS_EOB 0x00000100 280 #define SK_IMR_TX1_S_CHECK 0x00000200 281 #define SK_IMR_TX1_S_EOF 0x00000400 282 #define SK_IMR_TX1_S_EOB 0x00000800 283 #define SK_IMR_RX2_CHECK 0x00001000 284 #define SK_IMR_RX2_EOF 0x00002000 285 #define SK_IMR_RX2_EOB 0x00004000 286 #define SK_IMR_RX1_CHECK 0x00008000 287 #define SK_IMR_RX1_EOF 0x00010000 288 #define SK_IMR_RX1_EOB 0x00020000 289 #define SK_IMR_LINK2_OFLOW 0x00040000 290 #define SK_IMR_MAC2 0x00080000 291 #define SK_IMR_LINK1_OFLOW 0x00100000 292 #define SK_IMR_MAC1 0x00200000 293 #define SK_IMR_TIMER 0x00400000 294 #define SK_IMR_EXTERNAL_REG 0x00800000 295 #define SK_IMR_SW 0x01000000 296 #define SK_IMR_I2C_RDY 0x02000000 297 #define SK_IMR_TX2_TIMEO 0x04000000 298 #define SK_IMR_TX1_TIMEO 0x08000000 299 #define SK_IMR_RX2_TIMEO 0x10000000 300 #define SK_IMR_RX1_TIMEO 0x20000000 301 #define SK_IMR_RSVD 0x40000000 302 #define SK_IMR_HWERR 0x80000000 303 304 #define SK_INTRS1 \ 305 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 306 307 #define SK_INTRS2 \ 308 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 309 310 /* SK_IESR register */ 311 #define SK_IESR_PAR_RX2 0x00000001 312 #define SK_IESR_PAR_RX1 0x00000002 313 #define SK_IESR_PAR_MAC2 0x00000004 314 #define SK_IESR_PAR_MAC1 0x00000008 315 #define SK_IESR_PAR_WR_RAM 0x00000010 316 #define SK_IESR_PAR_RD_RAM 0x00000020 317 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 318 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 319 #define SK_IESR_NO_STS_MAC2 0x00000100 320 #define SK_IESR_NO_STS_MAC1 0x00000200 321 #define SK_IESR_IRQ_STS 0x00000400 322 #define SK_IESR_MASTERERR 0x00000800 323 324 /* SK_IEMR register */ 325 #define SK_IEMR_PAR_RX2 0x00000001 326 #define SK_IEMR_PAR_RX1 0x00000002 327 #define SK_IEMR_PAR_MAC2 0x00000004 328 #define SK_IEMR_PAR_MAC1 0x00000008 329 #define SK_IEMR_PAR_WR_RAM 0x00000010 330 #define SK_IEMR_PAR_RD_RAM 0x00000020 331 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 332 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 333 #define SK_IEMR_NO_STS_MAC2 0x00000100 334 #define SK_IEMR_NO_STS_MAC1 0x00000200 335 #define SK_IEMR_IRQ_STS 0x00000400 336 #define SK_IEMR_MASTERERR 0x00000800 337 338 /* Block 2 */ 339 #define SK_MAC0_0 0x0100 340 #define SK_MAC0_1 0x0104 341 #define SK_MAC1_0 0x0108 342 #define SK_MAC1_1 0x010C 343 #define SK_MAC2_0 0x0110 344 #define SK_MAC2_1 0x0114 345 #define SK_CONNTYPE 0x0118 346 #define SK_PMDTYPE 0x0119 347 #define SK_CONFIG 0x011A 348 #define SK_CHIPVER 0x011B 349 #define SK_EPROM0 0x011C 350 #define SK_EPROM1 0x011D /* yukon/genesis */ 351 #define SK_EPROM2 0x011E /* yukon/genesis */ 352 #define SK_EPROM3 0x011F 353 #define SK_EP_ADDR 0x0120 354 #define SK_EP_DATA 0x0124 355 #define SK_EP_LOADCTL 0x0128 356 #define SK_EP_LOADTST 0x0129 357 #define SK_TIMERINIT 0x0130 358 #define SK_TIMER 0x0134 359 #define SK_TIMERCTL 0x0138 360 #define SK_TIMERTST 0x0139 361 #define SK_IMTIMERINIT 0x0140 362 #define SK_IMTIMER 0x0144 363 #define SK_IMTIMERCTL 0x0148 364 #define SK_IMTIMERTST 0x0149 365 #define SK_IMMR 0x014C 366 #define SK_IHWEMR 0x0150 367 #define SK_TESTCTL1 0x0158 368 #define SK_TESTCTL2 0x0159 369 #define SK_GPIO 0x015C 370 #define SK_I2CHWCTL 0x0160 371 #define SK_I2CHWDATA 0x0164 372 #define SK_I2CHWIRQ 0x0168 373 #define SK_I2CSW 0x016C 374 #define SK_BLNKINIT 0x0170 375 #define SK_BLNKCOUNT 0x0174 376 #define SK_BLNKCTL 0x0178 377 #define SK_BLNKSTS 0x0179 378 #define SK_BLNKTST 0x017A 379 380 #define SK_IMCTL_STOP 0x02 381 #define SK_IMCTL_START 0x04 382 383 #define SK_IMTIMER_TICKS_GENESIS 53 384 #define SK_IMTIMER_TICKS_YUKON 78 385 #define SK_IM_USECS(x, t) ((x) * (t)) 386 387 #define SK_IM_MIN 10 388 #define SK_IM_DEFAULT 100 389 #define SK_IM_MAX 10000 390 391 /* 392 * The SK_EPROM0 register contains a byte that describes the 393 * amount of SRAM mounted on the NIC. The value also tells if 394 * the chips are 64K or 128K. This affects the RAMbuffer address 395 * offset that we need to use. 396 */ 397 #define SK_RAMSIZE_512K_64 0x1 398 #define SK_RAMSIZE_1024K_128 0x2 399 #define SK_RAMSIZE_1024K_64 0x3 400 #define SK_RAMSIZE_2048K_128 0x4 401 402 #define SK_RBOFF_0 0x0 403 #define SK_RBOFF_80000 0x80000 404 405 /* 406 * SK_EEPROM1 contains the PHY type, which may be XMAC for 407 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 408 * PHY. 409 */ 410 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 411 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 412 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 413 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 414 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 415 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 416 417 /* 418 * PHY addresses. 419 */ 420 #define SK_PHYADDR_XMAC 0x0 421 #define SK_PHYADDR_BCOM 0x1 422 #define SK_PHYADDR_LONE 0x3 423 #define SK_PHYADDR_NAT 0x0 424 #define SK_PHYADDR_MARV 0x0 425 426 #define SK_CONFIG_SINGLEMAC 0x01 427 #define SK_CONFIG_DIS_DSL_CLK 0x02 428 429 #define SK_PMD_1000BASELX 0x4C 430 #define SK_PMD_1000BASESX 0x53 431 #define SK_PMD_1000BASECX 0x43 432 #define SK_PMD_1000BASETX 0x54 433 434 /* GPIO bits */ 435 #define SK_GPIO_DAT0 0x00000001 436 #define SK_GPIO_DAT1 0x00000002 437 #define SK_GPIO_DAT2 0x00000004 438 #define SK_GPIO_DAT3 0x00000008 439 #define SK_GPIO_DAT4 0x00000010 440 #define SK_GPIO_DAT5 0x00000020 441 #define SK_GPIO_DAT6 0x00000040 442 #define SK_GPIO_DAT7 0x00000080 443 #define SK_GPIO_DAT8 0x00000100 444 #define SK_GPIO_DAT9 0x00000200 445 #define SK_GPIO_DIR0 0x00010000 446 #define SK_GPIO_DIR1 0x00020000 447 #define SK_GPIO_DIR2 0x00040000 448 #define SK_GPIO_DIR3 0x00080000 449 #define SK_GPIO_DIR4 0x00100000 450 #define SK_GPIO_DIR5 0x00200000 451 #define SK_GPIO_DIR6 0x00400000 452 #define SK_GPIO_DIR7 0x00800000 453 #define SK_GPIO_DIR8 0x01000000 454 #define SK_GPIO_DIR9 0x02000000 455 456 /* Block 3 Ram interface and MAC arbiter registers */ 457 #define SK_RAMADDR 0x0180 458 #define SK_RAMDATA0 0x0184 459 #define SK_RAMDATA1 0x0188 460 #define SK_TO0 0x0190 461 #define SK_TO1 0x0191 462 #define SK_TO2 0x0192 463 #define SK_TO3 0x0193 464 #define SK_TO4 0x0194 465 #define SK_TO5 0x0195 466 #define SK_TO6 0x0196 467 #define SK_TO7 0x0197 468 #define SK_TO8 0x0198 469 #define SK_TO9 0x0199 470 #define SK_TO10 0x019A 471 #define SK_TO11 0x019B 472 #define SK_RITIMEO_TMR 0x019C 473 #define SK_RAMCTL 0x01A0 474 #define SK_RITIMER_TST 0x01A2 475 476 #define SK_RAMCTL_RESET 0x0001 477 #define SK_RAMCTL_UNRESET 0x0002 478 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 479 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 480 481 /* Mac arbiter registers */ 482 #define SK_MINIT_RX1 0x01B0 483 #define SK_MINIT_RX2 0x01B1 484 #define SK_MINIT_TX1 0x01B2 485 #define SK_MINIT_TX2 0x01B3 486 #define SK_MTIMEO_RX1 0x01B4 487 #define SK_MTIMEO_RX2 0x01B5 488 #define SK_MTIMEO_TX1 0x01B6 489 #define SK_MTIEMO_TX2 0x01B7 490 #define SK_MACARB_CTL 0x01B8 491 #define SK_MTIMER_TST 0x01BA 492 #define SK_RCINIT_RX1 0x01C0 493 #define SK_RCINIT_RX2 0x01C1 494 #define SK_RCINIT_TX1 0x01C2 495 #define SK_RCINIT_TX2 0x01C3 496 #define SK_RCTIMEO_RX1 0x01C4 497 #define SK_RCTIMEO_RX2 0x01C5 498 #define SK_RCTIMEO_TX1 0x01C6 499 #define SK_RCTIMEO_TX2 0x01C7 500 #define SK_RECOVERY_CTL 0x01C8 501 #define SK_RCTIMER_TST 0x01CA 502 503 /* Packet arbiter registers */ 504 #define SK_RXPA1_TINIT 0x01D0 505 #define SK_RXPA2_TINIT 0x01D4 506 #define SK_TXPA1_TINIT 0x01D8 507 #define SK_TXPA2_TINIT 0x01DC 508 #define SK_RXPA1_TIMEO 0x01E0 509 #define SK_RXPA2_TIMEO 0x01E4 510 #define SK_TXPA1_TIMEO 0x01E8 511 #define SK_TXPA2_TIMEO 0x01EC 512 #define SK_PKTARB_CTL 0x01F0 513 #define SK_PKTATB_TST 0x01F2 514 515 #define SK_PKTARB_TIMEOUT 0x2000 516 517 #define SK_PKTARBCTL_RESET 0x0001 518 #define SK_PKTARBCTL_UNRESET 0x0002 519 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 520 #define SK_PKTARBCTL_RXTO1_ON 0x0008 521 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 522 #define SK_PKTARBCTL_RXTO2_ON 0x0020 523 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 524 #define SK_PKTARBCTL_TXTO1_ON 0x0080 525 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 526 #define SK_PKTARBCTL_TXTO2_ON 0x0200 527 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 528 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 529 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 530 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 531 532 #define SK_MINIT_XMAC_B2 54 533 #define SK_MINIT_XMAC_C1 63 534 535 #define SK_MACARBCTL_RESET 0x0001 536 #define SK_MACARBCTL_UNRESET 0x0002 537 #define SK_MACARBCTL_FASTOE_OFF 0x0004 538 #define SK_MACARBCRL_FASTOE_ON 0x0008 539 540 #define SK_RCINIT_XMAC_B2 54 541 #define SK_RCINIT_XMAC_C1 0 542 543 #define SK_RECOVERYCTL_RX1_OFF 0x0001 544 #define SK_RECOVERYCTL_RX1_ON 0x0002 545 #define SK_RECOVERYCTL_RX2_OFF 0x0004 546 #define SK_RECOVERYCTL_RX2_ON 0x0008 547 #define SK_RECOVERYCTL_TX1_OFF 0x0010 548 #define SK_RECOVERYCTL_TX1_ON 0x0020 549 #define SK_RECOVERYCTL_TX2_OFF 0x0040 550 #define SK_RECOVERYCTL_TX2_ON 0x0080 551 552 #define SK_RECOVERY_XMAC_B2 \ 553 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 554 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 555 556 #define SK_RECOVERY_XMAC_C1 \ 557 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 558 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 559 560 /* Block 4 -- TX Arbiter MAC 1 */ 561 #define SK_TXAR1_TIMERINIT 0x0200 562 #define SK_TXAR1_TIMERVAL 0x0204 563 #define SK_TXAR1_LIMITINIT 0x0208 564 #define SK_TXAR1_LIMITCNT 0x020C 565 #define SK_TXAR1_COUNTERCTL 0x0210 566 #define SK_TXAR1_COUNTERTST 0x0212 567 #define SK_TXAR1_COUNTERSTS 0x0212 568 569 /* Block 5 -- TX Arbiter MAC 2 */ 570 #define SK_TXAR2_TIMERINIT 0x0280 571 #define SK_TXAR2_TIMERVAL 0x0284 572 #define SK_TXAR2_LIMITINIT 0x0288 573 #define SK_TXAR2_LIMITCNT 0x028C 574 #define SK_TXAR2_COUNTERCTL 0x0290 575 #define SK_TXAR2_COUNTERTST 0x0291 576 #define SK_TXAR2_COUNTERSTS 0x0292 577 578 #define SK_TXARCTL_OFF 0x01 579 #define SK_TXARCTL_ON 0x02 580 #define SK_TXARCTL_RATECTL_OFF 0x04 581 #define SK_TXARCTL_RATECTL_ON 0x08 582 #define SK_TXARCTL_ALLOC_OFF 0x10 583 #define SK_TXARCTL_ALLOC_ON 0x20 584 #define SK_TXARCTL_FSYNC_OFF 0x40 585 #define SK_TXARCTL_FSYNC_ON 0x80 586 587 /* Block 6 -- External registers */ 588 #define SK_EXTREG_BASE 0x300 589 #define SK_EXTREG_END 0x37C 590 591 /* Block 7 -- PCI config registers */ 592 #define SK_PCI_BASE 0x0380 593 #define SK_PCI_END 0x03FC 594 595 /* Compute offset of mirrored PCI register */ 596 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 597 598 /* Block 8 -- RX queue 1 */ 599 #define SK_RXQ1_BUFCNT 0x0400 600 #define SK_RXQ1_BUFCTL 0x0402 601 #define SK_RXQ1_NEXTDESC 0x0404 602 #define SK_RXQ1_RXBUF_LO 0x0408 603 #define SK_RXQ1_RXBUF_HI 0x040C 604 #define SK_RXQ1_RXSTAT 0x0410 605 #define SK_RXQ1_TIMESTAMP 0x0414 606 #define SK_RXQ1_CSUM1 0x0418 607 #define SK_RXQ1_CSUM2 0x041A 608 #define SK_RXQ1_CSUM1_START 0x041C 609 #define SK_RXQ1_CSUM2_START 0x041E 610 #define SK_RXQ1_CURADDR_LO 0x0420 611 #define SK_RXQ1_CURADDR_HI 0x0424 612 #define SK_RXQ1_CURCNT_LO 0x0428 613 #define SK_RXQ1_CURCNT_HI 0x042C 614 #define SK_RXQ1_CURBYTES 0x0430 615 #define SK_RXQ1_BMU_CSR 0x0434 616 #define SK_RXQ1_WATERMARK 0x0438 617 #define SK_RXQ1_FLAG 0x043A 618 #define SK_RXQ1_TEST1 0x043C 619 #define SK_RXQ1_TEST2 0x0440 620 #define SK_RXQ1_TEST3 0x0444 621 622 /* Block 9 -- RX queue 2 */ 623 #define SK_RXQ2_BUFCNT 0x0480 624 #define SK_RXQ2_BUFCTL 0x0482 625 #define SK_RXQ2_NEXTDESC 0x0484 626 #define SK_RXQ2_RXBUF_LO 0x0488 627 #define SK_RXQ2_RXBUF_HI 0x048C 628 #define SK_RXQ2_RXSTAT 0x0490 629 #define SK_RXQ2_TIMESTAMP 0x0494 630 #define SK_RXQ2_CSUM1 0x0498 631 #define SK_RXQ2_CSUM2 0x049A 632 #define SK_RXQ2_CSUM1_START 0x049C 633 #define SK_RXQ2_CSUM2_START 0x049E 634 #define SK_RXQ2_CURADDR_LO 0x04A0 635 #define SK_RXQ2_CURADDR_HI 0x04A4 636 #define SK_RXQ2_CURCNT_LO 0x04A8 637 #define SK_RXQ2_CURCNT_HI 0x04AC 638 #define SK_RXQ2_CURBYTES 0x04B0 639 #define SK_RXQ2_BMU_CSR 0x04B4 640 #define SK_RXQ2_WATERMARK 0x04B8 641 #define SK_RXQ2_FLAG 0x04BA 642 #define SK_RXQ2_TEST1 0x04BC 643 #define SK_RXQ2_TEST2 0x04C0 644 #define SK_RXQ2_TEST3 0x04C4 645 646 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 647 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 648 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 649 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 650 #define SK_RXBMU_RX_START 0x00000010 651 #define SK_RXBMU_RX_STOP 0x00000020 652 #define SK_RXBMU_POLL_OFF 0x00000040 653 #define SK_RXBMU_POLL_ON 0x00000080 654 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 655 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 656 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 657 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 658 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 659 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 660 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 661 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 662 #define SK_RXBMU_PFI_SM_RESET 0x00010000 663 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 664 #define SK_RXBMU_FIFO_RESET 0x00040000 665 #define SK_RXBMU_FIFO_UNRESET 0x00080000 666 #define SK_RXBMU_DESC_RESET 0x00100000 667 #define SK_RXBMU_DESC_UNRESET 0x00200000 668 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 669 670 #define SK_RXBMU_ONLINE \ 671 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 672 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 673 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 674 SK_RXBMU_DESC_UNRESET) 675 676 #define SK_RXBMU_OFFLINE \ 677 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 678 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 679 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 680 SK_RXBMU_DESC_RESET) 681 682 /* Block 12 -- TX sync queue 1 */ 683 #define SK_TXQS1_BUFCNT 0x0600 684 #define SK_TXQS1_BUFCTL 0x0602 685 #define SK_TXQS1_NEXTDESC 0x0604 686 #define SK_TXQS1_RXBUF_LO 0x0608 687 #define SK_TXQS1_RXBUF_HI 0x060C 688 #define SK_TXQS1_RXSTAT 0x0610 689 #define SK_TXQS1_CSUM_STARTVAL 0x0614 690 #define SK_TXQS1_CSUM_STARTPOS 0x0618 691 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 692 #define SK_TXQS1_CURADDR_LO 0x0620 693 #define SK_TXQS1_CURADDR_HI 0x0624 694 #define SK_TXQS1_CURCNT_LO 0x0628 695 #define SK_TXQS1_CURCNT_HI 0x062C 696 #define SK_TXQS1_CURBYTES 0x0630 697 #define SK_TXQS1_BMU_CSR 0x0634 698 #define SK_TXQS1_WATERMARK 0x0638 699 #define SK_TXQS1_FLAG 0x063A 700 #define SK_TXQS1_TEST1 0x063C 701 #define SK_TXQS1_TEST2 0x0640 702 #define SK_TXQS1_TEST3 0x0644 703 704 /* Block 13 -- TX async queue 1 */ 705 #define SK_TXQA1_BUFCNT 0x0680 706 #define SK_TXQA1_BUFCTL 0x0682 707 #define SK_TXQA1_NEXTDESC 0x0684 708 #define SK_TXQA1_RXBUF_LO 0x0688 709 #define SK_TXQA1_RXBUF_HI 0x068C 710 #define SK_TXQA1_RXSTAT 0x0690 711 #define SK_TXQA1_CSUM_STARTVAL 0x0694 712 #define SK_TXQA1_CSUM_STARTPOS 0x0698 713 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 714 #define SK_TXQA1_CURADDR_LO 0x06A0 715 #define SK_TXQA1_CURADDR_HI 0x06A4 716 #define SK_TXQA1_CURCNT_LO 0x06A8 717 #define SK_TXQA1_CURCNT_HI 0x06AC 718 #define SK_TXQA1_CURBYTES 0x06B0 719 #define SK_TXQA1_BMU_CSR 0x06B4 720 #define SK_TXQA1_WATERMARK 0x06B8 721 #define SK_TXQA1_FLAG 0x06BA 722 #define SK_TXQA1_TEST1 0x06BC 723 #define SK_TXQA1_TEST2 0x06C0 724 #define SK_TXQA1_TEST3 0x06C4 725 726 /* Block 14 -- TX sync queue 2 */ 727 #define SK_TXQS2_BUFCNT 0x0700 728 #define SK_TXQS2_BUFCTL 0x0702 729 #define SK_TXQS2_NEXTDESC 0x0704 730 #define SK_TXQS2_RXBUF_LO 0x0708 731 #define SK_TXQS2_RXBUF_HI 0x070C 732 #define SK_TXQS2_RXSTAT 0x0710 733 #define SK_TXQS2_CSUM_STARTVAL 0x0714 734 #define SK_TXQS2_CSUM_STARTPOS 0x0718 735 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 736 #define SK_TXQS2_CURADDR_LO 0x0720 737 #define SK_TXQS2_CURADDR_HI 0x0724 738 #define SK_TXQS2_CURCNT_LO 0x0728 739 #define SK_TXQS2_CURCNT_HI 0x072C 740 #define SK_TXQS2_CURBYTES 0x0730 741 #define SK_TXQS2_BMU_CSR 0x0734 742 #define SK_TXQS2_WATERMARK 0x0738 743 #define SK_TXQS2_FLAG 0x073A 744 #define SK_TXQS2_TEST1 0x073C 745 #define SK_TXQS2_TEST2 0x0740 746 #define SK_TXQS2_TEST3 0x0744 747 748 /* Block 15 -- TX async queue 2 */ 749 #define SK_TXQA2_BUFCNT 0x0780 750 #define SK_TXQA2_BUFCTL 0x0782 751 #define SK_TXQA2_NEXTDESC 0x0784 752 #define SK_TXQA2_RXBUF_LO 0x0788 753 #define SK_TXQA2_RXBUF_HI 0x078C 754 #define SK_TXQA2_RXSTAT 0x0790 755 #define SK_TXQA2_CSUM_STARTVAL 0x0794 756 #define SK_TXQA2_CSUM_STARTPOS 0x0798 757 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 758 #define SK_TXQA2_CURADDR_LO 0x07A0 759 #define SK_TXQA2_CURADDR_HI 0x07A4 760 #define SK_TXQA2_CURCNT_LO 0x07A8 761 #define SK_TXQA2_CURCNT_HI 0x07AC 762 #define SK_TXQA2_CURBYTES 0x07B0 763 #define SK_TXQA2_BMU_CSR 0x07B4 764 #define SK_TXQA2_WATERMARK 0x07B8 765 #define SK_TXQA2_FLAG 0x07BA 766 #define SK_TXQA2_TEST1 0x07BC 767 #define SK_TXQA2_TEST2 0x07C0 768 #define SK_TXQA2_TEST3 0x07C4 769 770 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 771 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 772 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 773 #define SK_TXBMU_TX_START 0x00000010 774 #define SK_TXBMU_TX_STOP 0x00000020 775 #define SK_TXBMU_POLL_OFF 0x00000040 776 #define SK_TXBMU_POLL_ON 0x00000080 777 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 778 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 779 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 780 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 781 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 782 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 783 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 784 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 785 #define SK_TXBMU_PFI_SM_RESET 0x00010000 786 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 787 #define SK_TXBMU_FIFO_RESET 0x00040000 788 #define SK_TXBMU_FIFO_UNRESET 0x00080000 789 #define SK_TXBMU_DESC_RESET 0x00100000 790 #define SK_TXBMU_DESC_UNRESET 0x00200000 791 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 792 793 #define SK_TXBMU_ONLINE \ 794 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 795 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 796 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 797 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 798 799 #define SK_TXBMU_OFFLINE \ 800 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 801 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 802 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 803 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 804 805 /* Block 16 -- Receive RAMbuffer 1 */ 806 #define SK_RXRB1_START 0x0800 807 #define SK_RXRB1_END 0x0804 808 #define SK_RXRB1_WR_PTR 0x0808 809 #define SK_RXRB1_RD_PTR 0x080C 810 #define SK_RXRB1_UTHR_PAUSE 0x0810 811 #define SK_RXRB1_LTHR_PAUSE 0x0814 812 #define SK_RXRB1_UTHR_HIPRIO 0x0818 813 #define SK_RXRB1_UTHR_LOPRIO 0x081C 814 #define SK_RXRB1_PKTCNT 0x0820 815 #define SK_RXRB1_LVL 0x0824 816 #define SK_RXRB1_CTLTST 0x0828 817 818 /* Block 17 -- Receive RAMbuffer 2 */ 819 #define SK_RXRB2_START 0x0880 820 #define SK_RXRB2_END 0x0884 821 #define SK_RXRB2_WR_PTR 0x0888 822 #define SK_RXRB2_RD_PTR 0x088C 823 #define SK_RXRB2_UTHR_PAUSE 0x0890 824 #define SK_RXRB2_LTHR_PAUSE 0x0894 825 #define SK_RXRB2_UTHR_HIPRIO 0x0898 826 #define SK_RXRB2_UTHR_LOPRIO 0x089C 827 #define SK_RXRB2_PKTCNT 0x08A0 828 #define SK_RXRB2_LVL 0x08A4 829 #define SK_RXRB2_CTLTST 0x08A8 830 831 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 832 #define SK_TXRBS1_START 0x0A00 833 #define SK_TXRBS1_END 0x0A04 834 #define SK_TXRBS1_WR_PTR 0x0A08 835 #define SK_TXRBS1_RD_PTR 0x0A0C 836 #define SK_TXRBS1_PKTCNT 0x0A20 837 #define SK_TXRBS1_LVL 0x0A24 838 #define SK_TXRBS1_CTLTST 0x0A28 839 840 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 841 #define SK_TXRBA1_START 0x0A80 842 #define SK_TXRBA1_END 0x0A84 843 #define SK_TXRBA1_WR_PTR 0x0A88 844 #define SK_TXRBA1_RD_PTR 0x0A8C 845 #define SK_TXRBA1_PKTCNT 0x0AA0 846 #define SK_TXRBA1_LVL 0x0AA4 847 #define SK_TXRBA1_CTLTST 0x0AA8 848 849 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 850 #define SK_TXRBS2_START 0x0B00 851 #define SK_TXRBS2_END 0x0B04 852 #define SK_TXRBS2_WR_PTR 0x0B08 853 #define SK_TXRBS2_RD_PTR 0x0B0C 854 #define SK_TXRBS2_PKTCNT 0x0B20 855 #define SK_TXRBS2_LVL 0x0B24 856 #define SK_TXRBS2_CTLTST 0x0B28 857 858 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 859 #define SK_TXRBA2_START 0x0B80 860 #define SK_TXRBA2_END 0x0B84 861 #define SK_TXRBA2_WR_PTR 0x0B88 862 #define SK_TXRBA2_RD_PTR 0x0B8C 863 #define SK_TXRBA2_PKTCNT 0x0BA0 864 #define SK_TXRBA2_LVL 0x0BA4 865 #define SK_TXRBA2_CTLTST 0x0BA8 866 867 #define SK_RBCTL_RESET 0x00000001 868 #define SK_RBCTL_UNRESET 0x00000002 869 #define SK_RBCTL_OFF 0x00000004 870 #define SK_RBCTL_ON 0x00000008 871 #define SK_RBCTL_STORENFWD_OFF 0x00000010 872 #define SK_RBCTL_STORENFWD_ON 0x00000020 873 874 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 875 #define SK_RXF1_END 0x0C00 876 #define SK_RXF1_WPTR 0x0C04 877 #define SK_RXF1_RPTR 0x0C0C 878 #define SK_RXF1_PKTCNT 0x0C10 879 #define SK_RXF1_LVL 0x0C14 880 #define SK_RXF1_MACCTL 0x0C18 881 #define SK_RXF1_CTL 0x0C1C 882 #define SK_RXLED1_CNTINIT 0x0C20 883 #define SK_RXLED1_COUNTER 0x0C24 884 #define SK_RXLED1_CTL 0x0C28 885 #define SK_RXLED1_TST 0x0C29 886 #define SK_LINK_SYNC1_CINIT 0x0C30 887 #define SK_LINK_SYNC1_COUNTER 0x0C34 888 #define SK_LINK_SYNC1_CTL 0x0C38 889 #define SK_LINK_SYNC1_TST 0x0C39 890 #define SK_LINKLED1_CTL 0x0C3C 891 892 #define SK_FIFO_END 0x3F 893 894 /* Receive MAC FIFO 1 (Yukon Only) */ 895 #define SK_RXMF1_END 0x0C40 896 #define SK_RXMF1_THRESHOLD 0x0C44 897 #define SK_RXMF1_CTRL_TEST 0x0C48 898 #define SK_RXMF1_FLUSH_MASK 0x0C4C 899 #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 900 #define SK_RXMF1_WRITE_PTR 0x0C60 901 #define SK_RXMF1_WRITE_LEVEL 0x0C68 902 #define SK_RXMF1_READ_PTR 0x0C70 903 #define SK_RXMF1_READ_LEVEL 0x0C78 904 905 /* Receive MAC FIFO 1 Control/Test */ 906 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 907 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 908 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 909 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 910 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 911 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 912 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 913 #define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 914 #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 915 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 916 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 917 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 918 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 919 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 920 921 #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 922 923 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 924 #define SK_RXF2_END 0x0C80 925 #define SK_RXF2_WPTR 0x0C84 926 #define SK_RXF2_RPTR 0x0C8C 927 #define SK_RXF2_PKTCNT 0x0C90 928 #define SK_RXF2_LVL 0x0C94 929 #define SK_RXF2_MACCTL 0x0C98 930 #define SK_RXF2_CTL 0x0C9C 931 #define SK_RXLED2_CNTINIT 0x0CA0 932 #define SK_RXLED2_COUNTER 0x0CA4 933 #define SK_RXLED2_CTL 0x0CA8 934 #define SK_RXLED2_TST 0x0CA9 935 #define SK_LINK_SYNC2_CINIT 0x0CB0 936 #define SK_LINK_SYNC2_COUNTER 0x0CB4 937 #define SK_LINK_SYNC2_CTL 0x0CB8 938 #define SK_LINK_SYNC2_TST 0x0CB9 939 #define SK_LINKLED2_CTL 0x0CBC 940 941 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 942 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 943 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 944 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 945 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 946 #define SK_RXMACCTL_FLUSH_ON 0x00000020 947 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 948 #define SK_RXMACCTL_PAUSE_ON 0x00000080 949 #define SK_RXMACCTL_AFULL_OFF 0x00000100 950 #define SK_RXMACCTL_AFULL_ON 0x00000200 951 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 952 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 953 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 954 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 955 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 956 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 957 958 #define SK_RXLEDCTL_ENABLE 0x0001 959 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 960 #define SK_RXLEDCTL_COUNTER_START 0x0004 961 962 #define SK_LINKLED_OFF 0x0001 963 #define SK_LINKLED_ON 0x0002 964 #define SK_LINKLED_LINKSYNC_OFF 0x0004 965 #define SK_LINKLED_LINKSYNC_ON 0x0008 966 #define SK_LINKLED_BLINK_OFF 0x0010 967 #define SK_LINKLED_BLINK_ON 0x0020 968 969 /* Block 26 -- TX MAC FIFO 1 regisrers */ 970 #define SK_TXF1_END 0x0D00 971 #define SK_TXF1_WPTR 0x0D04 972 #define SK_TXF1_RPTR 0x0D0C 973 #define SK_TXF1_PKTCNT 0x0D10 974 #define SK_TXF1_LVL 0x0D14 975 #define SK_TXF1_MACCTL 0x0D18 976 #define SK_TXF1_CTL 0x0D1C 977 #define SK_TXLED1_CNTINIT 0x0D20 978 #define SK_TXLED1_COUNTER 0x0D24 979 #define SK_TXLED1_CTL 0x0D28 980 #define SK_TXLED1_TST 0x0D29 981 982 /* Transmit MAC FIFO 1 (Yukon Only) */ 983 #define SK_TXMF1_END 0x0D40 984 #define SK_TXMF1_THRESHOLD 0x0D44 985 #define SK_TXMF1_CTRL_TEST 0x0D48 986 #define SK_TXMF1_WRITE_PTR 0x0D60 987 #define SK_TXMF1_WRITE_SHADOW 0x0D64 988 #define SK_TXMF1_WRITE_LEVEL 0x0D68 989 #define SK_TXMF1_READ_PTR 0x0D70 990 #define SK_TXMF1_RESTART_PTR 0x0D74 991 #define SK_TXMF1_READ_LEVEL 0x0D78 992 993 /* Transmit MAC FIFO Control/Test */ 994 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 995 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 996 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 997 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 998 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 999 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 1000 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 1001 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 1002 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 1003 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1004 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1005 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1006 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1007 1008 /* Block 27 -- TX MAC FIFO 2 regisrers */ 1009 #define SK_TXF2_END 0x0D80 1010 #define SK_TXF2_WPTR 0x0D84 1011 #define SK_TXF2_RPTR 0x0D8C 1012 #define SK_TXF2_PKTCNT 0x0D90 1013 #define SK_TXF2_LVL 0x0D94 1014 #define SK_TXF2_MACCTL 0x0D98 1015 #define SK_TXF2_CTL 0x0D9C 1016 #define SK_TXLED2_CNTINIT 0x0DA0 1017 #define SK_TXLED2_COUNTER 0x0DA4 1018 #define SK_TXLED2_CTL 0x0DA8 1019 #define SK_TXLED2_TST 0x0DA9 1020 1021 #define SK_TXMACCTL_XMAC_RESET 0x00000001 1022 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1023 #define SK_TXMACCTL_LOOP_OFF 0x00000004 1024 #define SK_TXMACCTL_LOOP_ON 0x00000008 1025 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 1026 #define SK_TXMACCTL_FLUSH_ON 0x00000020 1027 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1028 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1029 #define SK_TXMACCTL_AFULL_OFF 0x00000100 1030 #define SK_TXMACCTL_AFULL_ON 0x00000200 1031 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1032 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1033 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1034 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1035 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1036 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1037 1038 #define SK_TXLEDCTL_ENABLE 0x0001 1039 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 1040 #define SK_TXLEDCTL_COUNTER_START 0x0004 1041 1042 #define SK_FIFO_RESET 0x00000001 1043 #define SK_FIFO_UNRESET 0x00000002 1044 #define SK_FIFO_OFF 0x00000004 1045 #define SK_FIFO_ON 0x00000008 1046 1047 /* Block 28 -- Descriptor Poll Timer */ 1048 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1049 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1050 1051 #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1052 1053 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1054 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1055 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1056 1057 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1058 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1059 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1060 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1061 1062 /* Block 29 -- reserved */ 1063 1064 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1065 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1066 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1067 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1068 #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1069 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1070 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1071 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1072 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1073 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1074 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1075 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1076 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1077 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1078 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1079 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1080 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1081 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1082 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1083 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1084 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1085 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1086 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1087 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1088 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1089 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1090 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1091 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1092 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1093 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1094 1095 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1096 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1097 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1098 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1099 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1100 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1101 1102 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1103 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1104 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1105 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1106 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1107 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1108 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1109 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1110 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1111 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1112 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1113 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1114 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1115 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1116 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1117 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1118 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1119 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1120 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1121 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1122 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1123 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1124 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1125 1126 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1127 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1128 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1129 SK_GPHY_HWCFG_M_2 ) 1130 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1131 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1132 1133 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1134 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1135 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1136 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1137 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1138 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1139 1140 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1141 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1142 1143 /* Block 31 -- reserved */ 1144 1145 /* Block 32-33 -- Pattern Ram */ 1146 #define SK_WOL_PRAM 0x1000 1147 1148 /* Block 0x22 - 0x3f -- reserved */ 1149 1150 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1151 #define SK_XMAC1_BASE 0x2000 1152 1153 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1154 #define SK_MARV1_BASE 0x2800 1155 1156 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1157 #define SK_XMAC2_BASE 0x3000 1158 1159 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1160 #define SK_MARV2_BASE 0x3800 1161 1162 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1163 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1164 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1165 1166 #if 0 1167 #define SK_XM_READ_4(sc, reg) \ 1168 ((sk_win_read_2(sc->sk_softc, \ 1169 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1170 ((sk_win_read_2(sc->sk_softc, \ 1171 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1172 1173 #define SK_XM_WRITE_4(sc, reg, val) \ 1174 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1175 ((val) & 0xFFFF)); \ 1176 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1177 ((val) >> 16) & 0xFFFF) 1178 #else 1179 #define SK_XM_READ_4(sc, reg) \ 1180 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1181 1182 #define SK_XM_WRITE_4(sc, reg, val) \ 1183 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1184 #endif 1185 1186 #define SK_XM_READ_2(sc, reg) \ 1187 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1188 1189 #define SK_XM_WRITE_2(sc, reg, val) \ 1190 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1191 1192 #define SK_XM_SETBIT_4(sc, reg, x) \ 1193 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1194 1195 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1196 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1197 1198 #define SK_XM_SETBIT_2(sc, reg, x) \ 1199 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1200 1201 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1202 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1203 1204 /* Compute relative offset of an MARV register in the MARV window(s). */ 1205 #define SK_YU_REG(sc, reg) \ 1206 ((reg) + SK_MARV1_BASE + \ 1207 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1208 1209 #define SK_YU_READ_4(sc, reg) \ 1210 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1211 1212 #define SK_YU_READ_2(sc, reg) \ 1213 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1214 1215 #define SK_YU_WRITE_4(sc, reg, val) \ 1216 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1217 1218 #define SK_YU_WRITE_2(sc, reg, val) \ 1219 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1220 1221 #define SK_YU_SETBIT_4(sc, reg, x) \ 1222 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1223 1224 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1225 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1226 1227 #define SK_YU_SETBIT_2(sc, reg, x) \ 1228 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1229 1230 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1231 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1232 1233 /* 1234 * The default FIFO threshold on the XMAC II is 4 bytes. On 1235 * dual port NICs, this often leads to transmit underruns, so we 1236 * bump the threshold a little. 1237 */ 1238 #define SK_XM_TX_FIFOTHRESH 512 1239 1240 #define SK_PCI_VENDOR_ID 0x0000 1241 #define SK_PCI_DEVICE_ID 0x0002 1242 #define SK_PCI_COMMAND 0x0004 1243 #define SK_PCI_STATUS 0x0006 1244 #define SK_PCI_REVID 0x0008 1245 #define SK_PCI_CLASSCODE 0x0009 1246 #define SK_PCI_CACHELEN 0x000C 1247 #define SK_PCI_LATENCY_TIMER 0x000D 1248 #define SK_PCI_HEADER_TYPE 0x000E 1249 #define SK_PCI_LOMEM 0x0010 1250 #define SK_PCI_LOIO 0x0014 1251 #define SK_PCI_SUBVEN_ID 0x002C 1252 #define SK_PCI_SYBSYS_ID 0x002E 1253 #define SK_PCI_BIOSROM 0x0030 1254 #define SK_PCI_INTLINE 0x003C 1255 #define SK_PCI_INTPIN 0x003D 1256 #define SK_PCI_MINGNT 0x003E 1257 #define SK_PCI_MINLAT 0x003F 1258 1259 /* device specific PCI registers */ 1260 #define SK_PCI_OURREG1 0x0040 1261 #define SK_PCI_OURREG2 0x0044 1262 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1263 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1264 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1265 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1266 #define SK_PCI_PME_EVENT 0x004F 1267 1268 #define SK_PSTATE_MASK 0x0003 1269 #define SK_PSTATE_D0 0x0000 1270 #define SK_PSTATE_D1 0x0001 1271 #define SK_PSTATE_D2 0x0002 1272 #define SK_PSTATE_D3 0x0003 1273 #define SK_PME_EN 0x0010 1274 #define SK_PME_STATUS 0x8000 1275 1276 #define CSR_WRITE_4(sc, reg, val) \ 1277 bus_write_4((sc)->sk_res[0], (reg), (val)) 1278 #define CSR_WRITE_2(sc, reg, val) \ 1279 bus_write_2((sc)->sk_res[0], (reg), (val)) 1280 #define CSR_WRITE_1(sc, reg, val) \ 1281 bus_write_1((sc)->sk_res[0], (reg), (val)) 1282 1283 #define CSR_READ_4(sc, reg) \ 1284 bus_read_4((sc)->sk_res[0], (reg)) 1285 #define CSR_READ_2(sc, reg) \ 1286 bus_read_2((sc)->sk_res[0], (reg)) 1287 #define CSR_READ_1(sc, reg) \ 1288 bus_read_1((sc)->sk_res[0], (reg)) 1289 1290 struct sk_type { 1291 u_int16_t sk_vid; 1292 u_int16_t sk_did; 1293 const char *sk_name; 1294 }; 1295 1296 #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 1297 #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) 1298 1299 #define SK_RING_ALIGN 64 1300 1301 /* RX queue descriptor data structure */ 1302 struct sk_rx_desc { 1303 u_int32_t sk_ctl; 1304 u_int32_t sk_next; 1305 u_int32_t sk_data_lo; 1306 u_int32_t sk_data_hi; 1307 u_int32_t sk_xmac_rxstat; 1308 u_int32_t sk_timestamp; 1309 u_int32_t sk_csum; 1310 u_int32_t sk_csum_start; 1311 }; 1312 1313 #define SK_OPCODE_DEFAULT 0x00550000 1314 #define SK_OPCODE_CSUM 0x00560000 1315 1316 #define SK_RXCTL_LEN 0x0000FFFF 1317 #define SK_RXCTL_OPCODE 0x00FF0000 1318 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1319 #define SK_RXCTL_STATUS_VALID 0x02000000 1320 #define SK_RXCTL_DEV0 0x04000000 1321 #define SK_RXCTL_EOF_INTR 0x08000000 1322 #define SK_RXCTL_EOB_INTR 0x10000000 1323 #define SK_RXCTL_LASTFRAG 0x20000000 1324 #define SK_RXCTL_FIRSTFRAG 0x40000000 1325 #define SK_RXCTL_OWN 0x80000000 1326 1327 #define SK_RXSTAT \ 1328 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1329 1330 struct sk_tx_desc { 1331 u_int32_t sk_ctl; 1332 u_int32_t sk_next; 1333 u_int32_t sk_data_lo; 1334 u_int32_t sk_data_hi; 1335 u_int32_t sk_xmac_txstat; 1336 u_int32_t sk_csum_startval; 1337 u_int32_t sk_csum_start; 1338 u_int32_t sk_rsvd1; 1339 }; 1340 1341 #define SK_TXCTL_LEN 0x0000FFFF 1342 #define SK_TXCTL_OPCODE 0x00FF0000 1343 #define SK_TXCTL_SW 0x01000000 1344 #define SK_TXCTL_NOCRC 0x02000000 1345 #define SK_TXCTL_STORENFWD 0x04000000 1346 #define SK_TXCTL_EOF_INTR 0x08000000 1347 #define SK_TXCTL_EOB_INTR 0x10000000 1348 #define SK_TXCTL_LASTFRAG 0x20000000 1349 #define SK_TXCTL_FIRSTFRAG 0x40000000 1350 #define SK_TXCTL_OWN 0x80000000 1351 1352 #define SK_TXSTAT \ 1353 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1354 1355 #define SK_RXBYTES(x) ((x) & 0x0000FFFF) 1356 #define SK_TXBYTES SK_RXBYTES 1357 1358 #define SK_TX_RING_CNT 512 1359 #define SK_RX_RING_CNT 256 1360 #define SK_JUMBO_RX_RING_CNT 256 1361 #define SK_MAXTXSEGS 32 1362 1363 #define SK_JUMBO_FRAMELEN 9018 1364 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1365 #define SK_MAX_FRAMELEN \ 1366 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 1367 #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1368 1369 struct sk_txdesc { 1370 struct mbuf *tx_m; 1371 bus_dmamap_t tx_dmamap; 1372 STAILQ_ENTRY(sk_txdesc) tx_q; 1373 }; 1374 1375 STAILQ_HEAD(sk_txdq, sk_txdesc); 1376 1377 struct sk_rxdesc { 1378 struct mbuf *rx_m; 1379 bus_dmamap_t rx_dmamap; 1380 }; 1381 1382 struct sk_chain_data { 1383 bus_dma_tag_t sk_parent_tag; 1384 bus_dma_tag_t sk_tx_tag; 1385 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT]; 1386 struct sk_txdq sk_txfreeq; 1387 struct sk_txdq sk_txbusyq; 1388 bus_dma_tag_t sk_rx_tag; 1389 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT]; 1390 bus_dma_tag_t sk_tx_ring_tag; 1391 bus_dma_tag_t sk_rx_ring_tag; 1392 bus_dmamap_t sk_tx_ring_map; 1393 bus_dmamap_t sk_rx_ring_map; 1394 bus_dmamap_t sk_rx_sparemap; 1395 bus_dma_tag_t sk_jumbo_rx_tag; 1396 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT]; 1397 bus_dma_tag_t sk_jumbo_rx_ring_tag; 1398 bus_dmamap_t sk_jumbo_rx_ring_map; 1399 bus_dmamap_t sk_jumbo_rx_sparemap; 1400 int sk_tx_prod; 1401 int sk_tx_cons; 1402 int sk_tx_cnt; 1403 int sk_rx_cons; 1404 int sk_jumbo_rx_cons; 1405 }; 1406 1407 struct sk_ring_data { 1408 struct sk_tx_desc *sk_tx_ring; 1409 bus_addr_t sk_tx_ring_paddr; 1410 struct sk_rx_desc *sk_rx_ring; 1411 bus_addr_t sk_rx_ring_paddr; 1412 struct sk_rx_desc *sk_jumbo_rx_ring; 1413 bus_addr_t sk_jumbo_rx_ring_paddr; 1414 }; 1415 1416 #define SK_TX_RING_ADDR(sc, i) \ 1417 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i)) 1418 #define SK_RX_RING_ADDR(sc, i) \ 1419 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1420 #define SK_JUMBO_RX_RING_ADDR(sc, i) \ 1421 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1422 1423 #define SK_TX_RING_SZ \ 1424 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT) 1425 #define SK_RX_RING_SZ \ 1426 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT) 1427 #define SK_JUMBO_RX_RING_SZ \ 1428 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT) 1429 1430 struct sk_bcom_hack { 1431 int reg; 1432 int val; 1433 }; 1434 1435 #define SK_INC(x, y) (x) = (x + 1) % y 1436 1437 /* Forward decl. */ 1438 struct sk_if_softc; 1439 1440 /* Softc for the GEnesis controller. */ 1441 struct sk_softc { 1442 struct resource *sk_res[2]; /* I/O and IRQ resources */ 1443 struct resource_spec *sk_res_spec; 1444 void *sk_intrhand; /* irq handler handle */ 1445 device_t sk_dev; 1446 u_int8_t sk_type; 1447 u_int8_t sk_rev; 1448 u_int8_t spare; 1449 u_int32_t sk_rboff; /* RAMbuffer offset */ 1450 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1451 u_int32_t sk_pmd; /* physical media type */ 1452 u_int32_t sk_coppertype; 1453 u_int32_t sk_intrmask; 1454 int sk_int_mod; 1455 int sk_int_ticks; 1456 int sk_suspended; 1457 struct sk_if_softc *sk_if[2]; 1458 device_t sk_devs[2]; 1459 struct mtx sk_mii_mtx; 1460 struct mtx sk_mtx; 1461 }; 1462 1463 #define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1464 #define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1465 #define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1466 #define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1467 #define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1468 #define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1469 #define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx) 1470 #define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx) 1471 1472 /* Softc for each logical interface */ 1473 struct sk_if_softc { 1474 struct ifnet *sk_ifp; /* interface info */ 1475 device_t sk_miibus; 1476 device_t sk_if_dev; 1477 u_int8_t sk_port; /* port # on controller */ 1478 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1479 u_int32_t sk_rx_ramstart; 1480 u_int32_t sk_rx_ramend; 1481 u_int32_t sk_tx_ramstart; 1482 u_int32_t sk_tx_ramend; 1483 int sk_phytype; 1484 int sk_phyaddr; 1485 int sk_link; 1486 struct callout sk_tick_ch; 1487 struct callout sk_watchdog_ch; 1488 int sk_watchdog_timer; 1489 struct sk_chain_data sk_cdata; 1490 struct sk_ring_data sk_rdata; 1491 struct sk_softc *sk_softc; /* parent controller */ 1492 int sk_tx_bmu; /* TX BMU register */ 1493 int sk_if_flags; 1494 int sk_jumbo_disable; 1495 }; 1496 1497 #define SK_TIMEOUT 1000
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