The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/sk/yukonreg.h

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    1 /*      $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */
    2 /*-
    3  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
    4  *
    5  * Permission to use, copy, modify, and distribute this software for any
    6  * purpose with or without fee is hereby granted, provided that the above
    7  * copyright notice and this permission notice appear in all copies.
    8  *
    9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   16  *
   17  * $FreeBSD$
   18  */
   19 
   20 /* General Purpose Status Register (GPSR) */
   21 #define YUKON_GPSR              0x0000
   22 
   23 #define YU_GPSR_SPEED           0x8000  /* speed 0 - 10Mbps, 1 - 100Mbps */
   24 #define YU_GPSR_DUPLEX          0x4000  /* 0 - half duplex, 1 - full duplex */
   25 #define YU_GPSR_FCTL_TX         0x2000  /* Tx flow control, 1 - disabled */
   26 #define YU_GPSR_LINK            0x1000  /* link status (down/up) */
   27 #define YU_GPSR_PAUSE           0x0800  /* flow control enable/disable */
   28 #define YU_GPSR_TX_IN_PROG      0x0400  /* transmit in progress */
   29 #define YU_GPSR_EXCESS_COL      0x0200  /* excessive collisions occurred */
   30 #define YU_GPSR_LATE_COL        0x0100  /* late collision occurred */
   31 #define YU_GPSR_MII_PHY_STC     0x0020  /* MII PHY status change */
   32 #define YU_GPSR_GIG_SPEED       0x0010  /* Gigabit Speed (0 - use speed bit) */
   33 #define YU_GPSR_PARTITION       0x0008  /* partition mode */
   34 #define YU_GPSR_FCTL_RX         0x0004  /* Rx flow control, 1 - disabled */
   35 #define YU_GPSR_PROMS_EN        0x0002  /* promiscuous mode, 1 - enabled */
   36 
   37 /* General Purpose Control Register (GPCR) */
   38 #define YUKON_GPCR              0x0004
   39 
   40 #define YU_GPCR_FCTL_TX_DIS     0x2000  /* Disable Tx flow control 802.3x */
   41 #define YU_GPCR_TXEN            0x1000  /* Transmit Enable */
   42 #define YU_GPCR_RXEN            0x0800  /* Receive Enable */
   43 #define YU_GPCR_BURSTEN         0x0400  /* Burst Mode Enable */
   44 #define YU_GPCR_LPBK            0x0200  /* MAC Loopback Enable */
   45 #define YU_GPCR_PAR             0x0100  /* Partition Enable */
   46 #define YU_GPCR_GIG             0x0080  /* Gigabit Speed 1000Mbps */
   47 #define YU_GPCR_FLP             0x0040  /* Force Link Pass */
   48 #define YU_GPCR_DUPLEX          0x0020  /* Duplex Enable */
   49 #define YU_GPCR_FCTL_RX_DIS     0x0010  /* Disable Rx flow control 802.3x */
   50 #define YU_GPCR_SPEED           0x0008  /* Port Speed 100Mbps */
   51 #define YU_GPCR_DPLX_DIS        0x0004  /* Disable Auto-Update for duplex */
   52 #define YU_GPCR_FCTL_DIS        0x0002  /* Disable Auto-Update for 802.3x */
   53 #define YU_GPCR_SPEED_DIS       0x0001  /* Disable Auto-Update for speed */
   54 
   55 /* Transmit Control Register (TCR) */
   56 #define YUKON_TCR               0x0008
   57 
   58 #define YU_TCR_FJ               0x8000  /* force jam / flow control */
   59 #define YU_TCR_CRCD             0x4000  /* insert CRC (0 - enable) */
   60 #define YU_TCR_PADD             0x2000  /* pad packets to 64b (0 - enable) */
   61 #define YU_TCR_COLTH            0x1c00  /* collision threshold */
   62 
   63 /* Receive Control Register (RCR) */
   64 #define YUKON_RCR               0x000c
   65 
   66 #define YU_RCR_UFLEN            0x8000  /* unicast filter enable */
   67 #define YU_RCR_MUFLEN           0x4000  /* multicast filter enable */
   68 #define YU_RCR_CRCR             0x2000  /* remove CRC */
   69 #define YU_RCR_PASSFC           0x1000  /* pass flow control packets */
   70 
   71 /* Transmit Flow Control Register (TFCR) */
   72 #define YUKON_TFCR              0x0010  /* Pause Time */
   73 
   74 /* Transmit Parameter Register (TPR) */
   75 #define YUKON_TPR               0x0014
   76 
   77 #define YU_TPR_JAM_LEN(x)       (((x) & 0x3) << 14)
   78 #define YU_TPR_JAM_IPG(x)       (((x) & 0x1f) << 9)
   79 #define YU_TPR_JAM2DATA_IPG(x)  (((x) & 0x1f) << 4)
   80 
   81 /* Serial Mode Register (SMR) */
   82 #define YUKON_SMR               0x0018
   83 
   84 #define YU_SMR_DATA_BLIND(x)    (((x) & 0x1f) << 11)
   85 #define YU_SMR_LIMIT4           0x0400  /* reset after 16 / 4 collisions */
   86 #define YU_SMR_MFL_JUMBO        0x0100  /* max frame length for jumbo frames */
   87 #define YU_SMR_MFL_VLAN         0x0200  /* max frame length + vlan tag */
   88 #define YU_SMR_IPG_DATA(x)      ((x) & 0x1f)
   89 
   90 /* Source Address Low #1 (SAL1) */
   91 #define YUKON_SAL1              0x001c  /* SA1[15:0] */
   92 
   93 /* Source Address Middle #1 (SAM1) */
   94 #define YUKON_SAM1              0x0020  /* SA1[31:16] */
   95 
   96 /* Source Address High #1 (SAH1) */
   97 #define YUKON_SAH1              0x0024  /* SA1[47:32] */
   98 
   99 /* Source Address Low #2 (SAL2) */
  100 #define YUKON_SAL2              0x0028  /* SA2[15:0] */
  101 
  102 /* Source Address Middle #2 (SAM2) */
  103 #define YUKON_SAM2              0x002c  /* SA2[31:16] */
  104 
  105 /* Source Address High #2 (SAH2) */
  106 #define YUKON_SAH2              0x0030  /* SA2[47:32] */
  107 
  108 /* Multicatst Address Hash Register 1 (MCAH1) */
  109 #define YUKON_MCAH1             0x0034
  110 
  111 /* Multicatst Address Hash Register 2 (MCAH2) */
  112 #define YUKON_MCAH2             0x0038
  113 
  114 /* Multicatst Address Hash Register 3 (MCAH3) */
  115 #define YUKON_MCAH3             0x003c
  116 
  117 /* Multicatst Address Hash Register 4 (MCAH4) */
  118 #define YUKON_MCAH4             0x0040
  119 
  120 /* Transmit Interrupt Register (TIR) */
  121 #define YUKON_TIR               0x0044
  122 
  123 #define YU_TIR_OUT_UNICAST      0x0001  /* Num Unicast Packets Transmitted */
  124 #define YU_TIR_OUT_BROADCAST    0x0002  /* Num Broadcast Packets Transmitted */
  125 #define YU_TIR_OUT_PAUSE        0x0004  /* Num Pause Packets Transmitted */
  126 #define YU_TIR_OUT_MULTICAST    0x0008  /* Num Multicast Packets Transmitted */
  127 #define YU_TIR_OUT_OCTETS       0x0030  /* Num Bytes Transmitted */
  128 #define YU_TIR_OUT_64_OCTETS    0x0000  /* Num Packets Transmitted */
  129 #define YU_TIR_OUT_127_OCTETS   0x0000  /* Num Packets Transmitted */
  130 #define YU_TIR_OUT_255_OCTETS   0x0000  /* Num Packets Transmitted */
  131 #define YU_TIR_OUT_511_OCTETS   0x0000  /* Num Packets Transmitted */
  132 #define YU_TIR_OUT_1023_OCTETS  0x0000  /* Num Packets Transmitted */
  133 #define YU_TIR_OUT_1518_OCTETS  0x0000  /* Num Packets Transmitted */
  134 #define YU_TIR_OUT_MAX_OCTETS   0x0000  /* Num Packets Transmitted */
  135 #define YU_TIR_OUT_SPARE        0x0000  /* Num Packets Transmitted */
  136 #define YU_TIR_OUT_COLLISIONS   0x0000  /* Num Packets Transmitted */
  137 #define YU_TIR_OUT_LATE         0x0000  /* Num Packets Transmitted */
  138 
  139 /* Receive Interrupt Register (RIR) */
  140 #define YUKON_RIR               0x0048
  141 
  142 /* Transmit and Receive Interrupt Register (TRIR) */
  143 #define YUKON_TRIR              0x004c
  144 
  145 /* Transmit Interrupt Mask Register (TIMR) */
  146 #define YUKON_TIMR              0x0050
  147 
  148 /* Receive Interrupt Mask Register (RIMR) */
  149 #define YUKON_RIMR              0x0054
  150 
  151 /* Transmit and Receive Interrupt Mask Register (TRIMR) */
  152 #define YUKON_TRIMR             0x0058
  153 
  154 /* SMI Control Register (SMICR) */
  155 #define YUKON_SMICR             0x0080
  156 
  157 #define YU_SMICR_PHYAD(x)       (((x) & 0x1f) << 11)
  158 #define YU_SMICR_REGAD(x)       (((x) & 0x1f) << 6)
  159 #define YU_SMICR_OPCODE         0x0020  /* opcode (0 - write, 1 - read) */
  160 #define YU_SMICR_OP_READ        0x0020  /* opcode read */
  161 #define YU_SMICR_OP_WRITE       0x0000  /* opcode write */
  162 #define YU_SMICR_READ_VALID     0x0010  /* read valid */
  163 #define YU_SMICR_BUSY           0x0008  /* busy (writing) */
  164 
  165 /* SMI Data Register (SMIDR) */
  166 #define YUKON_SMIDR             0x0084
  167 
  168 /* PHY Addres Register (PAR) */
  169 #define YUKON_PAR               0x0088
  170 
  171 #define YU_PAR_MIB_CLR          0x0020  /* MIB Counters Clear Mode */
  172 #define YU_PAR_LOAD_TSTCNT      0x0010  /* Load count 0xfffffff0 into cntr */
  173 
  174 /* Receive status */
  175 #define YU_RXSTAT_FOFL          0x00000001      /* Rx FIFO overflow */
  176 #define YU_RXSTAT_CRCERR        0x00000002      /* CRC error */
  177 #define YU_RXSTAT_FRAGMENT      0x00000008      /* fragment */
  178 #define YU_RXSTAT_LONGERR       0x00000010      /* too long packet */
  179 #define YU_RXSTAT_MIIERR        0x00000020      /* MII error */
  180 #define YU_RXSTAT_BADFC         0x00000040      /* bad flow-control packet */
  181 #define YU_RXSTAT_GOODFC        0x00000080      /* good flow-control packet */
  182 #define YU_RXSTAT_RXOK          0x00000100      /* receice OK (Good packet) */
  183 #define YU_RXSTAT_BROADCAST     0x00000200      /* broadcast packet */
  184 #define YU_RXSTAT_MULTICAST     0x00000400      /* multicast packet */
  185 #define YU_RXSTAT_RUNT          0x00000800      /* undersize packet */
  186 #define YU_RXSTAT_JABBER        0x00001000      /* jabber packet */
  187 #define YU_RXSTAT_VLAN          0x00002000      /* VLAN packet */
  188 #define YU_RXSTAT_LENSHIFT      16
  189 
  190 #define YU_RXSTAT_BYTES(x)      ((x) >> YU_RXSTAT_LENSHIFT)

Cache object: 64884e8e299303b17734a281d988d7b5


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