The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/smbus/x1241reg.h

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    1 /* $NetBSD: x1241reg.h,v 1.1 2002/11/12 01:00:59 simonb Exp $ */
    2 
    3 /*
    4  * Copyright 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Simon Burge for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   37 
   38 #ifndef _DEV_SMBUS_X1241REG_H_
   39 #define _DEV_SMBUS_X1241REG_H_
   40 
   41 /*
   42  * The X1241 appears at two fixed addresses on the SMBus, one each for
   43  * the EEPROM array and the real time clock.
   44  */
   45 #define X1241_ARRAY_SLAVEADDR   0x57
   46 #define X1241_RTC_SLAVEADDR     0x6f
   47 
   48 #define X1241REG_BL             0x10    /* Control register */
   49 #define X1241REG_SC             0x30    /* Seconds */
   50 #define X1241REG_MN             0x31    /* Minutes */
   51 #define X1241REG_HR             0x32    /* Hours */
   52 #define X1241REG_DT             0x33    /* Day of month */
   53 #define X1241REG_MO             0x34    /* Month */
   54 #define X1241REG_YR             0x35    /* Year */
   55 #define X1241REG_DW             0x36    /* Day of Week */
   56 #define X1241REG_Y2K            0x37    /* Year 2K */
   57 #define X1241REG_SR             0x3f    /* Status register */
   58 
   59 /* Register bits for the status register */
   60 #define X1241REG_SR_BAT         0x80    /* currently on battery power */
   61 #define X1241REG_SR_RWEL        0x04    /* r/w latch is enabled, can write RTC */
   62 #define X1241REG_SR_WEL         0x02    /* r/w latch is unlocked, can enable r/w now */
   63 #define X1241REG_SR_RTCF        0x01    /* clock failed */
   64 
   65 /* Register bits for the block protect register */
   66 #define X1241REG_BL_BP2         0x80    /* block protect 2 */
   67 #define X1241REG_BL_BP1         0x40    /* block protect 1 */
   68 #define X1241REG_BL_BP0         0x20    /* block protect 0 */
   69 #define X1241REG_BL_WD1         0x10    /* watchdog timeout 0 */
   70 #define X1241REG_BL_WD0         0x08    /* watchdog timeout 1 */
   71 
   72 /* Register bits for the hours register */
   73 #define X1241REG_HR_MIL         0x80    /* military time format */
   74 
   75 #endif /* _DEV_SMBUS_X1241REG_H_ */

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