Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/smc/if_smc.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Driver for SMSC LAN91C111, may work for older variants. 32 */ 33 34 #ifdef HAVE_KERNEL_OPTION_HEADERS 35 #include "opt_device_polling.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/kernel.h> 42 #include <sys/sockio.h> 43 #include <sys/malloc.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/socket.h> 47 #include <sys/syslog.h> 48 #include <sys/taskqueue.h> 49 50 #include <sys/module.h> 51 #include <sys/bus.h> 52 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #include <sys/rman.h> 56 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_types.h> 63 #include <net/if_mib.h> 64 #include <net/if_media.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #endif 72 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 76 #include <dev/smc/if_smcreg.h> 77 #include <dev/smc/if_smcvar.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/mii_bitbang.h> 81 #include <dev/mii/miivar.h> 82 83 #include "miibus_if.h" 84 85 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 86 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 87 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 88 89 #define SMC_INTR_PRIORITY 0 90 #define SMC_RX_PRIORITY 5 91 #define SMC_TX_PRIORITY 10 92 93 static const char *smc_chip_ids[16] = { 94 NULL, NULL, NULL, 95 /* 3 */ "SMSC LAN91C90 or LAN91C92", 96 /* 4 */ "SMSC LAN91C94", 97 /* 5 */ "SMSC LAN91C95", 98 /* 6 */ "SMSC LAN91C96", 99 /* 7 */ "SMSC LAN91C100", 100 /* 8 */ "SMSC LAN91C100FD", 101 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 102 NULL, NULL, NULL, 103 NULL, NULL, NULL 104 }; 105 106 static void smc_init(void *); 107 static void smc_start(struct ifnet *); 108 static void smc_stop(struct smc_softc *); 109 static int smc_ioctl(struct ifnet *, u_long, caddr_t); 110 111 static void smc_init_locked(struct smc_softc *); 112 static void smc_start_locked(struct ifnet *); 113 static void smc_reset(struct smc_softc *); 114 static int smc_mii_ifmedia_upd(struct ifnet *); 115 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 116 static void smc_mii_tick(void *); 117 static void smc_mii_mediachg(struct smc_softc *); 118 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 119 120 static void smc_task_intr(void *, int); 121 static void smc_task_rx(void *, int); 122 static void smc_task_tx(void *, int); 123 124 static driver_filter_t smc_intr; 125 static callout_func_t smc_watchdog; 126 #ifdef DEVICE_POLLING 127 static poll_handler_t smc_poll; 128 #endif 129 130 /* 131 * MII bit-bang glue 132 */ 133 static uint32_t smc_mii_bitbang_read(device_t); 134 static void smc_mii_bitbang_write(device_t, uint32_t); 135 136 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 137 smc_mii_bitbang_read, 138 smc_mii_bitbang_write, 139 { 140 MGMT_MDO, /* MII_BIT_MDO */ 141 MGMT_MDI, /* MII_BIT_MDI */ 142 MGMT_MCLK, /* MII_BIT_MDC */ 143 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 144 0, /* MII_BIT_DIR_PHY_HOST */ 145 } 146 }; 147 148 static __inline void 149 smc_select_bank(struct smc_softc *sc, uint16_t bank) 150 { 151 152 bus_barrier(sc->smc_reg, BSR, 2, 153 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 154 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 155 bus_barrier(sc->smc_reg, BSR, 2, 156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157 } 158 159 /* Never call this when not in bank 2. */ 160 static __inline void 161 smc_mmu_wait(struct smc_softc *sc) 162 { 163 164 KASSERT((bus_read_2(sc->smc_reg, BSR) & 165 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 166 device_get_nameunit(sc->smc_dev))); 167 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 168 ; 169 } 170 171 static __inline uint8_t 172 smc_read_1(struct smc_softc *sc, bus_size_t offset) 173 { 174 175 return (bus_read_1(sc->smc_reg, offset)); 176 } 177 178 static __inline void 179 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 180 { 181 182 bus_write_1(sc->smc_reg, offset, val); 183 } 184 185 static __inline uint16_t 186 smc_read_2(struct smc_softc *sc, bus_size_t offset) 187 { 188 189 return (bus_read_2(sc->smc_reg, offset)); 190 } 191 192 static __inline void 193 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 194 { 195 196 bus_write_2(sc->smc_reg, offset, val); 197 } 198 199 static __inline void 200 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 201 bus_size_t count) 202 { 203 204 bus_read_multi_2(sc->smc_reg, offset, datap, count); 205 } 206 207 static __inline void 208 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 209 bus_size_t count) 210 { 211 212 bus_write_multi_2(sc->smc_reg, offset, datap, count); 213 } 214 215 static __inline void 216 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 217 int flags) 218 { 219 220 bus_barrier(sc->smc_reg, offset, length, flags); 221 } 222 223 int 224 smc_probe(device_t dev) 225 { 226 int rid, type, error; 227 uint16_t val; 228 struct smc_softc *sc; 229 struct resource *reg; 230 231 sc = device_get_softc(dev); 232 rid = 0; 233 type = SYS_RES_IOPORT; 234 error = 0; 235 236 if (sc->smc_usemem) 237 type = SYS_RES_MEMORY; 238 239 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE); 240 if (reg == NULL) { 241 if (bootverbose) 242 device_printf(dev, 243 "could not allocate I/O resource for probe\n"); 244 return (ENXIO); 245 } 246 247 /* Check for the identification value in the BSR. */ 248 val = bus_read_2(reg, BSR); 249 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 250 if (bootverbose) 251 device_printf(dev, "identification value not in BSR\n"); 252 error = ENXIO; 253 goto done; 254 } 255 256 /* 257 * Try switching banks and make sure we still get the identification 258 * value. 259 */ 260 bus_write_2(reg, BSR, 0); 261 val = bus_read_2(reg, BSR); 262 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 263 if (bootverbose) 264 device_printf(dev, 265 "identification value not in BSR after write\n"); 266 error = ENXIO; 267 goto done; 268 } 269 270 #if 0 271 /* Check the BAR. */ 272 bus_write_2(reg, BSR, 1); 273 val = bus_read_2(reg, BAR); 274 val = BAR_ADDRESS(val); 275 if (rman_get_start(reg) != val) { 276 if (bootverbose) 277 device_printf(dev, "BAR address %x does not match " 278 "I/O resource address %lx\n", val, 279 rman_get_start(reg)); 280 error = ENXIO; 281 goto done; 282 } 283 #endif 284 285 /* Compare REV against known chip revisions. */ 286 bus_write_2(reg, BSR, 3); 287 val = bus_read_2(reg, REV); 288 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 289 if (smc_chip_ids[val] == NULL) { 290 if (bootverbose) 291 device_printf(dev, "Unknown chip revision: %d\n", val); 292 error = ENXIO; 293 goto done; 294 } 295 296 device_set_desc(dev, smc_chip_ids[val]); 297 298 done: 299 bus_release_resource(dev, type, rid, reg); 300 return (error); 301 } 302 303 int 304 smc_attach(device_t dev) 305 { 306 int type, error; 307 uint16_t val; 308 u_char eaddr[ETHER_ADDR_LEN]; 309 struct smc_softc *sc; 310 struct ifnet *ifp; 311 312 sc = device_get_softc(dev); 313 error = 0; 314 315 sc->smc_dev = dev; 316 317 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 318 if (ifp == NULL) { 319 error = ENOSPC; 320 goto done; 321 } 322 323 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 324 325 /* Set up watchdog callout. */ 326 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 327 328 type = SYS_RES_IOPORT; 329 if (sc->smc_usemem) 330 type = SYS_RES_MEMORY; 331 332 sc->smc_reg_rid = 0; 333 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid, 334 16, RF_ACTIVE); 335 if (sc->smc_reg == NULL) { 336 error = ENXIO; 337 goto done; 338 } 339 340 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ, 341 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE); 342 if (sc->smc_irq == NULL) { 343 error = ENXIO; 344 goto done; 345 } 346 347 SMC_LOCK(sc); 348 smc_reset(sc); 349 SMC_UNLOCK(sc); 350 351 smc_select_bank(sc, 3); 352 val = smc_read_2(sc, REV); 353 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 354 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 355 if (bootverbose) 356 device_printf(dev, "revision %x\n", sc->smc_rev); 357 358 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 359 CALLOUT_RETURNUNLOCKED); 360 if (sc->smc_chip >= REV_CHIP_91110FD) { 361 (void)mii_attach(dev, &sc->smc_miibus, ifp, 362 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 363 MII_PHY_ANY, MII_OFFSET_ANY, 0); 364 if (sc->smc_miibus != NULL) { 365 sc->smc_mii_tick = smc_mii_tick; 366 sc->smc_mii_mediachg = smc_mii_mediachg; 367 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 368 } 369 } 370 371 smc_select_bank(sc, 1); 372 eaddr[0] = smc_read_1(sc, IAR0); 373 eaddr[1] = smc_read_1(sc, IAR1); 374 eaddr[2] = smc_read_1(sc, IAR2); 375 eaddr[3] = smc_read_1(sc, IAR3); 376 eaddr[4] = smc_read_1(sc, IAR4); 377 eaddr[5] = smc_read_1(sc, IAR5); 378 379 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 380 ifp->if_softc = sc; 381 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 382 ifp->if_init = smc_init; 383 ifp->if_ioctl = smc_ioctl; 384 ifp->if_start = smc_start; 385 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 386 IFQ_SET_READY(&ifp->if_snd); 387 388 ifp->if_capabilities = ifp->if_capenable = 0; 389 390 #ifdef DEVICE_POLLING 391 ifp->if_capabilities |= IFCAP_POLLING; 392 #endif 393 394 ether_ifattach(ifp, eaddr); 395 396 /* Set up taskqueue */ 397 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 398 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 399 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 400 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 401 taskqueue_thread_enqueue, &sc->smc_tq); 402 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 403 device_get_nameunit(sc->smc_dev)); 404 405 /* Mask all interrupts. */ 406 sc->smc_mask = 0; 407 smc_write_1(sc, MSK, 0); 408 409 /* Wire up interrupt */ 410 error = bus_setup_intr(dev, sc->smc_irq, 411 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 412 if (error != 0) 413 goto done; 414 415 done: 416 if (error != 0) 417 smc_detach(dev); 418 return (error); 419 } 420 421 int 422 smc_detach(device_t dev) 423 { 424 int type; 425 struct smc_softc *sc; 426 427 sc = device_get_softc(dev); 428 SMC_LOCK(sc); 429 smc_stop(sc); 430 SMC_UNLOCK(sc); 431 432 if (sc->smc_ifp != NULL) { 433 ether_ifdetach(sc->smc_ifp); 434 } 435 436 callout_drain(&sc->smc_watchdog); 437 callout_drain(&sc->smc_mii_tick_ch); 438 439 #ifdef DEVICE_POLLING 440 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 441 ether_poll_deregister(sc->smc_ifp); 442 #endif 443 444 if (sc->smc_ih != NULL) 445 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 446 447 if (sc->smc_tq != NULL) { 448 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 449 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 450 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 451 taskqueue_free(sc->smc_tq); 452 sc->smc_tq = NULL; 453 } 454 455 if (sc->smc_ifp != NULL) { 456 if_free(sc->smc_ifp); 457 } 458 459 if (sc->smc_miibus != NULL) { 460 device_delete_child(sc->smc_dev, sc->smc_miibus); 461 bus_generic_detach(sc->smc_dev); 462 } 463 464 if (sc->smc_reg != NULL) { 465 type = SYS_RES_IOPORT; 466 if (sc->smc_usemem) 467 type = SYS_RES_MEMORY; 468 469 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 470 sc->smc_reg); 471 } 472 473 if (sc->smc_irq != NULL) 474 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 475 sc->smc_irq); 476 477 if (mtx_initialized(&sc->smc_mtx)) 478 mtx_destroy(&sc->smc_mtx); 479 480 return (0); 481 } 482 483 static device_method_t smc_methods[] = { 484 /* Device interface */ 485 DEVMETHOD(device_attach, smc_attach), 486 DEVMETHOD(device_detach, smc_detach), 487 488 /* MII interface */ 489 DEVMETHOD(miibus_readreg, smc_miibus_readreg), 490 DEVMETHOD(miibus_writereg, smc_miibus_writereg), 491 DEVMETHOD(miibus_statchg, smc_miibus_statchg), 492 { 0, 0 } 493 }; 494 495 driver_t smc_driver = { 496 "smc", 497 smc_methods, 498 sizeof(struct smc_softc), 499 }; 500 501 DRIVER_MODULE(miibus, smc, miibus_driver, 0, 0); 502 503 static void 504 smc_start(struct ifnet *ifp) 505 { 506 struct smc_softc *sc; 507 508 sc = ifp->if_softc; 509 SMC_LOCK(sc); 510 smc_start_locked(ifp); 511 SMC_UNLOCK(sc); 512 } 513 514 static void 515 smc_start_locked(struct ifnet *ifp) 516 { 517 struct smc_softc *sc; 518 struct mbuf *m; 519 u_int len, npages, spin_count; 520 521 sc = ifp->if_softc; 522 SMC_ASSERT_LOCKED(sc); 523 524 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 525 return; 526 if (IFQ_IS_EMPTY(&ifp->if_snd)) 527 return; 528 529 /* 530 * Grab the next packet. If it's too big, drop it. 531 */ 532 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 533 len = m_length(m, NULL); 534 len += (len & 1); 535 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 536 if_printf(ifp, "large packet discarded\n"); 537 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 538 m_freem(m); 539 return; /* XXX readcheck? */ 540 } 541 542 /* 543 * Flag that we're busy. 544 */ 545 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 546 sc->smc_pending = m; 547 548 /* 549 * Work out how many 256 byte "pages" we need. We have to include the 550 * control data for the packet in this calculation. 551 */ 552 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 553 if (npages == 0) 554 npages = 1; 555 556 /* 557 * Request memory. 558 */ 559 smc_select_bank(sc, 2); 560 smc_mmu_wait(sc); 561 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 562 563 /* 564 * Spin briefly to see if the allocation succeeds. 565 */ 566 spin_count = TX_ALLOC_WAIT_TIME; 567 do { 568 if (smc_read_1(sc, IST) & ALLOC_INT) { 569 smc_write_1(sc, ACK, ALLOC_INT); 570 break; 571 } 572 } while (--spin_count); 573 574 /* 575 * If the allocation is taking too long, unmask the alloc interrupt 576 * and wait. 577 */ 578 if (spin_count == 0) { 579 sc->smc_mask |= ALLOC_INT; 580 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 581 smc_write_1(sc, MSK, sc->smc_mask); 582 return; 583 } 584 585 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 586 } 587 588 static void 589 smc_task_tx(void *context, int pending) 590 { 591 struct ifnet *ifp; 592 struct smc_softc *sc; 593 struct mbuf *m, *m0; 594 u_int packet, len; 595 int last_len; 596 uint8_t *data; 597 598 (void)pending; 599 ifp = (struct ifnet *)context; 600 sc = ifp->if_softc; 601 602 SMC_LOCK(sc); 603 604 if (sc->smc_pending == NULL) { 605 SMC_UNLOCK(sc); 606 goto next_packet; 607 } 608 609 m = m0 = sc->smc_pending; 610 sc->smc_pending = NULL; 611 smc_select_bank(sc, 2); 612 613 /* 614 * Check the allocation result. 615 */ 616 packet = smc_read_1(sc, ARR); 617 618 /* 619 * If the allocation failed, requeue the packet and retry. 620 */ 621 if (packet & ARR_FAILED) { 622 IFQ_DRV_PREPEND(&ifp->if_snd, m); 623 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 624 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 625 smc_start_locked(ifp); 626 SMC_UNLOCK(sc); 627 return; 628 } 629 630 /* 631 * Tell the device to write to our packet number. 632 */ 633 smc_write_1(sc, PNR, packet); 634 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 635 636 /* 637 * Tell the device how long the packet is (including control data). 638 */ 639 len = m_length(m, 0); 640 len += PKT_CTRL_DATA_LEN; 641 smc_write_2(sc, DATA0, 0); 642 smc_write_2(sc, DATA0, len); 643 644 /* 645 * Push the data out to the device. 646 */ 647 data = NULL; 648 last_len = 0; 649 for (; m != NULL; m = m->m_next) { 650 data = mtod(m, uint8_t *); 651 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 652 last_len = m->m_len; 653 } 654 655 /* 656 * Push out the control byte and and the odd byte if needed. 657 */ 658 if ((len & 1) != 0 && data != NULL) 659 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 660 else 661 smc_write_2(sc, DATA0, 0); 662 663 /* 664 * Unmask the TX empty interrupt. 665 */ 666 sc->smc_mask |= TX_EMPTY_INT; 667 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 668 smc_write_1(sc, MSK, sc->smc_mask); 669 670 /* 671 * Enqueue the packet. 672 */ 673 smc_mmu_wait(sc); 674 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 675 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 676 677 /* 678 * Finish up. 679 */ 680 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 681 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 682 SMC_UNLOCK(sc); 683 BPF_MTAP(ifp, m0); 684 m_freem(m0); 685 686 next_packet: 687 /* 688 * See if there's anything else to do. 689 */ 690 smc_start(ifp); 691 } 692 693 static void 694 smc_task_rx(void *context, int pending) 695 { 696 u_int packet, status, len; 697 uint8_t *data; 698 struct ifnet *ifp; 699 struct smc_softc *sc; 700 struct mbuf *m, *mhead, *mtail; 701 702 (void)pending; 703 ifp = (struct ifnet *)context; 704 sc = ifp->if_softc; 705 mhead = mtail = NULL; 706 707 SMC_LOCK(sc); 708 709 packet = smc_read_1(sc, FIFO_RX); 710 while ((packet & FIFO_EMPTY) == 0) { 711 /* 712 * Grab an mbuf and attach a cluster. 713 */ 714 MGETHDR(m, M_NOWAIT, MT_DATA); 715 if (m == NULL) { 716 break; 717 } 718 if (!(MCLGET(m, M_NOWAIT))) { 719 m_freem(m); 720 break; 721 } 722 723 /* 724 * Point to the start of the packet. 725 */ 726 smc_select_bank(sc, 2); 727 smc_write_1(sc, PNR, packet); 728 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 729 730 /* 731 * Grab status and packet length. 732 */ 733 status = smc_read_2(sc, DATA0); 734 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 735 len -= 6; 736 if (status & RX_ODDFRM) 737 len += 1; 738 739 /* 740 * Check for errors. 741 */ 742 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 743 smc_mmu_wait(sc); 744 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 745 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 746 m_freem(m); 747 break; 748 } 749 750 /* 751 * Set the mbuf up the way we want it. 752 */ 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 755 m_adj(m, ETHER_ALIGN); 756 757 /* 758 * Pull the packet out of the device. Make sure we're in the 759 * right bank first as things may have changed while we were 760 * allocating our mbuf. 761 */ 762 smc_select_bank(sc, 2); 763 smc_write_1(sc, PNR, packet); 764 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 765 data = mtod(m, uint8_t *); 766 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 767 if (len & 1) { 768 data += len & ~1; 769 *data = smc_read_1(sc, DATA0); 770 } 771 772 /* 773 * Tell the device we're done. 774 */ 775 smc_mmu_wait(sc); 776 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 777 if (m == NULL) { 778 break; 779 } 780 781 if (mhead == NULL) { 782 mhead = mtail = m; 783 m->m_next = NULL; 784 } else { 785 mtail->m_next = m; 786 mtail = m; 787 } 788 packet = smc_read_1(sc, FIFO_RX); 789 } 790 791 sc->smc_mask |= RCV_INT; 792 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 793 smc_write_1(sc, MSK, sc->smc_mask); 794 795 SMC_UNLOCK(sc); 796 797 while (mhead != NULL) { 798 m = mhead; 799 mhead = mhead->m_next; 800 m->m_next = NULL; 801 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 802 (*ifp->if_input)(ifp, m); 803 } 804 } 805 806 #ifdef DEVICE_POLLING 807 static int 808 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 809 { 810 struct smc_softc *sc; 811 812 sc = ifp->if_softc; 813 814 SMC_LOCK(sc); 815 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 816 SMC_UNLOCK(sc); 817 return (0); 818 } 819 SMC_UNLOCK(sc); 820 821 if (cmd == POLL_AND_CHECK_STATUS) 822 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 823 return (0); 824 } 825 #endif 826 827 static int 828 smc_intr(void *context) 829 { 830 struct smc_softc *sc; 831 uint32_t curbank; 832 833 sc = (struct smc_softc *)context; 834 835 /* 836 * Save current bank and restore later in this function 837 */ 838 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 839 840 /* 841 * Block interrupts in order to let smc_task_intr to kick in 842 */ 843 smc_select_bank(sc, 2); 844 smc_write_1(sc, MSK, 0); 845 846 /* Restore bank */ 847 smc_select_bank(sc, curbank); 848 849 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 850 return (FILTER_HANDLED); 851 } 852 853 static void 854 smc_task_intr(void *context, int pending) 855 { 856 struct smc_softc *sc; 857 struct ifnet *ifp; 858 u_int status, packet, counter, tcr; 859 860 (void)pending; 861 ifp = (struct ifnet *)context; 862 sc = ifp->if_softc; 863 864 SMC_LOCK(sc); 865 866 smc_select_bank(sc, 2); 867 868 /* 869 * Find out what interrupts are flagged. 870 */ 871 status = smc_read_1(sc, IST) & sc->smc_mask; 872 873 /* 874 * Transmit error 875 */ 876 if (status & TX_INT) { 877 /* 878 * Kill off the packet if there is one and re-enable transmit. 879 */ 880 packet = smc_read_1(sc, FIFO_TX); 881 if ((packet & FIFO_EMPTY) == 0) { 882 callout_stop(&sc->smc_watchdog); 883 smc_select_bank(sc, 2); 884 smc_write_1(sc, PNR, packet); 885 smc_write_2(sc, PTR, 0 | PTR_READ | 886 PTR_AUTO_INCR); 887 smc_select_bank(sc, 0); 888 tcr = smc_read_2(sc, EPHSR); 889 #if 0 890 if ((tcr & EPHSR_TX_SUC) == 0) 891 device_printf(sc->smc_dev, 892 "bad packet\n"); 893 #endif 894 smc_select_bank(sc, 2); 895 smc_mmu_wait(sc); 896 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 897 898 smc_select_bank(sc, 0); 899 tcr = smc_read_2(sc, TCR); 900 tcr |= TCR_TXENA | TCR_PAD_EN; 901 smc_write_2(sc, TCR, tcr); 902 smc_select_bank(sc, 2); 903 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 904 } 905 906 /* 907 * Ack the interrupt. 908 */ 909 smc_write_1(sc, ACK, TX_INT); 910 } 911 912 /* 913 * Receive 914 */ 915 if (status & RCV_INT) { 916 smc_write_1(sc, ACK, RCV_INT); 917 sc->smc_mask &= ~RCV_INT; 918 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx); 919 } 920 921 /* 922 * Allocation 923 */ 924 if (status & ALLOC_INT) { 925 smc_write_1(sc, ACK, ALLOC_INT); 926 sc->smc_mask &= ~ALLOC_INT; 927 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 928 } 929 930 /* 931 * Receive overrun 932 */ 933 if (status & RX_OVRN_INT) { 934 smc_write_1(sc, ACK, RX_OVRN_INT); 935 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 936 } 937 938 /* 939 * Transmit empty 940 */ 941 if (status & TX_EMPTY_INT) { 942 smc_write_1(sc, ACK, TX_EMPTY_INT); 943 sc->smc_mask &= ~TX_EMPTY_INT; 944 callout_stop(&sc->smc_watchdog); 945 946 /* 947 * Update collision stats. 948 */ 949 smc_select_bank(sc, 0); 950 counter = smc_read_2(sc, ECR); 951 smc_select_bank(sc, 2); 952 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 953 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 954 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 955 956 /* 957 * See if there are any packets to transmit. 958 */ 959 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx); 960 } 961 962 /* 963 * Update the interrupt mask. 964 */ 965 smc_select_bank(sc, 2); 966 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 967 smc_write_1(sc, MSK, sc->smc_mask); 968 969 SMC_UNLOCK(sc); 970 } 971 972 static uint32_t 973 smc_mii_bitbang_read(device_t dev) 974 { 975 struct smc_softc *sc; 976 uint32_t val; 977 978 sc = device_get_softc(dev); 979 980 SMC_ASSERT_LOCKED(sc); 981 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 982 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 983 device_get_nameunit(sc->smc_dev), 984 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 985 986 val = smc_read_2(sc, MGMT); 987 smc_barrier(sc, MGMT, 2, 988 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 989 990 return (val); 991 } 992 993 static void 994 smc_mii_bitbang_write(device_t dev, uint32_t val) 995 { 996 struct smc_softc *sc; 997 998 sc = device_get_softc(dev); 999 1000 SMC_ASSERT_LOCKED(sc); 1001 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 1002 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 1003 device_get_nameunit(sc->smc_dev), 1004 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 1005 1006 smc_write_2(sc, MGMT, val); 1007 smc_barrier(sc, MGMT, 2, 1008 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1009 } 1010 1011 int 1012 smc_miibus_readreg(device_t dev, int phy, int reg) 1013 { 1014 struct smc_softc *sc; 1015 int val; 1016 1017 sc = device_get_softc(dev); 1018 1019 SMC_LOCK(sc); 1020 1021 smc_select_bank(sc, 3); 1022 1023 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1024 1025 SMC_UNLOCK(sc); 1026 return (val); 1027 } 1028 1029 int 1030 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1031 { 1032 struct smc_softc *sc; 1033 1034 sc = device_get_softc(dev); 1035 1036 SMC_LOCK(sc); 1037 1038 smc_select_bank(sc, 3); 1039 1040 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1041 1042 SMC_UNLOCK(sc); 1043 return (0); 1044 } 1045 1046 void 1047 smc_miibus_statchg(device_t dev) 1048 { 1049 struct smc_softc *sc; 1050 struct mii_data *mii; 1051 uint16_t tcr; 1052 1053 sc = device_get_softc(dev); 1054 mii = device_get_softc(sc->smc_miibus); 1055 1056 SMC_LOCK(sc); 1057 1058 smc_select_bank(sc, 0); 1059 tcr = smc_read_2(sc, TCR); 1060 1061 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1062 tcr |= TCR_SWFDUP; 1063 else 1064 tcr &= ~TCR_SWFDUP; 1065 1066 smc_write_2(sc, TCR, tcr); 1067 1068 SMC_UNLOCK(sc); 1069 } 1070 1071 static int 1072 smc_mii_ifmedia_upd(struct ifnet *ifp) 1073 { 1074 struct smc_softc *sc; 1075 struct mii_data *mii; 1076 1077 sc = ifp->if_softc; 1078 if (sc->smc_miibus == NULL) 1079 return (ENXIO); 1080 1081 mii = device_get_softc(sc->smc_miibus); 1082 return (mii_mediachg(mii)); 1083 } 1084 1085 static void 1086 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1087 { 1088 struct smc_softc *sc; 1089 struct mii_data *mii; 1090 1091 sc = ifp->if_softc; 1092 if (sc->smc_miibus == NULL) 1093 return; 1094 1095 mii = device_get_softc(sc->smc_miibus); 1096 mii_pollstat(mii); 1097 ifmr->ifm_active = mii->mii_media_active; 1098 ifmr->ifm_status = mii->mii_media_status; 1099 } 1100 1101 static void 1102 smc_mii_tick(void *context) 1103 { 1104 struct smc_softc *sc; 1105 1106 sc = (struct smc_softc *)context; 1107 1108 if (sc->smc_miibus == NULL) 1109 return; 1110 1111 SMC_UNLOCK(sc); 1112 1113 mii_tick(device_get_softc(sc->smc_miibus)); 1114 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1115 } 1116 1117 static void 1118 smc_mii_mediachg(struct smc_softc *sc) 1119 { 1120 1121 if (sc->smc_miibus == NULL) 1122 return; 1123 mii_mediachg(device_get_softc(sc->smc_miibus)); 1124 } 1125 1126 static int 1127 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1128 { 1129 struct mii_data *mii; 1130 1131 if (sc->smc_miibus == NULL) 1132 return (EINVAL); 1133 1134 mii = device_get_softc(sc->smc_miibus); 1135 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1136 } 1137 1138 static void 1139 smc_reset(struct smc_softc *sc) 1140 { 1141 u_int ctr; 1142 1143 SMC_ASSERT_LOCKED(sc); 1144 1145 smc_select_bank(sc, 2); 1146 1147 /* 1148 * Mask all interrupts. 1149 */ 1150 smc_write_1(sc, MSK, 0); 1151 1152 /* 1153 * Tell the device to reset. 1154 */ 1155 smc_select_bank(sc, 0); 1156 smc_write_2(sc, RCR, RCR_SOFT_RST); 1157 1158 /* 1159 * Set up the configuration register. 1160 */ 1161 smc_select_bank(sc, 1); 1162 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1163 DELAY(1); 1164 1165 /* 1166 * Turn off transmit and receive. 1167 */ 1168 smc_select_bank(sc, 0); 1169 smc_write_2(sc, TCR, 0); 1170 smc_write_2(sc, RCR, 0); 1171 1172 /* 1173 * Set up the control register. 1174 */ 1175 smc_select_bank(sc, 1); 1176 ctr = smc_read_2(sc, CTRL); 1177 ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE; 1178 smc_write_2(sc, CTRL, ctr); 1179 1180 /* 1181 * Reset the MMU. 1182 */ 1183 smc_select_bank(sc, 2); 1184 smc_mmu_wait(sc); 1185 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1186 } 1187 1188 static void 1189 smc_enable(struct smc_softc *sc) 1190 { 1191 struct ifnet *ifp; 1192 1193 SMC_ASSERT_LOCKED(sc); 1194 ifp = sc->smc_ifp; 1195 1196 /* 1197 * Set up the receive/PHY control register. 1198 */ 1199 smc_select_bank(sc, 0); 1200 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1201 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1202 1203 /* 1204 * Set up the transmit and receive control registers. 1205 */ 1206 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1207 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1208 1209 /* 1210 * Set up the interrupt mask. 1211 */ 1212 smc_select_bank(sc, 2); 1213 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1214 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1215 smc_write_1(sc, MSK, sc->smc_mask); 1216 } 1217 1218 static void 1219 smc_stop(struct smc_softc *sc) 1220 { 1221 1222 SMC_ASSERT_LOCKED(sc); 1223 1224 /* 1225 * Turn off callouts. 1226 */ 1227 callout_stop(&sc->smc_watchdog); 1228 callout_stop(&sc->smc_mii_tick_ch); 1229 1230 /* 1231 * Mask all interrupts. 1232 */ 1233 smc_select_bank(sc, 2); 1234 sc->smc_mask = 0; 1235 smc_write_1(sc, MSK, 0); 1236 #ifdef DEVICE_POLLING 1237 ether_poll_deregister(sc->smc_ifp); 1238 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1239 #endif 1240 1241 /* 1242 * Disable transmit and receive. 1243 */ 1244 smc_select_bank(sc, 0); 1245 smc_write_2(sc, TCR, 0); 1246 smc_write_2(sc, RCR, 0); 1247 1248 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1249 } 1250 1251 static void 1252 smc_watchdog(void *arg) 1253 { 1254 struct smc_softc *sc; 1255 1256 sc = (struct smc_softc *)arg; 1257 device_printf(sc->smc_dev, "watchdog timeout\n"); 1258 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr); 1259 } 1260 1261 static void 1262 smc_init(void *context) 1263 { 1264 struct smc_softc *sc; 1265 1266 sc = (struct smc_softc *)context; 1267 SMC_LOCK(sc); 1268 smc_init_locked(sc); 1269 SMC_UNLOCK(sc); 1270 } 1271 1272 static void 1273 smc_init_locked(struct smc_softc *sc) 1274 { 1275 struct ifnet *ifp; 1276 1277 SMC_ASSERT_LOCKED(sc); 1278 ifp = sc->smc_ifp; 1279 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1280 return; 1281 1282 smc_reset(sc); 1283 smc_enable(sc); 1284 1285 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1286 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1287 1288 smc_start_locked(ifp); 1289 1290 if (sc->smc_mii_tick != NULL) 1291 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1292 1293 #ifdef DEVICE_POLLING 1294 SMC_UNLOCK(sc); 1295 ether_poll_register(smc_poll, ifp); 1296 SMC_LOCK(sc); 1297 ifp->if_capenable |= IFCAP_POLLING; 1298 #endif 1299 } 1300 1301 static int 1302 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1303 { 1304 struct smc_softc *sc; 1305 int error; 1306 1307 sc = ifp->if_softc; 1308 error = 0; 1309 1310 switch (cmd) { 1311 case SIOCSIFFLAGS: 1312 if ((ifp->if_flags & IFF_UP) == 0 && 1313 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1314 SMC_LOCK(sc); 1315 smc_stop(sc); 1316 SMC_UNLOCK(sc); 1317 } else { 1318 smc_init(sc); 1319 if (sc->smc_mii_mediachg != NULL) 1320 sc->smc_mii_mediachg(sc); 1321 } 1322 break; 1323 1324 case SIOCADDMULTI: 1325 case SIOCDELMULTI: 1326 /* XXX 1327 SMC_LOCK(sc); 1328 smc_setmcast(sc); 1329 SMC_UNLOCK(sc); 1330 */ 1331 error = EINVAL; 1332 break; 1333 1334 case SIOCGIFMEDIA: 1335 case SIOCSIFMEDIA: 1336 if (sc->smc_mii_mediaioctl == NULL) { 1337 error = EINVAL; 1338 break; 1339 } 1340 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1341 break; 1342 1343 default: 1344 error = ether_ioctl(ifp, cmd, data); 1345 break; 1346 } 1347 1348 return (error); 1349 }
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