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sys/dev/sn/if_sn.c
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1 /*- 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o Setting of the hardware address isn't supported. 68 * o Hardware padding isn't used. 69 */ 70 71 /* 72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 73 * 74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 75 * BSD-nomads, Tokyo, Japan. 76 */ 77 /* 78 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 79 * Special thanks to itojun@itojun.org 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/errno.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/socket.h> 88 #include <sys/syslog.h> 89 90 #include <sys/module.h> 91 #include <sys/bus.h> 92 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/rman.h> 96 97 #include <net/ethernet.h> 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_dl.h> 101 #include <net/if_types.h> 102 #include <net/if_mib.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 #include <net/bpf.h> 112 #include <net/bpfdesc.h> 113 114 #include <dev/sn/if_snreg.h> 115 #include <dev/sn/if_snvar.h> 116 117 /* Exported variables */ 118 devclass_t sn_devclass; 119 120 static int snioctl(struct ifnet * ifp, u_long, caddr_t); 121 122 static void snresume(struct ifnet *); 123 124 static void sninit_locked(void *); 125 static void snstart_locked(struct ifnet *); 126 127 static void sninit(void *); 128 static void snread(struct ifnet *); 129 static void snstart(struct ifnet *); 130 static void snstop(struct sn_softc *); 131 static void snwatchdog(struct ifnet *); 132 133 static void sn_setmcast(struct sn_softc *); 134 static int sn_getmcf(struct ifnet *ifp, u_char *mcf); 135 136 /* I (GB) have been unlucky getting the hardware padding 137 * to work properly. 138 */ 139 #define SW_PAD 140 141 static const char *chip_ids[15] = { 142 NULL, NULL, NULL, 143 /* 3 */ "SMC91C90/91C92", 144 /* 4 */ "SMC91C94/91C96", 145 /* 5 */ "SMC91C95", 146 NULL, 147 /* 7 */ "SMC91C100", 148 /* 8 */ "SMC91C100FD", 149 /* 9 */ "SMC91C110", 150 NULL, NULL, 151 NULL, NULL, NULL 152 }; 153 154 int 155 sn_attach(device_t dev) 156 { 157 struct sn_softc *sc = device_get_softc(dev); 158 struct ifnet *ifp; 159 uint16_t i; 160 uint8_t *p; 161 int rev; 162 uint16_t address; 163 int err; 164 u_char eaddr[6]; 165 166 ifp = sc->ifp = if_alloc(IFT_ETHER); 167 if (ifp == NULL) { 168 device_printf(dev, "can not if_alloc()\n"); 169 return (ENOSPC); 170 } 171 172 SN_LOCK_INIT(sc); 173 snstop(sc); 174 sc->pages_wanted = -1; 175 176 if (bootverbose || 1) { 177 SMC_SELECT_BANK(sc, 3); 178 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 179 if (chip_ids[rev]) 180 device_printf(dev, " %s ", chip_ids[rev]); 181 else 182 device_printf(dev, " unsupported chip: rev %d ", rev); 183 SMC_SELECT_BANK(sc, 1); 184 i = CSR_READ_2(sc, CONFIG_REG_W); 185 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 186 } 187 188 /* 189 * Read the station address from the chip. The MAC address is bank 1, 190 * regs 4 - 9 191 */ 192 SMC_SELECT_BANK(sc, 1); 193 p = (uint8_t *) eaddr; 194 for (i = 0; i < 6; i += 2) { 195 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 196 p[i + 1] = address >> 8; 197 p[i] = address & 0xFF; 198 } 199 ifp->if_softc = sc; 200 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 201 ifp->if_mtu = ETHERMTU; 202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 203 ifp->if_start = snstart; 204 ifp->if_ioctl = snioctl; 205 ifp->if_watchdog = snwatchdog; 206 ifp->if_init = sninit; 207 ifp->if_baudrate = 10000000; 208 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 209 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 210 IFQ_SET_READY(&ifp->if_snd); 211 ifp->if_timer = 0; 212 213 ether_ifattach(ifp, eaddr); 214 215 /* 216 * Activate the interrupt so we can get card interrupts. This 217 * needs to be done last so that we don't have/hold the lock 218 * during startup to avoid LORs in the network layer. 219 */ 220 if ((err = bus_setup_intr(dev, sc->irq_res, 221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc, 222 &sc->intrhand)) != 0) { 223 sn_detach(dev); 224 return err; 225 } 226 return 0; 227 } 228 229 230 int 231 sn_detach(device_t dev) 232 { 233 struct sn_softc *sc = device_get_softc(dev); 234 struct ifnet *ifp = sc->ifp; 235 236 snstop(sc); 237 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 238 ether_ifdetach(ifp); 239 sn_deactivate(dev); 240 if_free(ifp); 241 SN_LOCK_DESTROY(sc); 242 return 0; 243 } 244 245 static void 246 sninit(void *xsc) 247 { 248 struct sn_softc *sc = xsc; 249 SN_LOCK(sc); 250 sninit_locked(sc); 251 SN_UNLOCK(sc); 252 } 253 254 /* 255 * Reset and initialize the chip 256 */ 257 static void 258 sninit_locked(void *xsc) 259 { 260 struct sn_softc *sc = xsc; 261 struct ifnet *ifp = sc->ifp; 262 int flags; 263 int mask; 264 265 SN_ASSERT_LOCKED(sc); 266 267 /* 268 * This resets the registers mostly to defaults, but doesn't affect 269 * EEPROM. After the reset cycle, we pause briefly for the chip to 270 * be happy. 271 */ 272 SMC_SELECT_BANK(sc, 0); 273 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 274 SMC_DELAY(sc); 275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 276 SMC_DELAY(sc); 277 SMC_DELAY(sc); 278 279 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 280 281 /* 282 * Set the control register to automatically release succesfully 283 * transmitted packets (making the best use out of our limited 284 * memory) and to enable the EPH interrupt on certain TX errors. 285 */ 286 SMC_SELECT_BANK(sc, 1); 287 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 288 CTR_CR_ENABLE | CTR_LE_ENABLE)); 289 290 /* Set squelch level to 240mV (default 480mV) */ 291 flags = CSR_READ_2(sc, CONFIG_REG_W); 292 flags |= CR_SET_SQLCH; 293 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 294 295 /* 296 * Reset the MMU and wait for it to be un-busy. 297 */ 298 SMC_SELECT_BANK(sc, 2); 299 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 300 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 301 ; 302 303 /* 304 * Disable all interrupts 305 */ 306 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 307 308 sn_setmcast(sc); 309 310 /* 311 * Set the transmitter control. We want it enabled. 312 */ 313 flags = TCR_ENABLE; 314 315 #ifndef SW_PAD 316 /* 317 * I (GB) have been unlucky getting this to work. 318 */ 319 flags |= TCR_PAD_ENABLE; 320 #endif /* SW_PAD */ 321 322 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 323 324 325 /* 326 * Now, enable interrupts 327 */ 328 SMC_SELECT_BANK(sc, 2); 329 330 mask = IM_EPH_INT | 331 IM_RX_OVRN_INT | 332 IM_RCV_INT | 333 IM_TX_INT; 334 335 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 336 sc->intr_mask = mask; 337 sc->pages_wanted = -1; 338 339 340 /* 341 * Mark the interface running but not active. 342 */ 343 ifp->if_drv_flags |= IFF_DRV_RUNNING; 344 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 345 346 /* 347 * Attempt to push out any waiting packets. 348 */ 349 snstart_locked(ifp); 350 } 351 352 static void 353 snstart(struct ifnet *ifp) 354 { 355 struct sn_softc *sc = ifp->if_softc; 356 SN_LOCK(sc); 357 snstart_locked(ifp); 358 SN_UNLOCK(sc); 359 } 360 361 362 static void 363 snstart_locked(struct ifnet *ifp) 364 { 365 struct sn_softc *sc = ifp->if_softc; 366 u_int len; 367 struct mbuf *m; 368 struct mbuf *top; 369 int pad; 370 int mask; 371 uint16_t length; 372 uint16_t numPages; 373 uint8_t packet_no; 374 int time_out; 375 int junk = 0; 376 377 SN_ASSERT_LOCKED(sc); 378 379 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 380 return; 381 if (sc->pages_wanted != -1) { 382 if_printf(ifp, "snstart() while memory allocation pending\n"); 383 return; 384 } 385 startagain: 386 387 /* 388 * Sneak a peek at the next packet 389 */ 390 m = ifp->if_snd.ifq_head; 391 if (m == 0) 392 return; 393 /* 394 * Compute the frame length and set pad to give an overall even 395 * number of bytes. Below we assume that the packet length is even. 396 */ 397 for (len = 0, top = m; m; m = m->m_next) 398 len += m->m_len; 399 400 pad = (len & 1); 401 402 /* 403 * We drop packets that are too large. Perhaps we should truncate 404 * them instead? 405 */ 406 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 407 if_printf(ifp, "large packet discarded (A)\n"); 408 ++ifp->if_oerrors; 409 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 410 m_freem(m); 411 goto readcheck; 412 } 413 #ifdef SW_PAD 414 415 /* 416 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 417 */ 418 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 419 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 420 421 #endif /* SW_PAD */ 422 423 length = pad + len; 424 425 /* 426 * The MMU wants the number of pages to be the number of 256 byte 427 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 428 * include space for the status word, byte count and control bytes in 429 * the allocation request. 430 */ 431 numPages = (length + 6) >> 8; 432 433 434 /* 435 * Now, try to allocate the memory 436 */ 437 SMC_SELECT_BANK(sc, 2); 438 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 439 440 /* 441 * Wait a short amount of time to see if the allocation request 442 * completes. Otherwise, I enable the interrupt and wait for 443 * completion asyncronously. 444 */ 445 446 time_out = MEMORY_WAIT_TIME; 447 do { 448 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 449 break; 450 } while (--time_out); 451 452 if (!time_out || junk > 10) { 453 454 /* 455 * No memory now. Oh well, wait until the chip finds memory 456 * later. Remember how many pages we were asking for and 457 * enable the allocation completion interrupt. Also set a 458 * watchdog in case we miss the interrupt. We mark the 459 * interface active since there is no point in attempting an 460 * snstart() until after the memory is available. 461 */ 462 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 463 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 464 sc->intr_mask = mask; 465 466 ifp->if_timer = 1; 467 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 468 sc->pages_wanted = numPages; 469 return; 470 } 471 /* 472 * The memory allocation completed. Check the results. 473 */ 474 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 475 if (packet_no & ARR_FAILED) { 476 if (junk++ > 10) 477 if_printf(ifp, "Memory allocation failed\n"); 478 goto startagain; 479 } 480 /* 481 * We have a packet number, so tell the card to use it. 482 */ 483 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 484 485 /* 486 * Point to the beginning of the packet 487 */ 488 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 489 490 /* 491 * Send the packet length (+6 for status, length and control byte) 492 * and the status word (set to zeros) 493 */ 494 CSR_WRITE_2(sc, DATA_REG_W, 0); 495 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 496 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 497 498 /* 499 * Get the packet from the kernel. This will include the Ethernet 500 * frame header, MAC Addresses etc. 501 */ 502 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 503 504 /* 505 * Push out the data to the card. 506 */ 507 for (top = m; m != 0; m = m->m_next) { 508 509 /* 510 * Push out words. 511 */ 512 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 513 m->m_len / 2); 514 515 /* 516 * Push out remaining byte. 517 */ 518 if (m->m_len & 1) 519 CSR_WRITE_1(sc, DATA_REG_B, 520 *(mtod(m, caddr_t) + m->m_len - 1)); 521 } 522 523 /* 524 * Push out padding. 525 */ 526 while (pad > 1) { 527 CSR_WRITE_2(sc, DATA_REG_W, 0); 528 pad -= 2; 529 } 530 if (pad) 531 CSR_WRITE_1(sc, DATA_REG_B, 0); 532 533 /* 534 * Push out control byte and unused packet byte The control byte is 0 535 * meaning the packet is even lengthed and no special CRC handling is 536 * desired. 537 */ 538 CSR_WRITE_2(sc, DATA_REG_W, 0); 539 540 /* 541 * Enable the interrupts and let the chipset deal with it Also set a 542 * watchdog in case we miss the interrupt. 543 */ 544 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 545 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 546 sc->intr_mask = mask; 547 548 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 549 550 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 551 ifp->if_timer = 1; 552 553 BPF_MTAP(ifp, top); 554 555 ifp->if_opackets++; 556 m_freem(top); 557 558 559 readcheck: 560 561 /* 562 * Is another packet coming in? We don't want to overflow the tiny 563 * RX FIFO. If nothing has arrived then attempt to queue another 564 * transmit packet. 565 */ 566 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 567 goto startagain; 568 return; 569 } 570 571 572 573 /* Resume a packet transmit operation after a memory allocation 574 * has completed. 575 * 576 * This is basically a hacked up copy of snstart() which handles 577 * a completed memory allocation the same way snstart() does. 578 * It then passes control to snstart to handle any other queued 579 * packets. 580 */ 581 static void 582 snresume(struct ifnet *ifp) 583 { 584 struct sn_softc *sc = ifp->if_softc; 585 u_int len; 586 struct mbuf *m; 587 struct mbuf *top; 588 int pad; 589 int mask; 590 uint16_t length; 591 uint16_t numPages; 592 uint16_t pages_wanted; 593 uint8_t packet_no; 594 595 if (sc->pages_wanted < 0) 596 return; 597 598 pages_wanted = sc->pages_wanted; 599 sc->pages_wanted = -1; 600 601 /* 602 * Sneak a peek at the next packet 603 */ 604 m = ifp->if_snd.ifq_head; 605 if (m == 0) { 606 if_printf(ifp, "snresume() with nothing to send\n"); 607 return; 608 } 609 /* 610 * Compute the frame length and set pad to give an overall even 611 * number of bytes. Below we assume that the packet length is even. 612 */ 613 for (len = 0, top = m; m; m = m->m_next) 614 len += m->m_len; 615 616 pad = (len & 1); 617 618 /* 619 * We drop packets that are too large. Perhaps we should truncate 620 * them instead? 621 */ 622 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 623 if_printf(ifp, "large packet discarded (B)\n"); 624 ++ifp->if_oerrors; 625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 626 m_freem(m); 627 return; 628 } 629 #ifdef SW_PAD 630 631 /* 632 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 633 */ 634 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 635 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 636 637 #endif /* SW_PAD */ 638 639 length = pad + len; 640 641 642 /* 643 * The MMU wants the number of pages to be the number of 256 byte 644 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 645 * include space for the status word, byte count and control bytes in 646 * the allocation request. 647 */ 648 numPages = (length + 6) >> 8; 649 650 651 SMC_SELECT_BANK(sc, 2); 652 653 /* 654 * The memory allocation completed. Check the results. If it failed, 655 * we simply set a watchdog timer and hope for the best. 656 */ 657 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 658 if (packet_no & ARR_FAILED) { 659 if_printf(ifp, "Memory allocation failed. Weird.\n"); 660 ifp->if_timer = 1; 661 goto try_start; 662 } 663 /* 664 * We have a packet number, so tell the card to use it. 665 */ 666 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 667 668 /* 669 * Now, numPages should match the pages_wanted recorded when the 670 * memory allocation was initiated. 671 */ 672 if (pages_wanted != numPages) { 673 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 674 /* 675 * If the allocation was the wrong size we simply release the 676 * memory once it is granted. Wait for the MMU to be un-busy. 677 */ 678 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 679 ; 680 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 681 682 return; 683 } 684 /* 685 * Point to the beginning of the packet 686 */ 687 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 688 689 /* 690 * Send the packet length (+6 for status, length and control byte) 691 * and the status word (set to zeros) 692 */ 693 CSR_WRITE_2(sc, DATA_REG_W, 0); 694 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 695 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 696 697 /* 698 * Get the packet from the kernel. This will include the Ethernet 699 * frame header, MAC Addresses etc. 700 */ 701 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 702 703 /* 704 * Push out the data to the card. 705 */ 706 for (top = m; m != 0; m = m->m_next) { 707 708 /* 709 * Push out words. 710 */ 711 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 712 m->m_len / 2); 713 /* 714 * Push out remaining byte. 715 */ 716 if (m->m_len & 1) 717 CSR_WRITE_1(sc, DATA_REG_B, 718 *(mtod(m, caddr_t) + m->m_len - 1)); 719 } 720 721 /* 722 * Push out padding. 723 */ 724 while (pad > 1) { 725 CSR_WRITE_2(sc, DATA_REG_W, 0); 726 pad -= 2; 727 } 728 if (pad) 729 CSR_WRITE_1(sc, DATA_REG_B, 0); 730 731 /* 732 * Push out control byte and unused packet byte The control byte is 0 733 * meaning the packet is even lengthed and no special CRC handling is 734 * desired. 735 */ 736 CSR_WRITE_2(sc, DATA_REG_W, 0); 737 738 /* 739 * Enable the interrupts and let the chipset deal with it Also set a 740 * watchdog in case we miss the interrupt. 741 */ 742 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 743 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 744 sc->intr_mask = mask; 745 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 746 747 BPF_MTAP(ifp, top); 748 749 ifp->if_opackets++; 750 m_freem(top); 751 752 try_start: 753 754 /* 755 * Now pass control to snstart() to queue any additional packets 756 */ 757 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 758 snstart(ifp); 759 760 /* 761 * We've sent something, so we're active. Set a watchdog in case the 762 * TX_EMPTY interrupt is lost. 763 */ 764 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 765 ifp->if_timer = 1; 766 767 return; 768 } 769 770 771 void 772 sn_intr(void *arg) 773 { 774 int status, interrupts; 775 struct sn_softc *sc = (struct sn_softc *) arg; 776 struct ifnet *ifp = sc->ifp; 777 778 /* 779 * Chip state registers 780 */ 781 uint8_t mask; 782 uint8_t packet_no; 783 uint16_t tx_status; 784 uint16_t card_stats; 785 786 SN_LOCK(sc); 787 788 /* 789 * Clear the watchdog. 790 */ 791 ifp->if_timer = 0; 792 793 SMC_SELECT_BANK(sc, 2); 794 795 /* 796 * Obtain the current interrupt mask and clear the hardware mask 797 * while servicing interrupts. 798 */ 799 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 800 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 801 802 /* 803 * Get the set of interrupts which occurred and eliminate any which 804 * are masked. 805 */ 806 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 807 status = interrupts & mask; 808 809 /* 810 * Now, process each of the interrupt types. 811 */ 812 813 /* 814 * Receive Overrun. 815 */ 816 if (status & IM_RX_OVRN_INT) { 817 /* 818 * Acknowlege Interrupt 819 */ 820 SMC_SELECT_BANK(sc, 2); 821 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 822 823 ++ifp->if_ierrors; 824 } 825 /* 826 * Got a packet. 827 */ 828 if (status & IM_RCV_INT) { 829 int packet_number; 830 831 SMC_SELECT_BANK(sc, 2); 832 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 833 834 if (packet_number & FIFO_REMPTY) { 835 /* 836 * we got called , but nothing was on the FIFO 837 */ 838 printf("sn: Receive interrupt with nothing on FIFO\n"); 839 goto out; 840 } 841 snread(ifp); 842 } 843 /* 844 * An on-card memory allocation came through. 845 */ 846 if (status & IM_ALLOC_INT) { 847 /* 848 * Disable this interrupt. 849 */ 850 mask &= ~IM_ALLOC_INT; 851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 852 snresume(ifp); 853 } 854 /* 855 * TX Completion. Handle a transmit error message. This will only be 856 * called when there is an error, because of the AUTO_RELEASE mode. 857 */ 858 if (status & IM_TX_INT) { 859 /* 860 * Acknowlege Interrupt 861 */ 862 SMC_SELECT_BANK(sc, 2); 863 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 864 865 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 866 packet_no &= FIFO_TX_MASK; 867 868 /* 869 * select this as the packet to read from 870 */ 871 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 872 873 /* 874 * Position the pointer to the first word from this packet 875 */ 876 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 877 878 /* 879 * Fetch the TX status word. The value found here will be a 880 * copy of the EPH_STATUS_REG_W at the time the transmit 881 * failed. 882 */ 883 tx_status = CSR_READ_2(sc, DATA_REG_W); 884 885 if (tx_status & EPHSR_TX_SUC) { 886 device_printf(sc->dev, 887 "Successful packet caused interrupt\n"); 888 } else { 889 ++ifp->if_oerrors; 890 } 891 892 if (tx_status & EPHSR_LATCOL) 893 ++ifp->if_collisions; 894 895 /* 896 * Some of these errors will have disabled transmit. 897 * Re-enable transmit now. 898 */ 899 SMC_SELECT_BANK(sc, 0); 900 901 #ifdef SW_PAD 902 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 903 #else 904 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 905 #endif /* SW_PAD */ 906 907 /* 908 * kill the failed packet. Wait for the MMU to be un-busy. 909 */ 910 SMC_SELECT_BANK(sc, 2); 911 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 912 ; 913 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 914 915 /* 916 * Attempt to queue more transmits. 917 */ 918 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 919 snstart_locked(ifp); 920 } 921 /* 922 * Transmit underrun. We use this opportunity to update transmit 923 * statistics from the card. 924 */ 925 if (status & IM_TX_EMPTY_INT) { 926 927 /* 928 * Acknowlege Interrupt 929 */ 930 SMC_SELECT_BANK(sc, 2); 931 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 932 933 /* 934 * Disable this interrupt. 935 */ 936 mask &= ~IM_TX_EMPTY_INT; 937 938 SMC_SELECT_BANK(sc, 0); 939 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 940 941 /* 942 * Single collisions 943 */ 944 ifp->if_collisions += card_stats & ECR_COLN_MASK; 945 946 /* 947 * Multiple collisions 948 */ 949 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 950 951 SMC_SELECT_BANK(sc, 2); 952 953 /* 954 * Attempt to enqueue some more stuff. 955 */ 956 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 957 snstart_locked(ifp); 958 } 959 /* 960 * Some other error. Try to fix it by resetting the adapter. 961 */ 962 if (status & IM_EPH_INT) { 963 snstop(sc); 964 sninit_locked(sc); 965 } 966 967 out: 968 /* 969 * Handled all interrupt sources. 970 */ 971 972 SMC_SELECT_BANK(sc, 2); 973 974 /* 975 * Reestablish interrupts from mask which have not been deselected 976 * during this interrupt. Note that the hardware mask, which was set 977 * to 0x00 at the start of this service routine, may have been 978 * updated by one or more of the interrupt handers and we must let 979 * those new interrupts stay enabled here. 980 */ 981 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 982 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 983 sc->intr_mask = mask; 984 SN_UNLOCK(sc); 985 } 986 987 static void 988 snread(struct ifnet *ifp) 989 { 990 struct sn_softc *sc = ifp->if_softc; 991 struct ether_header *eh; 992 struct mbuf *m; 993 short status; 994 int packet_number; 995 uint16_t packet_length; 996 uint8_t *data; 997 998 SMC_SELECT_BANK(sc, 2); 999 #if 0 1000 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1001 1002 if (packet_number & FIFO_REMPTY) { 1003 1004 /* 1005 * we got called , but nothing was on the FIFO 1006 */ 1007 printf("sn: Receive interrupt with nothing on FIFO\n"); 1008 return; 1009 } 1010 #endif 1011 read_another: 1012 1013 /* 1014 * Start reading from the start of the packet. Since PTR_RCV is set, 1015 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1016 */ 1017 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1018 1019 /* 1020 * First two words are status and packet_length 1021 */ 1022 status = CSR_READ_2(sc, DATA_REG_W); 1023 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1024 1025 /* 1026 * The packet length contains 3 extra words: status, length, and a 1027 * extra word with the control byte. 1028 */ 1029 packet_length -= 6; 1030 1031 /* 1032 * Account for receive errors and discard. 1033 */ 1034 if (status & RS_ERRORS) { 1035 ++ifp->if_ierrors; 1036 goto out; 1037 } 1038 /* 1039 * A packet is received. 1040 */ 1041 1042 /* 1043 * Adjust for odd-length packet. 1044 */ 1045 if (status & RS_ODDFRAME) 1046 packet_length++; 1047 1048 /* 1049 * Allocate a header mbuf from the kernel. 1050 */ 1051 MGETHDR(m, M_DONTWAIT, MT_DATA); 1052 if (m == NULL) 1053 goto out; 1054 1055 m->m_pkthdr.rcvif = ifp; 1056 m->m_pkthdr.len = m->m_len = packet_length; 1057 1058 /* 1059 * Attach an mbuf cluster 1060 */ 1061 MCLGET(m, M_DONTWAIT); 1062 1063 /* 1064 * Insist on getting a cluster 1065 */ 1066 if ((m->m_flags & M_EXT) == 0) { 1067 m_freem(m); 1068 ++ifp->if_ierrors; 1069 printf("sn: snread() kernel memory allocation problem\n"); 1070 goto out; 1071 } 1072 eh = mtod(m, struct ether_header *); 1073 1074 /* 1075 * Get packet, including link layer address, from interface. 1076 */ 1077 data = (uint8_t *) eh; 1078 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1079 if (packet_length & 1) { 1080 data += packet_length & ~1; 1081 *data = CSR_READ_1(sc, DATA_REG_B); 1082 } 1083 ++ifp->if_ipackets; 1084 1085 /* 1086 * Remove link layer addresses and whatnot. 1087 */ 1088 m->m_pkthdr.len = m->m_len = packet_length; 1089 1090 /* 1091 * Drop locks before calling if_input() since it may re-enter 1092 * snstart() in the netisr case. This would result in a 1093 * lock reversal. Better performance might be obtained by 1094 * chaining all packets received, dropping the lock, and then 1095 * calling if_input() on each one. 1096 */ 1097 SN_UNLOCK(sc); 1098 (*ifp->if_input)(ifp, m); 1099 SN_LOCK(sc); 1100 1101 out: 1102 1103 /* 1104 * Error or good, tell the card to get rid of this packet Wait for 1105 * the MMU to be un-busy. 1106 */ 1107 SMC_SELECT_BANK(sc, 2); 1108 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1109 ; 1110 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1111 1112 /* 1113 * Check whether another packet is ready 1114 */ 1115 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1116 if (packet_number & FIFO_REMPTY) { 1117 return; 1118 } 1119 goto read_another; 1120 } 1121 1122 1123 /* 1124 * Handle IOCTLS. This function is completely stolen from if_ep.c 1125 * As with its progenitor, it does not handle hardware address 1126 * changes. 1127 */ 1128 static int 1129 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1130 { 1131 struct sn_softc *sc = ifp->if_softc; 1132 int error = 0; 1133 1134 switch (cmd) { 1135 case SIOCSIFFLAGS: 1136 SN_LOCK(sc); 1137 if ((ifp->if_flags & IFF_UP) == 0 && 1138 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1139 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1140 snstop(sc); 1141 } else { 1142 /* reinitialize card on any parameter change */ 1143 sninit_locked(sc); 1144 } 1145 SN_UNLOCK(sc); 1146 break; 1147 1148 case SIOCADDMULTI: 1149 case SIOCDELMULTI: 1150 /* update multicast filter list. */ 1151 SN_LOCK(sc); 1152 sn_setmcast(sc); 1153 error = 0; 1154 SN_UNLOCK(sc); 1155 break; 1156 default: 1157 error = ether_ioctl(ifp, cmd, data); 1158 break; 1159 } 1160 return (error); 1161 } 1162 1163 static void 1164 snwatchdog(struct ifnet *ifp) 1165 { 1166 sn_intr(ifp->if_softc); 1167 } 1168 1169 1170 /* 1. zero the interrupt mask 1171 * 2. clear the enable receive flag 1172 * 3. clear the enable xmit flags 1173 */ 1174 static void 1175 snstop(struct sn_softc *sc) 1176 { 1177 1178 struct ifnet *ifp = sc->ifp; 1179 1180 /* 1181 * Clear interrupt mask; disable all interrupts. 1182 */ 1183 SMC_SELECT_BANK(sc, 2); 1184 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1185 1186 /* 1187 * Disable transmitter and Receiver 1188 */ 1189 SMC_SELECT_BANK(sc, 0); 1190 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1191 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1192 1193 /* 1194 * Cancel watchdog. 1195 */ 1196 ifp->if_timer = 0; 1197 } 1198 1199 1200 int 1201 sn_activate(device_t dev) 1202 { 1203 struct sn_softc *sc = device_get_softc(dev); 1204 1205 sc->port_rid = 0; 1206 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1207 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1208 if (!sc->port_res) { 1209 if (bootverbose) 1210 device_printf(dev, "Cannot allocate ioport\n"); 1211 return ENOMEM; 1212 } 1213 1214 sc->irq_rid = 0; 1215 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1216 RF_ACTIVE); 1217 if (!sc->irq_res) { 1218 if (bootverbose) 1219 device_printf(dev, "Cannot allocate irq\n"); 1220 sn_deactivate(dev); 1221 return ENOMEM; 1222 } 1223 sc->bst = rman_get_bustag(sc->port_res); 1224 sc->bsh = rman_get_bushandle(sc->port_res); 1225 return (0); 1226 } 1227 1228 void 1229 sn_deactivate(device_t dev) 1230 { 1231 struct sn_softc *sc = device_get_softc(dev); 1232 1233 if (sc->intrhand) 1234 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1235 sc->intrhand = 0; 1236 if (sc->port_res) 1237 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1238 sc->port_res); 1239 sc->port_res = 0; 1240 if (sc->modem_res) 1241 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid, 1242 sc->modem_res); 1243 sc->modem_res = 0; 1244 if (sc->irq_res) 1245 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1246 sc->irq_res); 1247 sc->irq_res = 0; 1248 return; 1249 } 1250 1251 /* 1252 * Function: sn_probe(device_t dev) 1253 * 1254 * Purpose: 1255 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1256 * Tries to cause as little damage as possible if it's not a SMC chip. 1257 * Returns a 0 on success 1258 * 1259 * Algorithm: 1260 * (1) see if the high byte of BANK_SELECT is 0x33 1261 * (2) compare the ioaddr with the base register's address 1262 * (3) see if I recognize the chip ID in the appropriate register 1263 * 1264 * 1265 */ 1266 int 1267 sn_probe(device_t dev) 1268 { 1269 struct sn_softc *sc = device_get_softc(dev); 1270 uint16_t bank; 1271 uint16_t revision_register; 1272 uint16_t base_address_register; 1273 int err; 1274 1275 if ((err = sn_activate(dev)) != 0) 1276 return err; 1277 1278 /* 1279 * First, see if the high byte is 0x33 1280 */ 1281 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1282 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1283 #ifdef SN_DEBUG 1284 device_printf(dev, "test1 failed\n"); 1285 #endif 1286 goto error; 1287 } 1288 /* 1289 * The above MIGHT indicate a device, but I need to write to further 1290 * test this. Go to bank 0, then test that the register still 1291 * reports the high byte is 0x33. 1292 */ 1293 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1294 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1295 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1296 #ifdef SN_DEBUG 1297 device_printf(dev, "test2 failed\n"); 1298 #endif 1299 goto error; 1300 } 1301 /* 1302 * well, we've already written once, so hopefully another time won't 1303 * hurt. This time, I need to switch the bank register to bank 1, so 1304 * I can access the base address register. The contents of the 1305 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1306 * to match the I/O port address where the adapter is being probed. 1307 */ 1308 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1309 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1310 1311 if (rman_get_start(sc->port_res) != base_address_register) { 1312 1313 /* 1314 * Well, the base address register didn't match. Must not 1315 * have been a SMC chip after all. 1316 */ 1317 #ifdef SN_DEBUG 1318 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1319 "base_address_register = 0x%x\n", 1320 rman_get_start(sc->port_res), base_address_register); 1321 #endif 1322 goto error; 1323 } 1324 1325 /* 1326 * Check if the revision register is something that I recognize. 1327 * These might need to be added to later, as future revisions could 1328 * be added. 1329 */ 1330 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1331 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1332 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1333 1334 /* 1335 * I don't regonize this chip, so... 1336 */ 1337 #ifdef SN_DEBUG 1338 device_printf(dev, "test4 failed\n"); 1339 #endif 1340 goto error; 1341 } 1342 1343 /* 1344 * at this point I'll assume that the chip is an SMC9xxx. It might be 1345 * prudent to check a listing of MAC addresses against the hardware 1346 * address, or do some other tests. 1347 */ 1348 sn_deactivate(dev); 1349 return 0; 1350 error: 1351 sn_deactivate(dev); 1352 return ENXIO; 1353 } 1354 1355 #define MCFSZ 8 1356 1357 static void 1358 sn_setmcast(struct sn_softc *sc) 1359 { 1360 struct ifnet *ifp = sc->ifp; 1361 int flags; 1362 uint8_t mcf[MCFSZ]; 1363 1364 SN_ASSERT_LOCKED(sc); 1365 1366 /* 1367 * Set the receiver filter. We want receive enabled and auto strip 1368 * of CRC from received packet. If we are promiscuous then set that 1369 * bit too. 1370 */ 1371 flags = RCR_ENABLE | RCR_STRIP_CRC; 1372 1373 if (ifp->if_flags & IFF_PROMISC) { 1374 flags |= RCR_PROMISC | RCR_ALMUL; 1375 } else if (ifp->if_flags & IFF_ALLMULTI) { 1376 flags |= RCR_ALMUL; 1377 } else { 1378 if (sn_getmcf(ifp, mcf)) { 1379 /* set filter */ 1380 SMC_SELECT_BANK(sc, 3); 1381 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1382 ((uint16_t)mcf[1] << 8) | mcf[0]); 1383 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1384 ((uint16_t)mcf[3] << 8) | mcf[2]); 1385 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1386 ((uint16_t)mcf[5] << 8) | mcf[4]); 1387 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1388 ((uint16_t)mcf[7] << 8) | mcf[6]); 1389 } else { 1390 flags |= RCR_ALMUL; 1391 } 1392 } 1393 SMC_SELECT_BANK(sc, 0); 1394 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1395 } 1396 1397 static int 1398 sn_getmcf(struct ifnet *ifp, uint8_t *mcf) 1399 { 1400 int i; 1401 uint32_t index, index2; 1402 uint8_t *af = mcf; 1403 struct ifmultiaddr *ifma; 1404 1405 bzero(mcf, MCFSZ); 1406 1407 IF_ADDR_LOCK(ifp); 1408 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1409 if (ifma->ifma_addr->sa_family != AF_LINK) { 1410 IF_ADDR_UNLOCK(ifp); 1411 return 0; 1412 } 1413 index = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1414 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f; 1415 index2 = 0; 1416 for (i = 0; i < 6; i++) { 1417 index2 <<= 1; 1418 index2 |= (index & 0x01); 1419 index >>= 1; 1420 } 1421 af[index2 >> 3] |= 1 << (index2 & 7); 1422 } 1423 IF_ADDR_UNLOCK(ifp); 1424 return 1; /* use multicast filter */ 1425 }
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