The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/snc/dp83932var.h

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    1 /*      $FreeBSD: releng/5.3/sys/dev/snc/dp83932var.h 110644 2003-02-10 13:31:49Z nyan $        */
    2 /*      $NecBSD: dp83932var.h,v 1.3 1999/01/24 01:39:51 kmatsuda Exp $  */
    3 /*      $NetBSD: if_snvar.h,v 1.12 1998/05/01 03:42:47 scottr Exp $     */
    4 
    5 /*
    6  * [NetBSD for NEC PC-98 series]
    7  *  Copyright (c) 1997, 1998, 1999
    8  *      Kouichi Matsuda.  All rights reserved.
    9  */
   10 /*
   11  * Copyright (c) 1991   Algorithmics Ltd (http://www.algor.co.uk)
   12  * You may use, copy, and modify this program so long as you retain the
   13  * copyright line.
   14  */
   15 
   16 /*
   17  * if_snvar.h -- National Semiconductor DP8393X (SONIC) NetBSD/mac68k vars
   18  */
   19 /*
   20  * Modified for NetBSD/pc98 1.2.1 from NetBSD/mac68k 1.2D by Kouichi Matsuda.
   21  * Make adapted for NEC PC-9801-83, 84, PC-9801-103, 104, PC-9801N-25 and
   22  * PC-9801N-J02, J02R, which uses National Semiconductor DP83934AVQB as
   23  * Ethernet Controller and National Semiconductor NS46C46 as
   24  * (64 * 16 bits) Microwire Serial EEPROM.
   25  */
   26 
   27 /* borrow from arch/mac68k/dev/if_mcvar.h for debug. */
   28 #ifdef DDB
   29 #define integrate
   30 #define hide
   31 #else
   32 #define integrate       static __inline
   33 #define hide            static
   34 #endif
   35 
   36 /* NetBSD Emulation */
   37 #ifdef __NetBSD__
   38 #define splhardnet      splnet
   39 #endif
   40 #ifdef __FreeBSD__
   41 #define splhardnet      splimp
   42 #ifndef NBPG
   43 #define NBPG PAGE_SIZE
   44 #endif
   45 #ifndef PGOFSET
   46 #define PGOFSET PAGE_MASK
   47 #endif
   48 typedef unsigned long ulong;
   49 #define delay(x) DELAY(x)
   50 #endif
   51 
   52 /*
   53  * Vendor types
   54  */
   55 
   56 /*
   57  * SONIC buffers need to be aligned 16 or 32 bit aligned.
   58  * These macros calculate and verify alignment.
   59  */
   60 #define ROUNDUP(p, N)   (((int) p + N - 1) & ~(N - 1))
   61 
   62 #define SOALIGN(m, array)       (m ? (ROUNDUP(array, 4)) : (ROUNDUP(array, 2)))
   63 
   64 #define LOWER(x) ((unsigned)(x) & 0xffff)
   65 #define UPPER(x) ((unsigned)(x) >> 16)
   66 
   67 /*
   68  * Memory access macros. Since we handle SONIC in 16 bit mode (PB5X0)
   69  * and 32 bit mode (everything else) using a single GENERIC kernel
   70  * binary, all structures have to be accessed using macros which can
   71  * adjust the offsets appropriately.
   72  */
   73 /* m is not sc->bitmode, we treat m as sc. */
   74 #define SWO(m, a, o, x) (*(m)->sc_writetodesc)((m), (a), (o), (x))
   75 #define SRO(m, a, o)    (*(m)->sc_readfromdesc)((m), (a), (o))
   76 
   77 /*
   78  * Register access macros. We use bus_space_* to talk to the Sonic
   79  * registers. A mapping table is used in case a particular configuration
   80  * hooked the regs up at non-word offsets.
   81  */
   82 #define NIC_GET(sc, reg)        (*(sc)->sc_nic_get)(sc, reg)
   83 #define NIC_PUT(sc, reg, val)   (*(sc)->sc_nic_put)(sc, reg, val)
   84 
   85 #define SONIC_GETDMA(p) (p)
   86 
   87 /* pc98 does not have any write buffers to flush... */
   88 #define wbflush()
   89 
   90 /*
   91  * buffer sizes in 32 bit mode
   92  * 1 TXpkt is 4 hdr words + (3 * FRAGMAX) + 1 link word == 23 words == 92 bytes
   93  *
   94  * 1 RxPkt is 7 words == 28 bytes
   95  * 1 Rda   is 4 words == 16 bytes
   96  *
   97  * The CDA is 17 words == 68 bytes
   98  *
   99  * total space in page 0 = NTDA * 92 + NRRA * 16 + NRDA * 28 + 68
  100  */
  101 
  102 #define NRBA    16              /* # receive buffers < NRRA */
  103 #define RBAMASK (NRBA-1)
  104 #define NTDA    16              /* # transmit descriptors */
  105 #define NRRA    64              /* # receive resource descriptors */
  106 #define RRAMASK (NRRA-1)        /* the reason why NRRA must be power of two */
  107 
  108 #define FCSSIZE 4               /* size of FCS appended to packets */
  109 
  110 /*
  111  * maximum receive packet size plus 2 byte pad to make each
  112  * one aligned. 4 byte slop (required for eobc)
  113  */
  114 #define RBASIZE(sc)     (sizeof(struct ether_header) + ETHERMTU + FCSSIZE + \
  115                          ((sc)->bitmode ? 6 : 2))
  116 
  117 /*
  118  * transmit buffer area
  119  */
  120 #define TXBSIZE 1536    /* 6*2^8 -- the same size as the 8390 TXBUF */
  121 
  122 #define SN_NPAGES       2 + NRBA + (NTDA/2)
  123 
  124 typedef struct mtd {
  125         u_int32_t       mtd_vtxp;
  126         u_int32_t       mtd_vbuf;
  127         struct mbuf     *mtd_mbuf;
  128 } mtd_t;
  129 
  130 /*
  131  * The snc_softc for PC-98 if_snc.
  132  */
  133 typedef struct snc_softc {
  134         struct arpcom   sc_ethercom;
  135 #define sc_if           sc_ethercom.ac_if       /* network visible interface */
  136 
  137         device_t        sc_dev;
  138 
  139         struct resource *       ioport;
  140         int                     ioport_rid;
  141         struct resource *       iomem;
  142         int                     iomem_rid;
  143         struct resource *       irq;
  144         int                     irq_rid;
  145         void *                  irq_handle;
  146 
  147         bus_space_tag_t         sc_iot;         /* bus identifier for io */
  148         bus_space_tag_t         sc_memt;        /* bus identifier for mem */
  149         bus_space_handle_t      sc_ioh;         /* io handle */
  150         bus_space_handle_t      sc_memh;        /* bus memory handle */
  151 
  152         int             bitmode;        /* 32 bit mode == 1, 16 == 0 */
  153 
  154         u_int16_t       sncr_dcr;       /* DCR for this instance */
  155         u_int16_t       sncr_dcr2;      /* DCR2 for this instance */
  156 
  157         int             sc_rramark;     /* index into v_rra of wp */
  158         u_int32_t       v_rra[NRRA];    /* DMA addresses of v_rra */
  159         u_int32_t       v_rea;          /* ptr to the end of the rra space */
  160 
  161         int             sc_rxmark;      /* current hw pos in rda ring */
  162         int             sc_rdamark;     /* current sw pos in rda ring */
  163         int             sc_nrda;        /* total number of RDAs */
  164         u_int32_t       v_rda;
  165 
  166         u_int32_t       rbuf[NRBA];
  167 
  168         struct mtd      mtda[NTDA];
  169         int             mtd_hw;         /* idx of first mtd given to hw */
  170         int             mtd_prev;       /* idx of last mtd given to hardware */
  171         int             mtd_free;       /* next free mtd to use */
  172         int             mtd_tlinko;     /*
  173                                          * offset of tlink of last txp given
  174                                          * to SONIC. Need to clear EOL on
  175                                          * this word to add a desc.
  176                                          */
  177         int             mtd_pint;       /* Counter to set TXP_PINT */
  178 
  179         u_int32_t       v_cda;
  180 
  181         u_int8_t        curbank;        /* current window bank */
  182 
  183         struct  ifmedia sc_media;       /* supported media information */
  184 
  185         /*
  186          * NIC register access functions:
  187          */
  188         u_int16_t       (*sc_nic_get)
  189                 (struct snc_softc *, u_int8_t);
  190         void            (*sc_nic_put)
  191                 (struct snc_softc *, u_int8_t, u_int16_t);
  192 
  193         /*
  194          * Memory functions:
  195          *
  196          *      copy to/from descriptor
  197          *      copy to/from buffer
  198          *      zero bytes in buffer
  199          */
  200         void            (*sc_writetodesc)
  201                 (struct snc_softc *, u_int32_t, u_int32_t, u_int16_t);
  202         u_int16_t       (*sc_readfromdesc)
  203                 (struct snc_softc *, u_int32_t, u_int32_t);
  204         void            (*sc_copytobuf)
  205                 (struct snc_softc *, void *, u_int32_t, size_t);
  206         void            (*sc_copyfrombuf)
  207                 (struct snc_softc *, void *, u_int32_t, size_t);
  208         void            (*sc_zerobuf)
  209                 (struct snc_softc *, u_int32_t, size_t);
  210 
  211         /*
  212          * Machine-dependent functions:
  213          *
  214          *      hardware reset hook - may be NULL
  215          *      hardware init hook - may be NULL
  216          *      media change hook - may be NULL
  217          */
  218         void    (*sc_hwreset)(struct snc_softc *);
  219         void    (*sc_hwinit)(struct snc_softc *);
  220         int     (*sc_mediachange)(struct snc_softc *);
  221         void    (*sc_mediastatus)(struct snc_softc *, struct ifmediareq *);
  222 
  223         int     sc_enabled;     /* boolean; power enabled on interface */
  224 
  225         int     (*sc_enable)(struct snc_softc *);
  226         void    (*sc_disable)(struct snc_softc *);
  227 
  228         void    *sc_sh;         /* shutdownhook cookie */
  229         int     gone;
  230 
  231 #if NRND > 0
  232         rndsource_element_t     rnd_source;
  233 #endif
  234 } snc_softc_t;
  235 
  236 /*
  237  * Accessing SONIC data structures and registers as 32 bit values
  238  * makes code endianess independent.  The SONIC is however always in
  239  * bigendian mode so it is necessary to ensure that data structures shared
  240  * between the CPU and the SONIC are always in bigendian order.
  241  */
  242 
  243 /*
  244  * Receive Resource Descriptor
  245  * This structure describes the buffers into which packets
  246  * will be received.  Note that more than one packet may be
  247  * packed into a single buffer if constraints permit.
  248  */
  249 #define RXRSRC_PTRLO    0       /* buffer address LO */
  250 #define RXRSRC_PTRHI    1       /* buffer address HI */
  251 #define RXRSRC_WCLO     2       /* buffer size (16bit words) LO */
  252 #define RXRSRC_WCHI     3       /* buffer size (16bit words) HI */
  253 
  254 #define RXRSRC_SIZE(sc) (sc->bitmode ? (4 * 4) : (4 * 2))
  255 
  256 /*
  257  * Receive Descriptor
  258  * This structure holds information about packets received.
  259  */
  260 #define RXPKT_STATUS    0
  261 #define RXPKT_BYTEC     1
  262 #define RXPKT_PTRLO     2
  263 #define RXPKT_PTRHI     3
  264 #define RXPKT_SEQNO     4
  265 #define RXPKT_RLINK     5
  266 #define RXPKT_INUSE     6
  267 #define RXPKT_SIZE(sc)  (sc->bitmode ? (7 * 4) : (7 * 2))
  268 
  269 #define RBASEQ(x) (((x)>>8)&0xff)
  270 #define PSNSEQ(x) ((x) & 0xff)
  271 
  272 /*
  273  * Transmit Descriptor
  274  * This structure holds information about packets to be transmitted.
  275  */
  276 #define FRAGMAX 8               /* maximum number of fragments in a packet */
  277 
  278 #define TXP_STATUS      0       /* + transmitted packet status */
  279 #define TXP_CONFIG      1       /* transmission configuration */
  280 #define TXP_PKTSIZE     2       /* entire packet size in bytes */
  281 #define TXP_FRAGCNT     3       /* # fragments in packet */
  282 
  283 #define TXP_FRAGOFF     4       /* offset to first fragment */
  284 #define TXP_FRAGSIZE    3       /* size of each fragment desc */
  285 #define TXP_FPTRLO      0       /* ptr to packet fragment LO */
  286 #define TXP_FPTRHI      1       /* ptr to packet fragment HI */
  287 #define TXP_FSIZE       2       /* fragment size */
  288 
  289 #define TXP_WORDS       (TXP_FRAGOFF + (FRAGMAX*TXP_FRAGSIZE) + 1)      /* 1 for tlink */
  290 #define TXP_SIZE(sc)    ((sc->bitmode) ? (TXP_WORDS*4) : (TXP_WORDS*2))
  291 
  292 #define EOL     0x0001          /* end of list marker for link fields */
  293 
  294 /*
  295  * CDA, the CAM descriptor area. The SONIC has a 16 entry CAM to
  296  * match incoming addresses against. It is programmed via DMA
  297  * from a memory region.
  298  */
  299 #define MAXCAM  16      /* number of user entries in CAM */
  300 #define CDA_CAMDESC     4       /* # words i na descriptor */
  301 #define CDA_CAMEP       0       /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
  302 #define CDA_CAMAP0      1       /* CAM Address Port 1 xx-xx-YY-YY-xx-xx */
  303 #define CDA_CAMAP1      2       /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
  304 #define CDA_CAMAP2      3
  305 #define CDA_ENABLE      64      /* mask enabling CAM entries */
  306 #define CDA_SIZE(sc)    ((4*16 + 1) * ((sc->bitmode) ? 4 : 2))
  307 
  308 void    sncconfig(struct snc_softc *, int *, int, int, u_int8_t *);
  309 void    sncintr(void *);
  310 void    sncshutdown(void *);

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