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sys/dev/sound/isa/emu8000.c
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1 /* 2 * Low level EMU8000 chip driver for FreeBSD. This handles io against 3 * /dev/midi, the midi {in, out}put event queues and the event/message 4 * operation to the EMU8000 chip. 5 * 6 * (C) 1999 Seigo Tanimura 7 * 8 * Redistribution and use in source and binary forms, with or 9 * without modification, are permitted provided that the following 10 * conditions are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS 19 * IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: releng/5.2/sys/dev/sound/isa/emu8000.c 93818 2002-04-04 21:03:38Z jhb $ 32 * 33 */ 34 35 #include <dev/sound/midi/midi.h> 36 37 #include <isa/isavar.h> 38 39 static devclass_t midi_devclass; 40 41 #ifndef DDB 42 #undef DDB 43 #define DDB(x) 44 #endif /* DDB */ 45 46 /* These are the specs of EMU8000. */ 47 #define EMU8K_MAXVOICE 32 48 #define EMU8K_MAXINFO 256 49 50 #define EMU8K_IDX_DATA0 0 51 #define EMU8K_IDX_DATA1 1 52 #define EMU8K_IDX_DATA2 1 53 #define EMU8K_IDX_DATA3 2 54 #define EMU8K_IDX_PTR 2 55 56 #define EMU8K_PORT_DATA0 0 57 #define EMU8K_PORT_DATA1 0 58 #define EMU8K_PORT_DATA2 2 59 #define EMU8K_PORT_DATA3 0 60 #define EMU8K_PORT_PTR 2 61 62 #define EMU8K_DRAM_RAM 0x200000 63 #define EMU8K_DRAM_MAX 0xffffe0 64 65 /* And some convinient macros. */ 66 #define EMU8K_DMA_LEFT 0x00 67 #define EMU8K_DMA_RIGHT 0x01 68 #define EMU8K_DMA_LR 0x01 69 #define EMU8K_DMA_READ 0x00 70 #define EMU8K_DMA_WRITE 0x02 71 #define EMU8K_DMA_RW 0x02 72 #define EMU8K_DMA_MASK 0x03 73 74 /* The followings are the init array for EMU8000, originally in ADIP. */ 75 76 /* Set 1 */ 77 static u_short init1_1[32] = 78 { 79 0x03ff, 0x0030, 0x07ff, 0x0130, 0x0bff, 0x0230, 0x0fff, 0x0330, 80 0x13ff, 0x0430, 0x17ff, 0x0530, 0x1bff, 0x0630, 0x1fff, 0x0730, 81 0x23ff, 0x0830, 0x27ff, 0x0930, 0x2bff, 0x0a30, 0x2fff, 0x0b30, 82 0x33ff, 0x0c30, 0x37ff, 0x0d30, 0x3bff, 0x0e30, 0x3fff, 0x0f30, 83 }; 84 85 static u_short init1_2[32] = 86 { 87 0x43ff, 0x0030, 0x47ff, 0x0130, 0x4bff, 0x0230, 0x4fff, 0x0330, 88 0x53ff, 0x0430, 0x57ff, 0x0530, 0x5bff, 0x0630, 0x5fff, 0x0730, 89 0x63ff, 0x0830, 0x67ff, 0x0930, 0x6bff, 0x0a30, 0x6fff, 0x0b30, 90 0x73ff, 0x0c30, 0x77ff, 0x0d30, 0x7bff, 0x0e30, 0x7fff, 0x0f30, 91 }; 92 93 static u_short init1_3[32] = 94 { 95 0x83ff, 0x0030, 0x87ff, 0x0130, 0x8bff, 0x0230, 0x8fff, 0x0330, 96 0x93ff, 0x0430, 0x97ff, 0x0530, 0x9bff, 0x0630, 0x9fff, 0x0730, 97 0xa3ff, 0x0830, 0xa7ff, 0x0930, 0xabff, 0x0a30, 0xafff, 0x0b30, 98 0xb3ff, 0x0c30, 0xb7ff, 0x0d30, 0xbbff, 0x0e30, 0xbfff, 0x0f30, 99 }; 100 101 static u_short init1_4[32] = 102 { 103 0xc3ff, 0x0030, 0xc7ff, 0x0130, 0xcbff, 0x0230, 0xcfff, 0x0330, 104 0xd3ff, 0x0430, 0xd7ff, 0x0530, 0xdbff, 0x0630, 0xdfff, 0x0730, 105 0xe3ff, 0x0830, 0xe7ff, 0x0930, 0xebff, 0x0a30, 0xefff, 0x0b30, 106 0xf3ff, 0x0c30, 0xf7ff, 0x0d30, 0xfbff, 0x0e30, 0xffff, 0x0f30, 107 }; 108 109 /* Set 2 */ 110 111 static u_short init2_1[32] = 112 { 113 0x03ff, 0x8030, 0x07ff, 0x8130, 0x0bff, 0x8230, 0x0fff, 0x8330, 114 0x13ff, 0x8430, 0x17ff, 0x8530, 0x1bff, 0x8630, 0x1fff, 0x8730, 115 0x23ff, 0x8830, 0x27ff, 0x8930, 0x2bff, 0x8a30, 0x2fff, 0x8b30, 116 0x33ff, 0x8c30, 0x37ff, 0x8d30, 0x3bff, 0x8e30, 0x3fff, 0x8f30, 117 }; 118 119 static u_short init2_2[32] = 120 { 121 0x43ff, 0x8030, 0x47ff, 0x8130, 0x4bff, 0x8230, 0x4fff, 0x8330, 122 0x53ff, 0x8430, 0x57ff, 0x8530, 0x5bff, 0x8630, 0x5fff, 0x8730, 123 0x63ff, 0x8830, 0x67ff, 0x8930, 0x6bff, 0x8a30, 0x6fff, 0x8b30, 124 0x73ff, 0x8c30, 0x77ff, 0x8d30, 0x7bff, 0x8e30, 0x7fff, 0x8f30, 125 }; 126 127 static u_short init2_3[32] = 128 { 129 0x83ff, 0x8030, 0x87ff, 0x8130, 0x8bff, 0x8230, 0x8fff, 0x8330, 130 0x93ff, 0x8430, 0x97ff, 0x8530, 0x9bff, 0x8630, 0x9fff, 0x8730, 131 0xa3ff, 0x8830, 0xa7ff, 0x8930, 0xabff, 0x8a30, 0xafff, 0x8b30, 132 0xb3ff, 0x8c30, 0xb7ff, 0x8d30, 0xbbff, 0x8e30, 0xbfff, 0x8f30, 133 }; 134 135 static u_short init2_4[32] = 136 { 137 0xc3ff, 0x8030, 0xc7ff, 0x8130, 0xcbff, 0x8230, 0xcfff, 0x8330, 138 0xd3ff, 0x8430, 0xd7ff, 0x8530, 0xdbff, 0x8630, 0xdfff, 0x8730, 139 0xe3ff, 0x8830, 0xe7ff, 0x8930, 0xebff, 0x8a30, 0xefff, 0x8b30, 140 0xf3ff, 0x8c30, 0xf7ff, 0x8d30, 0xfbff, 0x8e30, 0xffff, 0x8f30, 141 }; 142 143 /* Set 3 */ 144 145 static u_short init3_1[32] = 146 { 147 0x0C10, 0x8470, 0x14FE, 0xB488, 0x167F, 0xA470, 0x18E7, 0x84B5, 148 0x1B6E, 0x842A, 0x1F1D, 0x852A, 0x0DA3, 0x8F7C, 0x167E, 0xF254, 149 0x0000, 0x842A, 0x0001, 0x852A, 0x18E6, 0x8BAA, 0x1B6D, 0xF234, 150 0x229F, 0x8429, 0x2746, 0x8529, 0x1F1C, 0x86E7, 0x229E, 0xF224, 151 }; 152 153 static u_short init3_2[32] = 154 { 155 0x0DA4, 0x8429, 0x2C29, 0x8529, 0x2745, 0x87F6, 0x2C28, 0xF254, 156 0x383B, 0x8428, 0x320F, 0x8528, 0x320E, 0x8F02, 0x1341, 0xF264, 157 0x3EB6, 0x8428, 0x3EB9, 0x8528, 0x383A, 0x8FA9, 0x3EB5, 0xF294, 158 0x3EB7, 0x8474, 0x3EBA, 0x8575, 0x3EB8, 0xC4C3, 0x3EBB, 0xC5C3, 159 }; 160 161 static u_short init3_3[32] = 162 { 163 0x0000, 0xA404, 0x0001, 0xA504, 0x141F, 0x8671, 0x14FD, 0x8287, 164 0x3EBC, 0xE610, 0x3EC8, 0x8C7B, 0x031A, 0x87E6, 0x3EC8, 0x86F7, 165 0x3EC0, 0x821E, 0x3EBE, 0xD208, 0x3EBD, 0x821F, 0x3ECA, 0x8386, 166 0x3EC1, 0x8C03, 0x3EC9, 0x831E, 0x3ECA, 0x8C4C, 0x3EBF, 0x8C55, 167 }; 168 169 static u_short init3_4[32] = 170 { 171 0x3EC9, 0xC208, 0x3EC4, 0xBC84, 0x3EC8, 0x8EAD, 0x3EC8, 0xD308, 172 0x3EC2, 0x8F7E, 0x3ECB, 0x8219, 0x3ECB, 0xD26E, 0x3EC5, 0x831F, 173 0x3EC6, 0xC308, 0x3EC3, 0xB2FF, 0x3EC9, 0x8265, 0x3EC9, 0x8319, 174 0x1342, 0xD36E, 0x3EC7, 0xB3FF, 0x0000, 0x8365, 0x1420, 0x9570, 175 }; 176 177 /* Set 4 */ 178 179 static u_short init4_1[32] = 180 { 181 0x0C10, 0x8470, 0x14FE, 0xB488, 0x167F, 0xA470, 0x18E7, 0x84B5, 182 0x1B6E, 0x842A, 0x1F1D, 0x852A, 0x0DA3, 0x0F7C, 0x167E, 0x7254, 183 0x0000, 0x842A, 0x0001, 0x852A, 0x18E6, 0x0BAA, 0x1B6D, 0x7234, 184 0x229F, 0x8429, 0x2746, 0x8529, 0x1F1C, 0x06E7, 0x229E, 0x7224, 185 }; 186 187 static u_short init4_2[32] = 188 { 189 0x0DA4, 0x8429, 0x2C29, 0x8529, 0x2745, 0x07F6, 0x2C28, 0x7254, 190 0x383B, 0x8428, 0x320F, 0x8528, 0x320E, 0x0F02, 0x1341, 0x7264, 191 0x3EB6, 0x8428, 0x3EB9, 0x8528, 0x383A, 0x0FA9, 0x3EB5, 0x7294, 192 0x3EB7, 0x8474, 0x3EBA, 0x8575, 0x3EB8, 0x44C3, 0x3EBB, 0x45C3, 193 }; 194 195 static u_short init4_3[32] = 196 { 197 0x0000, 0xA404, 0x0001, 0xA504, 0x141F, 0x0671, 0x14FD, 0x0287, 198 0x3EBC, 0xE610, 0x3EC8, 0x0C7B, 0x031A, 0x07E6, 0x3EC8, 0x86F7, 199 0x3EC0, 0x821E, 0x3EBE, 0xD208, 0x3EBD, 0x021F, 0x3ECA, 0x0386, 200 0x3EC1, 0x0C03, 0x3EC9, 0x031E, 0x3ECA, 0x8C4C, 0x3EBF, 0x0C55, 201 }; 202 203 static u_short init4_4[32] = 204 { 205 0x3EC9, 0xC208, 0x3EC4, 0xBC84, 0x3EC8, 0x0EAD, 0x3EC8, 0xD308, 206 0x3EC2, 0x8F7E, 0x3ECB, 0x0219, 0x3ECB, 0xD26E, 0x3EC5, 0x031F, 207 0x3EC6, 0xC308, 0x3EC3, 0x32FF, 0x3EC9, 0x0265, 0x3EC9, 0x8319, 208 0x1342, 0xD36E, 0x3EC7, 0x33FF, 0x0000, 0x8365, 0x1420, 0x9570, 209 }; 210 211 /* The followings are the register, the channel and the port for the EMU8000 registers. */ 212 struct _emu_register { 213 int reg; /* Register */ 214 int index; /* Index */ 215 int port; /* Port */ 216 int chn; /* Channel */ 217 int size; /* Size, 0 == word, 1 == double word */ 218 }; 219 220 #define EMU8K_CHN_ANY (-1) 221 222 static struct _emu_register emu_regs[] = 223 { 224 /* Reg, Index, Port, Channel, Size */ 225 { 0, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* CPF */ 226 { 1, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* PTRX */ 227 { 2, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* CVCF */ 228 { 3, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* VTFT */ 229 { 6, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* PSST */ 230 { 7, EMU8K_IDX_DATA0, EMU8K_PORT_DATA0, EMU8K_CHN_ANY, 1}, /* CSL */ 231 { 0, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 1}, /* CCCA */ 232 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 9, 1}, /* HWCF4 */ 233 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 10, 1}, /* HWCF5 */ 234 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 13, 1}, /* HWCF6 */ 235 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 20, 1}, /* SMALR */ 236 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 21, 1}, /* SMARR */ 237 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 22, 1}, /* SMALW */ 238 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 23, 1}, /* SMARW */ 239 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 26, 0}, /* SMLD */ 240 { 1, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, 26, 0}, /* SMRD */ 241 { 1, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, 27, 0}, /* WC */ 242 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 29, 0}, /* HWCF1 */ 243 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 30, 0}, /* HWCF2 */ 244 { 1, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, 31, 0}, /* HWCF3 */ 245 { 2, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* INIT1 */ 246 { 2, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* INIT2 */ 247 { 3, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* INIT3 */ 248 { 3, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* INIT4 */ 249 { 4, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* ENVVOL */ 250 { 5, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* DCYSUSV */ 251 { 6, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* ENVVAL */ 252 { 7, EMU8K_IDX_DATA1, EMU8K_PORT_DATA1, EMU8K_CHN_ANY, 0}, /* DCYSUS */ 253 { 4, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* ATKHLDV */ 254 { 5, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* LFO1VAL */ 255 { 6, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* ATKHLD */ 256 { 7, EMU8K_IDX_DATA2, EMU8K_PORT_DATA2, EMU8K_CHN_ANY, 0}, /* LFO2VAL */ 257 { 0, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* IP */ 258 { 1, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* IFATN */ 259 { 2, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* PEFE */ 260 { 3, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* FMMOD */ 261 { 4, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* TREMFRQ */ 262 { 5, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, EMU8K_CHN_ANY, 0}, /* FM2FRQ2 */ 263 { 7, EMU8K_IDX_DATA3, EMU8K_PORT_DATA3, 0, 0}, /* PROBE */ 264 }; 265 266 /* These are the EMU8000 register names. */ 267 enum { 268 EMU8K_CPF = 0, 269 EMU8K_PTRX, 270 EMU8K_CVCF, 271 EMU8K_VTFT, 272 EMU8K_PSST, 273 EMU8K_CSL, 274 EMU8K_CCCA, 275 EMU8K_HWCF4, 276 EMU8K_HWCF5, 277 EMU8K_HWCF6, 278 EMU8K_SMALR, 279 EMU8K_SMARR, 280 EMU8K_SMALW, 281 EMU8K_SMARW, 282 EMU8K_SMLD, 283 EMU8K_SMRD, 284 EMU8K_WC, 285 EMU8K_HWCF1, 286 EMU8K_HWCF2, 287 EMU8K_HWCF3, 288 EMU8K_INIT1, 289 EMU8K_INIT2, 290 EMU8K_INIT3, 291 EMU8K_INIT4, 292 EMU8K_ENVVOL, 293 EMU8K_DCYSUSV, 294 EMU8K_ENVVAL, 295 EMU8K_DCYSUS, 296 EMU8K_ATKHLDV, 297 EMU8K_LFO1VAL, 298 EMU8K_ATKHLD, 299 EMU8K_LFO2VAL, 300 EMU8K_IP, 301 EMU8K_IFATN, 302 EMU8K_PEFE, 303 EMU8K_FMMOD, 304 EMU8K_TREMFRQ, 305 EMU8K_FM2FRQ2, 306 EMU8K_PROBE, 307 EMU8K_REGLAST, /* keep this! */ 308 }; 309 #define EMU8K_REGNUM (EMU8K_REGLAST) 310 311 /* These are the synthesizer and the midi device information. */ 312 static struct synth_info emu_synthinfo = { 313 "EMU8000 Wavetable Synth", 314 0, 315 SYNTH_TYPE_SAMPLE, 316 SAMPLE_TYPE_AWE32, 317 0, 318 EMU8K_MAXVOICE, 319 0, 320 EMU8K_MAXINFO, 321 0, 322 }; 323 324 static struct midi_info emu_midiinfo = { 325 "EMU8000 Wavetable Synth", 326 0, 327 0, 328 0, 329 }; 330 331 #if notyet 332 /* 333 * These functions goes into emusynthdev_op_desc. 334 */ 335 static mdsy_killnote_t emu_killnote; 336 static mdsy_setinstr_t emu_setinstr; 337 static mdsy_startnote_t emu_startnote; 338 static mdsy_reset_t emu_reset; 339 static mdsy_hwcontrol_t emu_hwcontrol; 340 static mdsy_loadpatch_t emu_loadpatch; 341 static mdsy_panning_t emu_panning; 342 static mdsy_aftertouch_t emu_aftertouch; 343 static mdsy_controller_t emu_controller; 344 static mdsy_patchmgr_t emu_patchmgr; 345 static mdsy_bender_t emu_bender; 346 static mdsy_allocvoice_t emu_allocvoice; 347 static mdsy_setupvoice_t emu_setupvoice; 348 static mdsy_sendsysex_t emu_sendsysex; 349 static mdsy_prefixcmd_t emu_prefixcmd; 350 static mdsy_volumemethod_t emu_volumemethod; 351 352 /* 353 * This is the synthdev_info for an EMU8000 chip. 354 */ 355 static synthdev_info emusynth_op_desc = { 356 emu_killnote, 357 emu_setinstr, 358 emu_startnote, 359 emu_reset, 360 emu_hwcontrol, 361 emu_loadpatch, 362 emu_panning, 363 emu_aftertouch, 364 emu_controller, 365 emu_patchmgr, 366 emu_bender, 367 emu_allocvoice, 368 emu_setupvoice, 369 emu_sendsysex, 370 emu_prefixcmd, 371 emu_volumemethod, 372 }; 373 #endif /* notyet */ 374 375 /* 376 * These functions goes into emu_op_desc to get called 377 * from sound.c. 378 */ 379 380 static int emu_probe(device_t dev); 381 static int emu_attach(device_t dev); 382 static int emupnp_attach(device_t dev) __unused; 383 384 static d_open_t emu_open; 385 static d_close_t emu_close; 386 static d_ioctl_t emu_ioctl; 387 static midi_callback_t emu_callback; 388 389 /* These go to mididev_info. */ 390 static mdsy_readraw_t emu_readraw; 391 static mdsy_writeraw_t emu_writeraw; 392 393 /* Here is the parameter structure per a device. */ 394 struct emu_softc { 395 device_t dev; /* device information */ 396 mididev_info *devinfo; /* midi device information */ 397 398 struct mtx mtx; /* Mutex to protect a device */ 399 400 struct resource *io[3]; /* Base of io port */ 401 int io_rid[3]; /* Io resource ID */ 402 403 u_int dramsize; /* DRAM size */ 404 struct synth_info synthinfo; /* Synthesizer information */ 405 406 int fflags; /* File flags */ 407 }; 408 409 typedef struct emu_softc *sc_p; 410 411 /* These functions are local. */ 412 static u_int emu_dramsize(sc_p scp); 413 static void emu_allocdmachn(sc_p scp, int chn, int mode); 414 static void emu_dmaaddress(sc_p scp, int mode, u_int addr); 415 static void emu_waitstream(sc_p scp, int mode); 416 static void emu_readblkstream(sc_p scp, int mode, u_short *data, size_t len); 417 static void emu_writeblkstream(sc_p scp, int mode, u_short *data, size_t len); 418 static void emu_readstream(sc_p scp, int mode, u_short *data); 419 static void emu_writestream(sc_p scp, int mode, u_short data); 420 static void emu_releasedmachn(sc_p scp, int chn, int mode); 421 static void emu_delay(sc_p scp, short n); 422 static void emu_readcpf(sc_p scp, int chn, u_int *cp, u_int *f) __unused; 423 static void emu_writecpf(sc_p scp, int chn, u_int cp, u_int f); 424 static void emu_readptrx(sc_p scp, int chn, u_int *pt, u_int *rs, u_int *auxd) __unused; 425 static void emu_writeptrx(sc_p scp, int chn, u_int pt, u_int rs, u_int auxd); 426 static void emu_readcvcf(sc_p scp, int chn, u_int *cv, u_int *cf) __unused; 427 static void emu_writecvcf(sc_p scp, int chn, u_int cv, u_int cf); 428 static void emu_readvtft(sc_p scp, int chn, u_int *vt, u_int *ft) __unused; 429 static void emu_writevtft(sc_p scp, int chn, u_int vt, u_int ft); 430 static void emu_readpsst(sc_p scp, int chn, u_int *pan, u_int *st) __unused; 431 static void emu_writepsst(sc_p scp, int chn, u_int pan, u_int st); 432 static void emu_readcsl(sc_p scp, int chn, u_int *cs, u_int *lp) __unused; 433 static void emu_writecsl(sc_p scp, int chn, u_int cs, u_int lp); 434 static void emu_readccca(sc_p scp, int chn, u_int *q, u_int *dma, u_int *wr, u_int *right, u_int *ca) __unused; 435 static void emu_writeccca(sc_p scp, int chn, u_int q, u_int dma, u_int wr, u_int right, u_int ca); 436 static void emu_readhwcf4(sc_p scp, u_int *val) __unused; 437 static void emu_writehwcf4(sc_p scp, u_int val); 438 static void emu_readhwcf5(sc_p scp, u_int *val) __unused; 439 static void emu_writehwcf5(sc_p scp, u_int val); 440 static void emu_readhwcf6(sc_p scp, u_int *val) __unused; 441 static void emu_writehwcf6(sc_p scp, u_int val); 442 static void emu_readsmalr(sc_p scp, u_int *mt, u_int *smalr); 443 static void emu_writesmalr(sc_p scp, u_int mt, u_int smalr); 444 static void emu_readsmarr(sc_p scp, u_int *mt, u_int *smarr); 445 static void emu_writesmarr(sc_p scp, u_int mt, u_int smarr); 446 static void emu_readsmalw(sc_p scp, u_int *full, u_int *smalw); 447 static void emu_writesmalw(sc_p scp, u_int full, u_int smalw); 448 static void emu_readsmarw(sc_p scp, u_int *full, u_int *smarw); 449 static void emu_writesmarw(sc_p scp, u_int full, u_int smarw); 450 static void emu_readsmld(sc_p scp, u_short *smld); 451 static void emu_writesmld(sc_p scp, u_short smld); 452 static void emu_readsmrd(sc_p scp, u_short *smrd); 453 static void emu_writesmrd(sc_p scp, u_short smrd); 454 static void emu_readwc(sc_p scp, u_int *wc); 455 static void emu_writewc(sc_p scp, u_int wc) __unused; 456 static void emu_readhwcf1(sc_p scp, u_int *val); 457 static void emu_writehwcf1(sc_p scp, u_int val); 458 static void emu_readhwcf2(sc_p scp, u_int *val); 459 static void emu_writehwcf2(sc_p scp, u_int val); 460 static void emu_readhwcf3(sc_p scp, u_int *val) __unused; 461 static void emu_writehwcf3(sc_p scp, u_int val); 462 static void emu_readinit1(sc_p scp, int chn, u_int *val) __unused; 463 static void emu_writeinit1(sc_p scp, int chn, u_int val); 464 static void emu_readinit2(sc_p scp, int chn, u_int *val) __unused; 465 static void emu_writeinit2(sc_p scp, int chn, u_int val); 466 static void emu_readinit3(sc_p scp, int chn, u_int *val) __unused; 467 static void emu_writeinit3(sc_p scp, int chn, u_int val); 468 static void emu_readinit4(sc_p scp, int chn, u_int *val) __unused; 469 static void emu_writeinit4(sc_p scp, int chn, u_int val); 470 static void emu_readenvvol(sc_p scp, int chn, u_int *envvol) __unused; 471 static void emu_writeenvvol(sc_p scp, int chn, u_int envvol); 472 static void emu_readdcysusv(sc_p scp, int chn, u_int *ph1v, u_int *susv, u_int *off, u_int *dcyv) __unused; 473 static void emu_writedcysusv(sc_p scp, int chn, u_int ph1v, u_int susv, u_int off, u_int dcyv); 474 static void emu_readenvval(sc_p scp, int chn, u_int *envval) __unused; 475 static void emu_writeenvval(sc_p scp, int chn, u_int envval); 476 static void emu_readdcysus(sc_p scp, int chn, u_int *ph1, u_int *sus, u_int *dcy) __unused; 477 static void emu_writedcysus(sc_p scp, int chn, u_int ph1, u_int sus, u_int dcy); 478 static void emu_readatkhldv(sc_p scp, int chn, u_int *atkhldv) __unused; 479 static void emu_writeatkhldv(sc_p scp, int chn, u_int atkhldv); 480 static void emu_readlfo1val(sc_p scp, int chn, u_int *lfo1val) __unused; 481 static void emu_writelfo1val(sc_p scp, int chn, u_int lfo1val); 482 static void emu_readatkhld(sc_p scp, int chn, u_int *atkhld) __unused; 483 static void emu_writeatkhld(sc_p scp, int chn, u_int atkhld); 484 static void emu_readlfo2val(sc_p scp, int chn, u_int *lfo2val) __unused; 485 static void emu_writelfo2val(sc_p scp, int chn, u_int lfo2val); 486 static void emu_readip(sc_p scp, int chn, u_int *ip) __unused; 487 static void emu_writeip(sc_p scp, int chn, u_int ip); 488 static void emu_readifatn(sc_p scp, int chn, u_int *ifc, u_int *atn) __unused; 489 static void emu_writeifatn(sc_p scp, int chn, u_int ifc, u_int atn); 490 static void emu_readpefe(sc_p scp, int chn, u_int *pe, u_int *fe) __unused; 491 static void emu_writepefe(sc_p scp, int chn, u_int pe, u_int fe); 492 static void emu_readfmmod(sc_p scp, int chn, u_int *fm, u_int *mod) __unused; 493 static void emu_writefmmod(sc_p scp, int chn, u_int fm, u_int mod); 494 static void emu_readtremfrq(sc_p scp, int chn, u_int *trem, u_int *frq) __unused; 495 static void emu_writetremfrq(sc_p scp, int chn, u_int trem, u_int frq); 496 static void emu_readfm2frq2(sc_p scp, int chn, u_int *fm2, u_int *frq2) __unused; 497 static void emu_writefm2frq2(sc_p scp, int chn, u_int fm2, u_int frq2); 498 static void emu_readprobe(sc_p scp, u_int *val); 499 static void emu_writeprobe(sc_p scp, u_int val) __unused; 500 static void emu_command(sc_p scp, int reg, int chn, u_long val); 501 static u_long emu_status(sc_p scp, int reg, int chn); 502 static int emu_allocres(sc_p scp, device_t dev); 503 static void emu_releaseres(sc_p scp, device_t dev); 504 505 /* PnP IDs */ 506 static struct isa_pnp_id emu_ids[] = { 507 {0x21008c0e, "CTL0021 WaveTable Synthesizer"}, /* CTL0021 */ 508 {0x22008c0e, "CTL0022 WaveTable Synthesizer"}, /* CTL0022 */ 509 }; 510 511 /* 512 * This is the device descriptor for the midi device. 513 */ 514 mididev_info emu_op_desc = { 515 "EMU8000 Wavetable Synth", 516 517 SNDCARD_AWE32, 518 519 emu_open, 520 emu_close, 521 emu_ioctl, 522 emu_callback, 523 524 MIDI_BUFFSIZE, /* Queue Length */ 525 526 0, /* XXX This is not an *audio* device! */ 527 }; 528 529 /* 530 * Here are the main functions to interact to the user process. 531 */ 532 533 static int 534 emu_probe(device_t dev) 535 { 536 sc_p scp; 537 int unit; 538 u_int probe, hwcf1, hwcf2; 539 540 /* Check isapnp ids */ 541 if (isa_get_logicalid(dev) != 0) 542 return (ISA_PNP_PROBE(device_get_parent(dev), dev, emu_ids)); 543 /* XXX non-pnp emu? */ 544 545 unit = device_get_unit(dev); 546 scp = device_get_softc(dev); 547 548 device_set_desc(dev, "EMU8000 Wavetable Synth"); 549 bzero(scp, sizeof(*scp)); 550 551 MIDI_DEBUG(printf("emu%d: probing.\n", unit)); 552 553 if (emu_allocres(scp, dev)) { 554 emu_releaseres(scp, dev); 555 return (ENXIO); 556 } 557 558 emu_readprobe(scp, &probe); 559 emu_readhwcf1(scp, &hwcf1); 560 emu_readhwcf2(scp, &hwcf2); 561 if ((probe & 0x000f) != 0x000c 562 || (hwcf1 & 0x007e) != 0x0058 563 || (hwcf2 & 0x0003) != 0x0003) { 564 emu_releaseres(scp, dev); 565 return (ENXIO); 566 } 567 568 MIDI_DEBUG(printf("emu%d: probed.\n", unit)); 569 570 return (0); 571 } 572 573 extern synthdev_info midisynth_op_desc; 574 575 static int 576 emu_attach(device_t dev) 577 { 578 sc_p scp; 579 mididev_info *devinfo; 580 int unit, i; 581 582 unit = device_get_unit(dev); 583 scp = device_get_softc(dev); 584 585 MIDI_DEBUG(printf("emu%d: attaching.\n", unit)); 586 587 if (emu_allocres(scp, dev)) { 588 emu_releaseres(scp, dev); 589 return (ENXIO); 590 } 591 592 /* EMU8000 needs some initialization processes. */ 593 594 /* 1. Write HWCF{1,2}. */ 595 emu_writehwcf1(scp, 0x0059); 596 emu_writehwcf2(scp, 0x0020); 597 598 /* Disable the audio. */ 599 emu_writehwcf3(scp, 0); 600 601 /* 2. Initialize the channels. */ 602 603 /* 2a. Write DCYSUSV. */ 604 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 605 emu_writedcysusv(scp, i, 0, 0, 1, 0); 606 607 /* 2b. Clear the envelope and sound engine registers. */ 608 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) { 609 emu_writeenvvol(scp, i, 0); 610 emu_writeenvval(scp, i, 0); 611 emu_writedcysus(scp, i, 0, 0, 0); 612 emu_writeatkhldv(scp, i, 0); 613 emu_writelfo1val(scp, i, 0); 614 emu_writeatkhld(scp, i, 0); 615 emu_writelfo2val(scp, i, 0); 616 emu_writeip(scp, i, 0); 617 emu_writeifatn(scp, i, 0, 0); 618 emu_writepefe(scp, i, 0, 0); 619 emu_writefmmod(scp, i, 0, 0); 620 emu_writetremfrq(scp, i, 0, 0); 621 emu_writefm2frq2(scp, i, 0, 0); 622 emu_writeptrx(scp, i, 0, 0, 0); 623 emu_writevtft(scp, i, 0, 0); 624 emu_writepsst(scp, i, 0, 0); 625 emu_writecsl(scp, i, 0, 0); 626 emu_writeccca(scp, i, 0, 0, 0, 0, 0); 627 } 628 629 /* 2c. Clear the current registers. */ 630 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) { 631 emu_writecpf(scp, i, 0, 0); 632 emu_writecvcf(scp, i, 0, 0); 633 } 634 635 /* 3. Initialize the sound memory DMA registers. */ 636 emu_writesmalr(scp, 0, 0); 637 emu_writesmarr(scp, 0, 0); 638 emu_writesmalw(scp, 0, 0); 639 emu_writesmarw(scp, 0, 0); 640 641 /* 4. Fill the array. */ 642 643 /* 4a. Set 1. */ 644 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 645 emu_writeinit1(scp, i, init1_1[i]); 646 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 647 emu_writeinit2(scp, i, init1_2[i]); 648 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 649 emu_writeinit3(scp, i, init1_3[i]); 650 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 651 emu_writeinit4(scp, i, init1_4[i]); 652 653 /* 4b. Have a rest. */ 654 emu_delay(scp, 1024); /* 1024 samples. */ 655 656 /* 4c. Set 2. */ 657 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 658 emu_writeinit1(scp, i, init2_1[i]); 659 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 660 emu_writeinit2(scp, i, init2_2[i]); 661 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 662 emu_writeinit3(scp, i, init2_3[i]); 663 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 664 emu_writeinit4(scp, i, init2_4[i]); 665 666 /* 4d. Set 3. */ 667 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 668 emu_writeinit1(scp, i, init3_1[i]); 669 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 670 emu_writeinit2(scp, i, init3_2[i]); 671 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 672 emu_writeinit3(scp, i, init3_3[i]); 673 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 674 emu_writeinit4(scp, i, init3_4[i]); 675 676 /* 4e. Write to HWCF{4,5,6}. */ 677 emu_writehwcf4(scp, 0); 678 emu_writehwcf5(scp, 0x00000083); 679 emu_writehwcf6(scp, 0x00008000); 680 681 /* 4f. Set 4. */ 682 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 683 emu_writeinit1(scp, i, init4_1[i]); 684 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 685 emu_writeinit2(scp, i, init4_2[i]); 686 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 687 emu_writeinit3(scp, i, init4_3[i]); 688 for (i = 0 ; i < EMU8K_MAXVOICE ; i++) 689 emu_writeinit4(scp, i, init4_4[i]); 690 691 /* 5. Determine the size of DRAM. */ 692 scp->dev = dev; 693 scp->dramsize = emu_dramsize(scp); 694 printf("emu%d: DRAM size = %dKB\n", unit, scp->dramsize / 1024); 695 696 /* We have inited the EMU8000. Now work on FM. */ 697 698 /* Write parameters for the left channel. */ 699 emu_writedcysusv(scp, 30, 0, 0, 1, 0); 700 emu_writepsst(scp, 30, 0x80, 0xffffe0); /* full left */ 701 emu_writecsl(scp, 30, 0, 0xfffff8); /* chorus */ 702 emu_writeptrx(scp, 30, 0, 0, 0); /* reverb */ 703 emu_writecpf(scp, 30, 0, 0); 704 emu_writeccca(scp, 30, 0, 0, 0, 0, 0xffffe3); 705 706 /* Then the right channel. */ 707 emu_writedcysusv(scp, 31, 0, 0, 1, 0); 708 emu_writepsst(scp, 31, 0x80, 0xfffff0); /* full right */ 709 emu_writecsl(scp, 31, 0, 0xfffff8); /* chorus */ 710 emu_writeptrx(scp, 31, 0, 0, 0xff); /* reverb */ 711 emu_writecpf(scp, 31, 0, 0); 712 emu_writeccca(scp, 31, 0, 0, 0, 0, 0xfffff3); 713 714 /* Skew volume and cutoff. */ 715 emu_writevtft(scp, 30, 0x8000, 0xffff); 716 emu_writevtft(scp, 31, 0x8000, 0xffff); 717 718 /* Ready to sound. */ 719 emu_writehwcf3(scp, 0x0004); 720 721 /* Fill the softc for this unit. */ 722 bcopy(&emu_synthinfo, &scp->synthinfo, sizeof(emu_synthinfo)); 723 mtx_init(&scp->mtx, "emumid", NULL, MTX_DEF); 724 scp->devinfo = devinfo = create_mididev_info_unit(MDT_SYNTH, &emu_op_desc, &midisynth_op_desc); 725 726 /* Fill the midi info. */ 727 devinfo->synth.readraw = emu_readraw; 728 devinfo->synth.writeraw = emu_writeraw; 729 snprintf(devinfo->midistat, sizeof(devinfo->midistat), "at 0x%x, 0x%x, 0x%x", 730 (u_int)rman_get_start(scp->io[0]), (u_int)rman_get_start(scp->io[1]), (u_int)rman_get_start(scp->io[2])); 731 732 midiinit(devinfo, dev); 733 734 MIDI_DEBUG(printf("emu%d: attached.\n", unit)); 735 736 return (0); 737 } 738 739 static int 740 emupnp_attach(device_t dev) 741 { 742 return (emu_attach(dev)); 743 } 744 745 static int 746 emu_open(dev_t i_dev, int flags, int mode, struct thread *td) 747 { 748 return (0); 749 } 750 751 static int 752 emu_close(dev_t i_dev, int flags, int mode, struct thread *td) 753 { 754 return (0); 755 } 756 757 static int 758 emu_ioctl(dev_t i_dev, u_long cmd, caddr_t arg, int mode, struct thread *td) 759 { 760 sc_p scp; 761 mididev_info *devinfo; 762 int unit; 763 struct synth_info *synthinfo; 764 struct midi_info *midiinfo; 765 766 unit = MIDIUNIT(i_dev); 767 768 MIDI_DEBUG(printf("emu_ioctl: unit %d, cmd %s.\n", unit, midi_cmdname(cmd, cmdtab_midiioctl))); 769 770 devinfo = get_mididev_info(i_dev, &unit); 771 if (devinfo == NULL) { 772 MIDI_DEBUG(printf("emu_ioctl: unit %d is not configured.\n", unit)); 773 return (ENXIO); 774 } 775 scp = devinfo->softc; 776 777 switch (cmd) { 778 case SNDCTL_SYNTH_INFO: 779 synthinfo = (struct synth_info *)arg; 780 if (synthinfo->device != unit) 781 return (ENXIO); 782 bcopy(&scp->synthinfo, synthinfo, sizeof(scp->synthinfo)); 783 synthinfo->device = unit; 784 return (0); 785 break; 786 case SNDCTL_MIDI_INFO: 787 midiinfo = (struct midi_info *)arg; 788 if (midiinfo->device != unit) 789 return (ENXIO); 790 bcopy(&emu_midiinfo, midiinfo, sizeof(emu_midiinfo)); 791 strcpy(midiinfo->name, scp->synthinfo.name); 792 midiinfo->device = unit; 793 return (0); 794 break; 795 case SNDCTL_SYNTH_MEMAVL: 796 *(int *)arg = 0x7fffffff; 797 return (0); 798 break; 799 default: 800 return (ENOSYS); 801 } 802 /* NOTREACHED */ 803 return (EINVAL); 804 } 805 806 static int 807 emu_callback(void *d, int reason) 808 { 809 mididev_info *devinfo; 810 811 devinfo = (mididev_info *)d; 812 813 mtx_assert(&devinfo->flagqueue_mtx, MA_OWNED); 814 815 return (0); 816 } 817 818 static int 819 emu_readraw(mididev_info *md, u_char *buf, int len, int *lenr, int nonblock) 820 { 821 sc_p scp; 822 int unit; 823 824 if (md == NULL) 825 return (ENXIO); 826 if (lenr == NULL) 827 return (EINVAL); 828 829 unit = md->unit; 830 scp = md->softc; 831 if ((md->fflags & FREAD) == 0) { 832 MIDI_DEBUG(printf("emu_readraw: unit %d is not for reading.\n", unit)); 833 return (EIO); 834 } 835 836 /* NOP. */ 837 *lenr = 0; 838 839 return (0); 840 } 841 842 static int 843 emu_writeraw(mididev_info *md, u_char *buf, int len, int *lenw, int nonblock) 844 { 845 sc_p scp; 846 int unit; 847 848 if (md == NULL) 849 return (ENXIO); 850 if (lenw == NULL) 851 return (EINVAL); 852 853 unit = md->unit; 854 scp = md->softc; 855 if ((md->fflags & FWRITE) == 0) { 856 MIDI_DEBUG(printf("emu_writeraw: unit %d is not for writing.\n", unit)); 857 return (EIO); 858 } 859 860 /* NOP. */ 861 *lenw = 0; 862 863 return (0); 864 } 865 866 /* 867 * The functions below here are the synthesizer interfaces. 868 */ 869 870 /* 871 * The functions below here are the libraries for the above ones. 872 */ 873 874 /* Determine the size of DRAM. */ 875 static u_int 876 emu_dramsize(sc_p scp) 877 { 878 u_int dramsize; 879 static u_short magiccode[] = {0x386d, 0xbd2a, 0x73df, 0xf2d8}; 880 static u_short magiccode2[] = {0x5ef3, 0x2b90, 0xa4c8, 0x6a13}; 881 u_short buf[sizeof(magiccode) / sizeof(*magiccode)]; 882 883 /* 884 * Write the magic code to the bottom of DRAM. 885 * Writing to a wrapped address clobbers the code. 886 */ 887 emu_allocdmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE); 888 emu_dmaaddress(scp, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE, EMU8K_DRAM_RAM); 889 emu_writeblkstream(scp, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE, magiccode, sizeof(magiccode) / sizeof(*magiccode)); 890 emu_releasedmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE); 891 892 for (dramsize = 0 ; dramsize + EMU8K_DRAM_RAM < EMU8K_DRAM_MAX ; ) { 893 894 /* Read the magic code. */ 895 emu_allocdmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_READ); 896 emu_dmaaddress(scp, EMU8K_DMA_LEFT | EMU8K_DMA_READ, EMU8K_DRAM_RAM); 897 emu_readblkstream(scp, EMU8K_DMA_LEFT | EMU8K_DMA_READ, buf, sizeof(buf) / sizeof(*buf)); 898 emu_releasedmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_READ); 899 900 /* Compare the code. */ 901 if (bcmp(magiccode, buf, sizeof(magiccode))) 902 break; 903 904 /* Increase the DRAM size. */ 905 dramsize += 0x8000; 906 907 /* Try writing a different magic code to dramsize. */ 908 emu_allocdmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE); 909 emu_dmaaddress(scp, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE, dramsize + EMU8K_DRAM_RAM); 910 emu_writeblkstream(scp, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE, magiccode2, sizeof(magiccode2) / sizeof(*magiccode2)); 911 emu_releasedmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_WRITE); 912 913 /* Then read the magic code. */ 914 emu_allocdmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_READ); 915 emu_dmaaddress(scp, EMU8K_DMA_LEFT | EMU8K_DMA_READ, dramsize + EMU8K_DRAM_RAM); 916 emu_readblkstream(scp, EMU8K_DMA_LEFT | EMU8K_DMA_READ, buf, sizeof(buf) / sizeof(*buf)); 917 emu_releasedmachn(scp, 31, EMU8K_DMA_LEFT | EMU8K_DMA_READ); 918 919 /* Compare the code. */ 920 if (bcmp(magiccode2, buf, sizeof(magiccode2))) 921 break; 922 } 923 if (dramsize + EMU8K_DRAM_RAM > EMU8K_DRAM_MAX) 924 dramsize = EMU8K_DRAM_MAX - EMU8K_DRAM_RAM; 925 926 return dramsize * 2; /* dramsize is in words. */ 927 } 928 929 /* Allocates a channel to a DMA stream. */ 930 static void 931 emu_allocdmachn(sc_p scp, int chn, int mode) 932 { 933 /* Turn off the sound, prepare for a DMA stream. */ 934 emu_writedcysusv(scp, chn, 0, 0, 1, 0); 935 emu_writevtft(scp, chn, 0, 0); 936 emu_writecvcf(scp, chn, 0, 0); 937 emu_writeptrx(scp, chn, 0x4000, 0, 0); 938 emu_writecpf(scp, chn, 0x4000, 0); 939 emu_writepsst(scp, chn, 0, 0); 940 emu_writecsl(scp, chn, 0, 0); 941 942 /* Enter DMA mode. */ 943 emu_writeccca(scp, chn, 0, 1, 944 ((mode & EMU8K_DMA_WRITE) > 0) ? 1 : 0, 945 ((mode & EMU8K_DMA_RIGHT) > 0) ? 1 : 0, 946 0); 947 } 948 949 /* Programs the initial address to a DMA. */ 950 static void 951 emu_dmaaddress(sc_p scp, int mode, u_int addr) 952 { 953 /* Wait until the stream comes ready. */ 954 emu_waitstream(scp, mode); 955 956 switch(mode & EMU8K_DMA_MASK) 957 { 958 case EMU8K_DMA_LEFT | EMU8K_DMA_READ: 959 emu_writesmalr(scp, 0, addr); 960 emu_readsmld(scp, NULL); /* Read the stale data. */ 961 break; 962 case EMU8K_DMA_RIGHT | EMU8K_DMA_READ: 963 emu_writesmarr(scp, 0, addr); 964 emu_readsmrd(scp, NULL); /* Read the stale data. */ 965 break; 966 case EMU8K_DMA_LEFT | EMU8K_DMA_WRITE: 967 emu_writesmalw(scp, 0, addr); 968 break; 969 case EMU8K_DMA_RIGHT | EMU8K_DMA_WRITE: 970 emu_writesmarw(scp, 0, addr); 971 break; 972 } 973 } 974 975 /* Waits until a stream gets ready. */ 976 static void 977 emu_waitstream(sc_p scp, int mode) 978 { 979 int i; 980 u_int busy; 981 982 for (i = 0 ; i < 100000 ; i++) { 983 switch(mode & EMU8K_DMA_MASK) 984 { 985 case EMU8K_DMA_LEFT | EMU8K_DMA_READ: 986 emu_readsmalr(scp, &busy, NULL); 987 break; 988 case EMU8K_DMA_RIGHT | EMU8K_DMA_READ: 989 emu_readsmarr(scp, &busy, NULL); 990 break; 991 case EMU8K_DMA_LEFT | EMU8K_DMA_WRITE: 992 emu_readsmalw(scp, &busy, NULL); 993 break; 994 case EMU8K_DMA_RIGHT | EMU8K_DMA_WRITE: 995 emu_readsmarw(scp, &busy, NULL); 996 break; 997 } 998 if (!busy) 999 break; 1000 emu_delay(scp, 1); 1001 } 1002 if (busy) 1003 printf("emu%d: stream data still busy, timed out.\n", device_get_unit(scp->dev)); 1004 } 1005 1006 /* Reads a word block from a stream. */ 1007 static void 1008 emu_readblkstream(sc_p scp, int mode, u_short *data, size_t len) 1009 { 1010 while((len--) > 0) 1011 emu_readstream(scp, mode, data++); 1012 } 1013 1014 /* Writes a word block stream to a stream. */ 1015 static void 1016 emu_writeblkstream(sc_p scp, int mode, u_short *data, size_t len) 1017 { 1018 while((len--) > 0) 1019 emu_writestream(scp, mode, *(data++)); 1020 } 1021 1022 /* Reads a word from a stream. */ 1023 static void 1024 emu_readstream(sc_p scp, int mode, u_short *data) 1025 { 1026 if ((mode & EMU8K_DMA_RW) != EMU8K_DMA_READ) 1027 return; 1028 1029 switch(mode & EMU8K_DMA_MASK) 1030 { 1031 case EMU8K_DMA_LEFT | EMU8K_DMA_READ: 1032 emu_readsmld(scp, data); 1033 break; 1034 case EMU8K_DMA_RIGHT | EMU8K_DMA_READ: 1035 emu_readsmrd(scp, data); 1036 break; 1037 } 1038 } 1039 1040 /* Writes a word to a stream. */ 1041 static void 1042 emu_writestream(sc_p scp, int mode, u_short data) 1043 { 1044 if ((mode & EMU8K_DMA_RW) != EMU8K_DMA_WRITE) 1045 return; 1046 1047 switch(mode & EMU8K_DMA_MASK) 1048 { 1049 case EMU8K_DMA_LEFT | EMU8K_DMA_WRITE: 1050 emu_writesmld(scp, data); 1051 break; 1052 case EMU8K_DMA_RIGHT | EMU8K_DMA_WRITE: 1053 emu_writesmrd(scp, data); 1054 break; 1055 } 1056 } 1057 1058 /* Releases a channel from a DMA stream. */ 1059 static void 1060 emu_releasedmachn(sc_p scp, int chn, int mode) 1061 { 1062 /* Wait until the stream comes ready. */ 1063 emu_waitstream(scp, mode); 1064 1065 /* Leave DMA mode. */ 1066 emu_writeccca(scp, chn, 0, 0, 0, 0, 0); 1067 } 1068 1069 /* 1070 * Waits cycles. 1071 * Idea-stolen-from: sys/i386/isa/clock.c:DELAY() 1072 */ 1073 static void 1074 emu_delay(sc_p scp, short n) 1075 { 1076 int wc_prev, wc, wc_left, wc_delta; 1077 1078 emu_readwc(scp, &wc_prev); 1079 wc_left = n; 1080 1081 while (wc_left > 0) { 1082 emu_readwc(scp, &wc); 1083 wc_delta = wc - wc_prev; /* The counter increases. */ 1084 wc_prev = wc; 1085 if (wc_delta < 0) 1086 wc_delta += 0xffff; 1087 wc_left -= wc_delta; 1088 } 1089 } 1090 1091 /* The followings provide abstract access to the registers. */ 1092 #define DECBIT(sts, shift, len) (((sts) >> (shift))) & (0xffffffff >> (32 - len)) 1093 #define GENBIT(val, shift, len) (((val) & (0xffffffff >> (32 - len))) << (shift)) 1094 1095 /* CPF: Current Pitch and Fractional Address */ 1096 static void 1097 emu_readcpf(sc_p scp, int chn, u_int *cp, u_int *f) 1098 { 1099 u_long sts; 1100 1101 sts = emu_status(scp, EMU8K_CPF, chn); 1102 if (cp != NULL) 1103 *cp = DECBIT(sts, 16, 16); 1104 if (f != NULL) 1105 *f = DECBIT(sts, 0, 16); 1106 } 1107 1108 static void 1109 emu_writecpf(sc_p scp, int chn, u_int cp, u_int f) 1110 { 1111 emu_command(scp, EMU8K_CPF, chn, 1112 GENBIT(cp, 16, 16) 1113 | GENBIT(f, 0, 16)); 1114 } 1115 1116 /* PTRX: Pitch Target, Rvb Send and Aux Byte */ 1117 static void 1118 emu_readptrx(sc_p scp, int chn, u_int *pt, u_int *rs, u_int *auxd) 1119 { 1120 u_long sts; 1121 1122 sts = emu_status(scp, EMU8K_PTRX, chn); 1123 if (pt != NULL) 1124 *pt = DECBIT(sts, 16, 16); 1125 if (rs != NULL) 1126 *rs = DECBIT(sts, 8, 8); 1127 if (auxd != NULL) 1128 *auxd = DECBIT(sts, 0, 8); 1129 } 1130 1131 static void 1132 emu_writeptrx(sc_p scp, int chn, u_int pt, u_int rs, u_int auxd) 1133 { 1134 emu_command(scp, EMU8K_PTRX, chn, 1135 GENBIT(pt, 16, 16) 1136 | GENBIT(rs, 8, 8) 1137 | GENBIT(auxd, 0, 8)); 1138 } 1139 1140 /* CVCF: Current Volume and Filter Cutoff */ 1141 static void 1142 emu_readcvcf(sc_p scp, int chn, u_int *cv, u_int *cf) 1143 { 1144 u_long sts; 1145 1146 sts = emu_status(scp, EMU8K_CVCF, chn); 1147 if (cv != NULL) 1148 *cv = DECBIT(sts, 16, 16); 1149 if (cf != NULL) 1150 *cf = DECBIT(sts, 0, 16); 1151 } 1152 1153 static void 1154 emu_writecvcf(sc_p scp, int chn, u_int cv, u_int cf) 1155 { 1156 emu_command(scp, EMU8K_CVCF, chn, 1157 GENBIT(cv, 16, 16) 1158 | GENBIT(cf, 0, 16)); 1159 } 1160 1161 /* VTFT: Volume and Filter Cutoff Targets */ 1162 static void 1163 emu_readvtft(sc_p scp, int chn, u_int *vt, u_int *ft) 1164 { 1165 u_long sts; 1166 1167 sts = emu_status(scp, EMU8K_VTFT, chn); 1168 if (vt != NULL) 1169 *vt = DECBIT(sts, 16, 16); 1170 if (ft != NULL) 1171 *ft = DECBIT(sts, 0, 16); 1172 } 1173 1174 static void 1175 emu_writevtft(sc_p scp, int chn, u_int vt, u_int ft) 1176 { 1177 emu_command(scp, EMU8K_VTFT, chn, 1178 GENBIT(vt, 16, 16) 1179 | GENBIT(ft, 0, 16)); 1180 } 1181 1182 /* PSST: Pan Send and Loop Start Address */ 1183 static void 1184 emu_readpsst(sc_p scp, int chn, u_int *pan, u_int *st) 1185 { 1186 u_long sts; 1187 1188 sts = emu_status(scp, EMU8K_PSST, chn); 1189 if (pan != NULL) 1190 *pan = DECBIT(sts, 24, 8); 1191 if (st != NULL) 1192 *st = DECBIT(sts, 0, 24); 1193 } 1194 1195 static void 1196 emu_writepsst(sc_p scp, int chn, u_int pan, u_int st) 1197 { 1198 emu_command(scp, EMU8K_PSST, chn, 1199 GENBIT(pan, 24, 8) 1200 | GENBIT(st, 0, 24)); 1201 } 1202 1203 /* CSL: Chorus Send and Loop End Address */ 1204 static void 1205 emu_readcsl(sc_p scp, int chn, u_int *cs, u_int *lp) 1206 { 1207 u_long sts; 1208 1209 sts = emu_status(scp, EMU8K_CSL, chn); 1210 if (cs != NULL) 1211 *cs = DECBIT(sts, 24, 8); 1212 if (lp != NULL) 1213 *lp = DECBIT(sts, 0, 24); 1214 } 1215 1216 static void 1217 emu_writecsl(sc_p scp, int chn, u_int cs, u_int lp) 1218 { 1219 emu_command(scp, EMU8K_CSL, chn, 1220 GENBIT(cs, 24, 8) 1221 | GENBIT(lp, 0, 24)); 1222 } 1223 1224 /* CCCA: Q, Control Bits and Current Address */ 1225 static void 1226 emu_readccca(sc_p scp, int chn, u_int *q, u_int *dma, u_int *wr, u_int *right, u_int *ca) 1227 { 1228 u_long sts; 1229 1230 sts = emu_status(scp, EMU8K_CCCA, chn); 1231 if (q != NULL) 1232 *q = DECBIT(sts, 28, 4); 1233 if (dma != NULL) 1234 *dma = DECBIT(sts, 26, 1); 1235 if (wr != NULL) 1236 *wr = DECBIT(sts, 25, 1); 1237 if (right != NULL) 1238 *right = DECBIT(sts, 24, 1); 1239 if (ca != NULL) 1240 *ca = DECBIT(sts, 0, 24); 1241 } 1242 1243 static void 1244 emu_writeccca(sc_p scp, int chn, u_int q, u_int dma, u_int wr, u_int right, u_int ca) 1245 { 1246 emu_command(scp, EMU8K_CCCA, chn, 1247 GENBIT(q, 28, 4) 1248 | GENBIT(dma, 26, 1) 1249 | GENBIT(wr, 25, 1) 1250 | GENBIT(right, 24, 1) 1251 | GENBIT(ca, 0, 24)); 1252 } 1253 1254 /* HWCF4: Configuration Double Word 4 */ 1255 static void 1256 emu_readhwcf4(sc_p scp, u_int *val) 1257 { 1258 u_long sts; 1259 1260 sts = emu_status(scp, EMU8K_HWCF4, 0); 1261 if (val != NULL) 1262 *val = sts; 1263 } 1264 1265 static void 1266 emu_writehwcf4(sc_p scp, u_int val) 1267 { 1268 if (val != 0) 1269 printf("emu%d: writing value 0x%x to HWCF4.\n", device_get_unit(scp->dev), val); 1270 emu_command(scp, EMU8K_HWCF4, 0, val); 1271 } 1272 1273 /* HWCF5: Configuration Double Word 5 */ 1274 static void 1275 emu_readhwcf5(sc_p scp, u_int *val) 1276 { 1277 u_long sts; 1278 1279 sts = emu_status(scp, EMU8K_HWCF5, 0); 1280 if (val != NULL) 1281 *val = sts; 1282 } 1283 1284 static void 1285 emu_writehwcf5(sc_p scp, u_int val) 1286 { 1287 if (val != 0x00000083) 1288 printf("emu%d: writing value 0x%x to HWCF5.\n", device_get_unit(scp->dev), val); 1289 emu_command(scp, EMU8K_HWCF5, 0, val); 1290 } 1291 1292 /* HWCF6: Configuration Double Word 6 */ 1293 static void 1294 emu_readhwcf6(sc_p scp, u_int *val) 1295 { 1296 u_long sts; 1297 1298 sts = emu_status(scp, EMU8K_HWCF6, 0); 1299 if (val != NULL) 1300 *val = sts; 1301 } 1302 1303 static void 1304 emu_writehwcf6(sc_p scp, u_int val) 1305 { 1306 if (val != 0x00008000) 1307 printf("emu%d: writing value 0x%x to HWCF6.\n", device_get_unit(scp->dev), val); 1308 emu_command(scp, EMU8K_HWCF6, 0, val); 1309 } 1310 1311 /* SMALR: Sound Memory Address for Left SM Reads */ 1312 static void 1313 emu_readsmalr(sc_p scp, u_int *mt, u_int *smalr) 1314 { 1315 u_long sts; 1316 1317 sts = emu_status(scp, EMU8K_SMALR, 0); 1318 if (mt != NULL) 1319 *mt = DECBIT(sts, 31, 1); 1320 if (smalr != NULL) 1321 *smalr = DECBIT(sts, 0, 24); 1322 } 1323 1324 static void 1325 emu_writesmalr(sc_p scp, u_int mt, u_int smalr) 1326 { 1327 emu_command(scp, EMU8K_SMALR, 0, 1328 GENBIT(mt, 31, 1) 1329 | GENBIT(smalr, 0, 24)); 1330 } 1331 1332 /* SMARR: Sound Memory Address for Right SM Reads */ 1333 static void 1334 emu_readsmarr(sc_p scp, u_int *mt, u_int *smarr) 1335 { 1336 u_long sts; 1337 1338 sts = emu_status(scp, EMU8K_SMARR, 0); 1339 if (mt != NULL) 1340 *mt = DECBIT(sts, 31, 1); 1341 if (smarr != NULL) 1342 *smarr = DECBIT(sts, 0, 24); 1343 } 1344 1345 static void 1346 emu_writesmarr(sc_p scp, u_int mt, u_int smarr) 1347 { 1348 emu_command(scp, EMU8K_SMARR, 0, 1349 GENBIT(mt, 31, 1) 1350 | GENBIT(smarr, 0, 24)); 1351 } 1352 1353 /* SMALW: Sound Memory Address for Left SM Writes */ 1354 static void 1355 emu_readsmalw(sc_p scp, u_int *full, u_int *smalw) 1356 { 1357 u_long sts; 1358 1359 sts = emu_status(scp, EMU8K_SMALW, 0); 1360 if (full != NULL) 1361 *full = DECBIT(sts, 31, 1); 1362 if (smalw != NULL) 1363 *smalw = DECBIT(sts, 0, 24); 1364 } 1365 1366 static void 1367 emu_writesmalw(sc_p scp, u_int full, u_int smalw) 1368 { 1369 emu_command(scp, EMU8K_SMALW, 0, 1370 GENBIT(full, 31, 1) 1371 | GENBIT(smalw, 0, 24)); 1372 } 1373 1374 /* SMARW: Sound Memory Address for Right SM Writes */ 1375 static void 1376 emu_readsmarw(sc_p scp, u_int *full, u_int *smarw) 1377 { 1378 u_long sts; 1379 1380 sts = emu_status(scp, EMU8K_SMARW, 0); 1381 if (full != NULL) 1382 *full = DECBIT(sts, 31, 1); 1383 if (smarw != NULL) 1384 *smarw = DECBIT(sts, 0, 24); 1385 } 1386 1387 static void 1388 emu_writesmarw(sc_p scp, u_int full, u_int smarw) 1389 { 1390 emu_command(scp, EMU8K_SMARW, 0, 1391 GENBIT(full, 31, 1) 1392 | GENBIT(smarw, 0, 24)); 1393 } 1394 1395 /* SMLD: Sound Memory Left Data */ 1396 static void 1397 emu_readsmld(sc_p scp, u_short *smld) 1398 { 1399 u_long sts; 1400 1401 sts = emu_status(scp, EMU8K_SMLD, 0); 1402 if (smld != NULL) 1403 *smld = sts; 1404 } 1405 1406 static void 1407 emu_writesmld(sc_p scp, u_short smld) 1408 { 1409 emu_command(scp, EMU8K_SMLD, 0, smld); 1410 } 1411 1412 /* SMRD: Sound Memory Right Data */ 1413 static void 1414 emu_readsmrd(sc_p scp, u_short *smrd) 1415 { 1416 u_long sts; 1417 1418 sts = emu_status(scp, EMU8K_SMRD, 0); 1419 if (smrd != NULL) 1420 *smrd = sts; 1421 } 1422 1423 static void 1424 emu_writesmrd(sc_p scp, u_short smrd) 1425 { 1426 emu_command(scp, EMU8K_SMRD, 0, smrd); 1427 } 1428 1429 /* WC: Sample COunter */ 1430 static void 1431 emu_readwc(sc_p scp, u_int *wc) 1432 { 1433 u_long sts; 1434 1435 sts = emu_status(scp, EMU8K_WC, 0); 1436 if (wc != NULL) 1437 *wc = sts; 1438 } 1439 1440 static void 1441 emu_writewc(sc_p scp, u_int wc) 1442 { 1443 emu_command(scp, EMU8K_WC, 0, wc); 1444 } 1445 1446 /* HWCF1: Configuration Double Word 1 */ 1447 static void 1448 emu_readhwcf1(sc_p scp, u_int *val) 1449 { 1450 u_long sts; 1451 1452 sts = emu_status(scp, EMU8K_HWCF1, 0); 1453 if (val != NULL) 1454 *val = sts; 1455 } 1456 1457 static void 1458 emu_writehwcf1(sc_p scp, u_int val) 1459 { 1460 if (val != 0x0059) 1461 printf("emu%d: writing value 0x%x to HWCF1.\n", device_get_unit(scp->dev), val); 1462 emu_command(scp, EMU8K_HWCF1, 0, val); 1463 } 1464 1465 /* HWCF2: Configuration Double Word 2 */ 1466 static void 1467 emu_readhwcf2(sc_p scp, u_int *val) 1468 { 1469 u_long sts; 1470 1471 sts = emu_status(scp, EMU8K_HWCF2, 0); 1472 if (val != NULL) 1473 *val = sts; 1474 } 1475 1476 static void 1477 emu_writehwcf2(sc_p scp, u_int val) 1478 { 1479 if (val != 0x0020) 1480 printf("emu%d: writing value 0x%x to HWCF2.\n", device_get_unit(scp->dev), val); 1481 emu_command(scp, EMU8K_HWCF2, 0, val); 1482 } 1483 1484 /* HWCF3: Configuration Double Word 3 */ 1485 static void 1486 emu_readhwcf3(sc_p scp, u_int *val) 1487 { 1488 u_long sts; 1489 1490 sts = emu_status(scp, EMU8K_HWCF3, 0); 1491 if (val != NULL) 1492 *val = sts; 1493 } 1494 1495 static void 1496 emu_writehwcf3(sc_p scp, u_int val) 1497 { 1498 if (val != 0x0004 && val != 0) 1499 printf("emu%d: writing value 0x%x to HWCF3.\n", device_get_unit(scp->dev), val); 1500 emu_command(scp, EMU8K_HWCF3, 0, val); 1501 } 1502 1503 /* INIT1: Initialization Array 1 */ 1504 static void 1505 emu_readinit1(sc_p scp, int chn, u_int *val) 1506 { 1507 u_long sts; 1508 1509 sts = emu_status(scp, EMU8K_INIT1, chn); 1510 if (val != NULL) 1511 *val = sts; 1512 } 1513 1514 static void 1515 emu_writeinit1(sc_p scp, int chn, u_int val) 1516 { 1517 emu_command(scp, EMU8K_INIT1, chn, val); 1518 } 1519 1520 /* INIT2: Initialization Array 2 */ 1521 static void 1522 emu_readinit2(sc_p scp, int chn, u_int *val) 1523 { 1524 u_long sts; 1525 1526 sts = emu_status(scp, EMU8K_INIT2, chn); 1527 if (val != NULL) 1528 *val = sts; 1529 } 1530 1531 static void 1532 emu_writeinit2(sc_p scp, int chn, u_int val) 1533 { 1534 emu_command(scp, EMU8K_INIT2, chn, val); 1535 } 1536 1537 /* INIT3: Initialization Array 3 */ 1538 static void 1539 emu_readinit3(sc_p scp, int chn, u_int *val) 1540 { 1541 u_long sts; 1542 1543 sts = emu_status(scp, EMU8K_INIT3, chn); 1544 if (val != NULL) 1545 *val = sts; 1546 } 1547 1548 static void 1549 emu_writeinit3(sc_p scp, int chn, u_int val) 1550 { 1551 emu_command(scp, EMU8K_INIT3, chn, val); 1552 } 1553 1554 /* INIT4: Initialization Array 4 */ 1555 static void 1556 emu_readinit4(sc_p scp, int chn, u_int *val) 1557 { 1558 u_long sts; 1559 1560 sts = emu_status(scp, EMU8K_INIT4, chn); 1561 if (val != NULL) 1562 *val = sts; 1563 } 1564 1565 static void 1566 emu_writeinit4(sc_p scp, int chn, u_int val) 1567 { 1568 emu_command(scp, EMU8K_INIT4, chn, val); 1569 } 1570 1571 /* ENVVOL: Volume Envelope Decay */ 1572 static void 1573 emu_readenvvol(sc_p scp, int chn, u_int *envvol) 1574 { 1575 u_long sts; 1576 1577 sts = emu_status(scp, EMU8K_ENVVOL, chn); 1578 if (envvol != NULL) 1579 *envvol = sts; 1580 } 1581 1582 static void 1583 emu_writeenvvol(sc_p scp, int chn, u_int envvol) 1584 { 1585 emu_command(scp, EMU8K_ENVVOL, chn, envvol); 1586 } 1587 1588 /* DCYSUSV: Volume Envelope Sustain and Decay */ 1589 static void 1590 emu_readdcysusv(sc_p scp, int chn, u_int *ph1v, u_int *susv, u_int *off, u_int *dcyv) 1591 { 1592 u_long sts; 1593 1594 sts = emu_status(scp, EMU8K_DCYSUSV, chn); 1595 if (ph1v != NULL) 1596 *ph1v = DECBIT(sts, 15, 1); 1597 if (susv != NULL) 1598 *susv = DECBIT(sts, 8, 7); 1599 if (off != NULL) 1600 *off = DECBIT(sts, 7, 1); 1601 if (dcyv != NULL) 1602 *dcyv = DECBIT(sts, 0, 7); 1603 } 1604 1605 static void 1606 emu_writedcysusv(sc_p scp, int chn, u_int ph1v, u_int susv, u_int off, u_int dcyv) 1607 { 1608 emu_command(scp, EMU8K_DCYSUSV, chn, 1609 GENBIT(ph1v, 15, 1) 1610 | GENBIT(susv, 8, 7) 1611 | GENBIT(off, 7, 1) 1612 | GENBIT(dcyv, 0, 7)); 1613 } 1614 1615 /* ENVVAL: Modulation Envelope Decay */ 1616 static void 1617 emu_readenvval(sc_p scp, int chn, u_int *envval) 1618 { 1619 u_long sts; 1620 1621 sts = emu_status(scp, EMU8K_ENVVAL, chn); 1622 if (envval != NULL) 1623 *envval = sts; 1624 } 1625 1626 static void 1627 emu_writeenvval(sc_p scp, int chn, u_int envval) 1628 { 1629 emu_command(scp, EMU8K_ENVVAL, chn, envval); 1630 } 1631 1632 /* DCYSUS: Modulation Envelope Sustain and Decay */ 1633 static void 1634 emu_readdcysus(sc_p scp, int chn, u_int *ph1, u_int *sus, u_int *dcy) 1635 { 1636 u_long sts; 1637 1638 sts = emu_status(scp, EMU8K_DCYSUS, chn); 1639 if (ph1 != NULL) 1640 *ph1 = DECBIT(sts, 15, 1); 1641 if (sus != NULL) 1642 *sus = DECBIT(sts, 8, 7); 1643 if (dcy != NULL) 1644 *dcy = DECBIT(sts, 0, 7); 1645 } 1646 1647 static void 1648 emu_writedcysus(sc_p scp, int chn, u_int ph1, u_int sus, u_int dcy) 1649 { 1650 emu_command(scp, EMU8K_DCYSUS, chn, 1651 GENBIT(ph1, 15, 1) 1652 | GENBIT(sus, 8, 7) 1653 | GENBIT(dcy, 0, 7)); 1654 } 1655 1656 /* ATKHLDV: Volume Envelope Hold and Attack */ 1657 static void 1658 emu_readatkhldv(sc_p scp, int chn, u_int *atkhldv) 1659 { 1660 u_long sts; 1661 1662 sts = emu_status(scp, EMU8K_ATKHLDV, chn); 1663 if (atkhldv != NULL) 1664 *atkhldv = sts; 1665 } 1666 1667 static void 1668 emu_writeatkhldv(sc_p scp, int chn, u_int atkhldv) 1669 { 1670 emu_command(scp, EMU8K_ATKHLDV, chn, atkhldv); 1671 } 1672 1673 /* LFO1VAL: LFO #1 Delay */ 1674 static void 1675 emu_readlfo1val(sc_p scp, int chn, u_int *lfo1val) 1676 { 1677 u_long sts; 1678 1679 sts = emu_status(scp, EMU8K_LFO1VAL, chn); 1680 if (lfo1val != NULL) 1681 *lfo1val = sts; 1682 } 1683 1684 static void 1685 emu_writelfo1val(sc_p scp, int chn, u_int lfo1val) 1686 { 1687 emu_command(scp, EMU8K_LFO1VAL, chn, lfo1val); 1688 } 1689 1690 /* ATKHLD: Modulation Envelope Hold and Attack */ 1691 static void 1692 emu_readatkhld(sc_p scp, int chn, u_int *atkhld) 1693 { 1694 u_long sts; 1695 1696 sts = emu_status(scp, EMU8K_ATKHLD, chn); 1697 if (atkhld != NULL) 1698 *atkhld = sts; 1699 } 1700 1701 static void 1702 emu_writeatkhld(sc_p scp, int chn, u_int atkhld) 1703 { 1704 emu_command(scp, EMU8K_ATKHLD, chn, atkhld); 1705 } 1706 1707 /* LFO2VAL: LFO #2 Delay */ 1708 static void 1709 emu_readlfo2val(sc_p scp, int chn, u_int *lfo2val) 1710 { 1711 u_long sts; 1712 1713 sts = emu_status(scp, EMU8K_LFO2VAL, chn); 1714 if (lfo2val != NULL) 1715 *lfo2val = sts; 1716 } 1717 1718 static void 1719 emu_writelfo2val(sc_p scp, int chn, u_int lfo2val) 1720 { 1721 emu_command(scp, EMU8K_LFO2VAL, chn, lfo2val); 1722 } 1723 1724 /* IP: Initial Pitch */ 1725 static void 1726 emu_readip(sc_p scp, int chn, u_int *ip) 1727 { 1728 u_long sts; 1729 1730 sts = emu_status(scp, EMU8K_IP, chn); 1731 if (ip != NULL) 1732 *ip = sts; 1733 } 1734 1735 static void 1736 emu_writeip(sc_p scp, int chn, u_int ip) 1737 { 1738 emu_command(scp, EMU8K_IP, chn, ip); 1739 } 1740 1741 /* IFATN: Initial Filter Cutoff and Attenuation */ 1742 static void 1743 emu_readifatn(sc_p scp, int chn, u_int *ifc, u_int *atn) 1744 { 1745 u_long sts; 1746 1747 sts = emu_status(scp, EMU8K_IFATN, chn); 1748 if (ifc != NULL) 1749 *ifc = DECBIT(sts, 8, 8); 1750 if (atn != NULL) 1751 *atn = DECBIT(sts, 0, 8); 1752 } 1753 1754 static void 1755 emu_writeifatn(sc_p scp, int chn, u_int ifc, u_int atn) 1756 { 1757 emu_command(scp, EMU8K_IFATN, chn, 1758 GENBIT(ifc, 8, 8) 1759 | GENBIT(atn, 0, 8)); 1760 } 1761 1762 /* PEFE: Pitch and Filter Envelope Heights */ 1763 static void 1764 emu_readpefe(sc_p scp, int chn, u_int *pe, u_int *fe) 1765 { 1766 u_long sts; 1767 1768 sts = emu_status(scp, EMU8K_PEFE, chn); 1769 if (pe != NULL) 1770 *pe = DECBIT(sts, 8, 8); 1771 if (fe != NULL) 1772 *fe = DECBIT(sts, 0, 8); 1773 } 1774 1775 static void 1776 emu_writepefe(sc_p scp, int chn, u_int pe, u_int fe) 1777 { 1778 emu_command(scp, EMU8K_PEFE, chn, 1779 GENBIT(pe, 8, 8) 1780 | GENBIT(fe, 0, 8)); 1781 } 1782 1783 /* FMMOD: Vibrato and Filter Modulation from LFO #1 */ 1784 static void 1785 emu_readfmmod(sc_p scp, int chn, u_int *fm, u_int *mod) 1786 { 1787 u_long sts; 1788 1789 sts = emu_status(scp, EMU8K_FMMOD, chn); 1790 if (fm != NULL) 1791 *fm = DECBIT(sts, 8, 8); 1792 if (mod != NULL) 1793 *mod = DECBIT(sts, 0, 8); 1794 } 1795 1796 static void 1797 emu_writefmmod(sc_p scp, int chn, u_int fm, u_int mod) 1798 { 1799 emu_command(scp, EMU8K_FMMOD, chn, 1800 GENBIT(fm, 8, 8) 1801 | GENBIT(mod, 0, 8)); 1802 } 1803 1804 /* TREMFRQ: LFO #1 Tremolo Amount and Frequency */ 1805 static void 1806 emu_readtremfrq(sc_p scp, int chn, u_int *trem, u_int *frq) 1807 { 1808 u_long sts; 1809 1810 sts = emu_status(scp, EMU8K_TREMFRQ, chn); 1811 if (trem != NULL) 1812 *trem = DECBIT(sts, 8, 8); 1813 if (frq != NULL) 1814 *frq = DECBIT(sts, 0, 8); 1815 } 1816 1817 static void 1818 emu_writetremfrq(sc_p scp, int chn, u_int trem, u_int frq) 1819 { 1820 emu_command(scp, EMU8K_TREMFRQ, chn, 1821 GENBIT(trem, 8, 8) 1822 | GENBIT(frq, 0, 8)); 1823 } 1824 1825 /* FM2FRQ2: LFO #2 Vibrato Amount and Frequency */ 1826 static void 1827 emu_readfm2frq2(sc_p scp, int chn, u_int *fm2, u_int *frq2) 1828 { 1829 u_long sts; 1830 1831 sts = emu_status(scp, EMU8K_FM2FRQ2, chn); 1832 if (fm2 != NULL) 1833 *fm2 = DECBIT(sts, 8, 8); 1834 if (frq2 != NULL) 1835 *frq2 = DECBIT(sts, 0, 8); 1836 } 1837 1838 static void 1839 emu_writefm2frq2(sc_p scp, int chn, u_int fm2, u_int frq2) 1840 { 1841 emu_command(scp, EMU8K_FM2FRQ2, chn, 1842 GENBIT(fm2, 8, 8) 1843 | GENBIT(frq2, 0, 8)); 1844 } 1845 1846 /* PROBE: Probe Register */ 1847 static void 1848 emu_readprobe(sc_p scp, u_int *val) 1849 { 1850 u_long sts; 1851 1852 sts = emu_status(scp, EMU8K_PROBE, 0); 1853 if (val != NULL) 1854 *val = sts; 1855 } 1856 1857 static void 1858 emu_writeprobe(sc_p scp, u_int val) 1859 { 1860 emu_command(scp, EMU8K_PROBE, 0, val); 1861 } 1862 1863 /* Writes to a register. */ 1864 static void 1865 emu_command(sc_p scp, int reg, int chn, u_long val) 1866 { 1867 if (chn < 0 || chn >= EMU8K_MAXVOICE || reg < 0 || reg >= EMU8K_REGNUM) 1868 return; 1869 1870 /* Override the channel if necessary. */ 1871 if (emu_regs[reg].chn != EMU8K_CHN_ANY) 1872 chn = emu_regs[reg].chn; 1873 1874 /* Select the register first. */ 1875 bus_space_write_2(rman_get_bustag(scp->io[EMU8K_IDX_PTR]), rman_get_bushandle(scp->io[EMU8K_IDX_PTR]), EMU8K_PORT_PTR, (chn & 0x1f) | ((emu_regs[reg].reg & 0x07) << 5)); 1876 1877 /* Then we write the data. */ 1878 bus_space_write_2(rman_get_bustag(scp->io[emu_regs[reg].index]), rman_get_bushandle(scp->io[emu_regs[reg].index]), emu_regs[reg].port, val & 0xffff); 1879 if (emu_regs[reg].size) 1880 /* double word */ 1881 bus_space_write_2(rman_get_bustag(scp->io[emu_regs[reg].index]), rman_get_bushandle(scp->io[emu_regs[reg].index]), emu_regs[reg].port + 2, (val >> 16) & 0xffff); 1882 } 1883 1884 /* Reads from a register. */ 1885 static u_long 1886 emu_status(sc_p scp, int reg, int chn) 1887 { 1888 u_long status; 1889 1890 if (chn < 0 || chn >= EMU8K_MAXVOICE || reg < 0 || reg >= EMU8K_REGNUM) 1891 return (0xffffffff); 1892 1893 /* Override the channel if necessary. */ 1894 if (emu_regs[reg].chn != EMU8K_CHN_ANY) 1895 chn = emu_regs[reg].chn; 1896 1897 /* Select the register first. */ 1898 bus_space_write_2(rman_get_bustag(scp->io[EMU8K_IDX_PTR]), rman_get_bushandle(scp->io[EMU8K_IDX_PTR]), EMU8K_PORT_PTR, (chn & 0x1f) | ((emu_regs[reg].reg & 0x07) << 5)); 1899 1900 /* Then we read the data. */ 1901 status = bus_space_read_2(rman_get_bustag(scp->io[emu_regs[reg].index]), rman_get_bushandle(scp->io[emu_regs[reg].index]), emu_regs[reg].port) & 0xffff; 1902 if (emu_regs[reg].size) 1903 /* double word */ 1904 status |= (bus_space_read_2(rman_get_bustag(scp->io[emu_regs[reg].index]), rman_get_bushandle(scp->io[emu_regs[reg].index]), emu_regs[reg].port + 2) & 0xffff) << 16; 1905 1906 return (status); 1907 } 1908 1909 /* Allocates resources. */ 1910 static int 1911 emu_allocres(sc_p scp, device_t dev) 1912 { 1913 int i; 1914 1915 /* 1916 * Attempt to allocate the EMU8000's three I/O port ranges. 1917 */ 1918 for (i = 0; i < 3; i++) 1919 { 1920 if (scp->io[i] == NULL) 1921 { 1922 scp->io_rid[i] = i; 1923 scp->io[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, 1924 &(scp->io_rid[i]), 1925 0, ~0, 4, RF_ACTIVE); 1926 } 1927 } 1928 1929 /* 1930 * Fail if any of the I/O ranges failed (I.e. weren't identified and 1931 * configured by PNP, which can happen if the ID of the card isn't 1932 * known by the PNP quirk-handling logic) 1933 */ 1934 if (scp->io[0] == NULL || scp->io[1] == NULL || scp->io[2] == NULL) 1935 { 1936 printf("emu%d: Resource alloc failed, pnp_quirks " 1937 "may need { 0x%08x, 0x%08x }\n", 1938 device_get_unit(dev), 1939 isa_get_vendorid(dev), 1940 isa_get_logicalid(dev)); 1941 1942 return 1; 1943 } 1944 1945 return 0; 1946 } 1947 1948 /* Releases resources. */ 1949 static void 1950 emu_releaseres(sc_p scp, device_t dev) 1951 { 1952 if (scp->io[0] != NULL) { 1953 bus_release_resource(dev, SYS_RES_IOPORT, scp->io_rid[0], scp->io[0]); 1954 scp->io[0] = NULL; 1955 } 1956 if (scp->io[1] != NULL) { 1957 bus_release_resource(dev, SYS_RES_IOPORT, scp->io_rid[1], scp->io[1]); 1958 scp->io[1] = NULL; 1959 } 1960 if (scp->io[2] != NULL) { 1961 bus_release_resource(dev, SYS_RES_IOPORT, scp->io_rid[2], scp->io[2]); 1962 scp->io[2] = NULL; 1963 } 1964 } 1965 1966 static device_method_t emu_methods[] = { 1967 /* Device interface */ 1968 DEVMETHOD(device_probe , emu_probe ), 1969 DEVMETHOD(device_attach, emu_attach), 1970 1971 { 0, 0 }, 1972 }; 1973 1974 static driver_t emu_driver = { 1975 "midi", 1976 emu_methods, 1977 sizeof(struct emu_softc), 1978 }; 1979 1980 DRIVER_MODULE(emu, isa, emu_driver, midi_devclass, 0, 0);
Cache object: f1c80028f4aed13b7ed8c03275e28679
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