The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/isa/mss.c

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    1 /*-
    2  * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
    3  * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
    4  * Copyright (c) 1997,1998 Luigi Rizzo
    5  * Copyright (c) 1994,1995 Hannu Savolainen
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 #ifdef HAVE_KERNEL_OPTION_HEADERS
   31 #include "opt_snd.h"
   32 #endif
   33 
   34 #include <dev/sound/pcm/sound.h>
   35 
   36 SND_DECLARE_FILE("$FreeBSD: releng/11.0/sys/dev/sound/isa/mss.c 297862 2016-04-12 17:23:03Z pfg $");
   37 
   38 /* board-specific include files */
   39 #include <dev/sound/isa/mss.h>
   40 #include <dev/sound/isa/sb.h>
   41 #include <dev/sound/chip.h>
   42 
   43 #include <isa/isavar.h>
   44 
   45 #include "mixer_if.h"
   46 
   47 #define MSS_DEFAULT_BUFSZ (4096)
   48 #define MSS_INDEXED_REGS 0x20
   49 #define OPL_INDEXED_REGS 0x19
   50 
   51 struct mss_info;
   52 
   53 struct mss_chinfo {
   54         struct mss_info *parent;
   55         struct pcm_channel *channel;
   56         struct snd_dbuf *buffer;
   57         int dir;
   58         u_int32_t fmt, blksz;
   59 };
   60 
   61 struct mss_info {
   62     struct resource *io_base;   /* primary I/O address for the board */
   63     int              io_rid;
   64     struct resource *conf_base; /* and the opti931 also has a config space */
   65     int              conf_rid;
   66     struct resource *irq;
   67     int              irq_rid;
   68     struct resource *drq1; /* play */
   69     int              drq1_rid;
   70     struct resource *drq2; /* rec */
   71     int              drq2_rid;
   72     void            *ih;
   73     bus_dma_tag_t    parent_dmat;
   74     struct mtx      *lock;
   75 
   76     char mss_indexed_regs[MSS_INDEXED_REGS];
   77     char opl_indexed_regs[OPL_INDEXED_REGS];
   78     int bd_id;      /* used to hold board-id info, eg. sb version,
   79                      * mss codec type, etc. etc.
   80                      */
   81     int opti_offset;            /* offset from config_base for opti931 */
   82     u_long  bd_flags;       /* board-specific flags */
   83     int optibase;               /* base address for OPTi9xx config */
   84     struct resource *indir;     /* Indirect register index address */
   85     int indir_rid;
   86     int password;               /* password for opti9xx cards */
   87     int passwdreg;              /* password register */
   88     unsigned int bufsize;
   89     struct mss_chinfo pch, rch;
   90 };
   91 
   92 static int              mss_probe(device_t dev);
   93 static int              mss_attach(device_t dev);
   94 
   95 static driver_intr_t    mss_intr;
   96 
   97 /* prototypes for local functions */
   98 static int              mss_detect(device_t dev, struct mss_info *mss);
   99 #ifndef PC98
  100 static int              opti_detect(device_t dev, struct mss_info *mss);
  101 #endif
  102 static char             *ymf_test(device_t dev, struct mss_info *mss);
  103 static void             ad_unmute(struct mss_info *mss);
  104 
  105 /* mixer set funcs */
  106 static int              mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
  107 static int              mss_set_recsrc(struct mss_info *mss, int mask);
  108 
  109 /* io funcs */
  110 static int              ad_wait_init(struct mss_info *mss, int x);
  111 static int              ad_read(struct mss_info *mss, int reg);
  112 static void             ad_write(struct mss_info *mss, int reg, u_char data);
  113 static void             ad_write_cnt(struct mss_info *mss, int reg, u_short data);
  114 static void             ad_enter_MCE(struct mss_info *mss);
  115 static void             ad_leave_MCE(struct mss_info *mss);
  116 
  117 /* OPTi-specific functions */
  118 static void             opti_write(struct mss_info *mss, u_char reg,
  119                                    u_char data);
  120 #ifndef PC98
  121 static u_char           opti_read(struct mss_info *mss, u_char reg);
  122 #endif
  123 static int              opti_init(device_t dev, struct mss_info *mss);
  124 
  125 /* io primitives */
  126 static void             conf_wr(struct mss_info *mss, u_char reg, u_char data);
  127 static u_char           conf_rd(struct mss_info *mss, u_char reg);
  128 
  129 static int              pnpmss_probe(device_t dev);
  130 static int              pnpmss_attach(device_t dev);
  131 
  132 static driver_intr_t    opti931_intr;
  133 
  134 static u_int32_t mss_fmt[] = {
  135         SND_FORMAT(AFMT_U8, 1, 0),
  136         SND_FORMAT(AFMT_U8, 2, 0),
  137         SND_FORMAT(AFMT_S16_LE, 1, 0),
  138         SND_FORMAT(AFMT_S16_LE, 2, 0),
  139         SND_FORMAT(AFMT_MU_LAW, 1, 0),
  140         SND_FORMAT(AFMT_MU_LAW, 2, 0),
  141         SND_FORMAT(AFMT_A_LAW, 1, 0),
  142         SND_FORMAT(AFMT_A_LAW, 2, 0),
  143         0
  144 };
  145 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
  146 
  147 static u_int32_t guspnp_fmt[] = {
  148         SND_FORMAT(AFMT_U8, 1, 0),
  149         SND_FORMAT(AFMT_U8, 2, 0),
  150         SND_FORMAT(AFMT_S16_LE, 1, 0),
  151         SND_FORMAT(AFMT_S16_LE, 2, 0),
  152         SND_FORMAT(AFMT_A_LAW, 1, 0),
  153         SND_FORMAT(AFMT_A_LAW, 2, 0),
  154         0
  155 };
  156 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
  157 
  158 static u_int32_t opti931_fmt[] = {
  159         SND_FORMAT(AFMT_U8, 1, 0),
  160         SND_FORMAT(AFMT_U8, 2, 0),
  161         SND_FORMAT(AFMT_S16_LE, 1, 0),
  162         SND_FORMAT(AFMT_S16_LE, 2, 0),
  163         0
  164 };
  165 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
  166 
  167 #define MD_AD1848       0x91
  168 #define MD_AD1845       0x92
  169 #define MD_CS42XX       0xA1
  170 #define MD_CS423X       0xA2
  171 #define MD_OPTI930      0xB0
  172 #define MD_OPTI931      0xB1
  173 #define MD_OPTI925      0xB2
  174 #define MD_OPTI924      0xB3
  175 #define MD_GUSPNP       0xB8
  176 #define MD_GUSMAX       0xB9
  177 #define MD_YM0020       0xC1
  178 #define MD_VIVO         0xD1
  179 
  180 #define DV_F_TRUE_MSS   0x00010000      /* mss _with_ base regs */
  181 
  182 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
  183 
  184 static void
  185 mss_lock(struct mss_info *mss)
  186 {
  187         snd_mtxlock(mss->lock);
  188 }
  189 
  190 static void
  191 mss_unlock(struct mss_info *mss)
  192 {
  193         snd_mtxunlock(mss->lock);
  194 }
  195 
  196 static int
  197 port_rd(struct resource *port, int off)
  198 {
  199         if (port)
  200                 return bus_space_read_1(rman_get_bustag(port),
  201                                         rman_get_bushandle(port),
  202                                         off);
  203         else
  204                 return -1;
  205 }
  206 
  207 static void
  208 port_wr(struct resource *port, int off, u_int8_t data)
  209 {
  210         if (port)
  211                 bus_space_write_1(rman_get_bustag(port),
  212                                   rman_get_bushandle(port),
  213                                   off, data);
  214 }
  215 
  216 static int
  217 io_rd(struct mss_info *mss, int reg)
  218 {
  219         if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
  220         return port_rd(mss->io_base, reg);
  221 }
  222 
  223 static void
  224 io_wr(struct mss_info *mss, int reg, u_int8_t data)
  225 {
  226         if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
  227         port_wr(mss->io_base, reg, data);
  228 }
  229 
  230 static void
  231 conf_wr(struct mss_info *mss, u_char reg, u_char value)
  232 {
  233         port_wr(mss->conf_base, 0, reg);
  234         port_wr(mss->conf_base, 1, value);
  235 }
  236 
  237 static u_char
  238 conf_rd(struct mss_info *mss, u_char reg)
  239 {
  240         port_wr(mss->conf_base, 0, reg);
  241         return port_rd(mss->conf_base, 1);
  242 }
  243 
  244 static void
  245 opti_wr(struct mss_info *mss, u_char reg, u_char value)
  246 {
  247         port_wr(mss->conf_base, mss->opti_offset + 0, reg);
  248         port_wr(mss->conf_base, mss->opti_offset + 1, value);
  249 }
  250 
  251 static u_char
  252 opti_rd(struct mss_info *mss, u_char reg)
  253 {
  254         port_wr(mss->conf_base, mss->opti_offset + 0, reg);
  255         return port_rd(mss->conf_base, mss->opti_offset + 1);
  256 }
  257 
  258 static void
  259 gus_wr(struct mss_info *mss, u_char reg, u_char value)
  260 {
  261         port_wr(mss->conf_base, 3, reg);
  262         port_wr(mss->conf_base, 5, value);
  263 }
  264 
  265 static u_char
  266 gus_rd(struct mss_info *mss, u_char reg)
  267 {
  268         port_wr(mss->conf_base, 3, reg);
  269         return port_rd(mss->conf_base, 5);
  270 }
  271 
  272 static void
  273 mss_release_resources(struct mss_info *mss, device_t dev)
  274 {
  275         if (mss->irq) {
  276                 if (mss->ih)
  277                         bus_teardown_intr(dev, mss->irq, mss->ih);
  278                 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
  279                                      mss->irq);
  280                 mss->irq = NULL;
  281         }
  282         if (mss->drq2) {
  283                 if (mss->drq2 != mss->drq1) {
  284                         isa_dma_release(rman_get_start(mss->drq2));
  285                         bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
  286                                         mss->drq2);
  287                 }
  288                 mss->drq2 = NULL;
  289         }
  290         if (mss->drq1) {
  291                 isa_dma_release(rman_get_start(mss->drq1));
  292                 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
  293                                      mss->drq1);
  294                 mss->drq1 = NULL;
  295         }
  296         if (mss->io_base) {
  297                 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
  298                                      mss->io_base);
  299                 mss->io_base = NULL;
  300         }
  301         if (mss->conf_base) {
  302                 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
  303                                      mss->conf_base);
  304                 mss->conf_base = NULL;
  305         }
  306         if (mss->indir) {
  307                 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
  308                                      mss->indir);
  309                 mss->indir = NULL;
  310         }
  311         if (mss->parent_dmat) {
  312                 bus_dma_tag_destroy(mss->parent_dmat);
  313                 mss->parent_dmat = 0;
  314         }
  315         if (mss->lock) snd_mtxfree(mss->lock);
  316 
  317         free(mss, M_DEVBUF);
  318 }
  319 
  320 static int
  321 mss_alloc_resources(struct mss_info *mss, device_t dev)
  322 {
  323         int pdma, rdma, ok = 1;
  324         if (!mss->io_base)
  325                 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  326                                                       &mss->io_rid, RF_ACTIVE);
  327         if (!mss->irq)
  328                 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  329                                                   &mss->irq_rid, RF_ACTIVE);
  330         if (!mss->drq1)
  331                 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
  332                                                    &mss->drq1_rid,
  333                                                    RF_ACTIVE);
  334         if (mss->conf_rid >= 0 && !mss->conf_base)
  335                 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  336                                                         &mss->conf_rid,
  337                                                         RF_ACTIVE);
  338         if (mss->drq2_rid >= 0 && !mss->drq2)
  339                 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
  340                                                    &mss->drq2_rid,
  341                                                    RF_ACTIVE);
  342 
  343         if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
  344         if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
  345         if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
  346 
  347         if (ok) {
  348                 pdma = rman_get_start(mss->drq1);
  349                 isa_dma_acquire(pdma);
  350                 isa_dmainit(pdma, mss->bufsize);
  351                 mss->bd_flags &= ~BD_F_DUPLEX;
  352                 if (mss->drq2) {
  353                         rdma = rman_get_start(mss->drq2);
  354                         isa_dma_acquire(rdma);
  355                         isa_dmainit(rdma, mss->bufsize);
  356                         mss->bd_flags |= BD_F_DUPLEX;
  357                 } else mss->drq2 = mss->drq1;
  358         }
  359         return ok;
  360 }
  361 
  362 /*
  363  * The various mixers use a variety of bitmasks etc. The Voxware
  364  * driver had a very nice technique to describe a mixer and interface
  365  * to it. A table defines, for each channel, which register, bits,
  366  * offset, polarity to use. This procedure creates the new value
  367  * using the table and the old value.
  368  */
  369 
  370 static void
  371 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
  372 {
  373         u_char mask;
  374         int shift;
  375 
  376         DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
  377                 "r %d p %d bit %d off %d\n",
  378                 dev, chn, newval, *regval,
  379                 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
  380                 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
  381 
  382         if ( (*t)[dev][chn].polarity == 1)      /* reverse */
  383                 newval = 100 - newval ;
  384 
  385         mask = (1 << (*t)[dev][chn].nbits) - 1;
  386         newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
  387         shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
  388 
  389         *regval &= ~(mask << shift);        /* Filter out the previous value */
  390         *regval |= (newval & mask) << shift;        /* Set the new value */
  391 }
  392 
  393 /* -------------------------------------------------------------------- */
  394 /* only one source can be set... */
  395 static int
  396 mss_set_recsrc(struct mss_info *mss, int mask)
  397 {
  398         u_char   recdev;
  399 
  400         switch (mask) {
  401         case SOUND_MASK_LINE:
  402         case SOUND_MASK_LINE3:
  403                 recdev = 0;
  404                 break;
  405 
  406         case SOUND_MASK_CD:
  407         case SOUND_MASK_LINE1:
  408                 recdev = 0x40;
  409                 break;
  410 
  411         case SOUND_MASK_IMIX:
  412                 recdev = 0xc0;
  413                 break;
  414 
  415         case SOUND_MASK_MIC:
  416         default:
  417                 mask = SOUND_MASK_MIC;
  418                 recdev = 0x80;
  419         }
  420         ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
  421         ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
  422         return mask;
  423 }
  424 
  425 /* there are differences in the mixer depending on the actual sound card. */
  426 static int
  427 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
  428 {
  429         int        regoffs;
  430         mixer_tab *mix_d;
  431         u_char     old, val;
  432 
  433         switch (mss->bd_id) {
  434                 case MD_OPTI931:
  435                         mix_d = &opti931_devices;
  436                         break;
  437                 case MD_OPTI930:
  438                         mix_d = &opti930_devices;
  439                         break;
  440                 default:
  441                         mix_d = &mix_devices;
  442         }
  443 
  444         if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
  445                 DEB(printf("nbits = 0 for dev %d\n", dev));
  446                 return -1;
  447         }
  448 
  449         if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
  450 
  451         /* Set the left channel */
  452 
  453         regoffs = (*mix_d)[dev][LEFT_CHN].regno;
  454         old = val = ad_read(mss, regoffs);
  455         /* if volume is 0, mute chan. Otherwise, unmute. */
  456         if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
  457         change_bits(mix_d, &val, dev, LEFT_CHN, left);
  458         ad_write(mss, regoffs, val);
  459 
  460         DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
  461                 dev, regoffs, old, val));
  462 
  463         if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
  464                 /* Set the right channel */
  465                 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
  466                 old = val = ad_read(mss, regoffs);
  467                 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
  468                 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
  469                 ad_write(mss, regoffs, val);
  470 
  471                 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
  472                 dev, regoffs, old, val));
  473         }
  474         return 0; /* success */
  475 }
  476 
  477 /* -------------------------------------------------------------------- */
  478 
  479 static int
  480 mssmix_init(struct snd_mixer *m)
  481 {
  482         struct mss_info *mss = mix_getdevinfo(m);
  483 
  484         mix_setdevs(m, MODE2_MIXER_DEVICES);
  485         mix_setrecdevs(m, MSS_REC_DEVICES);
  486         switch(mss->bd_id) {
  487         case MD_OPTI930:
  488                 mix_setdevs(m, OPTI930_MIXER_DEVICES);
  489                 break;
  490 
  491         case MD_OPTI931:
  492                 mix_setdevs(m, OPTI931_MIXER_DEVICES);
  493                 mss_lock(mss);
  494                 ad_write(mss, 20, 0x88);
  495                 ad_write(mss, 21, 0x88);
  496                 mss_unlock(mss);
  497                 break;
  498 
  499         case MD_AD1848:
  500                 mix_setdevs(m, MODE1_MIXER_DEVICES);
  501                 break;
  502 
  503         case MD_GUSPNP:
  504         case MD_GUSMAX:
  505                 /* this is only necessary in mode 3 ... */
  506                 mss_lock(mss);
  507                 ad_write(mss, 22, 0x88);
  508                 ad_write(mss, 23, 0x88);
  509                 mss_unlock(mss);
  510                 break;
  511         }
  512         return 0;
  513 }
  514 
  515 static int
  516 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
  517 {
  518         struct mss_info *mss = mix_getdevinfo(m);
  519 
  520         mss_lock(mss);
  521         mss_mixer_set(mss, dev, left, right);
  522         mss_unlock(mss);
  523 
  524         return left | (right << 8);
  525 }
  526 
  527 static u_int32_t
  528 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
  529 {
  530         struct mss_info *mss = mix_getdevinfo(m);
  531 
  532         mss_lock(mss);
  533         src = mss_set_recsrc(mss, src);
  534         mss_unlock(mss);
  535         return src;
  536 }
  537 
  538 static kobj_method_t mssmix_mixer_methods[] = {
  539         KOBJMETHOD(mixer_init,          mssmix_init),
  540         KOBJMETHOD(mixer_set,           mssmix_set),
  541         KOBJMETHOD(mixer_setrecsrc,     mssmix_setrecsrc),
  542         KOBJMETHOD_END
  543 };
  544 MIXER_DECLARE(mssmix_mixer);
  545 
  546 /* -------------------------------------------------------------------- */
  547 
  548 static int
  549 ymmix_init(struct snd_mixer *m)
  550 {
  551         struct mss_info *mss = mix_getdevinfo(m);
  552 
  553         mssmix_init(m);
  554         mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
  555                                       | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
  556         /* Set master volume */
  557         mss_lock(mss);
  558         conf_wr(mss, OPL3SAx_VOLUMEL, 7);
  559         conf_wr(mss, OPL3SAx_VOLUMER, 7);
  560         mss_unlock(mss);
  561 
  562         return 0;
  563 }
  564 
  565 static int
  566 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
  567 {
  568         struct mss_info *mss = mix_getdevinfo(m);
  569         int t, l, r;
  570 
  571         mss_lock(mss);
  572         switch (dev) {
  573         case SOUND_MIXER_VOLUME:
  574                 if (left) t = 15 - (left * 15) / 100;
  575                 else t = 0x80; /* mute */
  576                 conf_wr(mss, OPL3SAx_VOLUMEL, t);
  577                 if (right) t = 15 - (right * 15) / 100;
  578                 else t = 0x80; /* mute */
  579                 conf_wr(mss, OPL3SAx_VOLUMER, t);
  580                 break;
  581 
  582         case SOUND_MIXER_MIC:
  583                 t = left;
  584                 if (left) t = 31 - (left * 31) / 100;
  585                 else t = 0x80; /* mute */
  586                 conf_wr(mss, OPL3SAx_MIC, t);
  587                 break;
  588 
  589         case SOUND_MIXER_BASS:
  590                 l = (left * 7) / 100;
  591                 r = (right * 7) / 100;
  592                 t = (r << 4) | l;
  593                 conf_wr(mss, OPL3SAx_BASS, t);
  594                 break;
  595 
  596         case SOUND_MIXER_TREBLE:
  597                 l = (left * 7) / 100;
  598                 r = (right * 7) / 100;
  599                 t = (r << 4) | l;
  600                 conf_wr(mss, OPL3SAx_TREBLE, t);
  601                 break;
  602 
  603         default:
  604                 mss_mixer_set(mss, dev, left, right);
  605         }
  606         mss_unlock(mss);
  607 
  608         return left | (right << 8);
  609 }
  610 
  611 static u_int32_t
  612 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
  613 {
  614         struct mss_info *mss = mix_getdevinfo(m);
  615         mss_lock(mss);
  616         src = mss_set_recsrc(mss, src);
  617         mss_unlock(mss);
  618         return src;
  619 }
  620 
  621 static kobj_method_t ymmix_mixer_methods[] = {
  622         KOBJMETHOD(mixer_init,          ymmix_init),
  623         KOBJMETHOD(mixer_set,           ymmix_set),
  624         KOBJMETHOD(mixer_setrecsrc,     ymmix_setrecsrc),
  625         KOBJMETHOD_END
  626 };
  627 MIXER_DECLARE(ymmix_mixer);
  628 
  629 /* -------------------------------------------------------------------- */
  630 /*
  631  * XXX This might be better off in the gusc driver.
  632  */
  633 static void
  634 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
  635 {
  636         static const unsigned char irq_bits[16] = {
  637                 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
  638         };
  639         static const unsigned char dma_bits[8] = {
  640                 0, 1, 0, 2, 0, 3, 4, 5
  641         };
  642         device_t parent = device_get_parent(dev);
  643         unsigned char irqctl, dmactl;
  644         int s;
  645 
  646         s = splhigh();
  647 
  648         port_wr(alt, 0x0f, 0x05);
  649         port_wr(alt, 0x00, 0x0c);
  650         port_wr(alt, 0x0b, 0x00);
  651 
  652         port_wr(alt, 0x0f, 0x00);
  653 
  654         irqctl = irq_bits[isa_get_irq(parent)];
  655         /* Share the IRQ with the MIDI driver.  */
  656         irqctl |= 0x40;
  657         dmactl = dma_bits[isa_get_drq(parent)];
  658         if (device_get_flags(parent) & DV_F_DUAL_DMA)
  659                 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
  660                     << 3;
  661 
  662         /*
  663          * Set the DMA and IRQ control latches.
  664          */
  665         port_wr(alt, 0x00, 0x0c);
  666         port_wr(alt, 0x0b, dmactl | 0x80);
  667         port_wr(alt, 0x00, 0x4c);
  668         port_wr(alt, 0x0b, irqctl);
  669 
  670         port_wr(alt, 0x00, 0x0c);
  671         port_wr(alt, 0x0b, dmactl);
  672         port_wr(alt, 0x00, 0x4c);
  673         port_wr(alt, 0x0b, irqctl);
  674 
  675         port_wr(mss->conf_base, 2, 0);
  676         port_wr(alt, 0x00, 0x0c);
  677         port_wr(mss->conf_base, 2, 0);
  678 
  679         splx(s);
  680 }
  681 
  682 static int
  683 mss_init(struct mss_info *mss, device_t dev)
  684 {
  685         u_char r6, r9;
  686         struct resource *alt;
  687         int rid, tmp;
  688 
  689         mss->bd_flags |= BD_F_MCE_BIT;
  690         switch(mss->bd_id) {
  691         case MD_OPTI931:
  692                 /*
  693                  * The MED3931 v.1.0 allocates 3 bytes for the config
  694                  * space, whereas v.2.0 allocates 4 bytes. What I know
  695                  * for sure is that the upper two ports must be used,
  696                  * and they should end on a boundary of 4 bytes. So I
  697                  * need the following trick.
  698                  */
  699                 mss->opti_offset =
  700                         (rman_get_start(mss->conf_base) & ~3) + 2
  701                         - rman_get_start(mss->conf_base);
  702                 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
  703                 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
  704                 ad_write(mss, 10, 2); /* enable interrupts */
  705                 opti_wr(mss, 6, 2);  /* MCIR6: mss enable, sb disable */
  706                 opti_wr(mss, 5, 0x28);  /* MCIR5: codec in exp. mode,fifo */
  707                 break;
  708 
  709         case MD_GUSPNP:
  710         case MD_GUSMAX:
  711                 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
  712                 DELAY(1000 * 30);
  713                 /* release reset  and enable DAC */
  714                 gus_wr(mss, 0x4c /* _URSTI */, 3);
  715                 DELAY(1000 * 30);
  716                 /* end of reset */
  717 
  718                 rid = 0;
  719                 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
  720                                              RF_ACTIVE);
  721                 if (alt == NULL) {
  722                         printf("XXX couldn't init GUS PnP/MAX\n");
  723                         break;
  724                 }
  725                 port_wr(alt, 0, 0xC); /* enable int and dma */
  726                 if (mss->bd_id == MD_GUSMAX)
  727                         gusmax_setup(mss, dev, alt);
  728                 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
  729 
  730                 /*
  731                  * unmute left & right line. Need to go in mode3, unmute,
  732                  * and back to mode 2
  733                  */
  734                 tmp = ad_read(mss, 0x0c);
  735                 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
  736                 ad_write(mss, 0x19, 0); /* unmute left */
  737                 ad_write(mss, 0x1b, 0); /* unmute right */
  738                 ad_write(mss, 0x0c, tmp); /* restore old mode */
  739 
  740                 /* send codec interrupts on irq1 and only use that one */
  741                 gus_wr(mss, 0x5a, 0x4f);
  742 
  743                 /* enable access to hidden regs */
  744                 tmp = gus_rd(mss, 0x5b /* IVERI */);
  745                 gus_wr(mss, 0x5b, tmp | 1);
  746                 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
  747                 break;
  748 
  749         case MD_YM0020:
  750                 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
  751                 r6 = conf_rd(mss, OPL3SAx_DMACONF);
  752                 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
  753                 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
  754                 /* yamaha - set volume to max */
  755                 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
  756                 conf_wr(mss, OPL3SAx_VOLUMER, 0);
  757                 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
  758                 break;
  759         }
  760         if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
  761                 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
  762         ad_enter_MCE(mss);
  763         ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
  764         ad_leave_MCE(mss);
  765         ad_write(mss, 10, 2); /* int enable */
  766         io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
  767         /* the following seem required on the CS4232 */
  768         ad_unmute(mss);
  769         return 0;
  770 }
  771 
  772 
  773 /*
  774  * main irq handler for the CS423x. The OPTi931 code is
  775  * a separate one.
  776  * The correct way to operate for a device with multiple internal
  777  * interrupt sources is to loop on the status register and ack
  778  * interrupts until all interrupts are served and none are reported. At
  779  * this point the IRQ line to the ISA IRQ controller should go low
  780  * and be raised at the next interrupt.
  781  *
  782  * Since the ISA IRQ controller is sent EOI _before_ passing control
  783  * to the isr, it might happen that we serve an interrupt early, in
  784  * which case the status register at the next interrupt should just
  785  * say that there are no more interrupts...
  786  */
  787 
  788 static void
  789 mss_intr(void *arg)
  790 {
  791         struct mss_info *mss = arg;
  792         u_char c = 0, served = 0;
  793         int i;
  794 
  795         DEB(printf("mss_intr\n"));
  796         mss_lock(mss);
  797         ad_read(mss, 11); /* fake read of status bits */
  798 
  799         /* loop until there are interrupts, but no more than 10 times. */
  800         for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
  801                 /* get exact reason for full-duplex boards */
  802                 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
  803                 c &= ~served;
  804                 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
  805                         served |= 0x10;
  806                         mss_unlock(mss);
  807                         chn_intr(mss->pch.channel);
  808                         mss_lock(mss);
  809                 }
  810                 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
  811                         served |= 0x20;
  812                         mss_unlock(mss);
  813                         chn_intr(mss->rch.channel);
  814                         mss_lock(mss);
  815                 }
  816                 /* now ack the interrupt */
  817                 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
  818                 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
  819         }
  820         if (i == 10) {
  821                 BVDDB(printf("mss_intr: irq, but not from mss\n"));
  822         } else if (served == 0) {
  823                 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
  824                 /*
  825                 * this should not happen... I have no idea what to do now.
  826                 * maybe should do a sanity check and restart dmas ?
  827                 */
  828                 io_wr(mss, MSS_STATUS, 0);      /* Clear interrupt status */
  829         }
  830         mss_unlock(mss);
  831 }
  832 
  833 /*
  834  * AD_WAIT_INIT waits if we are initializing the board and
  835  * we cannot modify its settings
  836  */
  837 static int
  838 ad_wait_init(struct mss_info *mss, int x)
  839 {
  840         int arg = x, n = 0; /* to shut up the compiler... */
  841         for (; x > 0; x--)
  842                 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
  843                 else return n;
  844         printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
  845         return n;
  846 }
  847 
  848 static int
  849 ad_read(struct mss_info *mss, int reg)
  850 {
  851         int             x;
  852 
  853         ad_wait_init(mss, 201000);
  854         x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
  855         io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
  856         x = io_rd(mss, MSS_IDATA);
  857         /* printf("ad_read %d, %x\n", reg, x); */
  858         return x;
  859 }
  860 
  861 static void
  862 ad_write(struct mss_info *mss, int reg, u_char data)
  863 {
  864         int x;
  865 
  866         /* printf("ad_write %d, %x\n", reg, data); */
  867         ad_wait_init(mss, 1002000);
  868         x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
  869         io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
  870         io_wr(mss, MSS_IDATA, data);
  871 }
  872 
  873 static void
  874 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
  875 {
  876         ad_write(mss, reg+1, cnt & 0xff);
  877         ad_write(mss, reg, cnt >> 8); /* upper base must be last */
  878 }
  879 
  880 static void
  881 wait_for_calibration(struct mss_info *mss)
  882 {
  883         int t;
  884 
  885         /*
  886          * Wait until the auto calibration process has finished.
  887          *
  888          * 1) Wait until the chip becomes ready (reads don't return 0x80).
  889          * 2) Wait until the ACI bit of I11 gets on
  890          * 3) Wait until the ACI bit of I11 gets off
  891          */
  892 
  893         t = ad_wait_init(mss, 1000000);
  894         if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
  895 
  896         /*
  897          * The calibration mode for chips that support it is set so that
  898          * we never see ACI go on.
  899          */
  900         if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
  901                 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
  902         } else {
  903                 /*
  904                  * XXX This should only be enabled for cards that *really*
  905                  * need it.  Are there any?
  906                  */
  907                 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
  908         }
  909         for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
  910 }
  911 
  912 static void
  913 ad_unmute(struct mss_info *mss)
  914 {
  915         ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
  916         ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
  917 }
  918 
  919 static void
  920 ad_enter_MCE(struct mss_info *mss)
  921 {
  922         int prev;
  923 
  924         mss->bd_flags |= BD_F_MCE_BIT;
  925         ad_wait_init(mss, 203000);
  926         prev = io_rd(mss, MSS_INDEX);
  927         prev &= ~MSS_TRD;
  928         io_wr(mss, MSS_INDEX, prev | MSS_MCE);
  929 }
  930 
  931 static void
  932 ad_leave_MCE(struct mss_info *mss)
  933 {
  934         u_char   prev;
  935 
  936         if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
  937                 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
  938                 return;
  939         }
  940 
  941         ad_wait_init(mss, 1000000);
  942 
  943         mss->bd_flags &= ~BD_F_MCE_BIT;
  944 
  945         prev = io_rd(mss, MSS_INDEX);
  946         prev &= ~MSS_TRD;
  947         io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
  948         wait_for_calibration(mss);
  949 }
  950 
  951 static int
  952 mss_speed(struct mss_chinfo *ch, int speed)
  953 {
  954         struct mss_info *mss = ch->parent;
  955         /*
  956         * In the CS4231, the low 4 bits of I8 are used to hold the
  957         * sample rate.  Only a fixed number of values is allowed. This
  958         * table lists them. The speed-setting routines scans the table
  959         * looking for the closest match. This is the only supported method.
  960         *
  961         * In the CS4236, there is an alternate metod (which we do not
  962         * support yet) which provides almost arbitrary frequency setting.
  963         * In the AD1845, it looks like the sample rate can be
  964         * almost arbitrary, and written directly to a register.
  965         * In the OPTi931, there is a SB command which provides for
  966         * almost arbitrary frequency setting.
  967         *
  968         */
  969         ad_enter_MCE(mss);
  970         if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
  971                 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
  972                 ad_write(mss, 23, speed & 0xff);        /* Speed LSB */
  973                 /* XXX must also do something in I27 for the ad1845 */
  974         } else {
  975                 int i, sel = 0; /* assume entry 0 does not contain -1 */
  976                 static int speeds[] =
  977                 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
  978                 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
  979 
  980                 for (i = 1; i < 16; i++)
  981                         if (speeds[i] > 0 &&
  982                             abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
  983                 speed = speeds[sel];
  984                 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
  985                 ad_wait_init(mss, 10000);
  986         }
  987         ad_leave_MCE(mss);
  988 
  989         return speed;
  990 }
  991 
  992 /*
  993  * mss_format checks that the format is supported (or defaults to AFMT_U8)
  994  * and returns the bit setting for the 1848 register corresponding to
  995  * the desired format.
  996  *
  997  * fixed lr970724
  998  */
  999 
 1000 static int
 1001 mss_format(struct mss_chinfo *ch, u_int32_t format)
 1002 {
 1003         struct mss_info *mss = ch->parent;
 1004         int i, arg = AFMT_ENCODING(format);
 1005 
 1006         /*
 1007         * The data format uses 3 bits (just 2 on the 1848). For each
 1008         * bit setting, the following array returns the corresponding format.
 1009         * The code scans the array looking for a suitable format. In
 1010         * case it is not found, default to AFMT_U8 (not such a good
 1011         * choice, but let's do it for compatibility...).
 1012         */
 1013 
 1014         static int fmts[] =
 1015                 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
 1016                 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
 1017 
 1018         ch->fmt = format;
 1019         for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
 1020         arg = i << 1;
 1021         if (AFMT_CHANNEL(format) > 1) arg |= 1;
 1022         arg <<= 4;
 1023         ad_enter_MCE(mss);
 1024         ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
 1025         ad_wait_init(mss, 10000);
 1026         if (ad_read(mss, 12) & 0x40) {  /* mode2? */
 1027                 ad_write(mss, 28, arg); /* capture mode */
 1028                 ad_wait_init(mss, 10000);
 1029         }
 1030         ad_leave_MCE(mss);
 1031         return format;
 1032 }
 1033 
 1034 static int
 1035 mss_trigger(struct mss_chinfo *ch, int go)
 1036 {
 1037         struct mss_info *mss = ch->parent;
 1038         u_char m;
 1039         int retry, wr, cnt, ss;
 1040 
 1041         ss = 1;
 1042         ss <<= (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
 1043         ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
 1044 
 1045         wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
 1046         m = ad_read(mss, 9);
 1047         switch (go) {
 1048         case PCMTRIG_START:
 1049                 cnt = (ch->blksz / ss) - 1;
 1050 
 1051                 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
 1052                 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
 1053                 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
 1054                 break;
 1055 
 1056         case PCMTRIG_STOP:
 1057         case PCMTRIG_ABORT: /* XXX check this... */
 1058                 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
 1059 #if 0
 1060                 /*
 1061                 * try to disable DMA by clearing count registers. Not sure it
 1062                 * is needed, and it might cause false interrupts when the
 1063                 * DMA is re-enabled later.
 1064                 */
 1065                 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
 1066 #endif
 1067         }
 1068         /* on the OPTi931 the enable bit seems hard to set... */
 1069         for (retry = 10; retry > 0; retry--) {
 1070                 ad_write(mss, 9, m);
 1071                 if (ad_read(mss, 9) == m) break;
 1072         }
 1073         if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
 1074                                m, ad_read(mss, 9)));
 1075         return 0;
 1076 }
 1077 
 1078 
 1079 /*
 1080  * the opti931 seems to miss interrupts when working in full
 1081  * duplex, so we try some heuristics to catch them.
 1082  */
 1083 static void
 1084 opti931_intr(void *arg)
 1085 {
 1086         struct mss_info *mss = (struct mss_info *)arg;
 1087         u_char masked = 0, i11, mc11, c = 0;
 1088         u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
 1089         int loops = 10;
 1090 
 1091 #if 0
 1092         reason = io_rd(mss, MSS_STATUS);
 1093         if (!(reason & 1)) {/* no int, maybe a shared line ? */
 1094                 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
 1095                 return;
 1096         }
 1097 #endif
 1098         mss_lock(mss);
 1099         i11 = ad_read(mss, 11); /* XXX what's for ? */
 1100         again:
 1101 
 1102         c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
 1103         mc11 &= 0x0c;
 1104         if (c & 0x10) {
 1105                 DEB(printf("Warning: CD interrupt\n");)
 1106                 mc11 |= 0x10;
 1107         }
 1108         if (c & 0x20) {
 1109                 DEB(printf("Warning: MPU interrupt\n");)
 1110                 mc11 |= 0x20;
 1111         }
 1112         if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
 1113                                   mc11, masked));
 1114         masked |= mc11;
 1115         /*
 1116         * the nice OPTi931 sets the IRQ line before setting the bits in
 1117         * mc11. So, on some occasions I have to retry (max 10 times).
 1118         */
 1119         if (mc11 == 0) { /* perhaps can return ... */
 1120                 reason = io_rd(mss, MSS_STATUS);
 1121                 if (reason & 1) {
 1122                         DEB(printf("one more try...\n");)
 1123                         if (--loops) goto again;
 1124                         else BVDDB(printf("intr, but mc11 not set\n");)
 1125                 }
 1126                 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
 1127                 mss_unlock(mss);
 1128                 return;
 1129         }
 1130 
 1131         if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
 1132                 mss_unlock(mss);
 1133                 chn_intr(mss->rch.channel);
 1134                 mss_lock(mss);
 1135         }
 1136         if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
 1137                 mss_unlock(mss);
 1138                 chn_intr(mss->pch.channel);
 1139                 mss_lock(mss);
 1140         }
 1141         opti_wr(mss, 11, ~mc11); /* ack */
 1142         if (--loops) goto again;
 1143         mss_unlock(mss);
 1144         DEB(printf("xxx too many loops\n");)
 1145 }
 1146 
 1147 /* -------------------------------------------------------------------- */
 1148 /* channel interface */
 1149 static void *
 1150 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
 1151 {
 1152         struct mss_info *mss = devinfo;
 1153         struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
 1154 
 1155         ch->parent = mss;
 1156         ch->channel = c;
 1157         ch->buffer = b;
 1158         ch->dir = dir;
 1159         if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
 1160                 return NULL;
 1161         sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
 1162         return ch;
 1163 }
 1164 
 1165 static int
 1166 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
 1167 {
 1168         struct mss_chinfo *ch = data;
 1169         struct mss_info *mss = ch->parent;
 1170 
 1171         mss_lock(mss);
 1172         mss_format(ch, format);
 1173         mss_unlock(mss);
 1174         return 0;
 1175 }
 1176 
 1177 static u_int32_t
 1178 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
 1179 {
 1180         struct mss_chinfo *ch = data;
 1181         struct mss_info *mss = ch->parent;
 1182         u_int32_t r;
 1183 
 1184         mss_lock(mss);
 1185         r = mss_speed(ch, speed);
 1186         mss_unlock(mss);
 1187 
 1188         return r;
 1189 }
 1190 
 1191 static u_int32_t
 1192 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
 1193 {
 1194         struct mss_chinfo *ch = data;
 1195 
 1196         ch->blksz = blocksize;
 1197         sndbuf_resize(ch->buffer, 2, ch->blksz);
 1198 
 1199         return ch->blksz;
 1200 }
 1201 
 1202 static int
 1203 msschan_trigger(kobj_t obj, void *data, int go)
 1204 {
 1205         struct mss_chinfo *ch = data;
 1206         struct mss_info *mss = ch->parent;
 1207 
 1208         if (!PCMTRIG_COMMON(go))
 1209                 return 0;
 1210 
 1211         sndbuf_dma(ch->buffer, go);
 1212         mss_lock(mss);
 1213         mss_trigger(ch, go);
 1214         mss_unlock(mss);
 1215         return 0;
 1216 }
 1217 
 1218 static u_int32_t
 1219 msschan_getptr(kobj_t obj, void *data)
 1220 {
 1221         struct mss_chinfo *ch = data;
 1222         return sndbuf_dmaptr(ch->buffer);
 1223 }
 1224 
 1225 static struct pcmchan_caps *
 1226 msschan_getcaps(kobj_t obj, void *data)
 1227 {
 1228         struct mss_chinfo *ch = data;
 1229 
 1230         switch(ch->parent->bd_id) {
 1231         case MD_OPTI931:
 1232                 return &opti931_caps;
 1233                 break;
 1234 
 1235         case MD_GUSPNP:
 1236         case MD_GUSMAX:
 1237                 return &guspnp_caps;
 1238                 break;
 1239 
 1240         default:
 1241                 return &mss_caps;
 1242                 break;
 1243         }
 1244 }
 1245 
 1246 static kobj_method_t msschan_methods[] = {
 1247         KOBJMETHOD(channel_init,                msschan_init),
 1248         KOBJMETHOD(channel_setformat,           msschan_setformat),
 1249         KOBJMETHOD(channel_setspeed,            msschan_setspeed),
 1250         KOBJMETHOD(channel_setblocksize,        msschan_setblocksize),
 1251         KOBJMETHOD(channel_trigger,             msschan_trigger),
 1252         KOBJMETHOD(channel_getptr,              msschan_getptr),
 1253         KOBJMETHOD(channel_getcaps,             msschan_getcaps),
 1254         KOBJMETHOD_END
 1255 };
 1256 CHANNEL_DECLARE(msschan);
 1257 
 1258 /* -------------------------------------------------------------------- */
 1259 
 1260 /*
 1261  * mss_probe() is the probe routine. Note, it is not necessary to
 1262  * go through this for PnP devices, since they are already
 1263  * indentified precisely using their PnP id.
 1264  *
 1265  * The base address supplied in the device refers to the old MSS
 1266  * specs where the four 4 registers in io space contain configuration
 1267  * information. Some boards (as an example, early MSS boards)
 1268  * has such a block of registers, whereas others (generally CS42xx)
 1269  * do not.  In order to distinguish between the two and do not have
 1270  * to supply two separate probe routines, the flags entry in isa_device
 1271  * has a bit to mark this.
 1272  *
 1273  */
 1274 
 1275 static int
 1276 mss_probe(device_t dev)
 1277 {
 1278         u_char tmp, tmpx;
 1279         int flags, irq, drq, result = ENXIO, setres = 0;
 1280         struct mss_info *mss;
 1281 
 1282         if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
 1283 
 1284         mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
 1285         if (!mss) return ENXIO;
 1286 
 1287         mss->io_rid = 0;
 1288         mss->conf_rid = -1;
 1289         mss->irq_rid = 0;
 1290         mss->drq1_rid = 0;
 1291         mss->drq2_rid = -1;
 1292         mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
 1293                                                 &mss->io_rid, 8, RF_ACTIVE);
 1294         if (!mss->io_base) {
 1295                 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
 1296                 mss->io_rid = 0;
 1297                 /* XXX verify this */
 1298                 setres = 1;
 1299                 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
 1300                                 0x530, 8);
 1301                 mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
 1302                                                         &mss->io_rid,
 1303                                                         8, RF_ACTIVE);
 1304         }
 1305         if (!mss->io_base) goto no;
 1306 
 1307         /* got irq/dma regs? */
 1308         flags = device_get_flags(dev);
 1309         irq = isa_get_irq(dev);
 1310         drq = isa_get_drq(dev);
 1311 
 1312         if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
 1313 
 1314         /*
 1315         * Check if the IO port returns valid signature. The original MS
 1316         * Sound system returns 0x04 while some cards
 1317         * (AudioTriX Pro for example) return 0x00 or 0x0f.
 1318         */
 1319 
 1320         device_set_desc(dev, "MSS");
 1321         tmpx = tmp = io_rd(mss, 3);
 1322         if (tmp == 0xff) {      /* Bus float */
 1323                 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
 1324                 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
 1325                 goto mss_probe_end;
 1326         }
 1327         tmp &= 0x3f;
 1328         if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00 || tmp == 0x05)) {
 1329                 BVDDB(printf("No MSS signature detected on port 0x%jx (0x%x)\n",
 1330                         rman_get_start(mss->io_base), tmpx));
 1331                 goto no;
 1332         }
 1333 #ifdef PC98
 1334         if (irq > 12) {
 1335 #else
 1336         if (irq > 11) {
 1337 #endif
 1338                 printf("MSS: Bad IRQ %d\n", irq);
 1339                 goto no;
 1340         }
 1341         if (!(drq == 0 || drq == 1 || drq == 3)) {
 1342                 printf("MSS: Bad DMA %d\n", drq);
 1343                 goto no;
 1344         }
 1345         if (tmpx & 0x80) {
 1346                 /* 8-bit board: only drq1/3 and irq7/9 */
 1347                 if (drq == 0) {
 1348                         printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
 1349                         goto no;
 1350                 }
 1351                 if (!(irq == 7 || irq == 9)) {
 1352                         printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
 1353                                irq);
 1354                         goto no;
 1355                 }
 1356         }
 1357         mss_probe_end:
 1358         result = mss_detect(dev, mss);
 1359         no:
 1360         mss_release_resources(mss, dev);
 1361 #if 0
 1362         if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
 1363                                         SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
 1364 #endif
 1365         return result;
 1366 }
 1367 
 1368 static int
 1369 mss_detect(device_t dev, struct mss_info *mss)
 1370 {
 1371         int          i;
 1372         u_char       tmp = 0, tmp1, tmp2;
 1373         char        *name, *yamaha;
 1374 
 1375         if (mss->bd_id != 0) {
 1376                 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
 1377                         device_get_desc(dev));
 1378                 return 0;
 1379         }
 1380 
 1381         name = "AD1848";
 1382         mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
 1383 
 1384 #ifndef PC98
 1385         if (opti_detect(dev, mss)) {
 1386                 switch (mss->bd_id) {
 1387                         case MD_OPTI924:
 1388                                 name = "OPTi924";
 1389                                 break;
 1390                         case MD_OPTI930:
 1391                                 name = "OPTi930";
 1392                                 break;
 1393                 }
 1394                 printf("Found OPTi device %s\n", name);
 1395                 if (opti_init(dev, mss) == 0) goto gotit;
 1396         }
 1397 #endif
 1398 
 1399         /*
 1400         * Check that the I/O address is in use.
 1401         *
 1402         * bit 7 of the base I/O port is known to be 0 after the chip has
 1403         * performed its power on initialization. Just assume this has
 1404         * happened before the OS is starting.
 1405         *
 1406         * If the I/O address is unused, it typically returns 0xff.
 1407         */
 1408 
 1409         for (i = 0; i < 10; i++)
 1410                 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
 1411                 else break;
 1412 
 1413         if (i >= 10) {  /* Not an AD1848 */
 1414                 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
 1415                 goto no;
 1416         }
 1417         /*
 1418         * Test if it's possible to change contents of the indirect
 1419         * registers. Registers 0 and 1 are ADC volume registers. The bit
 1420         * 0x10 is read only so try to avoid using it.
 1421         */
 1422 
 1423         ad_write(mss, 0, 0xaa);
 1424         ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
 1425         tmp1 = ad_read(mss, 0);
 1426         tmp2 = ad_read(mss, 1);
 1427         if (tmp1 != 0xaa || tmp2 != 0x45) {
 1428                 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
 1429                 goto no;
 1430         }
 1431 
 1432         ad_write(mss, 0, 0x45);
 1433         ad_write(mss, 1, 0xaa);
 1434         tmp1 = ad_read(mss, 0);
 1435         tmp2 = ad_read(mss, 1);
 1436         if (tmp1 != 0x45 || tmp2 != 0xaa) {
 1437                 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
 1438                 goto no;
 1439         }
 1440 
 1441         /*
 1442         * The indirect register I12 has some read only bits. Lets try to
 1443         * change them.
 1444         */
 1445 
 1446         tmp = ad_read(mss, 12);
 1447         ad_write(mss, 12, (~tmp) & 0x0f);
 1448         tmp1 = ad_read(mss, 12);
 1449 
 1450         if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
 1451                 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
 1452                 goto no;
 1453         }
 1454 
 1455         /*
 1456         * NOTE! Last 4 bits of the reg I12 tell the chip revision.
 1457         *       0x01=RevB
 1458         *  0x0A=RevC. also CS4231/CS4231A and OPTi931
 1459         */
 1460 
 1461         BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
 1462 
 1463         /*
 1464         * The original AD1848/CS4248 has just 16 indirect registers. This
 1465         * means that I0 and I16 should return the same value (etc.). Ensure
 1466         * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
 1467         * with new parts.
 1468         */
 1469 
 1470         ad_write(mss, 12, 0);   /* Mode2=disabled */
 1471 #if 0
 1472         for (i = 0; i < 16; i++) {
 1473                 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
 1474                 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
 1475                         i, tmp1, tmp2));
 1476                 /*
 1477                 * note - this seems to fail on the 4232 on I11. So we just break
 1478                 * rather than fail.  (which makes this test pointless - cg)
 1479                 */
 1480                 break; /* return 0; */
 1481                 }
 1482         }
 1483 #endif
 1484         /*
 1485         * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
 1486         * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
 1487         *
 1488         * On the OPTi931, however, I12 is readonly and only contains the
 1489         * chip revision ID (as in the CS4231A). The upper bits return 0.
 1490         */
 1491 
 1492         ad_write(mss, 12, 0x40);        /* Set mode2, clear 0x80 */
 1493 
 1494         tmp1 = ad_read(mss, 12);
 1495         if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
 1496         if ((tmp1 & 0xf0) == 0x00) {
 1497                 BVDDB(printf("this should be an OPTi931\n");)
 1498         } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
 1499         /*
 1500         * The 4231 has bit7=1 always, and bit6 we just set to 1.
 1501         * We want to check that this is really a CS4231
 1502         * Verify that setting I0 doesn't change I16.
 1503         */
 1504         ad_write(mss, 16, 0);   /* Set I16 to known value */
 1505         ad_write(mss, 0, 0x45);
 1506         if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
 1507 
 1508         ad_write(mss, 0, 0xaa);
 1509         if ((tmp1 = ad_read(mss, 16)) == 0xaa) {        /* Rotten bits? */
 1510                 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
 1511                 goto no;
 1512         }
 1513         /* Verify that some bits of I25 are read only. */
 1514         tmp1 = ad_read(mss, 25);        /* Original bits */
 1515         ad_write(mss, 25, ~tmp1);       /* Invert all bits */
 1516         if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
 1517                 int id;
 1518 
 1519                 /* It's at least CS4231 */
 1520                 name = "CS4231";
 1521                 mss->bd_id = MD_CS42XX;
 1522 
 1523                 /*
 1524                 * It could be an AD1845 or CS4231A as well.
 1525                 * CS4231 and AD1845 report the same revision info in I25
 1526                 * while the CS4231A reports different.
 1527                 */
 1528 
 1529                 id = ad_read(mss, 25) & 0xe7;
 1530                 /*
 1531                 * b7-b5 = version number;
 1532                 *       100 : all CS4231
 1533                 *       101 : CS4231A
 1534                 *
 1535                 * b2-b0 = chip id;
 1536                 */
 1537                 switch (id) {
 1538 
 1539                 case 0xa0:
 1540                         name = "CS4231A";
 1541                         mss->bd_id = MD_CS42XX;
 1542                 break;
 1543 
 1544                 case 0xa2:
 1545                         name = "CS4232";
 1546                         mss->bd_id = MD_CS42XX;
 1547                 break;
 1548 
 1549                 case 0xb2:
 1550                 /* strange: the 4231 data sheet says b4-b3 are XX
 1551                 * so this should be the same as 0xa2
 1552                 */
 1553                         name = "CS4232A";
 1554                         mss->bd_id = MD_CS42XX;
 1555                 break;
 1556 
 1557                 case 0x80:
 1558                         /*
 1559                         * It must be a CS4231 or AD1845. The register I23
 1560                         * of CS4231 is undefined and it appears to be read
 1561                         * only. AD1845 uses I23 for setting sample rate.
 1562                         * Assume the chip is AD1845 if I23 is changeable.
 1563                         */
 1564 
 1565                         tmp = ad_read(mss, 23);
 1566 
 1567                         ad_write(mss, 23, ~tmp);
 1568                         if (ad_read(mss, 23) != tmp) {  /* AD1845 ? */
 1569                                 name = "AD1845";
 1570                                 mss->bd_id = MD_AD1845;
 1571                         }
 1572                         ad_write(mss, 23, tmp); /* Restore */
 1573 
 1574                         yamaha = ymf_test(dev, mss);
 1575                         if (yamaha) {
 1576                                 mss->bd_id = MD_YM0020;
 1577                                 name = yamaha;
 1578                         }
 1579                         break;
 1580 
 1581                 case 0x83:      /* CS4236 */
 1582                 case 0x03:      /* CS4236 on Intel PR440FX motherboard XXX */
 1583                         name = "CS4236";
 1584                         mss->bd_id = MD_CS42XX;
 1585                         break;
 1586 
 1587                 default:        /* Assume CS4231 */
 1588                         BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
 1589                         mss->bd_id = MD_CS42XX;
 1590                 }
 1591         }
 1592         ad_write(mss, 25, tmp1);        /* Restore bits */
 1593 gotit:
 1594         BVDDB(printf("mss_detect() - Detected %s\n", name));
 1595         device_set_desc(dev, name);
 1596         device_set_flags(dev,
 1597                          ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
 1598                           ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
 1599         return 0;
 1600 no:
 1601         return ENXIO;
 1602 }
 1603 
 1604 #ifndef PC98
 1605 static int
 1606 opti_detect(device_t dev, struct mss_info *mss)
 1607 {
 1608         int c;
 1609         static const struct opticard {
 1610                 int boardid;
 1611                 int passwdreg;
 1612                 int password;
 1613                 int base;
 1614                 int indir_reg;
 1615         } cards[] = {
 1616                 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e },  /* 930 */
 1617                 { MD_OPTI924, 3, 0xe5, 0xf8c, 0,    },  /* 924 */
 1618                 { 0 },
 1619         };
 1620         mss->conf_rid = 3;
 1621         mss->indir_rid = 4;
 1622         for (c = 0; cards[c].base; c++) {
 1623                 mss->optibase = cards[c].base;
 1624                 mss->password = cards[c].password;
 1625                 mss->passwdreg = cards[c].passwdreg;
 1626                 mss->bd_id = cards[c].boardid;
 1627 
 1628                 if (cards[c].indir_reg)
 1629                         mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
 1630                                 &mss->indir_rid, cards[c].indir_reg,
 1631                                 cards[c].indir_reg+1, 1, RF_ACTIVE);
 1632 
 1633                 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
 1634                         &mss->conf_rid, mss->optibase, mss->optibase+9,
 1635                         9, RF_ACTIVE);
 1636 
 1637                 if (opti_read(mss, 1) != 0xff) {
 1638                         return 1;
 1639                 } else {
 1640                         if (mss->indir)
 1641                                 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
 1642                         mss->indir = NULL;
 1643                         if (mss->conf_base)
 1644                                 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
 1645                         mss->conf_base = NULL;
 1646                 }
 1647         }
 1648         return 0;
 1649 }
 1650 #endif
 1651 
 1652 static char *
 1653 ymf_test(device_t dev, struct mss_info *mss)
 1654 {
 1655         static int ports[] = {0x370, 0x310, 0x538};
 1656         int p, i, j, version;
 1657         static char *chipset[] = {
 1658                 NULL,                   /* 0 */
 1659                 "OPL3-SA2 (YMF711)",    /* 1 */
 1660                 "OPL3-SA3 (YMF715)",    /* 2 */
 1661                 "OPL3-SA3 (YMF715)",    /* 3 */
 1662                 "OPL3-SAx (YMF719)",    /* 4 */
 1663                 "OPL3-SAx (YMF719)",    /* 5 */
 1664                 "OPL3-SAx (YMF719)",    /* 6 */
 1665                 "OPL3-SAx (YMF719)",    /* 7 */
 1666         };
 1667 
 1668         for (p = 0; p < 3; p++) {
 1669                 mss->conf_rid = 1;
 1670                 mss->conf_base = bus_alloc_resource(dev,
 1671                                                 SYS_RES_IOPORT,
 1672                                                 &mss->conf_rid,
 1673                                                 ports[p], ports[p] + 1, 2,
 1674                                                 RF_ACTIVE);
 1675                 if (!mss->conf_base) return 0;
 1676 
 1677                 /* Test the index port of the config registers */
 1678                 i = port_rd(mss->conf_base, 0);
 1679                 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
 1680                 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
 1681                 port_wr(mss->conf_base, 0, i);
 1682                 if (!j) {
 1683                         bus_release_resource(dev, SYS_RES_IOPORT,
 1684                                              mss->conf_rid, mss->conf_base);
 1685 #ifdef PC98
 1686                         /* PC98 need this. I don't know reason why. */
 1687                         bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
 1688 #endif
 1689                         mss->conf_base = NULL;
 1690                         continue;
 1691                 }
 1692                 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
 1693                 return chipset[version];
 1694         }
 1695         return NULL;
 1696 }
 1697 
 1698 static int
 1699 mss_doattach(device_t dev, struct mss_info *mss)
 1700 {
 1701         int pdma, rdma, flags = device_get_flags(dev);
 1702         char status[SND_STATUSLEN], status2[SND_STATUSLEN];
 1703 
 1704         mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
 1705         mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
 1706         if (!mss_alloc_resources(mss, dev)) goto no;
 1707         mss_init(mss, dev);
 1708         pdma = rman_get_start(mss->drq1);
 1709         rdma = rman_get_start(mss->drq2);
 1710         if (flags & DV_F_TRUE_MSS) {
 1711                 /* has IRQ/DMA registers, set IRQ and DMA addr */
 1712 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
 1713                 static char     interrupt_bits[13] =
 1714                 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
 1715 #else
 1716                 static char     interrupt_bits[12] =
 1717                 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
 1718 #endif
 1719                 static char     pdma_bits[4] =  {1, 2, -1, 3};
 1720                 static char     valid_rdma[4] = {1, 0, -1, 0};
 1721                 char            bits;
 1722 
 1723                 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
 1724                         goto no;
 1725 #ifndef PC98 /* CS423[12] in PC98 don't support this. */
 1726                 io_wr(mss, 0, bits | 0x40);     /* config port */
 1727                 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
 1728 #endif
 1729                 /* Write IRQ+DMA setup */
 1730                 if (pdma_bits[pdma] == -1) goto no;
 1731                 bits |= pdma_bits[pdma];
 1732                 if (pdma != rdma) {
 1733                         if (rdma == valid_rdma[pdma]) bits |= 4;
 1734                         else {
 1735                                 printf("invalid dual dma config %d:%d\n", pdma, rdma);
 1736                                 goto no;
 1737                         }
 1738                 }
 1739                 io_wr(mss, 0, bits);
 1740                 printf("drq/irq conf %x\n", io_rd(mss, 0));
 1741         }
 1742         mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
 1743         switch (mss->bd_id) {
 1744         case MD_OPTI931:
 1745                 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
 1746                 break;
 1747         default:
 1748                 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
 1749         }
 1750         if (pdma == rdma)
 1751                 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
 1752         if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
 1753                         /*boundary*/0,
 1754                         /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
 1755                         /*highaddr*/BUS_SPACE_MAXADDR,
 1756                         /*filter*/NULL, /*filterarg*/NULL,
 1757                         /*maxsize*/mss->bufsize, /*nsegments*/1,
 1758                         /*maxsegz*/0x3ffff, /*flags*/0,
 1759                         /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
 1760                         &mss->parent_dmat) != 0) {
 1761                 device_printf(dev, "unable to create dma tag\n");
 1762                 goto no;
 1763         }
 1764 
 1765         if (pdma != rdma)
 1766                 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
 1767         else
 1768                 status2[0] = '\0';
 1769 
 1770         snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd drq %d%s bufsz %u",
 1771                 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
 1772 
 1773         if (pcm_register(dev, mss, 1, 1)) goto no;
 1774         pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
 1775         pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
 1776         pcm_setstatus(dev, status);
 1777 
 1778         return 0;
 1779 no:
 1780         mss_release_resources(mss, dev);
 1781         return ENXIO;
 1782 }
 1783 
 1784 static int
 1785 mss_detach(device_t dev)
 1786 {
 1787         int r;
 1788         struct mss_info *mss;
 1789 
 1790         r = pcm_unregister(dev);
 1791         if (r)
 1792                 return r;
 1793 
 1794         mss = pcm_getdevinfo(dev);
 1795         mss_release_resources(mss, dev);
 1796 
 1797         return 0;
 1798 }
 1799 
 1800 static int
 1801 mss_attach(device_t dev)
 1802 {
 1803         struct mss_info *mss;
 1804         int flags = device_get_flags(dev);
 1805 
 1806         mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
 1807         if (!mss) return ENXIO;
 1808 
 1809         mss->io_rid = 0;
 1810         mss->conf_rid = -1;
 1811         mss->irq_rid = 0;
 1812         mss->drq1_rid = 0;
 1813         mss->drq2_rid = -1;
 1814         if (flags & DV_F_DUAL_DMA) {
 1815                 bus_set_resource(dev, SYS_RES_DRQ, 1,
 1816                                  flags & DV_F_DRQ_MASK, 1);
 1817                 mss->drq2_rid = 1;
 1818         }
 1819         mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
 1820         if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
 1821         return mss_doattach(dev, mss);
 1822 }
 1823 
 1824 /*
 1825  * mss_resume() is the code to allow a laptop to resume using the sound
 1826  * card.
 1827  *
 1828  * This routine re-sets the state of the board to the state before going
 1829  * to sleep.  According to the yamaha docs this is the right thing to do,
 1830  * but getting DMA restarted appears to be a bit of a trick, so the device
 1831  * has to be closed and re-opened to be re-used, but there is no skipping
 1832  * problem, and volume, bass/treble and most other things are restored
 1833  * properly.
 1834  *
 1835  */
 1836 
 1837 static int
 1838 mss_resume(device_t dev)
 1839 {
 1840         /*
 1841          * Restore the state taken below.
 1842          */
 1843         struct mss_info *mss;
 1844         int i;
 1845 
 1846         mss = pcm_getdevinfo(dev);
 1847 
 1848         if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
 1849                 /* This works on a Toshiba Libretto 100CT. */
 1850                 for (i = 0; i < MSS_INDEXED_REGS; i++)
 1851                         ad_write(mss, i, mss->mss_indexed_regs[i]);
 1852                 for (i = 0; i < OPL_INDEXED_REGS; i++)
 1853                         conf_wr(mss, i, mss->opl_indexed_regs[i]);
 1854                 mss_intr(mss);
 1855         }
 1856 
 1857         if (mss->bd_id == MD_CS423X) {
 1858                 /* Needed on IBM Thinkpad 600E */
 1859                 mss_lock(mss);
 1860                 mss_format(&mss->pch, mss->pch.channel->format);
 1861                 mss_speed(&mss->pch, mss->pch.channel->speed);
 1862                 mss_unlock(mss);
 1863         }
 1864 
 1865         return 0;
 1866 
 1867 }
 1868 
 1869 /*
 1870  * mss_suspend() is the code that gets called right before a laptop
 1871  * suspends.
 1872  *
 1873  * This code saves the state of the sound card right before shutdown
 1874  * so it can be restored above.
 1875  *
 1876  */
 1877 
 1878 static int
 1879 mss_suspend(device_t dev)
 1880 {
 1881         int i;
 1882         struct mss_info *mss;
 1883 
 1884         mss = pcm_getdevinfo(dev);
 1885 
 1886         if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
 1887         {
 1888                 /* this stops playback. */
 1889                 conf_wr(mss, 0x12, 0x0c);
 1890                 for(i = 0; i < MSS_INDEXED_REGS; i++)
 1891                         mss->mss_indexed_regs[i] = ad_read(mss, i);
 1892                 for(i = 0; i < OPL_INDEXED_REGS; i++)
 1893                         mss->opl_indexed_regs[i] = conf_rd(mss, i);
 1894                 mss->opl_indexed_regs[0x12] = 0x0;
 1895         }
 1896         return 0;
 1897 }
 1898 
 1899 static device_method_t mss_methods[] = {
 1900         /* Device interface */
 1901         DEVMETHOD(device_probe,         mss_probe),
 1902         DEVMETHOD(device_attach,        mss_attach),
 1903         DEVMETHOD(device_detach,        mss_detach),
 1904         DEVMETHOD(device_suspend,       mss_suspend),
 1905         DEVMETHOD(device_resume,        mss_resume),
 1906 
 1907         { 0, 0 }
 1908 };
 1909 
 1910 static driver_t mss_driver = {
 1911         "pcm",
 1912         mss_methods,
 1913         PCM_SOFTC_SIZE,
 1914 };
 1915 
 1916 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
 1917 MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
 1918 MODULE_VERSION(snd_mss, 1);
 1919 
 1920 static int
 1921 azt2320_mss_mode(struct mss_info *mss, device_t dev)
 1922 {
 1923         struct resource *sbport;
 1924         int             i, ret, rid;
 1925 
 1926         rid = 0;
 1927         ret = -1;
 1928         sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
 1929         if (sbport) {
 1930                 for (i = 0; i < 1000; i++) {
 1931                         if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
 1932                                 DELAY((i > 100) ? 1000 : 10);
 1933                         else {
 1934                                 port_wr(sbport, SBDSP_CMD, 0x09);
 1935                                 break;
 1936                         }
 1937                 }
 1938                 for (i = 0; i < 1000; i++) {
 1939                         if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
 1940                                 DELAY((i > 100) ? 1000 : 10);
 1941                         else {
 1942                                 port_wr(sbport, SBDSP_CMD, 0x00);
 1943                                 ret = 0;
 1944                                 break;
 1945                         }
 1946                 }
 1947                 DELAY(1000);
 1948                 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
 1949         }
 1950         return ret;
 1951 }
 1952 
 1953 static struct isa_pnp_id pnpmss_ids[] = {
 1954         {0x0000630e, "CS423x"},                         /* CSC0000 */
 1955         {0x0001630e, "CS423x-PCI"},                     /* CSC0100 */
 1956         {0x01000000, "CMI8330"},                        /* @@@0001 */
 1957         {0x2100a865, "Yamaha OPL-SAx"},                 /* YMH0021 */
 1958         {0x1110d315, "ENSONIQ SoundscapeVIVO"},         /* ENS1011 */
 1959         {0x1093143e, "OPTi931"},                        /* OPT9310 */
 1960         {0x5092143e, "OPTi925"},                        /* OPT9250 XXX guess */
 1961         {0x0000143e, "OPTi924"},                        /* OPT0924 */
 1962         {0x1022b839, "Neomagic 256AV (non-ac97)"},      /* NMX2210 */
 1963         {0x01005407, "Aztech 2320"},                    /* AZT0001 */
 1964 #if 0
 1965         {0x0000561e, "GusPnP"},                         /* GRV0000 */
 1966 #endif
 1967         {0},
 1968 };
 1969 
 1970 static int
 1971 pnpmss_probe(device_t dev)
 1972 {
 1973         u_int32_t lid, vid;
 1974 
 1975         lid = isa_get_logicalid(dev);
 1976         vid = isa_get_vendorid(dev);
 1977         if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
 1978                 return ENXIO;
 1979         return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
 1980 }
 1981 
 1982 static int
 1983 pnpmss_attach(device_t dev)
 1984 {
 1985         struct mss_info *mss;
 1986 
 1987         mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
 1988         mss->io_rid = 0;
 1989         mss->conf_rid = -1;
 1990         mss->irq_rid = 0;
 1991         mss->drq1_rid = 0;
 1992         mss->drq2_rid = 1;
 1993         mss->bd_id = MD_CS42XX;
 1994 
 1995         switch (isa_get_logicalid(dev)) {
 1996         case 0x0000630e:                        /* CSC0000 */
 1997         case 0x0001630e:                        /* CSC0100 */
 1998             mss->bd_flags |= BD_F_MSS_OFFSET;
 1999             mss->bd_id = MD_CS423X;
 2000             break;
 2001 
 2002         case 0x2100a865:                        /* YHM0021 */
 2003             mss->io_rid = 1;
 2004             mss->conf_rid = 4;
 2005             mss->bd_id = MD_YM0020;
 2006             break;
 2007 
 2008         case 0x1110d315:                        /* ENS1011 */
 2009             mss->io_rid = 1;
 2010             mss->bd_id = MD_VIVO;
 2011             break;
 2012 
 2013         case 0x1093143e:                        /* OPT9310 */
 2014             mss->bd_flags |= BD_F_MSS_OFFSET;
 2015             mss->conf_rid = 3;
 2016             mss->bd_id = MD_OPTI931;
 2017             break;
 2018 
 2019         case 0x5092143e:                        /* OPT9250 XXX guess */
 2020             mss->io_rid = 1;
 2021             mss->conf_rid = 3;
 2022             mss->bd_id = MD_OPTI925;
 2023             break;
 2024 
 2025         case 0x0000143e:                        /* OPT0924 */
 2026             mss->password = 0xe5;
 2027             mss->passwdreg = 3;
 2028             mss->optibase = 0xf0c;
 2029             mss->io_rid = 2;
 2030             mss->conf_rid = 3;
 2031             mss->bd_id = MD_OPTI924;
 2032             mss->bd_flags |= BD_F_924PNP;
 2033             if(opti_init(dev, mss) != 0) {
 2034                     free(mss, M_DEVBUF);
 2035                     return ENXIO;
 2036             }
 2037             break;
 2038 
 2039         case 0x1022b839:                        /* NMX2210 */
 2040             mss->io_rid = 1;
 2041             break;
 2042 
 2043         case 0x01005407:                        /* AZT0001 */
 2044             /* put into MSS mode first (snatched from NetBSD) */
 2045             if (azt2320_mss_mode(mss, dev) == -1) {
 2046                     free(mss, M_DEVBUF);
 2047                     return ENXIO;
 2048             }
 2049 
 2050             mss->bd_flags |= BD_F_MSS_OFFSET;
 2051             mss->io_rid = 2;
 2052             break;
 2053             
 2054 #if 0
 2055         case 0x0000561e:                        /* GRV0000 */
 2056             mss->bd_flags |= BD_F_MSS_OFFSET;
 2057             mss->io_rid = 2;
 2058             mss->conf_rid = 1;
 2059             mss->drq1_rid = 1;
 2060             mss->drq2_rid = 0;
 2061             mss->bd_id = MD_GUSPNP;
 2062             break;
 2063 #endif
 2064         case 0x01000000:                        /* @@@0001 */
 2065             mss->drq2_rid = -1;
 2066             break;
 2067 
 2068         /* Unknown MSS default.  We could let the CSC0000 stuff match too */
 2069         default:
 2070             mss->bd_flags |= BD_F_MSS_OFFSET;
 2071             break;
 2072         }
 2073         return mss_doattach(dev, mss);
 2074 }
 2075 
 2076 static int
 2077 opti_init(device_t dev, struct mss_info *mss)
 2078 {
 2079         int flags = device_get_flags(dev);
 2080         int basebits = 0;
 2081 
 2082         if (!mss->conf_base) {
 2083                 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
 2084                         mss->optibase, 0x9);
 2085 
 2086                 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
 2087                         &mss->conf_rid, mss->optibase, mss->optibase+0x9,
 2088                         0x9, RF_ACTIVE);
 2089         }
 2090 
 2091         if (!mss->conf_base)
 2092                 return ENXIO;
 2093 
 2094         if (!mss->io_base)
 2095                 mss->io_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
 2096                         &mss->io_rid, 8, RF_ACTIVE);
 2097 
 2098         if (!mss->io_base)      /* No hint specified, use 0x530 */
 2099                 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
 2100                         &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
 2101 
 2102         if (!mss->io_base)
 2103                 return ENXIO;
 2104 
 2105         switch (rman_get_start(mss->io_base)) {
 2106                 case 0x530:
 2107                         basebits = 0x0;
 2108                         break;
 2109                 case 0xe80:
 2110                         basebits = 0x10;
 2111                         break;
 2112                 case 0xf40:
 2113                         basebits = 0x20;
 2114                         break;
 2115                 case 0x604:
 2116                         basebits = 0x30;
 2117                         break;
 2118                 default:
 2119                         printf("opti_init: invalid MSS base address!\n");
 2120                         return ENXIO;
 2121         }
 2122 
 2123 
 2124         switch (mss->bd_id) {
 2125         case MD_OPTI924:
 2126                 opti_write(mss, 1, 0x80 | basebits);    /* MSS mode */
 2127                 opti_write(mss, 2, 0x00);       /* Disable CD */
 2128                 opti_write(mss, 3, 0xf0);       /* Disable SB IRQ */
 2129                 opti_write(mss, 4, 0xf0);
 2130                 opti_write(mss, 5, 0x00);
 2131                 opti_write(mss, 6, 0x02);       /* MPU stuff */
 2132                 break;
 2133 
 2134         case MD_OPTI930:
 2135                 opti_write(mss, 1, 0x00 | basebits);
 2136                 opti_write(mss, 3, 0x00);       /* Disable SB IRQ/DMA */
 2137                 opti_write(mss, 4, 0x52);       /* Empty FIFO */
 2138                 opti_write(mss, 5, 0x3c);       /* Mode 2 */
 2139                 opti_write(mss, 6, 0x02);       /* Enable MSS */
 2140                 break;
 2141         }
 2142 
 2143         if (mss->bd_flags & BD_F_924PNP) {
 2144                 u_int32_t irq = isa_get_irq(dev);
 2145                 u_int32_t drq = isa_get_drq(dev);
 2146                 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
 2147                 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
 2148                 if (flags & DV_F_DUAL_DMA) {
 2149                         bus_set_resource(dev, SYS_RES_DRQ, 1,
 2150                                 flags & DV_F_DRQ_MASK, 1);
 2151                         mss->drq2_rid = 1;
 2152                 }
 2153         }
 2154 
 2155         /* OPTixxx has I/DRQ registers */
 2156 
 2157         device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
 2158 
 2159         return 0;
 2160 }
 2161 
 2162 static void
 2163 opti_write(struct mss_info *mss, u_char reg, u_char val)
 2164 {
 2165         port_wr(mss->conf_base, mss->passwdreg, mss->password);
 2166 
 2167         switch(mss->bd_id) {
 2168         case MD_OPTI924:
 2169                 if (reg > 7) {          /* Indirect register */
 2170                         port_wr(mss->conf_base, mss->passwdreg, reg);
 2171                         port_wr(mss->conf_base, mss->passwdreg,
 2172                                 mss->password);
 2173                         port_wr(mss->conf_base, 9, val);
 2174                         return;
 2175                 }
 2176                 port_wr(mss->conf_base, reg, val);
 2177                 break;
 2178 
 2179         case MD_OPTI930:
 2180                 port_wr(mss->indir, 0, reg);
 2181                 port_wr(mss->conf_base, mss->passwdreg, mss->password);
 2182                 port_wr(mss->indir, 1, val);
 2183                 break;
 2184         }
 2185 }
 2186 
 2187 #ifndef PC98
 2188 u_char
 2189 opti_read(struct mss_info *mss, u_char reg)
 2190 {
 2191         port_wr(mss->conf_base, mss->passwdreg, mss->password);
 2192 
 2193         switch(mss->bd_id) {
 2194         case MD_OPTI924:
 2195                 if (reg > 7) {          /* Indirect register */
 2196                         port_wr(mss->conf_base, mss->passwdreg, reg);
 2197                         port_wr(mss->conf_base, mss->passwdreg, mss->password);
 2198                         return(port_rd(mss->conf_base, 9));
 2199                 }
 2200                 return(port_rd(mss->conf_base, reg));
 2201                 break;
 2202 
 2203         case MD_OPTI930:
 2204                 port_wr(mss->indir, 0, reg);
 2205                 port_wr(mss->conf_base, mss->passwdreg, mss->password);
 2206                 return port_rd(mss->indir, 1);
 2207                 break;
 2208         }
 2209         return -1;
 2210 }
 2211 #endif
 2212 
 2213 static device_method_t pnpmss_methods[] = {
 2214         /* Device interface */
 2215         DEVMETHOD(device_probe,         pnpmss_probe),
 2216         DEVMETHOD(device_attach,        pnpmss_attach),
 2217         DEVMETHOD(device_detach,        mss_detach),
 2218         DEVMETHOD(device_suspend,       mss_suspend),
 2219         DEVMETHOD(device_resume,        mss_resume),
 2220 
 2221         { 0, 0 }
 2222 };
 2223 
 2224 static driver_t pnpmss_driver = {
 2225         "pcm",
 2226         pnpmss_methods,
 2227         PCM_SOFTC_SIZE,
 2228 };
 2229 
 2230 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
 2231 DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
 2232 MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
 2233 MODULE_VERSION(snd_pnpmss, 1);
 2234 
 2235 static int
 2236 guspcm_probe(device_t dev)
 2237 {
 2238         struct sndcard_func *func;
 2239 
 2240         func = device_get_ivars(dev);
 2241         if (func == NULL || func->func != SCF_PCM)
 2242                 return ENXIO;
 2243 
 2244         device_set_desc(dev, "GUS CS4231");
 2245         return 0;
 2246 }
 2247 
 2248 static int
 2249 guspcm_attach(device_t dev)
 2250 {
 2251         device_t parent = device_get_parent(dev);
 2252         struct mss_info *mss;
 2253         int base, flags;
 2254         unsigned char ctl;
 2255 
 2256         mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
 2257         if (mss == NULL)
 2258                 return ENOMEM;
 2259 
 2260         mss->bd_flags = BD_F_MSS_OFFSET;
 2261         mss->io_rid = 2;
 2262         mss->conf_rid = 1;
 2263         mss->irq_rid = 0;
 2264         mss->drq1_rid = 1;
 2265         mss->drq2_rid = -1;
 2266 
 2267         if (isa_get_logicalid(parent) == 0)
 2268                 mss->bd_id = MD_GUSMAX;
 2269         else {
 2270                 mss->bd_id = MD_GUSPNP;
 2271                 mss->drq2_rid = 0;
 2272                 goto skip_setup;
 2273         }
 2274 
 2275         flags = device_get_flags(parent);
 2276         if (flags & DV_F_DUAL_DMA)
 2277                 mss->drq2_rid = 0;
 2278 
 2279         mss->conf_base = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
 2280                                                      &mss->conf_rid,
 2281                                                      8, RF_ACTIVE);
 2282 
 2283         if (mss->conf_base == NULL) {
 2284                 mss_release_resources(mss, dev);
 2285                 return ENXIO;
 2286         }
 2287 
 2288         base = isa_get_port(parent);
 2289 
 2290         ctl = 0x40;                     /* CS4231 enable */
 2291         if (isa_get_drq(dev) > 3)
 2292                 ctl |= 0x10;            /* 16-bit dma channel 1 */
 2293         if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
 2294                 ctl |= 0x20;            /* 16-bit dma channel 2 */
 2295         ctl |= (base >> 4) & 0x0f;      /* 2X0 -> 3XC */
 2296         port_wr(mss->conf_base, 6, ctl);
 2297 
 2298 skip_setup:
 2299         return mss_doattach(dev, mss);
 2300 }
 2301 
 2302 static device_method_t guspcm_methods[] = {
 2303         DEVMETHOD(device_probe,         guspcm_probe),
 2304         DEVMETHOD(device_attach,        guspcm_attach),
 2305         DEVMETHOD(device_detach,        mss_detach),
 2306 
 2307         { 0, 0 }
 2308 };
 2309 
 2310 static driver_t guspcm_driver = {
 2311         "pcm",
 2312         guspcm_methods,
 2313         PCM_SOFTC_SIZE,
 2314 };
 2315 
 2316 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
 2317 MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
 2318 MODULE_VERSION(snd_guspcm, 1);
 2319 
 2320 

Cache object: 6d2f261334367aafde23171ebc79c67f


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