Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/isa/mss.c
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1 /* 2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org> 3 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 4 * Copyright Luigi Rizzo, 1997,1998 5 * Copyright by Hannu Savolainen 1994, 1995 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <dev/sound/pcm/sound.h> 31 32 SND_DECLARE_FILE("$FreeBSD: releng/5.1/sys/dev/sound/isa/mss.c 110499 2003-02-07 14:05:34Z nyan $"); 33 34 /* board-specific include files */ 35 #include <dev/sound/isa/mss.h> 36 #include <dev/sound/isa/sb.h> 37 #include <dev/sound/chip.h> 38 39 #include <isa/isavar.h> 40 41 #include "mixer_if.h" 42 43 #define MSS_DEFAULT_BUFSZ (4096) 44 #define MSS_INDEXED_REGS 0x20 45 #define OPL_INDEXED_REGS 0x19 46 47 struct mss_info; 48 49 struct mss_chinfo { 50 struct mss_info *parent; 51 struct pcm_channel *channel; 52 struct snd_dbuf *buffer; 53 int dir; 54 u_int32_t fmt, blksz; 55 }; 56 57 struct mss_info { 58 struct resource *io_base; /* primary I/O address for the board */ 59 int io_rid; 60 struct resource *conf_base; /* and the opti931 also has a config space */ 61 int conf_rid; 62 struct resource *irq; 63 int irq_rid; 64 struct resource *drq1; /* play */ 65 int drq1_rid; 66 struct resource *drq2; /* rec */ 67 int drq2_rid; 68 void *ih; 69 bus_dma_tag_t parent_dmat; 70 struct mtx *lock; 71 72 char mss_indexed_regs[MSS_INDEXED_REGS]; 73 char opl_indexed_regs[OPL_INDEXED_REGS]; 74 int bd_id; /* used to hold board-id info, eg. sb version, 75 * mss codec type, etc. etc. 76 */ 77 int opti_offset; /* offset from config_base for opti931 */ 78 u_long bd_flags; /* board-specific flags */ 79 int optibase; /* base address for OPTi9xx config */ 80 struct resource *indir; /* Indirect register index address */ 81 int indir_rid; 82 int password; /* password for opti9xx cards */ 83 int passwdreg; /* password register */ 84 unsigned int bufsize; 85 struct mss_chinfo pch, rch; 86 }; 87 88 static int mss_probe(device_t dev); 89 static int mss_attach(device_t dev); 90 91 static driver_intr_t mss_intr; 92 93 /* prototypes for local functions */ 94 static int mss_detect(device_t dev, struct mss_info *mss); 95 static int opti_detect(device_t dev, struct mss_info *mss); 96 static char *ymf_test(device_t dev, struct mss_info *mss); 97 static void ad_unmute(struct mss_info *mss); 98 99 /* mixer set funcs */ 100 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right); 101 static int mss_set_recsrc(struct mss_info *mss, int mask); 102 103 /* io funcs */ 104 static int ad_wait_init(struct mss_info *mss, int x); 105 static int ad_read(struct mss_info *mss, int reg); 106 static void ad_write(struct mss_info *mss, int reg, u_char data); 107 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data); 108 static void ad_enter_MCE(struct mss_info *mss); 109 static void ad_leave_MCE(struct mss_info *mss); 110 111 /* OPTi-specific functions */ 112 static void opti_write(struct mss_info *mss, u_char reg, 113 u_char data); 114 static u_char opti_read(struct mss_info *mss, u_char reg); 115 static int opti_init(device_t dev, struct mss_info *mss); 116 117 /* io primitives */ 118 static void conf_wr(struct mss_info *mss, u_char reg, u_char data); 119 static u_char conf_rd(struct mss_info *mss, u_char reg); 120 121 static int pnpmss_probe(device_t dev); 122 static int pnpmss_attach(device_t dev); 123 124 static driver_intr_t opti931_intr; 125 126 static u_int32_t mss_fmt[] = { 127 AFMT_U8, 128 AFMT_STEREO | AFMT_U8, 129 AFMT_S16_LE, 130 AFMT_STEREO | AFMT_S16_LE, 131 AFMT_MU_LAW, 132 AFMT_STEREO | AFMT_MU_LAW, 133 AFMT_A_LAW, 134 AFMT_STEREO | AFMT_A_LAW, 135 0 136 }; 137 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0}; 138 139 static u_int32_t guspnp_fmt[] = { 140 AFMT_U8, 141 AFMT_STEREO | AFMT_U8, 142 AFMT_S16_LE, 143 AFMT_STEREO | AFMT_S16_LE, 144 AFMT_A_LAW, 145 AFMT_STEREO | AFMT_A_LAW, 146 0 147 }; 148 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0}; 149 150 static u_int32_t opti931_fmt[] = { 151 AFMT_U8, 152 AFMT_STEREO | AFMT_U8, 153 AFMT_S16_LE, 154 AFMT_STEREO | AFMT_S16_LE, 155 0 156 }; 157 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0}; 158 159 #define MD_AD1848 0x91 160 #define MD_AD1845 0x92 161 #define MD_CS42XX 0xA1 162 #define MD_CS423X 0xA2 163 #define MD_OPTI930 0xB0 164 #define MD_OPTI931 0xB1 165 #define MD_OPTI925 0xB2 166 #define MD_OPTI924 0xB3 167 #define MD_GUSPNP 0xB8 168 #define MD_GUSMAX 0xB9 169 #define MD_YM0020 0xC1 170 #define MD_VIVO 0xD1 171 172 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */ 173 174 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX) 175 176 static void 177 mss_lock(struct mss_info *mss) 178 { 179 snd_mtxlock(mss->lock); 180 } 181 182 static void 183 mss_unlock(struct mss_info *mss) 184 { 185 snd_mtxunlock(mss->lock); 186 } 187 188 static int 189 port_rd(struct resource *port, int off) 190 { 191 if (port) 192 return bus_space_read_1(rman_get_bustag(port), 193 rman_get_bushandle(port), 194 off); 195 else 196 return -1; 197 } 198 199 static void 200 port_wr(struct resource *port, int off, u_int8_t data) 201 { 202 if (port) 203 bus_space_write_1(rman_get_bustag(port), 204 rman_get_bushandle(port), 205 off, data); 206 } 207 208 static int 209 io_rd(struct mss_info *mss, int reg) 210 { 211 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 212 return port_rd(mss->io_base, reg); 213 } 214 215 static void 216 io_wr(struct mss_info *mss, int reg, u_int8_t data) 217 { 218 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 219 port_wr(mss->io_base, reg, data); 220 } 221 222 static void 223 conf_wr(struct mss_info *mss, u_char reg, u_char value) 224 { 225 port_wr(mss->conf_base, 0, reg); 226 port_wr(mss->conf_base, 1, value); 227 } 228 229 static u_char 230 conf_rd(struct mss_info *mss, u_char reg) 231 { 232 port_wr(mss->conf_base, 0, reg); 233 return port_rd(mss->conf_base, 1); 234 } 235 236 static void 237 opti_wr(struct mss_info *mss, u_char reg, u_char value) 238 { 239 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 240 port_wr(mss->conf_base, mss->opti_offset + 1, value); 241 } 242 243 static u_char 244 opti_rd(struct mss_info *mss, u_char reg) 245 { 246 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 247 return port_rd(mss->conf_base, mss->opti_offset + 1); 248 } 249 250 static void 251 gus_wr(struct mss_info *mss, u_char reg, u_char value) 252 { 253 port_wr(mss->conf_base, 3, reg); 254 port_wr(mss->conf_base, 5, value); 255 } 256 257 static u_char 258 gus_rd(struct mss_info *mss, u_char reg) 259 { 260 port_wr(mss->conf_base, 3, reg); 261 return port_rd(mss->conf_base, 5); 262 } 263 264 static void 265 mss_release_resources(struct mss_info *mss, device_t dev) 266 { 267 if (mss->irq) { 268 if (mss->ih) 269 bus_teardown_intr(dev, mss->irq, mss->ih); 270 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid, 271 mss->irq); 272 mss->irq = 0; 273 } 274 if (mss->drq2) { 275 if (mss->drq2 != mss->drq1) { 276 isa_dma_release(rman_get_start(mss->drq2)); 277 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid, 278 mss->drq2); 279 } 280 mss->drq2 = 0; 281 } 282 if (mss->drq1) { 283 isa_dma_release(rman_get_start(mss->drq1)); 284 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid, 285 mss->drq1); 286 mss->drq1 = 0; 287 } 288 if (mss->io_base) { 289 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid, 290 mss->io_base); 291 mss->io_base = 0; 292 } 293 if (mss->conf_base) { 294 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 295 mss->conf_base); 296 mss->conf_base = 0; 297 } 298 if (mss->indir) { 299 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, 300 mss->indir); 301 mss->indir = 0; 302 } 303 if (mss->parent_dmat) { 304 bus_dma_tag_destroy(mss->parent_dmat); 305 mss->parent_dmat = 0; 306 } 307 if (mss->lock) snd_mtxfree(mss->lock); 308 309 free(mss, M_DEVBUF); 310 } 311 312 static int 313 mss_alloc_resources(struct mss_info *mss, device_t dev) 314 { 315 int pdma, rdma, ok = 1; 316 if (!mss->io_base) 317 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 318 0, ~0, 1, RF_ACTIVE); 319 if (!mss->irq) 320 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid, 321 0, ~0, 1, RF_ACTIVE); 322 if (!mss->drq1) 323 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid, 324 0, ~0, 1, RF_ACTIVE); 325 if (mss->conf_rid >= 0 && !mss->conf_base) 326 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 327 0, ~0, 1, RF_ACTIVE); 328 if (mss->drq2_rid >= 0 && !mss->drq2) 329 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid, 330 0, ~0, 1, RF_ACTIVE); 331 332 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0; 333 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0; 334 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0; 335 336 if (ok) { 337 pdma = rman_get_start(mss->drq1); 338 isa_dma_acquire(pdma); 339 isa_dmainit(pdma, mss->bufsize); 340 mss->bd_flags &= ~BD_F_DUPLEX; 341 if (mss->drq2) { 342 rdma = rman_get_start(mss->drq2); 343 isa_dma_acquire(rdma); 344 isa_dmainit(rdma, mss->bufsize); 345 mss->bd_flags |= BD_F_DUPLEX; 346 } else mss->drq2 = mss->drq1; 347 } 348 return ok; 349 } 350 351 /* 352 * The various mixers use a variety of bitmasks etc. The Voxware 353 * driver had a very nice technique to describe a mixer and interface 354 * to it. A table defines, for each channel, which register, bits, 355 * offset, polarity to use. This procedure creates the new value 356 * using the table and the old value. 357 */ 358 359 static void 360 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval) 361 { 362 u_char mask; 363 int shift; 364 365 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x " 366 "r %d p %d bit %d off %d\n", 367 dev, chn, newval, *regval, 368 (*t)[dev][chn].regno, (*t)[dev][chn].polarity, 369 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) ); 370 371 if ( (*t)[dev][chn].polarity == 1) /* reverse */ 372 newval = 100 - newval ; 373 374 mask = (1 << (*t)[dev][chn].nbits) - 1; 375 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */ 376 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/; 377 378 *regval &= ~(mask << shift); /* Filter out the previous value */ 379 *regval |= (newval & mask) << shift; /* Set the new value */ 380 } 381 382 /* -------------------------------------------------------------------- */ 383 /* only one source can be set... */ 384 static int 385 mss_set_recsrc(struct mss_info *mss, int mask) 386 { 387 u_char recdev; 388 389 switch (mask) { 390 case SOUND_MASK_LINE: 391 case SOUND_MASK_LINE3: 392 recdev = 0; 393 break; 394 395 case SOUND_MASK_CD: 396 case SOUND_MASK_LINE1: 397 recdev = 0x40; 398 break; 399 400 case SOUND_MASK_IMIX: 401 recdev = 0xc0; 402 break; 403 404 case SOUND_MASK_MIC: 405 default: 406 mask = SOUND_MASK_MIC; 407 recdev = 0x80; 408 } 409 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev); 410 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev); 411 return mask; 412 } 413 414 /* there are differences in the mixer depending on the actual sound card. */ 415 static int 416 mss_mixer_set(struct mss_info *mss, int dev, int left, int right) 417 { 418 int regoffs; 419 mixer_tab *mix_d; 420 u_char old, val; 421 422 switch (mss->bd_id) { 423 case MD_OPTI931: 424 mix_d = &opti931_devices; 425 break; 426 case MD_OPTI930: 427 mix_d = &opti930_devices; 428 break; 429 default: 430 mix_d = &mix_devices; 431 } 432 433 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) { 434 DEB(printf("nbits = 0 for dev %d\n", dev)); 435 return -1; 436 } 437 438 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */ 439 440 /* Set the left channel */ 441 442 regoffs = (*mix_d)[dev][LEFT_CHN].regno; 443 old = val = ad_read(mss, regoffs); 444 /* if volume is 0, mute chan. Otherwise, unmute. */ 445 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f; 446 change_bits(mix_d, &val, dev, LEFT_CHN, left); 447 ad_write(mss, regoffs, val); 448 449 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n", 450 dev, regoffs, old, val)); 451 452 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */ 453 /* Set the right channel */ 454 regoffs = (*mix_d)[dev][RIGHT_CHN].regno; 455 old = val = ad_read(mss, regoffs); 456 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f; 457 change_bits(mix_d, &val, dev, RIGHT_CHN, right); 458 ad_write(mss, regoffs, val); 459 460 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n", 461 dev, regoffs, old, val)); 462 } 463 return 0; /* success */ 464 } 465 466 /* -------------------------------------------------------------------- */ 467 468 static int 469 mssmix_init(struct snd_mixer *m) 470 { 471 struct mss_info *mss = mix_getdevinfo(m); 472 473 mix_setdevs(m, MODE2_MIXER_DEVICES); 474 mix_setrecdevs(m, MSS_REC_DEVICES); 475 switch(mss->bd_id) { 476 case MD_OPTI930: 477 mix_setdevs(m, OPTI930_MIXER_DEVICES); 478 break; 479 480 case MD_OPTI931: 481 mix_setdevs(m, OPTI931_MIXER_DEVICES); 482 mss_lock(mss); 483 ad_write(mss, 20, 0x88); 484 ad_write(mss, 21, 0x88); 485 mss_unlock(mss); 486 break; 487 488 case MD_AD1848: 489 mix_setdevs(m, MODE1_MIXER_DEVICES); 490 break; 491 492 case MD_GUSPNP: 493 case MD_GUSMAX: 494 /* this is only necessary in mode 3 ... */ 495 mss_lock(mss); 496 ad_write(mss, 22, 0x88); 497 ad_write(mss, 23, 0x88); 498 mss_unlock(mss); 499 break; 500 } 501 return 0; 502 } 503 504 static int 505 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 506 { 507 struct mss_info *mss = mix_getdevinfo(m); 508 509 mss_lock(mss); 510 mss_mixer_set(mss, dev, left, right); 511 mss_unlock(mss); 512 513 return left | (right << 8); 514 } 515 516 static int 517 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 518 { 519 struct mss_info *mss = mix_getdevinfo(m); 520 521 mss_lock(mss); 522 src = mss_set_recsrc(mss, src); 523 mss_unlock(mss); 524 return src; 525 } 526 527 static kobj_method_t mssmix_mixer_methods[] = { 528 KOBJMETHOD(mixer_init, mssmix_init), 529 KOBJMETHOD(mixer_set, mssmix_set), 530 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc), 531 { 0, 0 } 532 }; 533 MIXER_DECLARE(mssmix_mixer); 534 535 /* -------------------------------------------------------------------- */ 536 537 static int 538 ymmix_init(struct snd_mixer *m) 539 { 540 struct mss_info *mss = mix_getdevinfo(m); 541 542 mssmix_init(m); 543 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC 544 | SOUND_MASK_BASS | SOUND_MASK_TREBLE); 545 /* Set master volume */ 546 mss_lock(mss); 547 conf_wr(mss, OPL3SAx_VOLUMEL, 7); 548 conf_wr(mss, OPL3SAx_VOLUMER, 7); 549 mss_unlock(mss); 550 551 return 0; 552 } 553 554 static int 555 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 556 { 557 struct mss_info *mss = mix_getdevinfo(m); 558 int t, l, r; 559 560 mss_lock(mss); 561 switch (dev) { 562 case SOUND_MIXER_VOLUME: 563 if (left) t = 15 - (left * 15) / 100; 564 else t = 0x80; /* mute */ 565 conf_wr(mss, OPL3SAx_VOLUMEL, t); 566 if (right) t = 15 - (right * 15) / 100; 567 else t = 0x80; /* mute */ 568 conf_wr(mss, OPL3SAx_VOLUMER, t); 569 break; 570 571 case SOUND_MIXER_MIC: 572 t = left; 573 if (left) t = 31 - (left * 31) / 100; 574 else t = 0x80; /* mute */ 575 conf_wr(mss, OPL3SAx_MIC, t); 576 break; 577 578 case SOUND_MIXER_BASS: 579 l = (left * 7) / 100; 580 r = (right * 7) / 100; 581 t = (r << 4) | l; 582 conf_wr(mss, OPL3SAx_BASS, t); 583 break; 584 585 case SOUND_MIXER_TREBLE: 586 l = (left * 7) / 100; 587 r = (right * 7) / 100; 588 t = (r << 4) | l; 589 conf_wr(mss, OPL3SAx_TREBLE, t); 590 break; 591 592 default: 593 mss_mixer_set(mss, dev, left, right); 594 } 595 mss_unlock(mss); 596 597 return left | (right << 8); 598 } 599 600 static int 601 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 602 { 603 struct mss_info *mss = mix_getdevinfo(m); 604 mss_lock(mss); 605 src = mss_set_recsrc(mss, src); 606 mss_unlock(mss); 607 return src; 608 } 609 610 static kobj_method_t ymmix_mixer_methods[] = { 611 KOBJMETHOD(mixer_init, ymmix_init), 612 KOBJMETHOD(mixer_set, ymmix_set), 613 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc), 614 { 0, 0 } 615 }; 616 MIXER_DECLARE(ymmix_mixer); 617 618 /* -------------------------------------------------------------------- */ 619 /* 620 * XXX This might be better off in the gusc driver. 621 */ 622 static void 623 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt) 624 { 625 static const unsigned char irq_bits[16] = { 626 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7 627 }; 628 static const unsigned char dma_bits[8] = { 629 0, 1, 0, 2, 0, 3, 4, 5 630 }; 631 device_t parent = device_get_parent(dev); 632 unsigned char irqctl, dmactl; 633 int s; 634 635 s = splhigh(); 636 637 port_wr(alt, 0x0f, 0x05); 638 port_wr(alt, 0x00, 0x0c); 639 port_wr(alt, 0x0b, 0x00); 640 641 port_wr(alt, 0x0f, 0x00); 642 643 irqctl = irq_bits[isa_get_irq(parent)]; 644 /* Share the IRQ with the MIDI driver. */ 645 irqctl |= 0x40; 646 dmactl = dma_bits[isa_get_drq(parent)]; 647 if (device_get_flags(parent) & DV_F_DUAL_DMA) 648 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK] 649 << 3; 650 651 /* 652 * Set the DMA and IRQ control latches. 653 */ 654 port_wr(alt, 0x00, 0x0c); 655 port_wr(alt, 0x0b, dmactl | 0x80); 656 port_wr(alt, 0x00, 0x4c); 657 port_wr(alt, 0x0b, irqctl); 658 659 port_wr(alt, 0x00, 0x0c); 660 port_wr(alt, 0x0b, dmactl); 661 port_wr(alt, 0x00, 0x4c); 662 port_wr(alt, 0x0b, irqctl); 663 664 port_wr(mss->conf_base, 2, 0); 665 port_wr(alt, 0x00, 0x0c); 666 port_wr(mss->conf_base, 2, 0); 667 668 splx(s); 669 } 670 671 static int 672 mss_init(struct mss_info *mss, device_t dev) 673 { 674 u_char r6, r9; 675 struct resource *alt; 676 int rid, tmp; 677 678 mss->bd_flags |= BD_F_MCE_BIT; 679 switch(mss->bd_id) { 680 case MD_OPTI931: 681 /* 682 * The MED3931 v.1.0 allocates 3 bytes for the config 683 * space, whereas v.2.0 allocates 4 bytes. What I know 684 * for sure is that the upper two ports must be used, 685 * and they should end on a boundary of 4 bytes. So I 686 * need the following trick. 687 */ 688 mss->opti_offset = 689 (rman_get_start(mss->conf_base) & ~3) + 2 690 - rman_get_start(mss->conf_base); 691 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset)); 692 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */ 693 ad_write(mss, 10, 2); /* enable interrupts */ 694 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */ 695 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */ 696 break; 697 698 case MD_GUSPNP: 699 case MD_GUSMAX: 700 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */ 701 DELAY(1000 * 30); 702 /* release reset and enable DAC */ 703 gus_wr(mss, 0x4c /* _URSTI */, 3); 704 DELAY(1000 * 30); 705 /* end of reset */ 706 707 rid = 0; 708 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 709 0, ~0, 1, RF_ACTIVE); 710 if (alt == NULL) { 711 printf("XXX couldn't init GUS PnP/MAX\n"); 712 break; 713 } 714 port_wr(alt, 0, 0xC); /* enable int and dma */ 715 if (mss->bd_id == MD_GUSMAX) 716 gusmax_setup(mss, dev, alt); 717 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt); 718 719 /* 720 * unmute left & right line. Need to go in mode3, unmute, 721 * and back to mode 2 722 */ 723 tmp = ad_read(mss, 0x0c); 724 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */ 725 ad_write(mss, 0x19, 0); /* unmute left */ 726 ad_write(mss, 0x1b, 0); /* unmute right */ 727 ad_write(mss, 0x0c, tmp); /* restore old mode */ 728 729 /* send codec interrupts on irq1 and only use that one */ 730 gus_wr(mss, 0x5a, 0x4f); 731 732 /* enable access to hidden regs */ 733 tmp = gus_rd(mss, 0x5b /* IVERI */); 734 gus_wr(mss, 0x5b, tmp | 1); 735 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4))); 736 break; 737 738 case MD_YM0020: 739 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */ 740 r6 = conf_rd(mss, OPL3SAx_DMACONF); 741 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */ 742 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);) 743 /* yamaha - set volume to max */ 744 conf_wr(mss, OPL3SAx_VOLUMEL, 0); 745 conf_wr(mss, OPL3SAx_VOLUMER, 0); 746 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b); 747 break; 748 } 749 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931) 750 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */ 751 ad_enter_MCE(mss); 752 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4); 753 ad_leave_MCE(mss); 754 ad_write(mss, 10, 2); /* int enable */ 755 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 756 /* the following seem required on the CS4232 */ 757 ad_unmute(mss); 758 return 0; 759 } 760 761 762 /* 763 * main irq handler for the CS423x. The OPTi931 code is 764 * a separate one. 765 * The correct way to operate for a device with multiple internal 766 * interrupt sources is to loop on the status register and ack 767 * interrupts until all interrupts are served and none are reported. At 768 * this point the IRQ line to the ISA IRQ controller should go low 769 * and be raised at the next interrupt. 770 * 771 * Since the ISA IRQ controller is sent EOI _before_ passing control 772 * to the isr, it might happen that we serve an interrupt early, in 773 * which case the status register at the next interrupt should just 774 * say that there are no more interrupts... 775 */ 776 777 static void 778 mss_intr(void *arg) 779 { 780 struct mss_info *mss = arg; 781 u_char c = 0, served = 0; 782 int i; 783 784 DEB(printf("mss_intr\n")); 785 mss_lock(mss); 786 ad_read(mss, 11); /* fake read of status bits */ 787 788 /* loop until there are interrupts, but no more than 10 times. */ 789 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) { 790 /* get exact reason for full-duplex boards */ 791 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30; 792 c &= ~served; 793 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) { 794 served |= 0x10; 795 chn_intr(mss->pch.channel); 796 } 797 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) { 798 served |= 0x20; 799 chn_intr(mss->rch.channel); 800 } 801 /* now ack the interrupt */ 802 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */ 803 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 804 } 805 if (i == 10) { 806 BVDDB(printf("mss_intr: irq, but not from mss\n")); 807 } else if (served == 0) { 808 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c)); 809 /* 810 * this should not happen... I have no idea what to do now. 811 * maybe should do a sanity check and restart dmas ? 812 */ 813 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 814 } 815 mss_unlock(mss); 816 } 817 818 /* 819 * AD_WAIT_INIT waits if we are initializing the board and 820 * we cannot modify its settings 821 */ 822 static int 823 ad_wait_init(struct mss_info *mss, int x) 824 { 825 int arg = x, n = 0; /* to shut up the compiler... */ 826 for (; x > 0; x--) 827 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10); 828 else return n; 829 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n); 830 return n; 831 } 832 833 static int 834 ad_read(struct mss_info *mss, int reg) 835 { 836 int x; 837 838 ad_wait_init(mss, 201000); 839 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 840 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 841 x = io_rd(mss, MSS_IDATA); 842 /* printf("ad_read %d, %x\n", reg, x); */ 843 return x; 844 } 845 846 static void 847 ad_write(struct mss_info *mss, int reg, u_char data) 848 { 849 int x; 850 851 /* printf("ad_write %d, %x\n", reg, data); */ 852 ad_wait_init(mss, 1002000); 853 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 854 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 855 io_wr(mss, MSS_IDATA, data); 856 } 857 858 static void 859 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt) 860 { 861 ad_write(mss, reg+1, cnt & 0xff); 862 ad_write(mss, reg, cnt >> 8); /* upper base must be last */ 863 } 864 865 static void 866 wait_for_calibration(struct mss_info *mss) 867 { 868 int t; 869 870 /* 871 * Wait until the auto calibration process has finished. 872 * 873 * 1) Wait until the chip becomes ready (reads don't return 0x80). 874 * 2) Wait until the ACI bit of I11 gets on 875 * 3) Wait until the ACI bit of I11 gets off 876 */ 877 878 t = ad_wait_init(mss, 1000000); 879 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n"); 880 881 /* 882 * The calibration mode for chips that support it is set so that 883 * we never see ACI go on. 884 */ 885 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) { 886 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--); 887 } else { 888 /* 889 * XXX This should only be enabled for cards that *really* 890 * need it. Are there any? 891 */ 892 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100); 893 } 894 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100); 895 } 896 897 static void 898 ad_unmute(struct mss_info *mss) 899 { 900 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE); 901 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE); 902 } 903 904 static void 905 ad_enter_MCE(struct mss_info *mss) 906 { 907 int prev; 908 909 mss->bd_flags |= BD_F_MCE_BIT; 910 ad_wait_init(mss, 203000); 911 prev = io_rd(mss, MSS_INDEX); 912 prev &= ~MSS_TRD; 913 io_wr(mss, MSS_INDEX, prev | MSS_MCE); 914 } 915 916 static void 917 ad_leave_MCE(struct mss_info *mss) 918 { 919 u_char prev; 920 921 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) { 922 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n")); 923 return; 924 } 925 926 ad_wait_init(mss, 1000000); 927 928 mss->bd_flags &= ~BD_F_MCE_BIT; 929 930 prev = io_rd(mss, MSS_INDEX); 931 prev &= ~MSS_TRD; 932 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */ 933 wait_for_calibration(mss); 934 } 935 936 static int 937 mss_speed(struct mss_chinfo *ch, int speed) 938 { 939 struct mss_info *mss = ch->parent; 940 /* 941 * In the CS4231, the low 4 bits of I8 are used to hold the 942 * sample rate. Only a fixed number of values is allowed. This 943 * table lists them. The speed-setting routines scans the table 944 * looking for the closest match. This is the only supported method. 945 * 946 * In the CS4236, there is an alternate metod (which we do not 947 * support yet) which provides almost arbitrary frequency setting. 948 * In the AD1845, it looks like the sample rate can be 949 * almost arbitrary, and written directly to a register. 950 * In the OPTi931, there is a SB command which provides for 951 * almost arbitrary frequency setting. 952 * 953 */ 954 ad_enter_MCE(mss); 955 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */ 956 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */ 957 ad_write(mss, 23, speed & 0xff); /* Speed LSB */ 958 /* XXX must also do something in I27 for the ad1845 */ 959 } else { 960 int i, sel = 0; /* assume entry 0 does not contain -1 */ 961 static int speeds[] = 962 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050, 963 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615}; 964 965 for (i = 1; i < 16; i++) 966 if (speeds[i] > 0 && 967 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i; 968 speed = speeds[sel]; 969 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel); 970 } 971 ad_leave_MCE(mss); 972 973 return speed; 974 } 975 976 /* 977 * mss_format checks that the format is supported (or defaults to AFMT_U8) 978 * and returns the bit setting for the 1848 register corresponding to 979 * the desired format. 980 * 981 * fixed lr970724 982 */ 983 984 static int 985 mss_format(struct mss_chinfo *ch, u_int32_t format) 986 { 987 struct mss_info *mss = ch->parent; 988 int i, arg = format & ~AFMT_STEREO; 989 990 /* 991 * The data format uses 3 bits (just 2 on the 1848). For each 992 * bit setting, the following array returns the corresponding format. 993 * The code scans the array looking for a suitable format. In 994 * case it is not found, default to AFMT_U8 (not such a good 995 * choice, but let's do it for compatibility...). 996 */ 997 998 static int fmts[] = 999 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW, 1000 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1}; 1001 1002 ch->fmt = format; 1003 for (i = 0; i < 8; i++) if (arg == fmts[i]) break; 1004 arg = i << 1; 1005 if (format & AFMT_STEREO) arg |= 1; 1006 arg <<= 4; 1007 ad_enter_MCE(mss); 1008 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg); 1009 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */ 1010 ad_leave_MCE(mss); 1011 return format; 1012 } 1013 1014 static int 1015 mss_trigger(struct mss_chinfo *ch, int go) 1016 { 1017 struct mss_info *mss = ch->parent; 1018 u_char m; 1019 int retry, wr, cnt, ss; 1020 1021 ss = 1; 1022 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0; 1023 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0; 1024 1025 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0; 1026 m = ad_read(mss, 9); 1027 switch (go) { 1028 case PCMTRIG_START: 1029 cnt = (ch->blksz / ss) - 1; 1030 1031 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m);); 1032 m |= wr? I9_PEN : I9_CEN; /* enable DMA */ 1033 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt); 1034 break; 1035 1036 case PCMTRIG_STOP: 1037 case PCMTRIG_ABORT: /* XXX check this... */ 1038 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */ 1039 #if 0 1040 /* 1041 * try to disable DMA by clearing count registers. Not sure it 1042 * is needed, and it might cause false interrupts when the 1043 * DMA is re-enabled later. 1044 */ 1045 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0); 1046 #endif 1047 } 1048 /* on the OPTi931 the enable bit seems hard to set... */ 1049 for (retry = 10; retry > 0; retry--) { 1050 ad_write(mss, 9, m); 1051 if (ad_read(mss, 9) == m) break; 1052 } 1053 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \ 1054 m, ad_read(mss, 9))); 1055 return 0; 1056 } 1057 1058 1059 /* 1060 * the opti931 seems to miss interrupts when working in full 1061 * duplex, so we try some heuristics to catch them. 1062 */ 1063 static void 1064 opti931_intr(void *arg) 1065 { 1066 struct mss_info *mss = (struct mss_info *)arg; 1067 u_char masked = 0, i11, mc11, c = 0; 1068 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */ 1069 int loops = 10; 1070 1071 #if 0 1072 reason = io_rd(mss, MSS_STATUS); 1073 if (!(reason & 1)) {/* no int, maybe a shared line ? */ 1074 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11))); 1075 return; 1076 } 1077 #endif 1078 mss_lock(mss); 1079 i11 = ad_read(mss, 11); /* XXX what's for ? */ 1080 again: 1081 1082 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc; 1083 mc11 &= 0x0c; 1084 if (c & 0x10) { 1085 DEB(printf("Warning: CD interrupt\n");) 1086 mc11 |= 0x10; 1087 } 1088 if (c & 0x20) { 1089 DEB(printf("Warning: MPU interrupt\n");) 1090 mc11 |= 0x20; 1091 } 1092 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\ 1093 mc11, masked)); 1094 masked |= mc11; 1095 /* 1096 * the nice OPTi931 sets the IRQ line before setting the bits in 1097 * mc11. So, on some occasions I have to retry (max 10 times). 1098 */ 1099 if (mc11 == 0) { /* perhaps can return ... */ 1100 reason = io_rd(mss, MSS_STATUS); 1101 if (reason & 1) { 1102 DEB(printf("one more try...\n");) 1103 if (--loops) goto again; 1104 else DDB(printf("intr, but mc11 not set\n");) 1105 } 1106 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11)); 1107 mss_unlock(mss); 1108 return; 1109 } 1110 1111 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) chn_intr(mss->rch.channel); 1112 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) chn_intr(mss->pch.channel); 1113 opti_wr(mss, 11, ~mc11); /* ack */ 1114 if (--loops) goto again; 1115 mss_unlock(mss); 1116 DEB(printf("xxx too many loops\n");) 1117 } 1118 1119 /* -------------------------------------------------------------------- */ 1120 /* channel interface */ 1121 static void * 1122 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 1123 { 1124 struct mss_info *mss = devinfo; 1125 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch; 1126 1127 ch->parent = mss; 1128 ch->channel = c; 1129 ch->buffer = b; 1130 ch->dir = dir; 1131 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) == -1) return NULL; 1132 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2); 1133 return ch; 1134 } 1135 1136 static int 1137 msschan_setformat(kobj_t obj, void *data, u_int32_t format) 1138 { 1139 struct mss_chinfo *ch = data; 1140 struct mss_info *mss = ch->parent; 1141 1142 mss_lock(mss); 1143 mss_format(ch, format); 1144 mss_unlock(mss); 1145 return 0; 1146 } 1147 1148 static int 1149 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed) 1150 { 1151 struct mss_chinfo *ch = data; 1152 struct mss_info *mss = ch->parent; 1153 int r; 1154 1155 mss_lock(mss); 1156 r = mss_speed(ch, speed); 1157 mss_unlock(mss); 1158 1159 return r; 1160 } 1161 1162 static int 1163 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 1164 { 1165 struct mss_chinfo *ch = data; 1166 1167 ch->blksz = blocksize; 1168 sndbuf_resize(ch->buffer, 2, ch->blksz); 1169 1170 return ch->blksz; 1171 } 1172 1173 static int 1174 msschan_trigger(kobj_t obj, void *data, int go) 1175 { 1176 struct mss_chinfo *ch = data; 1177 struct mss_info *mss = ch->parent; 1178 1179 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 1180 return 0; 1181 1182 sndbuf_dma(ch->buffer, go); 1183 mss_lock(mss); 1184 mss_trigger(ch, go); 1185 mss_unlock(mss); 1186 return 0; 1187 } 1188 1189 static int 1190 msschan_getptr(kobj_t obj, void *data) 1191 { 1192 struct mss_chinfo *ch = data; 1193 return sndbuf_dmaptr(ch->buffer); 1194 } 1195 1196 static struct pcmchan_caps * 1197 msschan_getcaps(kobj_t obj, void *data) 1198 { 1199 struct mss_chinfo *ch = data; 1200 1201 switch(ch->parent->bd_id) { 1202 case MD_OPTI931: 1203 return &opti931_caps; 1204 break; 1205 1206 case MD_GUSPNP: 1207 case MD_GUSMAX: 1208 return &guspnp_caps; 1209 break; 1210 1211 default: 1212 return &mss_caps; 1213 break; 1214 } 1215 } 1216 1217 static kobj_method_t msschan_methods[] = { 1218 KOBJMETHOD(channel_init, msschan_init), 1219 KOBJMETHOD(channel_setformat, msschan_setformat), 1220 KOBJMETHOD(channel_setspeed, msschan_setspeed), 1221 KOBJMETHOD(channel_setblocksize, msschan_setblocksize), 1222 KOBJMETHOD(channel_trigger, msschan_trigger), 1223 KOBJMETHOD(channel_getptr, msschan_getptr), 1224 KOBJMETHOD(channel_getcaps, msschan_getcaps), 1225 { 0, 0 } 1226 }; 1227 CHANNEL_DECLARE(msschan); 1228 1229 /* -------------------------------------------------------------------- */ 1230 1231 /* 1232 * mss_probe() is the probe routine. Note, it is not necessary to 1233 * go through this for PnP devices, since they are already 1234 * indentified precisely using their PnP id. 1235 * 1236 * The base address supplied in the device refers to the old MSS 1237 * specs where the four 4 registers in io space contain configuration 1238 * information. Some boards (as an example, early MSS boards) 1239 * has such a block of registers, whereas others (generally CS42xx) 1240 * do not. In order to distinguish between the two and do not have 1241 * to supply two separate probe routines, the flags entry in isa_device 1242 * has a bit to mark this. 1243 * 1244 */ 1245 1246 static int 1247 mss_probe(device_t dev) 1248 { 1249 u_char tmp, tmpx; 1250 int flags, irq, drq, result = ENXIO, setres = 0; 1251 struct mss_info *mss; 1252 1253 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */ 1254 1255 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1256 if (!mss) return ENXIO; 1257 1258 mss->io_rid = 0; 1259 mss->conf_rid = -1; 1260 mss->irq_rid = 0; 1261 mss->drq1_rid = 0; 1262 mss->drq2_rid = -1; 1263 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1264 0, ~0, 8, RF_ACTIVE); 1265 if (!mss->io_base) { 1266 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530)); 1267 mss->io_rid = 0; 1268 /* XXX verify this */ 1269 setres = 1; 1270 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid, 1271 0x530, 8); 1272 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1273 0, ~0, 8, RF_ACTIVE); 1274 } 1275 if (!mss->io_base) goto no; 1276 1277 /* got irq/dma regs? */ 1278 flags = device_get_flags(dev); 1279 irq = isa_get_irq(dev); 1280 drq = isa_get_drq(dev); 1281 1282 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end; 1283 1284 /* 1285 * Check if the IO port returns valid signature. The original MS 1286 * Sound system returns 0x04 while some cards 1287 * (AudioTriX Pro for example) return 0x00 or 0x0f. 1288 */ 1289 1290 device_set_desc(dev, "MSS"); 1291 tmpx = tmp = io_rd(mss, 3); 1292 if (tmp == 0xff) { /* Bus float */ 1293 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp)); 1294 device_set_flags(dev, flags & ~DV_F_TRUE_MSS); 1295 goto mss_probe_end; 1296 } 1297 tmp &= 0x3f; 1298 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) { 1299 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n", 1300 rman_get_start(mss->io_base), tmpx)); 1301 goto no; 1302 } 1303 #ifdef PC98 1304 if (irq > 12) { 1305 #else 1306 if (irq > 11) { 1307 #endif 1308 printf("MSS: Bad IRQ %d\n", irq); 1309 goto no; 1310 } 1311 if (!(drq == 0 || drq == 1 || drq == 3)) { 1312 printf("MSS: Bad DMA %d\n", drq); 1313 goto no; 1314 } 1315 if (tmpx & 0x80) { 1316 /* 8-bit board: only drq1/3 and irq7/9 */ 1317 if (drq == 0) { 1318 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n"); 1319 goto no; 1320 } 1321 if (!(irq == 7 || irq == 9)) { 1322 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", 1323 irq); 1324 goto no; 1325 } 1326 } 1327 mss_probe_end: 1328 result = mss_detect(dev, mss); 1329 no: 1330 mss_release_resources(mss, dev); 1331 #if 0 1332 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev, 1333 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */ 1334 #endif 1335 return result; 1336 } 1337 1338 static int 1339 mss_detect(device_t dev, struct mss_info *mss) 1340 { 1341 int i; 1342 u_char tmp = 0, tmp1, tmp2; 1343 char *name, *yamaha; 1344 1345 if (mss->bd_id != 0) { 1346 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id, 1347 device_get_desc(dev)); 1348 return 0; 1349 } 1350 1351 name = "AD1848"; 1352 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */ 1353 1354 if (opti_detect(dev, mss)) { 1355 switch (mss->bd_id) { 1356 case MD_OPTI924: 1357 name = "OPTi924"; 1358 break; 1359 case MD_OPTI930: 1360 name = "OPTi930"; 1361 break; 1362 } 1363 printf("Found OPTi device %s\n", name); 1364 if (opti_init(dev, mss) == 0) goto gotit; 1365 } 1366 1367 /* 1368 * Check that the I/O address is in use. 1369 * 1370 * bit 7 of the base I/O port is known to be 0 after the chip has 1371 * performed its power on initialization. Just assume this has 1372 * happened before the OS is starting. 1373 * 1374 * If the I/O address is unused, it typically returns 0xff. 1375 */ 1376 1377 for (i = 0; i < 10; i++) 1378 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 1379 else break; 1380 1381 if (i >= 10) { /* Not an AD1848 */ 1382 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp)); 1383 goto no; 1384 } 1385 /* 1386 * Test if it's possible to change contents of the indirect 1387 * registers. Registers 0 and 1 are ADC volume registers. The bit 1388 * 0x10 is read only so try to avoid using it. 1389 */ 1390 1391 ad_write(mss, 0, 0xaa); 1392 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */ 1393 tmp1 = ad_read(mss, 0); 1394 tmp2 = ad_read(mss, 1); 1395 if (tmp1 != 0xaa || tmp2 != 0x45) { 1396 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2)); 1397 goto no; 1398 } 1399 1400 ad_write(mss, 0, 0x45); 1401 ad_write(mss, 1, 0xaa); 1402 tmp1 = ad_read(mss, 0); 1403 tmp2 = ad_read(mss, 1); 1404 if (tmp1 != 0x45 || tmp2 != 0xaa) { 1405 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2)); 1406 goto no; 1407 } 1408 1409 /* 1410 * The indirect register I12 has some read only bits. Lets try to 1411 * change them. 1412 */ 1413 1414 tmp = ad_read(mss, 12); 1415 ad_write(mss, 12, (~tmp) & 0x0f); 1416 tmp1 = ad_read(mss, 12); 1417 1418 if ((tmp & 0x0f) != (tmp1 & 0x0f)) { 1419 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp)); 1420 goto no; 1421 } 1422 1423 /* 1424 * NOTE! Last 4 bits of the reg I12 tell the chip revision. 1425 * 0x01=RevB 1426 * 0x0A=RevC. also CS4231/CS4231A and OPTi931 1427 */ 1428 1429 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);) 1430 1431 /* 1432 * The original AD1848/CS4248 has just 16 indirect registers. This 1433 * means that I0 and I16 should return the same value (etc.). Ensure 1434 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails 1435 * with new parts. 1436 */ 1437 1438 ad_write(mss, 12, 0); /* Mode2=disabled */ 1439 #if 0 1440 for (i = 0; i < 16; i++) { 1441 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) { 1442 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n", 1443 i, tmp1, tmp2)); 1444 /* 1445 * note - this seems to fail on the 4232 on I11. So we just break 1446 * rather than fail. (which makes this test pointless - cg) 1447 */ 1448 break; /* return 0; */ 1449 } 1450 } 1451 #endif 1452 /* 1453 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 1454 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231. 1455 * 1456 * On the OPTi931, however, I12 is readonly and only contains the 1457 * chip revision ID (as in the CS4231A). The upper bits return 0. 1458 */ 1459 1460 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */ 1461 1462 tmp1 = ad_read(mss, 12); 1463 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */ 1464 if ((tmp1 & 0xf0) == 0x00) { 1465 BVDDB(printf("this should be an OPTi931\n");) 1466 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit; 1467 /* 1468 * The 4231 has bit7=1 always, and bit6 we just set to 1. 1469 * We want to check that this is really a CS4231 1470 * Verify that setting I0 doesn't change I16. 1471 */ 1472 ad_write(mss, 16, 0); /* Set I16 to known value */ 1473 ad_write(mss, 0, 0x45); 1474 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit; 1475 1476 ad_write(mss, 0, 0xaa); 1477 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */ 1478 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1)); 1479 goto no; 1480 } 1481 /* Verify that some bits of I25 are read only. */ 1482 tmp1 = ad_read(mss, 25); /* Original bits */ 1483 ad_write(mss, 25, ~tmp1); /* Invert all bits */ 1484 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) { 1485 int id; 1486 1487 /* It's at least CS4231 */ 1488 name = "CS4231"; 1489 mss->bd_id = MD_CS42XX; 1490 1491 /* 1492 * It could be an AD1845 or CS4231A as well. 1493 * CS4231 and AD1845 report the same revision info in I25 1494 * while the CS4231A reports different. 1495 */ 1496 1497 id = ad_read(mss, 25) & 0xe7; 1498 /* 1499 * b7-b5 = version number; 1500 * 100 : all CS4231 1501 * 101 : CS4231A 1502 * 1503 * b2-b0 = chip id; 1504 */ 1505 switch (id) { 1506 1507 case 0xa0: 1508 name = "CS4231A"; 1509 mss->bd_id = MD_CS42XX; 1510 break; 1511 1512 case 0xa2: 1513 name = "CS4232"; 1514 mss->bd_id = MD_CS42XX; 1515 break; 1516 1517 case 0xb2: 1518 /* strange: the 4231 data sheet says b4-b3 are XX 1519 * so this should be the same as 0xa2 1520 */ 1521 name = "CS4232A"; 1522 mss->bd_id = MD_CS42XX; 1523 break; 1524 1525 case 0x80: 1526 /* 1527 * It must be a CS4231 or AD1845. The register I23 1528 * of CS4231 is undefined and it appears to be read 1529 * only. AD1845 uses I23 for setting sample rate. 1530 * Assume the chip is AD1845 if I23 is changeable. 1531 */ 1532 1533 tmp = ad_read(mss, 23); 1534 1535 ad_write(mss, 23, ~tmp); 1536 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */ 1537 name = "AD1845"; 1538 mss->bd_id = MD_AD1845; 1539 } 1540 ad_write(mss, 23, tmp); /* Restore */ 1541 1542 yamaha = ymf_test(dev, mss); 1543 if (yamaha) { 1544 mss->bd_id = MD_YM0020; 1545 name = yamaha; 1546 } 1547 break; 1548 1549 case 0x83: /* CS4236 */ 1550 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */ 1551 name = "CS4236"; 1552 mss->bd_id = MD_CS42XX; 1553 break; 1554 1555 default: /* Assume CS4231 */ 1556 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);) 1557 mss->bd_id = MD_CS42XX; 1558 } 1559 } 1560 ad_write(mss, 25, tmp1); /* Restore bits */ 1561 gotit: 1562 BVDDB(printf("mss_detect() - Detected %s\n", name)); 1563 device_set_desc(dev, name); 1564 device_set_flags(dev, 1565 ((device_get_flags(dev) & ~DV_F_DEV_MASK) | 1566 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK))); 1567 return 0; 1568 no: 1569 return ENXIO; 1570 } 1571 1572 static int 1573 opti_detect(device_t dev, struct mss_info *mss) 1574 { 1575 int c; 1576 static const struct opticard { 1577 int boardid; 1578 int passwdreg; 1579 int password; 1580 int base; 1581 int indir_reg; 1582 } cards[] = { 1583 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */ 1584 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */ 1585 { 0 }, 1586 }; 1587 mss->conf_rid = 3; 1588 mss->indir_rid = 4; 1589 for (c = 0; cards[c].base; c++) { 1590 mss->optibase = cards[c].base; 1591 mss->password = cards[c].password; 1592 mss->passwdreg = cards[c].passwdreg; 1593 mss->bd_id = cards[c].boardid; 1594 1595 if (cards[c].indir_reg) 1596 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT, 1597 &mss->indir_rid, cards[c].indir_reg, 1598 cards[c].indir_reg+1, 1, RF_ACTIVE); 1599 1600 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 1601 &mss->conf_rid, mss->optibase, mss->optibase+9, 1602 9, RF_ACTIVE); 1603 1604 if (opti_read(mss, 1) != 0xff) { 1605 return 1; 1606 } else { 1607 if (mss->indir) 1608 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir); 1609 mss->indir = NULL; 1610 if (mss->conf_base) 1611 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base); 1612 mss->conf_base = NULL; 1613 } 1614 } 1615 return 0; 1616 } 1617 1618 static char * 1619 ymf_test(device_t dev, struct mss_info *mss) 1620 { 1621 static int ports[] = {0x370, 0x310, 0x538}; 1622 int p, i, j, version; 1623 static char *chipset[] = { 1624 NULL, /* 0 */ 1625 "OPL3-SA2 (YMF711)", /* 1 */ 1626 "OPL3-SA3 (YMF715)", /* 2 */ 1627 "OPL3-SA3 (YMF715)", /* 3 */ 1628 "OPL3-SAx (YMF719)", /* 4 */ 1629 "OPL3-SAx (YMF719)", /* 5 */ 1630 "OPL3-SAx (YMF719)", /* 6 */ 1631 "OPL3-SAx (YMF719)", /* 7 */ 1632 }; 1633 1634 for (p = 0; p < 3; p++) { 1635 mss->conf_rid = 1; 1636 mss->conf_base = bus_alloc_resource(dev, 1637 SYS_RES_IOPORT, 1638 &mss->conf_rid, 1639 ports[p], ports[p] + 1, 2, 1640 RF_ACTIVE); 1641 if (!mss->conf_base) return 0; 1642 1643 /* Test the index port of the config registers */ 1644 i = port_rd(mss->conf_base, 0); 1645 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF); 1646 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0; 1647 port_wr(mss->conf_base, 0, i); 1648 if (!j) { 1649 bus_release_resource(dev, SYS_RES_IOPORT, 1650 mss->conf_rid, mss->conf_base); 1651 #ifdef PC98 1652 /* PC98 need this. I don't know reason why. */ 1653 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid); 1654 #endif 1655 mss->conf_base = 0; 1656 continue; 1657 } 1658 version = conf_rd(mss, OPL3SAx_MISC) & 0x07; 1659 return chipset[version]; 1660 } 1661 return NULL; 1662 } 1663 1664 static int 1665 mss_doattach(device_t dev, struct mss_info *mss) 1666 { 1667 int pdma, rdma, flags = device_get_flags(dev); 1668 char status[SND_STATUSLEN], status2[SND_STATUSLEN]; 1669 1670 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1671 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536); 1672 if (!mss_alloc_resources(mss, dev)) goto no; 1673 mss_init(mss, dev); 1674 pdma = rman_get_start(mss->drq1); 1675 rdma = rman_get_start(mss->drq2); 1676 if (flags & DV_F_TRUE_MSS) { 1677 /* has IRQ/DMA registers, set IRQ and DMA addr */ 1678 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */ 1679 static char interrupt_bits[13] = 1680 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20}; 1681 #else 1682 static char interrupt_bits[12] = 1683 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20}; 1684 #endif 1685 static char pdma_bits[4] = {1, 2, -1, 3}; 1686 static char valid_rdma[4] = {1, 0, -1, 0}; 1687 char bits; 1688 1689 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1) 1690 goto no; 1691 #ifndef PC98 /* CS423[12] in PC98 don't support this. */ 1692 io_wr(mss, 0, bits | 0x40); /* config port */ 1693 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n"); 1694 #endif 1695 /* Write IRQ+DMA setup */ 1696 if (pdma_bits[pdma] == -1) goto no; 1697 bits |= pdma_bits[pdma]; 1698 if (pdma != rdma) { 1699 if (rdma == valid_rdma[pdma]) bits |= 4; 1700 else { 1701 printf("invalid dual dma config %d:%d\n", pdma, rdma); 1702 goto no; 1703 } 1704 } 1705 io_wr(mss, 0, bits); 1706 printf("drq/irq conf %x\n", io_rd(mss, 0)); 1707 } 1708 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss); 1709 switch (mss->bd_id) { 1710 case MD_OPTI931: 1711 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, opti931_intr, mss, &mss->ih); 1712 break; 1713 default: 1714 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, mss_intr, mss, &mss->ih); 1715 } 1716 if (pdma == rdma) 1717 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX); 1718 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1719 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT, 1720 /*highaddr*/BUS_SPACE_MAXADDR, 1721 /*filter*/NULL, /*filterarg*/NULL, 1722 /*maxsize*/mss->bufsize, /*nsegments*/1, 1723 /*maxsegz*/0x3ffff, 1724 /*flags*/0, &mss->parent_dmat) != 0) { 1725 device_printf(dev, "unable to create dma tag\n"); 1726 goto no; 1727 } 1728 1729 if (pdma != rdma) 1730 snprintf(status2, SND_STATUSLEN, ":%d", rdma); 1731 else 1732 status2[0] = '\0'; 1733 1734 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u", 1735 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize); 1736 1737 if (pcm_register(dev, mss, 1, 1)) goto no; 1738 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss); 1739 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss); 1740 pcm_setstatus(dev, status); 1741 1742 return 0; 1743 no: 1744 mss_release_resources(mss, dev); 1745 return ENXIO; 1746 } 1747 1748 static int 1749 mss_detach(device_t dev) 1750 { 1751 int r; 1752 struct mss_info *mss; 1753 1754 r = pcm_unregister(dev); 1755 if (r) 1756 return r; 1757 1758 mss = pcm_getdevinfo(dev); 1759 mss_release_resources(mss, dev); 1760 1761 return 0; 1762 } 1763 1764 static int 1765 mss_attach(device_t dev) 1766 { 1767 struct mss_info *mss; 1768 int flags = device_get_flags(dev); 1769 1770 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1771 if (!mss) return ENXIO; 1772 1773 mss->io_rid = 0; 1774 mss->conf_rid = -1; 1775 mss->irq_rid = 0; 1776 mss->drq1_rid = 0; 1777 mss->drq2_rid = -1; 1778 if (flags & DV_F_DUAL_DMA) { 1779 bus_set_resource(dev, SYS_RES_DRQ, 1, 1780 flags & DV_F_DRQ_MASK, 1); 1781 mss->drq2_rid = 1; 1782 } 1783 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT; 1784 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss); 1785 return mss_doattach(dev, mss); 1786 } 1787 1788 /* 1789 * mss_resume() is the code to allow a laptop to resume using the sound 1790 * card. 1791 * 1792 * This routine re-sets the state of the board to the state before going 1793 * to sleep. According to the yamaha docs this is the right thing to do, 1794 * but getting DMA restarted appears to be a bit of a trick, so the device 1795 * has to be closed and re-opened to be re-used, but there is no skipping 1796 * problem, and volume, bass/treble and most other things are restored 1797 * properly. 1798 * 1799 */ 1800 1801 static int 1802 mss_resume(device_t dev) 1803 { 1804 /* 1805 * Restore the state taken below. 1806 */ 1807 struct mss_info *mss; 1808 int i; 1809 1810 mss = pcm_getdevinfo(dev); 1811 1812 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) { 1813 /* This works on a Toshiba Libretto 100CT. */ 1814 for (i = 0; i < MSS_INDEXED_REGS; i++) 1815 ad_write(mss, i, mss->mss_indexed_regs[i]); 1816 for (i = 0; i < OPL_INDEXED_REGS; i++) 1817 conf_wr(mss, i, mss->opl_indexed_regs[i]); 1818 mss_intr(mss); 1819 } 1820 1821 if (mss->bd_id == MD_CS423X) { 1822 /* Needed on IBM Thinkpad 600E */ 1823 chn_setformat(mss->pch.channel, mss->pch.channel->format); 1824 chn_setspeed(mss->pch.channel, mss->pch.channel->speed); 1825 } 1826 1827 return 0; 1828 1829 } 1830 1831 /* 1832 * mss_suspend() is the code that gets called right before a laptop 1833 * suspends. 1834 * 1835 * This code saves the state of the sound card right before shutdown 1836 * so it can be restored above. 1837 * 1838 */ 1839 1840 static int 1841 mss_suspend(device_t dev) 1842 { 1843 int i; 1844 struct mss_info *mss; 1845 1846 mss = pcm_getdevinfo(dev); 1847 1848 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) 1849 { 1850 /* this stops playback. */ 1851 conf_wr(mss, 0x12, 0x0c); 1852 for(i = 0; i < MSS_INDEXED_REGS; i++) 1853 mss->mss_indexed_regs[i] = ad_read(mss, i); 1854 for(i = 0; i < OPL_INDEXED_REGS; i++) 1855 mss->opl_indexed_regs[i] = conf_rd(mss, i); 1856 mss->opl_indexed_regs[0x12] = 0x0; 1857 } 1858 return 0; 1859 } 1860 1861 static device_method_t mss_methods[] = { 1862 /* Device interface */ 1863 DEVMETHOD(device_probe, mss_probe), 1864 DEVMETHOD(device_attach, mss_attach), 1865 DEVMETHOD(device_detach, mss_detach), 1866 DEVMETHOD(device_suspend, mss_suspend), 1867 DEVMETHOD(device_resume, mss_resume), 1868 1869 { 0, 0 } 1870 }; 1871 1872 static driver_t mss_driver = { 1873 "pcm", 1874 mss_methods, 1875 PCM_SOFTC_SIZE, 1876 }; 1877 1878 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0); 1879 DRIVER_MODULE(snd_mss, acpi, mss_driver, pcm_devclass, 0, 0); 1880 MODULE_DEPEND(snd_mss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1881 MODULE_VERSION(snd_mss, 1); 1882 1883 static int 1884 azt2320_mss_mode(struct mss_info *mss, device_t dev) 1885 { 1886 struct resource *sbport; 1887 int i, ret, rid; 1888 1889 rid = 0; 1890 ret = -1; 1891 sbport = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1892 0, ~0, 1, RF_ACTIVE); 1893 if (sbport) { 1894 for (i = 0; i < 1000; i++) { 1895 if ((port_rd(sbport, SBDSP_STATUS) & 0x80)) 1896 DELAY((i > 100) ? 1000 : 10); 1897 else { 1898 port_wr(sbport, SBDSP_CMD, 0x09); 1899 break; 1900 } 1901 } 1902 for (i = 0; i < 1000; i++) { 1903 if ((port_rd(sbport, SBDSP_STATUS) & 0x80)) 1904 DELAY((i > 100) ? 1000 : 10); 1905 else { 1906 port_wr(sbport, SBDSP_CMD, 0x00); 1907 ret = 0; 1908 break; 1909 } 1910 } 1911 DELAY(1000); 1912 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport); 1913 } 1914 return ret; 1915 } 1916 1917 static struct isa_pnp_id pnpmss_ids[] = { 1918 {0x0000630e, "CS423x"}, /* CSC0000 */ 1919 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */ 1920 {0x01000000, "CMI8330"}, /* @@@0001 */ 1921 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */ 1922 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */ 1923 {0x1093143e, "OPTi931"}, /* OPT9310 */ 1924 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */ 1925 {0x0000143e, "OPTi924"}, /* OPT0924 */ 1926 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */ 1927 {0x01005407, "Aztech 2320"}, /* AZT0001 */ 1928 #if 0 1929 {0x0000561e, "GusPnP"}, /* GRV0000 */ 1930 #endif 1931 {0}, 1932 }; 1933 1934 static int 1935 pnpmss_probe(device_t dev) 1936 { 1937 u_int32_t lid, vid; 1938 1939 lid = isa_get_logicalid(dev); 1940 vid = isa_get_vendorid(dev); 1941 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */ 1942 return ENXIO; 1943 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids); 1944 } 1945 1946 static int 1947 pnpmss_attach(device_t dev) 1948 { 1949 struct mss_info *mss; 1950 1951 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1952 if (!mss) 1953 return ENXIO; 1954 1955 mss->io_rid = 0; 1956 mss->conf_rid = -1; 1957 mss->irq_rid = 0; 1958 mss->drq1_rid = 0; 1959 mss->drq2_rid = 1; 1960 mss->bd_id = MD_CS42XX; 1961 1962 switch (isa_get_logicalid(dev)) { 1963 case 0x0000630e: /* CSC0000 */ 1964 case 0x0001630e: /* CSC0100 */ 1965 mss->bd_flags |= BD_F_MSS_OFFSET; 1966 mss->bd_id = MD_CS423X; 1967 break; 1968 1969 case 0x2100a865: /* YHM0021 */ 1970 mss->io_rid = 1; 1971 mss->conf_rid = 4; 1972 mss->bd_id = MD_YM0020; 1973 break; 1974 1975 case 0x1110d315: /* ENS1011 */ 1976 mss->io_rid = 1; 1977 mss->bd_id = MD_VIVO; 1978 break; 1979 1980 case 0x1093143e: /* OPT9310 */ 1981 mss->bd_flags |= BD_F_MSS_OFFSET; 1982 mss->conf_rid = 3; 1983 mss->bd_id = MD_OPTI931; 1984 break; 1985 1986 case 0x5092143e: /* OPT9250 XXX guess */ 1987 mss->io_rid = 1; 1988 mss->conf_rid = 3; 1989 mss->bd_id = MD_OPTI925; 1990 break; 1991 1992 case 0x0000143e: /* OPT0924 */ 1993 mss->password = 0xe5; 1994 mss->passwdreg = 3; 1995 mss->optibase = 0xf0c; 1996 mss->io_rid = 2; 1997 mss->conf_rid = 3; 1998 mss->bd_id = MD_OPTI924; 1999 mss->bd_flags |= BD_F_924PNP; 2000 if(opti_init(dev, mss) != 0) 2001 return ENXIO; 2002 break; 2003 2004 case 0x1022b839: /* NMX2210 */ 2005 mss->io_rid = 1; 2006 break; 2007 2008 case 0x01005407: /* AZT0001 */ 2009 /* put into MSS mode first (snatched from NetBSD) */ 2010 if (azt2320_mss_mode(mss, dev) == -1) 2011 return ENXIO; 2012 2013 mss->bd_flags |= BD_F_MSS_OFFSET; 2014 mss->io_rid = 2; 2015 break; 2016 2017 #if 0 2018 case 0x0000561e: /* GRV0000 */ 2019 mss->bd_flags |= BD_F_MSS_OFFSET; 2020 mss->io_rid = 2; 2021 mss->conf_rid = 1; 2022 mss->drq1_rid = 1; 2023 mss->drq2_rid = 0; 2024 mss->bd_id = MD_GUSPNP; 2025 break; 2026 #endif 2027 case 0x01000000: /* @@@0001 */ 2028 mss->drq2_rid = -1; 2029 break; 2030 2031 /* Unknown MSS default. We could let the CSC0000 stuff match too */ 2032 default: 2033 mss->bd_flags |= BD_F_MSS_OFFSET; 2034 break; 2035 } 2036 return mss_doattach(dev, mss); 2037 } 2038 2039 static int 2040 opti_init(device_t dev, struct mss_info *mss) 2041 { 2042 int flags = device_get_flags(dev); 2043 int basebits = 0; 2044 2045 if (!mss->conf_base) { 2046 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 2047 mss->optibase, 0x9); 2048 2049 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2050 &mss->conf_rid, mss->optibase, mss->optibase+0x9, 2051 0x9, RF_ACTIVE); 2052 } 2053 2054 if (!mss->conf_base) 2055 return ENXIO; 2056 2057 if (!mss->io_base) 2058 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2059 &mss->io_rid, 0, ~0, 8, RF_ACTIVE); 2060 2061 if (!mss->io_base) /* No hint specified, use 0x530 */ 2062 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2063 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE); 2064 2065 if (!mss->io_base) 2066 return ENXIO; 2067 2068 switch (rman_get_start(mss->io_base)) { 2069 case 0x530: 2070 basebits = 0x0; 2071 break; 2072 case 0xe80: 2073 basebits = 0x10; 2074 break; 2075 case 0xf40: 2076 basebits = 0x20; 2077 break; 2078 case 0x604: 2079 basebits = 0x30; 2080 break; 2081 default: 2082 printf("opti_init: invalid MSS base address!\n"); 2083 return ENXIO; 2084 } 2085 2086 2087 switch (mss->bd_id) { 2088 case MD_OPTI924: 2089 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */ 2090 opti_write(mss, 2, 0x00); /* Disable CD */ 2091 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */ 2092 opti_write(mss, 4, 0xf0); 2093 opti_write(mss, 5, 0x00); 2094 opti_write(mss, 6, 0x02); /* MPU stuff */ 2095 break; 2096 2097 case MD_OPTI930: 2098 opti_write(mss, 1, 0x00 | basebits); 2099 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */ 2100 opti_write(mss, 4, 0x52); /* Empty FIFO */ 2101 opti_write(mss, 5, 0x3c); /* Mode 2 */ 2102 opti_write(mss, 6, 0x02); /* Enable MSS */ 2103 break; 2104 } 2105 2106 if (mss->bd_flags & BD_F_924PNP) { 2107 u_int32_t irq = isa_get_irq(dev); 2108 u_int32_t drq = isa_get_drq(dev); 2109 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1); 2110 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1); 2111 if (flags & DV_F_DUAL_DMA) { 2112 bus_set_resource(dev, SYS_RES_DRQ, 1, 2113 flags & DV_F_DRQ_MASK, 1); 2114 mss->drq2_rid = 1; 2115 } 2116 } 2117 2118 /* OPTixxx has I/DRQ registers */ 2119 2120 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS); 2121 2122 return 0; 2123 } 2124 2125 static void 2126 opti_write(struct mss_info *mss, u_char reg, u_char val) 2127 { 2128 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2129 2130 switch(mss->bd_id) { 2131 case MD_OPTI924: 2132 if (reg > 7) { /* Indirect register */ 2133 port_wr(mss->conf_base, mss->passwdreg, reg); 2134 port_wr(mss->conf_base, mss->passwdreg, 2135 mss->password); 2136 port_wr(mss->conf_base, 9, val); 2137 return; 2138 } 2139 port_wr(mss->conf_base, reg, val); 2140 break; 2141 2142 case MD_OPTI930: 2143 port_wr(mss->indir, 0, reg); 2144 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2145 port_wr(mss->indir, 1, val); 2146 break; 2147 } 2148 } 2149 2150 u_char 2151 opti_read(struct mss_info *mss, u_char reg) 2152 { 2153 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2154 2155 switch(mss->bd_id) { 2156 case MD_OPTI924: 2157 if (reg > 7) { /* Indirect register */ 2158 port_wr(mss->conf_base, mss->passwdreg, reg); 2159 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2160 return(port_rd(mss->conf_base, 9)); 2161 } 2162 return(port_rd(mss->conf_base, reg)); 2163 break; 2164 2165 case MD_OPTI930: 2166 port_wr(mss->indir, 0, reg); 2167 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2168 return port_rd(mss->indir, 1); 2169 break; 2170 } 2171 return -1; 2172 } 2173 2174 static device_method_t pnpmss_methods[] = { 2175 /* Device interface */ 2176 DEVMETHOD(device_probe, pnpmss_probe), 2177 DEVMETHOD(device_attach, pnpmss_attach), 2178 DEVMETHOD(device_detach, mss_detach), 2179 DEVMETHOD(device_suspend, mss_suspend), 2180 DEVMETHOD(device_resume, mss_resume), 2181 2182 { 0, 0 } 2183 }; 2184 2185 static driver_t pnpmss_driver = { 2186 "pcm", 2187 pnpmss_methods, 2188 PCM_SOFTC_SIZE, 2189 }; 2190 2191 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0); 2192 MODULE_DEPEND(snd_pnpmss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 2193 MODULE_VERSION(snd_pnpmss, 1); 2194 2195 static int 2196 guspcm_probe(device_t dev) 2197 { 2198 struct sndcard_func *func; 2199 2200 func = device_get_ivars(dev); 2201 if (func == NULL || func->func != SCF_PCM) 2202 return ENXIO; 2203 2204 device_set_desc(dev, "GUS CS4231"); 2205 return 0; 2206 } 2207 2208 static int 2209 guspcm_attach(device_t dev) 2210 { 2211 device_t parent = device_get_parent(dev); 2212 struct mss_info *mss; 2213 int base, flags; 2214 unsigned char ctl; 2215 2216 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 2217 if (mss == NULL) 2218 return ENOMEM; 2219 2220 mss->bd_flags = BD_F_MSS_OFFSET; 2221 mss->io_rid = 2; 2222 mss->conf_rid = 1; 2223 mss->irq_rid = 0; 2224 mss->drq1_rid = 1; 2225 mss->drq2_rid = -1; 2226 2227 if (isa_get_logicalid(parent) == 0) 2228 mss->bd_id = MD_GUSMAX; 2229 else { 2230 mss->bd_id = MD_GUSPNP; 2231 mss->drq2_rid = 0; 2232 goto skip_setup; 2233 } 2234 2235 flags = device_get_flags(parent); 2236 if (flags & DV_F_DUAL_DMA) 2237 mss->drq2_rid = 0; 2238 2239 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 2240 0, ~0, 8, RF_ACTIVE); 2241 2242 if (mss->conf_base == NULL) { 2243 mss_release_resources(mss, dev); 2244 return ENXIO; 2245 } 2246 2247 base = isa_get_port(parent); 2248 2249 ctl = 0x40; /* CS4231 enable */ 2250 if (isa_get_drq(dev) > 3) 2251 ctl |= 0x10; /* 16-bit dma channel 1 */ 2252 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3) 2253 ctl |= 0x20; /* 16-bit dma channel 2 */ 2254 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */ 2255 port_wr(mss->conf_base, 6, ctl); 2256 2257 skip_setup: 2258 return mss_doattach(dev, mss); 2259 } 2260 2261 static device_method_t guspcm_methods[] = { 2262 DEVMETHOD(device_probe, guspcm_probe), 2263 DEVMETHOD(device_attach, guspcm_attach), 2264 DEVMETHOD(device_detach, mss_detach), 2265 2266 { 0, 0 } 2267 }; 2268 2269 static driver_t guspcm_driver = { 2270 "pcm", 2271 guspcm_methods, 2272 PCM_SOFTC_SIZE, 2273 }; 2274 2275 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0); 2276 MODULE_DEPEND(snd_guspcm, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 2277 MODULE_VERSION(snd_guspcm, 1); 2278 2279
Cache object: 4aff71ffe2406c39d1b7804f56467b51
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