FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/isa/mss.c
1 /*-
2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
4 * Copyright Luigi Rizzo, 1997,1998
5 * Copyright by Hannu Savolainen 1994, 1995
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <dev/sound/pcm/sound.h>
31
32 SND_DECLARE_FILE("$FreeBSD: releng/6.1/sys/dev/sound/isa/mss.c 157487 2006-04-04 17:30:59Z ariff $");
33
34 /* board-specific include files */
35 #include <dev/sound/isa/mss.h>
36 #include <dev/sound/isa/sb.h>
37 #include <dev/sound/chip.h>
38
39 #include <isa/isavar.h>
40
41 #include "mixer_if.h"
42
43 #define MSS_DEFAULT_BUFSZ (4096)
44 #define MSS_INDEXED_REGS 0x20
45 #define OPL_INDEXED_REGS 0x19
46
47 struct mss_info;
48
49 struct mss_chinfo {
50 struct mss_info *parent;
51 struct pcm_channel *channel;
52 struct snd_dbuf *buffer;
53 int dir;
54 u_int32_t fmt, blksz;
55 };
56
57 struct mss_info {
58 struct resource *io_base; /* primary I/O address for the board */
59 int io_rid;
60 struct resource *conf_base; /* and the opti931 also has a config space */
61 int conf_rid;
62 struct resource *irq;
63 int irq_rid;
64 struct resource *drq1; /* play */
65 int drq1_rid;
66 struct resource *drq2; /* rec */
67 int drq2_rid;
68 void *ih;
69 bus_dma_tag_t parent_dmat;
70 struct mtx *lock;
71
72 char mss_indexed_regs[MSS_INDEXED_REGS];
73 char opl_indexed_regs[OPL_INDEXED_REGS];
74 int bd_id; /* used to hold board-id info, eg. sb version,
75 * mss codec type, etc. etc.
76 */
77 int opti_offset; /* offset from config_base for opti931 */
78 u_long bd_flags; /* board-specific flags */
79 int optibase; /* base address for OPTi9xx config */
80 struct resource *indir; /* Indirect register index address */
81 int indir_rid;
82 int password; /* password for opti9xx cards */
83 int passwdreg; /* password register */
84 unsigned int bufsize;
85 struct mss_chinfo pch, rch;
86 };
87
88 static int mss_probe(device_t dev);
89 static int mss_attach(device_t dev);
90
91 static driver_intr_t mss_intr;
92
93 /* prototypes for local functions */
94 static int mss_detect(device_t dev, struct mss_info *mss);
95 #ifndef PC98
96 static int opti_detect(device_t dev, struct mss_info *mss);
97 #endif
98 static char *ymf_test(device_t dev, struct mss_info *mss);
99 static void ad_unmute(struct mss_info *mss);
100
101 /* mixer set funcs */
102 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
103 static int mss_set_recsrc(struct mss_info *mss, int mask);
104
105 /* io funcs */
106 static int ad_wait_init(struct mss_info *mss, int x);
107 static int ad_read(struct mss_info *mss, int reg);
108 static void ad_write(struct mss_info *mss, int reg, u_char data);
109 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
110 static void ad_enter_MCE(struct mss_info *mss);
111 static void ad_leave_MCE(struct mss_info *mss);
112
113 /* OPTi-specific functions */
114 static void opti_write(struct mss_info *mss, u_char reg,
115 u_char data);
116 #ifndef PC98
117 static u_char opti_read(struct mss_info *mss, u_char reg);
118 #endif
119 static int opti_init(device_t dev, struct mss_info *mss);
120
121 /* io primitives */
122 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
123 static u_char conf_rd(struct mss_info *mss, u_char reg);
124
125 static int pnpmss_probe(device_t dev);
126 static int pnpmss_attach(device_t dev);
127
128 static driver_intr_t opti931_intr;
129
130 static u_int32_t mss_fmt[] = {
131 AFMT_U8,
132 AFMT_STEREO | AFMT_U8,
133 AFMT_S16_LE,
134 AFMT_STEREO | AFMT_S16_LE,
135 AFMT_MU_LAW,
136 AFMT_STEREO | AFMT_MU_LAW,
137 AFMT_A_LAW,
138 AFMT_STEREO | AFMT_A_LAW,
139 0
140 };
141 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
142
143 static u_int32_t guspnp_fmt[] = {
144 AFMT_U8,
145 AFMT_STEREO | AFMT_U8,
146 AFMT_S16_LE,
147 AFMT_STEREO | AFMT_S16_LE,
148 AFMT_A_LAW,
149 AFMT_STEREO | AFMT_A_LAW,
150 0
151 };
152 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
153
154 static u_int32_t opti931_fmt[] = {
155 AFMT_U8,
156 AFMT_STEREO | AFMT_U8,
157 AFMT_S16_LE,
158 AFMT_STEREO | AFMT_S16_LE,
159 0
160 };
161 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
162
163 #define MD_AD1848 0x91
164 #define MD_AD1845 0x92
165 #define MD_CS42XX 0xA1
166 #define MD_CS423X 0xA2
167 #define MD_OPTI930 0xB0
168 #define MD_OPTI931 0xB1
169 #define MD_OPTI925 0xB2
170 #define MD_OPTI924 0xB3
171 #define MD_GUSPNP 0xB8
172 #define MD_GUSMAX 0xB9
173 #define MD_YM0020 0xC1
174 #define MD_VIVO 0xD1
175
176 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
177
178 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
179
180 static void
181 mss_lock(struct mss_info *mss)
182 {
183 snd_mtxlock(mss->lock);
184 }
185
186 static void
187 mss_unlock(struct mss_info *mss)
188 {
189 snd_mtxunlock(mss->lock);
190 }
191
192 static int
193 port_rd(struct resource *port, int off)
194 {
195 if (port)
196 return bus_space_read_1(rman_get_bustag(port),
197 rman_get_bushandle(port),
198 off);
199 else
200 return -1;
201 }
202
203 static void
204 port_wr(struct resource *port, int off, u_int8_t data)
205 {
206 if (port)
207 bus_space_write_1(rman_get_bustag(port),
208 rman_get_bushandle(port),
209 off, data);
210 }
211
212 static int
213 io_rd(struct mss_info *mss, int reg)
214 {
215 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
216 return port_rd(mss->io_base, reg);
217 }
218
219 static void
220 io_wr(struct mss_info *mss, int reg, u_int8_t data)
221 {
222 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
223 port_wr(mss->io_base, reg, data);
224 }
225
226 static void
227 conf_wr(struct mss_info *mss, u_char reg, u_char value)
228 {
229 port_wr(mss->conf_base, 0, reg);
230 port_wr(mss->conf_base, 1, value);
231 }
232
233 static u_char
234 conf_rd(struct mss_info *mss, u_char reg)
235 {
236 port_wr(mss->conf_base, 0, reg);
237 return port_rd(mss->conf_base, 1);
238 }
239
240 static void
241 opti_wr(struct mss_info *mss, u_char reg, u_char value)
242 {
243 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
244 port_wr(mss->conf_base, mss->opti_offset + 1, value);
245 }
246
247 static u_char
248 opti_rd(struct mss_info *mss, u_char reg)
249 {
250 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
251 return port_rd(mss->conf_base, mss->opti_offset + 1);
252 }
253
254 static void
255 gus_wr(struct mss_info *mss, u_char reg, u_char value)
256 {
257 port_wr(mss->conf_base, 3, reg);
258 port_wr(mss->conf_base, 5, value);
259 }
260
261 static u_char
262 gus_rd(struct mss_info *mss, u_char reg)
263 {
264 port_wr(mss->conf_base, 3, reg);
265 return port_rd(mss->conf_base, 5);
266 }
267
268 static void
269 mss_release_resources(struct mss_info *mss, device_t dev)
270 {
271 if (mss->irq) {
272 if (mss->ih)
273 bus_teardown_intr(dev, mss->irq, mss->ih);
274 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
275 mss->irq);
276 mss->irq = 0;
277 }
278 if (mss->drq2) {
279 if (mss->drq2 != mss->drq1) {
280 isa_dma_release(rman_get_start(mss->drq2));
281 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
282 mss->drq2);
283 }
284 mss->drq2 = 0;
285 }
286 if (mss->drq1) {
287 isa_dma_release(rman_get_start(mss->drq1));
288 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
289 mss->drq1);
290 mss->drq1 = 0;
291 }
292 if (mss->io_base) {
293 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
294 mss->io_base);
295 mss->io_base = 0;
296 }
297 if (mss->conf_base) {
298 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
299 mss->conf_base);
300 mss->conf_base = 0;
301 }
302 if (mss->indir) {
303 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
304 mss->indir);
305 mss->indir = 0;
306 }
307 if (mss->parent_dmat) {
308 bus_dma_tag_destroy(mss->parent_dmat);
309 mss->parent_dmat = 0;
310 }
311 if (mss->lock) snd_mtxfree(mss->lock);
312
313 free(mss, M_DEVBUF);
314 }
315
316 static int
317 mss_alloc_resources(struct mss_info *mss, device_t dev)
318 {
319 int pdma, rdma, ok = 1;
320 if (!mss->io_base)
321 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
322 &mss->io_rid, RF_ACTIVE);
323 if (!mss->irq)
324 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
325 &mss->irq_rid, RF_ACTIVE);
326 if (!mss->drq1)
327 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
328 &mss->drq1_rid,
329 RF_ACTIVE);
330 if (mss->conf_rid >= 0 && !mss->conf_base)
331 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
332 &mss->conf_rid,
333 RF_ACTIVE);
334 if (mss->drq2_rid >= 0 && !mss->drq2)
335 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
336 &mss->drq2_rid,
337 RF_ACTIVE);
338
339 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
340 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
341 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
342
343 if (ok) {
344 pdma = rman_get_start(mss->drq1);
345 isa_dma_acquire(pdma);
346 isa_dmainit(pdma, mss->bufsize);
347 mss->bd_flags &= ~BD_F_DUPLEX;
348 if (mss->drq2) {
349 rdma = rman_get_start(mss->drq2);
350 isa_dma_acquire(rdma);
351 isa_dmainit(rdma, mss->bufsize);
352 mss->bd_flags |= BD_F_DUPLEX;
353 } else mss->drq2 = mss->drq1;
354 }
355 return ok;
356 }
357
358 /*
359 * The various mixers use a variety of bitmasks etc. The Voxware
360 * driver had a very nice technique to describe a mixer and interface
361 * to it. A table defines, for each channel, which register, bits,
362 * offset, polarity to use. This procedure creates the new value
363 * using the table and the old value.
364 */
365
366 static void
367 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
368 {
369 u_char mask;
370 int shift;
371
372 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
373 "r %d p %d bit %d off %d\n",
374 dev, chn, newval, *regval,
375 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
376 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
377
378 if ( (*t)[dev][chn].polarity == 1) /* reverse */
379 newval = 100 - newval ;
380
381 mask = (1 << (*t)[dev][chn].nbits) - 1;
382 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
383 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
384
385 *regval &= ~(mask << shift); /* Filter out the previous value */
386 *regval |= (newval & mask) << shift; /* Set the new value */
387 }
388
389 /* -------------------------------------------------------------------- */
390 /* only one source can be set... */
391 static int
392 mss_set_recsrc(struct mss_info *mss, int mask)
393 {
394 u_char recdev;
395
396 switch (mask) {
397 case SOUND_MASK_LINE:
398 case SOUND_MASK_LINE3:
399 recdev = 0;
400 break;
401
402 case SOUND_MASK_CD:
403 case SOUND_MASK_LINE1:
404 recdev = 0x40;
405 break;
406
407 case SOUND_MASK_IMIX:
408 recdev = 0xc0;
409 break;
410
411 case SOUND_MASK_MIC:
412 default:
413 mask = SOUND_MASK_MIC;
414 recdev = 0x80;
415 }
416 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
417 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
418 return mask;
419 }
420
421 /* there are differences in the mixer depending on the actual sound card. */
422 static int
423 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
424 {
425 int regoffs;
426 mixer_tab *mix_d;
427 u_char old, val;
428
429 switch (mss->bd_id) {
430 case MD_OPTI931:
431 mix_d = &opti931_devices;
432 break;
433 case MD_OPTI930:
434 mix_d = &opti930_devices;
435 break;
436 default:
437 mix_d = &mix_devices;
438 }
439
440 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
441 DEB(printf("nbits = 0 for dev %d\n", dev));
442 return -1;
443 }
444
445 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
446
447 /* Set the left channel */
448
449 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
450 old = val = ad_read(mss, regoffs);
451 /* if volume is 0, mute chan. Otherwise, unmute. */
452 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
453 change_bits(mix_d, &val, dev, LEFT_CHN, left);
454 ad_write(mss, regoffs, val);
455
456 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
457 dev, regoffs, old, val));
458
459 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
460 /* Set the right channel */
461 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
462 old = val = ad_read(mss, regoffs);
463 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
464 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
465 ad_write(mss, regoffs, val);
466
467 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
468 dev, regoffs, old, val));
469 }
470 return 0; /* success */
471 }
472
473 /* -------------------------------------------------------------------- */
474
475 static int
476 mssmix_init(struct snd_mixer *m)
477 {
478 struct mss_info *mss = mix_getdevinfo(m);
479
480 mix_setdevs(m, MODE2_MIXER_DEVICES);
481 mix_setrecdevs(m, MSS_REC_DEVICES);
482 switch(mss->bd_id) {
483 case MD_OPTI930:
484 mix_setdevs(m, OPTI930_MIXER_DEVICES);
485 break;
486
487 case MD_OPTI931:
488 mix_setdevs(m, OPTI931_MIXER_DEVICES);
489 mss_lock(mss);
490 ad_write(mss, 20, 0x88);
491 ad_write(mss, 21, 0x88);
492 mss_unlock(mss);
493 break;
494
495 case MD_AD1848:
496 mix_setdevs(m, MODE1_MIXER_DEVICES);
497 break;
498
499 case MD_GUSPNP:
500 case MD_GUSMAX:
501 /* this is only necessary in mode 3 ... */
502 mss_lock(mss);
503 ad_write(mss, 22, 0x88);
504 ad_write(mss, 23, 0x88);
505 mss_unlock(mss);
506 break;
507 }
508 return 0;
509 }
510
511 static int
512 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
513 {
514 struct mss_info *mss = mix_getdevinfo(m);
515
516 mss_lock(mss);
517 mss_mixer_set(mss, dev, left, right);
518 mss_unlock(mss);
519
520 return left | (right << 8);
521 }
522
523 static int
524 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
525 {
526 struct mss_info *mss = mix_getdevinfo(m);
527
528 mss_lock(mss);
529 src = mss_set_recsrc(mss, src);
530 mss_unlock(mss);
531 return src;
532 }
533
534 static kobj_method_t mssmix_mixer_methods[] = {
535 KOBJMETHOD(mixer_init, mssmix_init),
536 KOBJMETHOD(mixer_set, mssmix_set),
537 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
538 { 0, 0 }
539 };
540 MIXER_DECLARE(mssmix_mixer);
541
542 /* -------------------------------------------------------------------- */
543
544 static int
545 ymmix_init(struct snd_mixer *m)
546 {
547 struct mss_info *mss = mix_getdevinfo(m);
548
549 mssmix_init(m);
550 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
551 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
552 /* Set master volume */
553 mss_lock(mss);
554 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
555 conf_wr(mss, OPL3SAx_VOLUMER, 7);
556 mss_unlock(mss);
557
558 return 0;
559 }
560
561 static int
562 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
563 {
564 struct mss_info *mss = mix_getdevinfo(m);
565 int t, l, r;
566
567 mss_lock(mss);
568 switch (dev) {
569 case SOUND_MIXER_VOLUME:
570 if (left) t = 15 - (left * 15) / 100;
571 else t = 0x80; /* mute */
572 conf_wr(mss, OPL3SAx_VOLUMEL, t);
573 if (right) t = 15 - (right * 15) / 100;
574 else t = 0x80; /* mute */
575 conf_wr(mss, OPL3SAx_VOLUMER, t);
576 break;
577
578 case SOUND_MIXER_MIC:
579 t = left;
580 if (left) t = 31 - (left * 31) / 100;
581 else t = 0x80; /* mute */
582 conf_wr(mss, OPL3SAx_MIC, t);
583 break;
584
585 case SOUND_MIXER_BASS:
586 l = (left * 7) / 100;
587 r = (right * 7) / 100;
588 t = (r << 4) | l;
589 conf_wr(mss, OPL3SAx_BASS, t);
590 break;
591
592 case SOUND_MIXER_TREBLE:
593 l = (left * 7) / 100;
594 r = (right * 7) / 100;
595 t = (r << 4) | l;
596 conf_wr(mss, OPL3SAx_TREBLE, t);
597 break;
598
599 default:
600 mss_mixer_set(mss, dev, left, right);
601 }
602 mss_unlock(mss);
603
604 return left | (right << 8);
605 }
606
607 static int
608 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
609 {
610 struct mss_info *mss = mix_getdevinfo(m);
611 mss_lock(mss);
612 src = mss_set_recsrc(mss, src);
613 mss_unlock(mss);
614 return src;
615 }
616
617 static kobj_method_t ymmix_mixer_methods[] = {
618 KOBJMETHOD(mixer_init, ymmix_init),
619 KOBJMETHOD(mixer_set, ymmix_set),
620 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
621 { 0, 0 }
622 };
623 MIXER_DECLARE(ymmix_mixer);
624
625 /* -------------------------------------------------------------------- */
626 /*
627 * XXX This might be better off in the gusc driver.
628 */
629 static void
630 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
631 {
632 static const unsigned char irq_bits[16] = {
633 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
634 };
635 static const unsigned char dma_bits[8] = {
636 0, 1, 0, 2, 0, 3, 4, 5
637 };
638 device_t parent = device_get_parent(dev);
639 unsigned char irqctl, dmactl;
640 int s;
641
642 s = splhigh();
643
644 port_wr(alt, 0x0f, 0x05);
645 port_wr(alt, 0x00, 0x0c);
646 port_wr(alt, 0x0b, 0x00);
647
648 port_wr(alt, 0x0f, 0x00);
649
650 irqctl = irq_bits[isa_get_irq(parent)];
651 /* Share the IRQ with the MIDI driver. */
652 irqctl |= 0x40;
653 dmactl = dma_bits[isa_get_drq(parent)];
654 if (device_get_flags(parent) & DV_F_DUAL_DMA)
655 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
656 << 3;
657
658 /*
659 * Set the DMA and IRQ control latches.
660 */
661 port_wr(alt, 0x00, 0x0c);
662 port_wr(alt, 0x0b, dmactl | 0x80);
663 port_wr(alt, 0x00, 0x4c);
664 port_wr(alt, 0x0b, irqctl);
665
666 port_wr(alt, 0x00, 0x0c);
667 port_wr(alt, 0x0b, dmactl);
668 port_wr(alt, 0x00, 0x4c);
669 port_wr(alt, 0x0b, irqctl);
670
671 port_wr(mss->conf_base, 2, 0);
672 port_wr(alt, 0x00, 0x0c);
673 port_wr(mss->conf_base, 2, 0);
674
675 splx(s);
676 }
677
678 static int
679 mss_init(struct mss_info *mss, device_t dev)
680 {
681 u_char r6, r9;
682 struct resource *alt;
683 int rid, tmp;
684
685 mss->bd_flags |= BD_F_MCE_BIT;
686 switch(mss->bd_id) {
687 case MD_OPTI931:
688 /*
689 * The MED3931 v.1.0 allocates 3 bytes for the config
690 * space, whereas v.2.0 allocates 4 bytes. What I know
691 * for sure is that the upper two ports must be used,
692 * and they should end on a boundary of 4 bytes. So I
693 * need the following trick.
694 */
695 mss->opti_offset =
696 (rman_get_start(mss->conf_base) & ~3) + 2
697 - rman_get_start(mss->conf_base);
698 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
699 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
700 ad_write(mss, 10, 2); /* enable interrupts */
701 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
702 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
703 break;
704
705 case MD_GUSPNP:
706 case MD_GUSMAX:
707 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
708 DELAY(1000 * 30);
709 /* release reset and enable DAC */
710 gus_wr(mss, 0x4c /* _URSTI */, 3);
711 DELAY(1000 * 30);
712 /* end of reset */
713
714 rid = 0;
715 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
716 RF_ACTIVE);
717 if (alt == NULL) {
718 printf("XXX couldn't init GUS PnP/MAX\n");
719 break;
720 }
721 port_wr(alt, 0, 0xC); /* enable int and dma */
722 if (mss->bd_id == MD_GUSMAX)
723 gusmax_setup(mss, dev, alt);
724 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
725
726 /*
727 * unmute left & right line. Need to go in mode3, unmute,
728 * and back to mode 2
729 */
730 tmp = ad_read(mss, 0x0c);
731 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
732 ad_write(mss, 0x19, 0); /* unmute left */
733 ad_write(mss, 0x1b, 0); /* unmute right */
734 ad_write(mss, 0x0c, tmp); /* restore old mode */
735
736 /* send codec interrupts on irq1 and only use that one */
737 gus_wr(mss, 0x5a, 0x4f);
738
739 /* enable access to hidden regs */
740 tmp = gus_rd(mss, 0x5b /* IVERI */);
741 gus_wr(mss, 0x5b, tmp | 1);
742 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
743 break;
744
745 case MD_YM0020:
746 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
747 r6 = conf_rd(mss, OPL3SAx_DMACONF);
748 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
749 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
750 /* yamaha - set volume to max */
751 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
752 conf_wr(mss, OPL3SAx_VOLUMER, 0);
753 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
754 break;
755 }
756 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
757 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
758 ad_enter_MCE(mss);
759 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
760 ad_leave_MCE(mss);
761 ad_write(mss, 10, 2); /* int enable */
762 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
763 /* the following seem required on the CS4232 */
764 ad_unmute(mss);
765 return 0;
766 }
767
768
769 /*
770 * main irq handler for the CS423x. The OPTi931 code is
771 * a separate one.
772 * The correct way to operate for a device with multiple internal
773 * interrupt sources is to loop on the status register and ack
774 * interrupts until all interrupts are served and none are reported. At
775 * this point the IRQ line to the ISA IRQ controller should go low
776 * and be raised at the next interrupt.
777 *
778 * Since the ISA IRQ controller is sent EOI _before_ passing control
779 * to the isr, it might happen that we serve an interrupt early, in
780 * which case the status register at the next interrupt should just
781 * say that there are no more interrupts...
782 */
783
784 static void
785 mss_intr(void *arg)
786 {
787 struct mss_info *mss = arg;
788 u_char c = 0, served = 0;
789 int i;
790
791 DEB(printf("mss_intr\n"));
792 mss_lock(mss);
793 ad_read(mss, 11); /* fake read of status bits */
794
795 /* loop until there are interrupts, but no more than 10 times. */
796 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
797 /* get exact reason for full-duplex boards */
798 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
799 c &= ~served;
800 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
801 served |= 0x10;
802 mss_unlock(mss);
803 chn_intr(mss->pch.channel);
804 mss_lock(mss);
805 }
806 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
807 served |= 0x20;
808 mss_unlock(mss);
809 chn_intr(mss->rch.channel);
810 mss_lock(mss);
811 }
812 /* now ack the interrupt */
813 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
814 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
815 }
816 if (i == 10) {
817 BVDDB(printf("mss_intr: irq, but not from mss\n"));
818 } else if (served == 0) {
819 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
820 /*
821 * this should not happen... I have no idea what to do now.
822 * maybe should do a sanity check and restart dmas ?
823 */
824 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
825 }
826 mss_unlock(mss);
827 }
828
829 /*
830 * AD_WAIT_INIT waits if we are initializing the board and
831 * we cannot modify its settings
832 */
833 static int
834 ad_wait_init(struct mss_info *mss, int x)
835 {
836 int arg = x, n = 0; /* to shut up the compiler... */
837 for (; x > 0; x--)
838 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
839 else return n;
840 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
841 return n;
842 }
843
844 static int
845 ad_read(struct mss_info *mss, int reg)
846 {
847 int x;
848
849 ad_wait_init(mss, 201000);
850 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
851 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
852 x = io_rd(mss, MSS_IDATA);
853 /* printf("ad_read %d, %x\n", reg, x); */
854 return x;
855 }
856
857 static void
858 ad_write(struct mss_info *mss, int reg, u_char data)
859 {
860 int x;
861
862 /* printf("ad_write %d, %x\n", reg, data); */
863 ad_wait_init(mss, 1002000);
864 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
865 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
866 io_wr(mss, MSS_IDATA, data);
867 }
868
869 static void
870 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
871 {
872 ad_write(mss, reg+1, cnt & 0xff);
873 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
874 }
875
876 static void
877 wait_for_calibration(struct mss_info *mss)
878 {
879 int t;
880
881 /*
882 * Wait until the auto calibration process has finished.
883 *
884 * 1) Wait until the chip becomes ready (reads don't return 0x80).
885 * 2) Wait until the ACI bit of I11 gets on
886 * 3) Wait until the ACI bit of I11 gets off
887 */
888
889 t = ad_wait_init(mss, 1000000);
890 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
891
892 /*
893 * The calibration mode for chips that support it is set so that
894 * we never see ACI go on.
895 */
896 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
897 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
898 } else {
899 /*
900 * XXX This should only be enabled for cards that *really*
901 * need it. Are there any?
902 */
903 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
904 }
905 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
906 }
907
908 static void
909 ad_unmute(struct mss_info *mss)
910 {
911 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
912 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
913 }
914
915 static void
916 ad_enter_MCE(struct mss_info *mss)
917 {
918 int prev;
919
920 mss->bd_flags |= BD_F_MCE_BIT;
921 ad_wait_init(mss, 203000);
922 prev = io_rd(mss, MSS_INDEX);
923 prev &= ~MSS_TRD;
924 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
925 }
926
927 static void
928 ad_leave_MCE(struct mss_info *mss)
929 {
930 u_char prev;
931
932 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
933 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
934 return;
935 }
936
937 ad_wait_init(mss, 1000000);
938
939 mss->bd_flags &= ~BD_F_MCE_BIT;
940
941 prev = io_rd(mss, MSS_INDEX);
942 prev &= ~MSS_TRD;
943 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
944 wait_for_calibration(mss);
945 }
946
947 static int
948 mss_speed(struct mss_chinfo *ch, int speed)
949 {
950 struct mss_info *mss = ch->parent;
951 /*
952 * In the CS4231, the low 4 bits of I8 are used to hold the
953 * sample rate. Only a fixed number of values is allowed. This
954 * table lists them. The speed-setting routines scans the table
955 * looking for the closest match. This is the only supported method.
956 *
957 * In the CS4236, there is an alternate metod (which we do not
958 * support yet) which provides almost arbitrary frequency setting.
959 * In the AD1845, it looks like the sample rate can be
960 * almost arbitrary, and written directly to a register.
961 * In the OPTi931, there is a SB command which provides for
962 * almost arbitrary frequency setting.
963 *
964 */
965 ad_enter_MCE(mss);
966 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
967 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
968 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
969 /* XXX must also do something in I27 for the ad1845 */
970 } else {
971 int i, sel = 0; /* assume entry 0 does not contain -1 */
972 static int speeds[] =
973 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
974 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
975
976 for (i = 1; i < 16; i++)
977 if (speeds[i] > 0 &&
978 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
979 speed = speeds[sel];
980 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
981 ad_wait_init(mss, 10000);
982 }
983 ad_leave_MCE(mss);
984
985 return speed;
986 }
987
988 /*
989 * mss_format checks that the format is supported (or defaults to AFMT_U8)
990 * and returns the bit setting for the 1848 register corresponding to
991 * the desired format.
992 *
993 * fixed lr970724
994 */
995
996 static int
997 mss_format(struct mss_chinfo *ch, u_int32_t format)
998 {
999 struct mss_info *mss = ch->parent;
1000 int i, arg = format & ~AFMT_STEREO;
1001
1002 /*
1003 * The data format uses 3 bits (just 2 on the 1848). For each
1004 * bit setting, the following array returns the corresponding format.
1005 * The code scans the array looking for a suitable format. In
1006 * case it is not found, default to AFMT_U8 (not such a good
1007 * choice, but let's do it for compatibility...).
1008 */
1009
1010 static int fmts[] =
1011 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1012 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1013
1014 ch->fmt = format;
1015 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1016 arg = i << 1;
1017 if (format & AFMT_STEREO) arg |= 1;
1018 arg <<= 4;
1019 ad_enter_MCE(mss);
1020 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1021 ad_wait_init(mss, 10000);
1022 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1023 ad_write(mss, 28, arg); /* capture mode */
1024 ad_wait_init(mss, 10000);
1025 }
1026 ad_leave_MCE(mss);
1027 return format;
1028 }
1029
1030 static int
1031 mss_trigger(struct mss_chinfo *ch, int go)
1032 {
1033 struct mss_info *mss = ch->parent;
1034 u_char m;
1035 int retry, wr, cnt, ss;
1036
1037 ss = 1;
1038 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1039 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1040
1041 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1042 m = ad_read(mss, 9);
1043 switch (go) {
1044 case PCMTRIG_START:
1045 cnt = (ch->blksz / ss) - 1;
1046
1047 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1048 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1049 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1050 break;
1051
1052 case PCMTRIG_STOP:
1053 case PCMTRIG_ABORT: /* XXX check this... */
1054 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1055 #if 0
1056 /*
1057 * try to disable DMA by clearing count registers. Not sure it
1058 * is needed, and it might cause false interrupts when the
1059 * DMA is re-enabled later.
1060 */
1061 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1062 #endif
1063 }
1064 /* on the OPTi931 the enable bit seems hard to set... */
1065 for (retry = 10; retry > 0; retry--) {
1066 ad_write(mss, 9, m);
1067 if (ad_read(mss, 9) == m) break;
1068 }
1069 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1070 m, ad_read(mss, 9)));
1071 return 0;
1072 }
1073
1074
1075 /*
1076 * the opti931 seems to miss interrupts when working in full
1077 * duplex, so we try some heuristics to catch them.
1078 */
1079 static void
1080 opti931_intr(void *arg)
1081 {
1082 struct mss_info *mss = (struct mss_info *)arg;
1083 u_char masked = 0, i11, mc11, c = 0;
1084 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1085 int loops = 10;
1086
1087 #if 0
1088 reason = io_rd(mss, MSS_STATUS);
1089 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1090 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1091 return;
1092 }
1093 #endif
1094 mss_lock(mss);
1095 i11 = ad_read(mss, 11); /* XXX what's for ? */
1096 again:
1097
1098 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1099 mc11 &= 0x0c;
1100 if (c & 0x10) {
1101 DEB(printf("Warning: CD interrupt\n");)
1102 mc11 |= 0x10;
1103 }
1104 if (c & 0x20) {
1105 DEB(printf("Warning: MPU interrupt\n");)
1106 mc11 |= 0x20;
1107 }
1108 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1109 mc11, masked));
1110 masked |= mc11;
1111 /*
1112 * the nice OPTi931 sets the IRQ line before setting the bits in
1113 * mc11. So, on some occasions I have to retry (max 10 times).
1114 */
1115 if (mc11 == 0) { /* perhaps can return ... */
1116 reason = io_rd(mss, MSS_STATUS);
1117 if (reason & 1) {
1118 DEB(printf("one more try...\n");)
1119 if (--loops) goto again;
1120 else BVDDB(printf("intr, but mc11 not set\n");)
1121 }
1122 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1123 mss_unlock(mss);
1124 return;
1125 }
1126
1127 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1128 mss_unlock(mss);
1129 chn_intr(mss->rch.channel);
1130 mss_lock(mss);
1131 }
1132 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1133 mss_unlock(mss);
1134 chn_intr(mss->pch.channel);
1135 mss_lock(mss);
1136 }
1137 opti_wr(mss, 11, ~mc11); /* ack */
1138 if (--loops) goto again;
1139 mss_unlock(mss);
1140 DEB(printf("xxx too many loops\n");)
1141 }
1142
1143 /* -------------------------------------------------------------------- */
1144 /* channel interface */
1145 static void *
1146 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1147 {
1148 struct mss_info *mss = devinfo;
1149 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1150
1151 ch->parent = mss;
1152 ch->channel = c;
1153 ch->buffer = b;
1154 ch->dir = dir;
1155 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) != 0)
1156 return NULL;
1157 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1158 return ch;
1159 }
1160
1161 static int
1162 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1163 {
1164 struct mss_chinfo *ch = data;
1165 struct mss_info *mss = ch->parent;
1166
1167 mss_lock(mss);
1168 mss_format(ch, format);
1169 mss_unlock(mss);
1170 return 0;
1171 }
1172
1173 static int
1174 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1175 {
1176 struct mss_chinfo *ch = data;
1177 struct mss_info *mss = ch->parent;
1178 int r;
1179
1180 mss_lock(mss);
1181 r = mss_speed(ch, speed);
1182 mss_unlock(mss);
1183
1184 return r;
1185 }
1186
1187 static int
1188 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1189 {
1190 struct mss_chinfo *ch = data;
1191
1192 ch->blksz = blocksize;
1193 sndbuf_resize(ch->buffer, 2, ch->blksz);
1194
1195 return ch->blksz;
1196 }
1197
1198 static int
1199 msschan_trigger(kobj_t obj, void *data, int go)
1200 {
1201 struct mss_chinfo *ch = data;
1202 struct mss_info *mss = ch->parent;
1203
1204 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
1205 return 0;
1206
1207 sndbuf_dma(ch->buffer, go);
1208 mss_lock(mss);
1209 mss_trigger(ch, go);
1210 mss_unlock(mss);
1211 return 0;
1212 }
1213
1214 static int
1215 msschan_getptr(kobj_t obj, void *data)
1216 {
1217 struct mss_chinfo *ch = data;
1218 return sndbuf_dmaptr(ch->buffer);
1219 }
1220
1221 static struct pcmchan_caps *
1222 msschan_getcaps(kobj_t obj, void *data)
1223 {
1224 struct mss_chinfo *ch = data;
1225
1226 switch(ch->parent->bd_id) {
1227 case MD_OPTI931:
1228 return &opti931_caps;
1229 break;
1230
1231 case MD_GUSPNP:
1232 case MD_GUSMAX:
1233 return &guspnp_caps;
1234 break;
1235
1236 default:
1237 return &mss_caps;
1238 break;
1239 }
1240 }
1241
1242 static kobj_method_t msschan_methods[] = {
1243 KOBJMETHOD(channel_init, msschan_init),
1244 KOBJMETHOD(channel_setformat, msschan_setformat),
1245 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1246 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1247 KOBJMETHOD(channel_trigger, msschan_trigger),
1248 KOBJMETHOD(channel_getptr, msschan_getptr),
1249 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1250 { 0, 0 }
1251 };
1252 CHANNEL_DECLARE(msschan);
1253
1254 /* -------------------------------------------------------------------- */
1255
1256 /*
1257 * mss_probe() is the probe routine. Note, it is not necessary to
1258 * go through this for PnP devices, since they are already
1259 * indentified precisely using their PnP id.
1260 *
1261 * The base address supplied in the device refers to the old MSS
1262 * specs where the four 4 registers in io space contain configuration
1263 * information. Some boards (as an example, early MSS boards)
1264 * has such a block of registers, whereas others (generally CS42xx)
1265 * do not. In order to distinguish between the two and do not have
1266 * to supply two separate probe routines, the flags entry in isa_device
1267 * has a bit to mark this.
1268 *
1269 */
1270
1271 static int
1272 mss_probe(device_t dev)
1273 {
1274 u_char tmp, tmpx;
1275 int flags, irq, drq, result = ENXIO, setres = 0;
1276 struct mss_info *mss;
1277
1278 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1279
1280 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1281 if (!mss) return ENXIO;
1282
1283 mss->io_rid = 0;
1284 mss->conf_rid = -1;
1285 mss->irq_rid = 0;
1286 mss->drq1_rid = 0;
1287 mss->drq2_rid = -1;
1288 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1289 0, ~0, 8, RF_ACTIVE);
1290 if (!mss->io_base) {
1291 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1292 mss->io_rid = 0;
1293 /* XXX verify this */
1294 setres = 1;
1295 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1296 0x530, 8);
1297 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1298 0, ~0, 8, RF_ACTIVE);
1299 }
1300 if (!mss->io_base) goto no;
1301
1302 /* got irq/dma regs? */
1303 flags = device_get_flags(dev);
1304 irq = isa_get_irq(dev);
1305 drq = isa_get_drq(dev);
1306
1307 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1308
1309 /*
1310 * Check if the IO port returns valid signature. The original MS
1311 * Sound system returns 0x04 while some cards
1312 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1313 */
1314
1315 device_set_desc(dev, "MSS");
1316 tmpx = tmp = io_rd(mss, 3);
1317 if (tmp == 0xff) { /* Bus float */
1318 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1319 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1320 goto mss_probe_end;
1321 }
1322 tmp &= 0x3f;
1323 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
1324 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
1325 rman_get_start(mss->io_base), tmpx));
1326 goto no;
1327 }
1328 #ifdef PC98
1329 if (irq > 12) {
1330 #else
1331 if (irq > 11) {
1332 #endif
1333 printf("MSS: Bad IRQ %d\n", irq);
1334 goto no;
1335 }
1336 if (!(drq == 0 || drq == 1 || drq == 3)) {
1337 printf("MSS: Bad DMA %d\n", drq);
1338 goto no;
1339 }
1340 if (tmpx & 0x80) {
1341 /* 8-bit board: only drq1/3 and irq7/9 */
1342 if (drq == 0) {
1343 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1344 goto no;
1345 }
1346 if (!(irq == 7 || irq == 9)) {
1347 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1348 irq);
1349 goto no;
1350 }
1351 }
1352 mss_probe_end:
1353 result = mss_detect(dev, mss);
1354 no:
1355 mss_release_resources(mss, dev);
1356 #if 0
1357 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1358 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1359 #endif
1360 return result;
1361 }
1362
1363 static int
1364 mss_detect(device_t dev, struct mss_info *mss)
1365 {
1366 int i;
1367 u_char tmp = 0, tmp1, tmp2;
1368 char *name, *yamaha;
1369
1370 if (mss->bd_id != 0) {
1371 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1372 device_get_desc(dev));
1373 return 0;
1374 }
1375
1376 name = "AD1848";
1377 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1378
1379 #ifndef PC98
1380 if (opti_detect(dev, mss)) {
1381 switch (mss->bd_id) {
1382 case MD_OPTI924:
1383 name = "OPTi924";
1384 break;
1385 case MD_OPTI930:
1386 name = "OPTi930";
1387 break;
1388 }
1389 printf("Found OPTi device %s\n", name);
1390 if (opti_init(dev, mss) == 0) goto gotit;
1391 }
1392 #endif
1393
1394 /*
1395 * Check that the I/O address is in use.
1396 *
1397 * bit 7 of the base I/O port is known to be 0 after the chip has
1398 * performed its power on initialization. Just assume this has
1399 * happened before the OS is starting.
1400 *
1401 * If the I/O address is unused, it typically returns 0xff.
1402 */
1403
1404 for (i = 0; i < 10; i++)
1405 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1406 else break;
1407
1408 if (i >= 10) { /* Not an AD1848 */
1409 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1410 goto no;
1411 }
1412 /*
1413 * Test if it's possible to change contents of the indirect
1414 * registers. Registers 0 and 1 are ADC volume registers. The bit
1415 * 0x10 is read only so try to avoid using it.
1416 */
1417
1418 ad_write(mss, 0, 0xaa);
1419 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1420 tmp1 = ad_read(mss, 0);
1421 tmp2 = ad_read(mss, 1);
1422 if (tmp1 != 0xaa || tmp2 != 0x45) {
1423 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1424 goto no;
1425 }
1426
1427 ad_write(mss, 0, 0x45);
1428 ad_write(mss, 1, 0xaa);
1429 tmp1 = ad_read(mss, 0);
1430 tmp2 = ad_read(mss, 1);
1431 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1432 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1433 goto no;
1434 }
1435
1436 /*
1437 * The indirect register I12 has some read only bits. Lets try to
1438 * change them.
1439 */
1440
1441 tmp = ad_read(mss, 12);
1442 ad_write(mss, 12, (~tmp) & 0x0f);
1443 tmp1 = ad_read(mss, 12);
1444
1445 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1446 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1447 goto no;
1448 }
1449
1450 /*
1451 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1452 * 0x01=RevB
1453 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1454 */
1455
1456 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1457
1458 /*
1459 * The original AD1848/CS4248 has just 16 indirect registers. This
1460 * means that I0 and I16 should return the same value (etc.). Ensure
1461 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1462 * with new parts.
1463 */
1464
1465 ad_write(mss, 12, 0); /* Mode2=disabled */
1466 #if 0
1467 for (i = 0; i < 16; i++) {
1468 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1469 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1470 i, tmp1, tmp2));
1471 /*
1472 * note - this seems to fail on the 4232 on I11. So we just break
1473 * rather than fail. (which makes this test pointless - cg)
1474 */
1475 break; /* return 0; */
1476 }
1477 }
1478 #endif
1479 /*
1480 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1481 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1482 *
1483 * On the OPTi931, however, I12 is readonly and only contains the
1484 * chip revision ID (as in the CS4231A). The upper bits return 0.
1485 */
1486
1487 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1488
1489 tmp1 = ad_read(mss, 12);
1490 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1491 if ((tmp1 & 0xf0) == 0x00) {
1492 BVDDB(printf("this should be an OPTi931\n");)
1493 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1494 /*
1495 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1496 * We want to check that this is really a CS4231
1497 * Verify that setting I0 doesn't change I16.
1498 */
1499 ad_write(mss, 16, 0); /* Set I16 to known value */
1500 ad_write(mss, 0, 0x45);
1501 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1502
1503 ad_write(mss, 0, 0xaa);
1504 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1505 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1506 goto no;
1507 }
1508 /* Verify that some bits of I25 are read only. */
1509 tmp1 = ad_read(mss, 25); /* Original bits */
1510 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1511 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1512 int id;
1513
1514 /* It's at least CS4231 */
1515 name = "CS4231";
1516 mss->bd_id = MD_CS42XX;
1517
1518 /*
1519 * It could be an AD1845 or CS4231A as well.
1520 * CS4231 and AD1845 report the same revision info in I25
1521 * while the CS4231A reports different.
1522 */
1523
1524 id = ad_read(mss, 25) & 0xe7;
1525 /*
1526 * b7-b5 = version number;
1527 * 100 : all CS4231
1528 * 101 : CS4231A
1529 *
1530 * b2-b0 = chip id;
1531 */
1532 switch (id) {
1533
1534 case 0xa0:
1535 name = "CS4231A";
1536 mss->bd_id = MD_CS42XX;
1537 break;
1538
1539 case 0xa2:
1540 name = "CS4232";
1541 mss->bd_id = MD_CS42XX;
1542 break;
1543
1544 case 0xb2:
1545 /* strange: the 4231 data sheet says b4-b3 are XX
1546 * so this should be the same as 0xa2
1547 */
1548 name = "CS4232A";
1549 mss->bd_id = MD_CS42XX;
1550 break;
1551
1552 case 0x80:
1553 /*
1554 * It must be a CS4231 or AD1845. The register I23
1555 * of CS4231 is undefined and it appears to be read
1556 * only. AD1845 uses I23 for setting sample rate.
1557 * Assume the chip is AD1845 if I23 is changeable.
1558 */
1559
1560 tmp = ad_read(mss, 23);
1561
1562 ad_write(mss, 23, ~tmp);
1563 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1564 name = "AD1845";
1565 mss->bd_id = MD_AD1845;
1566 }
1567 ad_write(mss, 23, tmp); /* Restore */
1568
1569 yamaha = ymf_test(dev, mss);
1570 if (yamaha) {
1571 mss->bd_id = MD_YM0020;
1572 name = yamaha;
1573 }
1574 break;
1575
1576 case 0x83: /* CS4236 */
1577 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1578 name = "CS4236";
1579 mss->bd_id = MD_CS42XX;
1580 break;
1581
1582 default: /* Assume CS4231 */
1583 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1584 mss->bd_id = MD_CS42XX;
1585 }
1586 }
1587 ad_write(mss, 25, tmp1); /* Restore bits */
1588 gotit:
1589 BVDDB(printf("mss_detect() - Detected %s\n", name));
1590 device_set_desc(dev, name);
1591 device_set_flags(dev,
1592 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1593 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1594 return 0;
1595 no:
1596 return ENXIO;
1597 }
1598
1599 #ifndef PC98
1600 static int
1601 opti_detect(device_t dev, struct mss_info *mss)
1602 {
1603 int c;
1604 static const struct opticard {
1605 int boardid;
1606 int passwdreg;
1607 int password;
1608 int base;
1609 int indir_reg;
1610 } cards[] = {
1611 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1612 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1613 { 0 },
1614 };
1615 mss->conf_rid = 3;
1616 mss->indir_rid = 4;
1617 for (c = 0; cards[c].base; c++) {
1618 mss->optibase = cards[c].base;
1619 mss->password = cards[c].password;
1620 mss->passwdreg = cards[c].passwdreg;
1621 mss->bd_id = cards[c].boardid;
1622
1623 if (cards[c].indir_reg)
1624 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1625 &mss->indir_rid, cards[c].indir_reg,
1626 cards[c].indir_reg+1, 1, RF_ACTIVE);
1627
1628 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1629 &mss->conf_rid, mss->optibase, mss->optibase+9,
1630 9, RF_ACTIVE);
1631
1632 if (opti_read(mss, 1) != 0xff) {
1633 return 1;
1634 } else {
1635 if (mss->indir)
1636 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1637 mss->indir = NULL;
1638 if (mss->conf_base)
1639 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1640 mss->conf_base = NULL;
1641 }
1642 }
1643 return 0;
1644 }
1645 #endif
1646
1647 static char *
1648 ymf_test(device_t dev, struct mss_info *mss)
1649 {
1650 static int ports[] = {0x370, 0x310, 0x538};
1651 int p, i, j, version;
1652 static char *chipset[] = {
1653 NULL, /* 0 */
1654 "OPL3-SA2 (YMF711)", /* 1 */
1655 "OPL3-SA3 (YMF715)", /* 2 */
1656 "OPL3-SA3 (YMF715)", /* 3 */
1657 "OPL3-SAx (YMF719)", /* 4 */
1658 "OPL3-SAx (YMF719)", /* 5 */
1659 "OPL3-SAx (YMF719)", /* 6 */
1660 "OPL3-SAx (YMF719)", /* 7 */
1661 };
1662
1663 for (p = 0; p < 3; p++) {
1664 mss->conf_rid = 1;
1665 mss->conf_base = bus_alloc_resource(dev,
1666 SYS_RES_IOPORT,
1667 &mss->conf_rid,
1668 ports[p], ports[p] + 1, 2,
1669 RF_ACTIVE);
1670 if (!mss->conf_base) return 0;
1671
1672 /* Test the index port of the config registers */
1673 i = port_rd(mss->conf_base, 0);
1674 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1675 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1676 port_wr(mss->conf_base, 0, i);
1677 if (!j) {
1678 bus_release_resource(dev, SYS_RES_IOPORT,
1679 mss->conf_rid, mss->conf_base);
1680 #ifdef PC98
1681 /* PC98 need this. I don't know reason why. */
1682 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1683 #endif
1684 mss->conf_base = 0;
1685 continue;
1686 }
1687 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1688 return chipset[version];
1689 }
1690 return NULL;
1691 }
1692
1693 static int
1694 mss_doattach(device_t dev, struct mss_info *mss)
1695 {
1696 int pdma, rdma, flags = device_get_flags(dev);
1697 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1698
1699 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1700 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1701 if (!mss_alloc_resources(mss, dev)) goto no;
1702 mss_init(mss, dev);
1703 pdma = rman_get_start(mss->drq1);
1704 rdma = rman_get_start(mss->drq2);
1705 if (flags & DV_F_TRUE_MSS) {
1706 /* has IRQ/DMA registers, set IRQ and DMA addr */
1707 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
1708 static char interrupt_bits[13] =
1709 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
1710 #else
1711 static char interrupt_bits[12] =
1712 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
1713 #endif
1714 static char pdma_bits[4] = {1, 2, -1, 3};
1715 static char valid_rdma[4] = {1, 0, -1, 0};
1716 char bits;
1717
1718 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1719 goto no;
1720 #ifndef PC98 /* CS423[12] in PC98 don't support this. */
1721 io_wr(mss, 0, bits | 0x40); /* config port */
1722 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1723 #endif
1724 /* Write IRQ+DMA setup */
1725 if (pdma_bits[pdma] == -1) goto no;
1726 bits |= pdma_bits[pdma];
1727 if (pdma != rdma) {
1728 if (rdma == valid_rdma[pdma]) bits |= 4;
1729 else {
1730 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1731 goto no;
1732 }
1733 }
1734 io_wr(mss, 0, bits);
1735 printf("drq/irq conf %x\n", io_rd(mss, 0));
1736 }
1737 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1738 switch (mss->bd_id) {
1739 case MD_OPTI931:
1740 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
1741 break;
1742 default:
1743 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
1744 }
1745 if (pdma == rdma)
1746 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1747 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1748 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1749 /*highaddr*/BUS_SPACE_MAXADDR,
1750 /*filter*/NULL, /*filterarg*/NULL,
1751 /*maxsize*/mss->bufsize, /*nsegments*/1,
1752 /*maxsegz*/0x3ffff, /*flags*/0,
1753 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
1754 &mss->parent_dmat) != 0) {
1755 device_printf(dev, "unable to create dma tag\n");
1756 goto no;
1757 }
1758
1759 if (pdma != rdma)
1760 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
1761 else
1762 status2[0] = '\0';
1763
1764 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
1765 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1766
1767 if (pcm_register(dev, mss, 1, 1)) goto no;
1768 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1769 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1770 pcm_setstatus(dev, status);
1771
1772 return 0;
1773 no:
1774 mss_release_resources(mss, dev);
1775 return ENXIO;
1776 }
1777
1778 static int
1779 mss_detach(device_t dev)
1780 {
1781 int r;
1782 struct mss_info *mss;
1783
1784 r = pcm_unregister(dev);
1785 if (r)
1786 return r;
1787
1788 mss = pcm_getdevinfo(dev);
1789 mss_release_resources(mss, dev);
1790
1791 return 0;
1792 }
1793
1794 static int
1795 mss_attach(device_t dev)
1796 {
1797 struct mss_info *mss;
1798 int flags = device_get_flags(dev);
1799
1800 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1801 if (!mss) return ENXIO;
1802
1803 mss->io_rid = 0;
1804 mss->conf_rid = -1;
1805 mss->irq_rid = 0;
1806 mss->drq1_rid = 0;
1807 mss->drq2_rid = -1;
1808 if (flags & DV_F_DUAL_DMA) {
1809 bus_set_resource(dev, SYS_RES_DRQ, 1,
1810 flags & DV_F_DRQ_MASK, 1);
1811 mss->drq2_rid = 1;
1812 }
1813 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1814 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1815 return mss_doattach(dev, mss);
1816 }
1817
1818 /*
1819 * mss_resume() is the code to allow a laptop to resume using the sound
1820 * card.
1821 *
1822 * This routine re-sets the state of the board to the state before going
1823 * to sleep. According to the yamaha docs this is the right thing to do,
1824 * but getting DMA restarted appears to be a bit of a trick, so the device
1825 * has to be closed and re-opened to be re-used, but there is no skipping
1826 * problem, and volume, bass/treble and most other things are restored
1827 * properly.
1828 *
1829 */
1830
1831 static int
1832 mss_resume(device_t dev)
1833 {
1834 /*
1835 * Restore the state taken below.
1836 */
1837 struct mss_info *mss;
1838 int i;
1839
1840 mss = pcm_getdevinfo(dev);
1841
1842 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
1843 /* This works on a Toshiba Libretto 100CT. */
1844 for (i = 0; i < MSS_INDEXED_REGS; i++)
1845 ad_write(mss, i, mss->mss_indexed_regs[i]);
1846 for (i = 0; i < OPL_INDEXED_REGS; i++)
1847 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1848 mss_intr(mss);
1849 }
1850
1851 if (mss->bd_id == MD_CS423X) {
1852 /* Needed on IBM Thinkpad 600E */
1853 mss_lock(mss);
1854 mss_format(&mss->pch, mss->pch.channel->format);
1855 mss_speed(&mss->pch, mss->pch.channel->speed);
1856 mss_unlock(mss);
1857 }
1858
1859 return 0;
1860
1861 }
1862
1863 /*
1864 * mss_suspend() is the code that gets called right before a laptop
1865 * suspends.
1866 *
1867 * This code saves the state of the sound card right before shutdown
1868 * so it can be restored above.
1869 *
1870 */
1871
1872 static int
1873 mss_suspend(device_t dev)
1874 {
1875 int i;
1876 struct mss_info *mss;
1877
1878 mss = pcm_getdevinfo(dev);
1879
1880 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
1881 {
1882 /* this stops playback. */
1883 conf_wr(mss, 0x12, 0x0c);
1884 for(i = 0; i < MSS_INDEXED_REGS; i++)
1885 mss->mss_indexed_regs[i] = ad_read(mss, i);
1886 for(i = 0; i < OPL_INDEXED_REGS; i++)
1887 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1888 mss->opl_indexed_regs[0x12] = 0x0;
1889 }
1890 return 0;
1891 }
1892
1893 static device_method_t mss_methods[] = {
1894 /* Device interface */
1895 DEVMETHOD(device_probe, mss_probe),
1896 DEVMETHOD(device_attach, mss_attach),
1897 DEVMETHOD(device_detach, mss_detach),
1898 DEVMETHOD(device_suspend, mss_suspend),
1899 DEVMETHOD(device_resume, mss_resume),
1900
1901 { 0, 0 }
1902 };
1903
1904 static driver_t mss_driver = {
1905 "pcm",
1906 mss_methods,
1907 PCM_SOFTC_SIZE,
1908 };
1909
1910 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1911 MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1912 MODULE_VERSION(snd_mss, 1);
1913
1914 static int
1915 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1916 {
1917 struct resource *sbport;
1918 int i, ret, rid;
1919
1920 rid = 0;
1921 ret = -1;
1922 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1923 if (sbport) {
1924 for (i = 0; i < 1000; i++) {
1925 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1926 DELAY((i > 100) ? 1000 : 10);
1927 else {
1928 port_wr(sbport, SBDSP_CMD, 0x09);
1929 break;
1930 }
1931 }
1932 for (i = 0; i < 1000; i++) {
1933 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1934 DELAY((i > 100) ? 1000 : 10);
1935 else {
1936 port_wr(sbport, SBDSP_CMD, 0x00);
1937 ret = 0;
1938 break;
1939 }
1940 }
1941 DELAY(1000);
1942 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1943 }
1944 return ret;
1945 }
1946
1947 static struct isa_pnp_id pnpmss_ids[] = {
1948 {0x0000630e, "CS423x"}, /* CSC0000 */
1949 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1950 {0x01000000, "CMI8330"}, /* @@@0001 */
1951 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1952 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1953 {0x1093143e, "OPTi931"}, /* OPT9310 */
1954 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1955 {0x0000143e, "OPTi924"}, /* OPT0924 */
1956 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1957 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1958 #if 0
1959 {0x0000561e, "GusPnP"}, /* GRV0000 */
1960 #endif
1961 {0},
1962 };
1963
1964 static int
1965 pnpmss_probe(device_t dev)
1966 {
1967 u_int32_t lid, vid;
1968
1969 lid = isa_get_logicalid(dev);
1970 vid = isa_get_vendorid(dev);
1971 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1972 return ENXIO;
1973 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1974 }
1975
1976 static int
1977 pnpmss_attach(device_t dev)
1978 {
1979 struct mss_info *mss;
1980
1981 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1982 if (!mss)
1983 return ENXIO;
1984
1985 mss->io_rid = 0;
1986 mss->conf_rid = -1;
1987 mss->irq_rid = 0;
1988 mss->drq1_rid = 0;
1989 mss->drq2_rid = 1;
1990 mss->bd_id = MD_CS42XX;
1991
1992 switch (isa_get_logicalid(dev)) {
1993 case 0x0000630e: /* CSC0000 */
1994 case 0x0001630e: /* CSC0100 */
1995 mss->bd_flags |= BD_F_MSS_OFFSET;
1996 mss->bd_id = MD_CS423X;
1997 break;
1998
1999 case 0x2100a865: /* YHM0021 */
2000 mss->io_rid = 1;
2001 mss->conf_rid = 4;
2002 mss->bd_id = MD_YM0020;
2003 break;
2004
2005 case 0x1110d315: /* ENS1011 */
2006 mss->io_rid = 1;
2007 mss->bd_id = MD_VIVO;
2008 break;
2009
2010 case 0x1093143e: /* OPT9310 */
2011 mss->bd_flags |= BD_F_MSS_OFFSET;
2012 mss->conf_rid = 3;
2013 mss->bd_id = MD_OPTI931;
2014 break;
2015
2016 case 0x5092143e: /* OPT9250 XXX guess */
2017 mss->io_rid = 1;
2018 mss->conf_rid = 3;
2019 mss->bd_id = MD_OPTI925;
2020 break;
2021
2022 case 0x0000143e: /* OPT0924 */
2023 mss->password = 0xe5;
2024 mss->passwdreg = 3;
2025 mss->optibase = 0xf0c;
2026 mss->io_rid = 2;
2027 mss->conf_rid = 3;
2028 mss->bd_id = MD_OPTI924;
2029 mss->bd_flags |= BD_F_924PNP;
2030 if(opti_init(dev, mss) != 0) {
2031 free(mss, M_DEVBUF);
2032 return ENXIO;
2033 }
2034 break;
2035
2036 case 0x1022b839: /* NMX2210 */
2037 mss->io_rid = 1;
2038 break;
2039
2040 case 0x01005407: /* AZT0001 */
2041 /* put into MSS mode first (snatched from NetBSD) */
2042 if (azt2320_mss_mode(mss, dev) == -1) {
2043 free(mss, M_DEVBUF);
2044 return ENXIO;
2045 }
2046
2047 mss->bd_flags |= BD_F_MSS_OFFSET;
2048 mss->io_rid = 2;
2049 break;
2050
2051 #if 0
2052 case 0x0000561e: /* GRV0000 */
2053 mss->bd_flags |= BD_F_MSS_OFFSET;
2054 mss->io_rid = 2;
2055 mss->conf_rid = 1;
2056 mss->drq1_rid = 1;
2057 mss->drq2_rid = 0;
2058 mss->bd_id = MD_GUSPNP;
2059 break;
2060 #endif
2061 case 0x01000000: /* @@@0001 */
2062 mss->drq2_rid = -1;
2063 break;
2064
2065 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2066 default:
2067 mss->bd_flags |= BD_F_MSS_OFFSET;
2068 break;
2069 }
2070 return mss_doattach(dev, mss);
2071 }
2072
2073 static int
2074 opti_init(device_t dev, struct mss_info *mss)
2075 {
2076 int flags = device_get_flags(dev);
2077 int basebits = 0;
2078
2079 if (!mss->conf_base) {
2080 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2081 mss->optibase, 0x9);
2082
2083 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2084 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2085 0x9, RF_ACTIVE);
2086 }
2087
2088 if (!mss->conf_base)
2089 return ENXIO;
2090
2091 if (!mss->io_base)
2092 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2093 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2094
2095 if (!mss->io_base) /* No hint specified, use 0x530 */
2096 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2097 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2098
2099 if (!mss->io_base)
2100 return ENXIO;
2101
2102 switch (rman_get_start(mss->io_base)) {
2103 case 0x530:
2104 basebits = 0x0;
2105 break;
2106 case 0xe80:
2107 basebits = 0x10;
2108 break;
2109 case 0xf40:
2110 basebits = 0x20;
2111 break;
2112 case 0x604:
2113 basebits = 0x30;
2114 break;
2115 default:
2116 printf("opti_init: invalid MSS base address!\n");
2117 return ENXIO;
2118 }
2119
2120
2121 switch (mss->bd_id) {
2122 case MD_OPTI924:
2123 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2124 opti_write(mss, 2, 0x00); /* Disable CD */
2125 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2126 opti_write(mss, 4, 0xf0);
2127 opti_write(mss, 5, 0x00);
2128 opti_write(mss, 6, 0x02); /* MPU stuff */
2129 break;
2130
2131 case MD_OPTI930:
2132 opti_write(mss, 1, 0x00 | basebits);
2133 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2134 opti_write(mss, 4, 0x52); /* Empty FIFO */
2135 opti_write(mss, 5, 0x3c); /* Mode 2 */
2136 opti_write(mss, 6, 0x02); /* Enable MSS */
2137 break;
2138 }
2139
2140 if (mss->bd_flags & BD_F_924PNP) {
2141 u_int32_t irq = isa_get_irq(dev);
2142 u_int32_t drq = isa_get_drq(dev);
2143 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2144 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2145 if (flags & DV_F_DUAL_DMA) {
2146 bus_set_resource(dev, SYS_RES_DRQ, 1,
2147 flags & DV_F_DRQ_MASK, 1);
2148 mss->drq2_rid = 1;
2149 }
2150 }
2151
2152 /* OPTixxx has I/DRQ registers */
2153
2154 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2155
2156 return 0;
2157 }
2158
2159 static void
2160 opti_write(struct mss_info *mss, u_char reg, u_char val)
2161 {
2162 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2163
2164 switch(mss->bd_id) {
2165 case MD_OPTI924:
2166 if (reg > 7) { /* Indirect register */
2167 port_wr(mss->conf_base, mss->passwdreg, reg);
2168 port_wr(mss->conf_base, mss->passwdreg,
2169 mss->password);
2170 port_wr(mss->conf_base, 9, val);
2171 return;
2172 }
2173 port_wr(mss->conf_base, reg, val);
2174 break;
2175
2176 case MD_OPTI930:
2177 port_wr(mss->indir, 0, reg);
2178 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2179 port_wr(mss->indir, 1, val);
2180 break;
2181 }
2182 }
2183
2184 #ifndef PC98
2185 u_char
2186 opti_read(struct mss_info *mss, u_char reg)
2187 {
2188 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2189
2190 switch(mss->bd_id) {
2191 case MD_OPTI924:
2192 if (reg > 7) { /* Indirect register */
2193 port_wr(mss->conf_base, mss->passwdreg, reg);
2194 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2195 return(port_rd(mss->conf_base, 9));
2196 }
2197 return(port_rd(mss->conf_base, reg));
2198 break;
2199
2200 case MD_OPTI930:
2201 port_wr(mss->indir, 0, reg);
2202 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2203 return port_rd(mss->indir, 1);
2204 break;
2205 }
2206 return -1;
2207 }
2208 #endif
2209
2210 static device_method_t pnpmss_methods[] = {
2211 /* Device interface */
2212 DEVMETHOD(device_probe, pnpmss_probe),
2213 DEVMETHOD(device_attach, pnpmss_attach),
2214 DEVMETHOD(device_detach, mss_detach),
2215 DEVMETHOD(device_suspend, mss_suspend),
2216 DEVMETHOD(device_resume, mss_resume),
2217
2218 { 0, 0 }
2219 };
2220
2221 static driver_t pnpmss_driver = {
2222 "pcm",
2223 pnpmss_methods,
2224 PCM_SOFTC_SIZE,
2225 };
2226
2227 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2228 DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
2229 MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2230 MODULE_VERSION(snd_pnpmss, 1);
2231
2232 static int
2233 guspcm_probe(device_t dev)
2234 {
2235 struct sndcard_func *func;
2236
2237 func = device_get_ivars(dev);
2238 if (func == NULL || func->func != SCF_PCM)
2239 return ENXIO;
2240
2241 device_set_desc(dev, "GUS CS4231");
2242 return 0;
2243 }
2244
2245 static int
2246 guspcm_attach(device_t dev)
2247 {
2248 device_t parent = device_get_parent(dev);
2249 struct mss_info *mss;
2250 int base, flags;
2251 unsigned char ctl;
2252
2253 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2254 if (mss == NULL)
2255 return ENOMEM;
2256
2257 mss->bd_flags = BD_F_MSS_OFFSET;
2258 mss->io_rid = 2;
2259 mss->conf_rid = 1;
2260 mss->irq_rid = 0;
2261 mss->drq1_rid = 1;
2262 mss->drq2_rid = -1;
2263
2264 if (isa_get_logicalid(parent) == 0)
2265 mss->bd_id = MD_GUSMAX;
2266 else {
2267 mss->bd_id = MD_GUSPNP;
2268 mss->drq2_rid = 0;
2269 goto skip_setup;
2270 }
2271
2272 flags = device_get_flags(parent);
2273 if (flags & DV_F_DUAL_DMA)
2274 mss->drq2_rid = 0;
2275
2276 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2277 0, ~0, 8, RF_ACTIVE);
2278
2279 if (mss->conf_base == NULL) {
2280 mss_release_resources(mss, dev);
2281 return ENXIO;
2282 }
2283
2284 base = isa_get_port(parent);
2285
2286 ctl = 0x40; /* CS4231 enable */
2287 if (isa_get_drq(dev) > 3)
2288 ctl |= 0x10; /* 16-bit dma channel 1 */
2289 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2290 ctl |= 0x20; /* 16-bit dma channel 2 */
2291 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2292 port_wr(mss->conf_base, 6, ctl);
2293
2294 skip_setup:
2295 return mss_doattach(dev, mss);
2296 }
2297
2298 static device_method_t guspcm_methods[] = {
2299 DEVMETHOD(device_probe, guspcm_probe),
2300 DEVMETHOD(device_attach, guspcm_attach),
2301 DEVMETHOD(device_detach, mss_detach),
2302
2303 { 0, 0 }
2304 };
2305
2306 static driver_t guspcm_driver = {
2307 "pcm",
2308 guspcm_methods,
2309 PCM_SOFTC_SIZE,
2310 };
2311
2312 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2313 MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2314 MODULE_VERSION(snd_guspcm, 1);
2315
2316
Cache object: 8df47ccb4c929ed17a1f480b193d57f1
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