The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/isa/mss.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 1999 Doug Rabson
    5  * Copyright (c) 1997 Luigi Rizzo
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: stable/12/sys/dev/sound/isa/mss.h 327231 2017-12-27 03:23:21Z eadler $
   30  */
   31 
   32 /*
   33  * This file contains information and macro definitions for
   34  * AD1848-compatible devices, used in the MSS/WSS compatible boards.
   35  */
   36 
   37 /*
   38  *
   39 
   40 The codec part of the board is seen as a set of 4 registers mapped
   41 at the base address for the board (default 0x534). Note that some
   42 (early) boards implemented 4 additional registers 4 location before
   43 (usually 0x530) to store configuration information. This is a source
   44 of confusion in that one never knows what address to specify. The
   45 (current) convention is to use the old address (0x530) in the kernel
   46 configuration file and consider MSS registers start four location
   47 ahead.
   48 
   49  *
   50  */
   51 
   52 struct mixer_def {
   53         u_int regno:7;
   54         u_int polarity:1;       /* 1 means reversed */
   55         u_int bitoffs:4;
   56         u_int nbits:4;
   57 };
   58 typedef struct mixer_def mixer_ent;
   59 typedef struct mixer_def mixer_tab[32][2];
   60 
   61 #define MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) \
   62         {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}}
   63 
   64 #define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \
   65         {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}}
   66 
   67 #define MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0)
   68 
   69 /*
   70  * The four visible registers of the MSS :
   71  *
   72  */
   73 
   74 #define MSS_INDEX        (0 + 4)
   75 #define MSS_IDXBUSY             0x80    /* readonly, set when busy */
   76 #define MSS_MCE                 0x40    /* the MCE bit. */
   77         /*
   78          * the MCE bit must be set whenever the current mode of the
   79          * codec is changed; this in particular is true for the
   80          * Data Format (I8, I28) and Interface Config(I9) registers.
   81          * Only exception are CEN and PEN which can be changed on the fly.
   82          * The DAC output is muted when MCE is set.
   83          */
   84 #define MSS_TRD                 0x20    /* Transfer request disable */
   85         /*
   86          * When TRD is set, DMA transfers cease when the INT bit in
   87          * the MSS status reg is set. Must be cleared for automode
   88          * DMA, set otherwise.
   89          */
   90 #define MSS_IDXMASK             0x1f    /* mask for indirect address */
   91 
   92 #define MSS_IDATA       (1 + 4)
   93         /*
   94          * data to be transferred to the indirect register addressed
   95          * by index addr. During init and sw. powerdown, cannot be
   96          * written to, and is always read as 0x80 (consistent with the
   97          * busy flag).
   98          */
   99 
  100 #define MSS_STATUS      (2 + 4)
  101 
  102 #define IS_CUL          0x80    /* capture upper/lower */
  103 #define IS_CLR          0x40    /* capture left/right */
  104 #define IS_CRDY         0x20    /* capture ready for programmed i/o */
  105 #define IS_SER          0x10    /* sample error (overrun/underrun) */
  106 #define IS_PUL          0x08    /* playback upper/lower */
  107 #define IS_PLR          0x04    /* playback left/right */
  108 #define IS_PRDY         0x02    /* playback ready for programmed i/o */
  109 #define IS_INT          0x01    /* int status (1 = active) */
  110         /*
  111          * IS_INT is clreared by any write to the status register.
  112          */
  113 #if 0
  114 #define io_Polled_IO(d)         ((d)->io_base+3+4)
  115         /*
  116          * this register is used in case of polled i/o
  117          */
  118 #endif
  119 
  120 /*
  121  * The MSS has a set of 16 (or 32 depending on the model) indirect
  122  * registers accessible through the data port by specifying the
  123  * appropriate address in the address register.
  124  *
  125  * The 16 low registers are uniformly handled in AD1848/CS4248 compatible
  126  * mode (often called MODE1). For the upper 16 registers there are
  127  * some differences among different products, mainly Crystal uses them
  128  * differently from OPTi.
  129  *
  130  */
  131 
  132 /*
  133  * volume registers
  134  */
  135 
  136 #define I6_MUTE         0x80
  137 
  138 /*
  139  * register I9 -- interface configuration.
  140  */
  141 
  142 #define I9_PEN          0x01    /* playback enable */
  143 #define I9_CEN          0x02    /* capture enable */
  144 
  145 /*
  146  * values used in bd_flags
  147  */
  148 #define BD_F_MCE_BIT    0x0001
  149 #define BD_F_IRQ_OK     0x0002
  150 #define BD_F_TMR_RUN    0x0004
  151 #define BD_F_MSS_OFFSET 0x0008  /* offset mss writes by -4 */
  152 #define BD_F_DUPLEX     0x0010
  153 #define BD_F_924PNP     0x0020  /* OPTi924 is in PNP mode */
  154 
  155 /*
  156  * sound/ad1848_mixer.h
  157  *
  158  * Definitions for the mixer of AD1848 and compatible codecs.
  159  *
  160  * Copyright by Hannu Savolainen 1994
  161  *
  162  * Redistribution and use in source and binary forms, with or without
  163  * modification, are permitted provided that the following conditions are
  164  * met: 1. Redistributions of source code must retain the above copyright
  165  * notice, this list of conditions and the following disclaimer. 2.
  166  * Redistributions in binary form must reproduce the above copyright notice,
  167  * this list of conditions and the following disclaimer in the documentation
  168  * and/or other materials provided with the distribution.
  169  *
  170  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  171  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  172  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  173  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  174  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  175  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  176  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  177  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  178  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  179  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  180  * SUCH DAMAGE.
  181  */
  182 /*
  183  * The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
  184  * Soundcard manufacturers have connected actual inputs (CD, synth, line,
  185  * etc) to these inputs in different order. Therefore it's difficult
  186  * to assign mixer channels to these inputs correctly. The following
  187  * contains two alternative mappings. The first one is for GUS MAX and
  188  * the second is just a generic one (line1, line2 and line3).
  189  * (Actually this is not a mapping but rather some kind of interleaving
  190  * solution).
  191  */
  192 
  193 #define MSS_REC_DEVICES \
  194     (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
  195 
  196 
  197 /*
  198  * Table of mixer registers. There is a default table for the
  199  * AD1848/CS423x clones, one for the OPTI931 and one for the
  200  * OPTi930. As more MSS clones come out, there ought to be
  201  * more tables.
  202  *
  203  * Fields in the table are : polarity, register, offset, bits
  204  *
  205  * The channel numbering used by individual soundcards is not fixed.
  206  * Some cards have assigned different meanings for the AUX1, AUX2
  207  * and LINE inputs. Some have different features...
  208  *
  209  * Following there is a macro ...MIXER_DEVICES which is a bitmap
  210  * of all non-zero fields in the table.
  211  * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
  212  * registers I0..I15)
  213  *
  214  */
  215 
  216 mixer_ent mix_devices[32][2] = {
  217 MIX_NONE(SOUND_MIXER_VOLUME),
  218 MIX_NONE(SOUND_MIXER_BASS),
  219 MIX_NONE(SOUND_MIXER_TREBLE),
  220 MIX_ENT(SOUND_MIXER_SYNTH,       2, 1, 0, 5,     3, 1, 0, 5),
  221 MIX_ENT(SOUND_MIXER_PCM,         6, 1, 0, 6,     7, 1, 0, 6),
  222 MIX_ENT(SOUND_MIXER_SPEAKER,    26, 1, 0, 4,     0, 0, 0, 0),
  223 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 0, 5,    19, 1, 0, 5),
  224 MIX_ENT(SOUND_MIXER_MIC,         0, 0, 5, 1,     1, 0, 5, 1),
  225 MIX_ENT(SOUND_MIXER_CD,          4, 1, 0, 5,     5, 1, 0, 5),
  226 MIX_ENT(SOUND_MIXER_IMIX,       13, 1, 2, 6,     0, 0, 0, 0),
  227 MIX_NONE(SOUND_MIXER_ALTPCM),
  228 MIX_NONE(SOUND_MIXER_RECLEV),
  229 MIX_ENT(SOUND_MIXER_IGAIN,       0, 0, 0, 4,     1, 0, 0, 4),
  230 MIX_NONE(SOUND_MIXER_OGAIN),
  231 MIX_NONE(SOUND_MIXER_LINE1),
  232 MIX_NONE(SOUND_MIXER_LINE2),
  233 MIX_NONE(SOUND_MIXER_LINE3),
  234 };
  235 
  236 #define MODE2_MIXER_DEVICES     \
  237     (SOUND_MASK_SYNTH | SOUND_MASK_PCM    | SOUND_MASK_SPEAKER | \
  238      SOUND_MASK_LINE  | SOUND_MASK_MIC    | SOUND_MASK_CD      | \
  239      SOUND_MASK_IMIX  | SOUND_MASK_IGAIN                         )
  240 
  241 #define MODE1_MIXER_DEVICES     \
  242     (SOUND_MASK_SYNTH | SOUND_MASK_PCM    | SOUND_MASK_MIC     | \
  243      SOUND_MASK_CD    | SOUND_MASK_IMIX   | SOUND_MASK_IGAIN     )
  244 
  245 
  246 mixer_ent opti930_devices[32][2] = {
  247 MIX_ENT(SOUND_MIXER_VOLUME,     22, 1, 0, 4,    23, 1, 0, 4),
  248 MIX_NONE(SOUND_MIXER_BASS),
  249 MIX_NONE(SOUND_MIXER_TREBLE),
  250 MIX_ENT(SOUND_MIXER_SYNTH,      4,  1, 0, 4,    5,  1, 0, 4),
  251 MIX_ENT(SOUND_MIXER_PCM,        6,  1, 1, 5,    7,  1, 1, 5),
  252 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 1, 4,    19, 1, 1, 4),
  253 MIX_NONE(SOUND_MIXER_SPEAKER),
  254 MIX_ENT(SOUND_MIXER_MIC,        21, 1, 0, 4,    22, 1, 0, 4),
  255 MIX_ENT(SOUND_MIXER_CD,         2,  1, 1, 4,    3,  1, 1, 4),
  256 MIX_NONE(SOUND_MIXER_IMIX),
  257 MIX_NONE(SOUND_MIXER_ALTPCM),
  258 MIX_NONE(SOUND_MIXER_RECLEV),
  259 MIX_NONE(SOUND_MIXER_IGAIN),
  260 MIX_NONE(SOUND_MIXER_OGAIN),
  261 MIX_NONE(SOUND_MIXER_LINE1),
  262 MIX_NONE(SOUND_MIXER_LINE2),
  263 MIX_NONE(SOUND_MIXER_LINE3),
  264 };
  265 
  266 #define OPTI930_MIXER_DEVICES   \
  267     (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
  268      SOUND_MASK_LINE   | SOUND_MASK_MIC   | SOUND_MASK_CD )
  269 
  270 /*
  271  * entries for the opti931...
  272  */
  273 
  274 mixer_ent opti931_devices[32][2] = {    /* for the opti931 */
  275 MIX_ENT(SOUND_MIXER_VOLUME,     22, 1, 1, 5,    23, 1, 1, 5),
  276 MIX_NONE(SOUND_MIXER_BASS),
  277 MIX_NONE(SOUND_MIXER_TREBLE),
  278 MIX_ENT(SOUND_MIXER_SYNTH,       4, 1, 1, 4,     5, 1, 1, 4),
  279 MIX_ENT(SOUND_MIXER_PCM,         6, 1, 0, 5,     7, 1, 0, 5),
  280 MIX_NONE(SOUND_MIXER_SPEAKER),
  281 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 1, 4,    19, 1, 1, 4),
  282 MIX_ENT(SOUND_MIXER_MIC,         0, 0, 5, 1,     1, 0, 5, 1),
  283 MIX_ENT(SOUND_MIXER_CD,          2, 1, 1, 4,     3, 1, 1, 4),
  284 MIX_NONE(SOUND_MIXER_IMIX),
  285 MIX_NONE(SOUND_MIXER_ALTPCM),
  286 MIX_NONE(SOUND_MIXER_RECLEV),
  287 MIX_ENT(SOUND_MIXER_IGAIN,       0, 0, 0, 4,     1, 0, 0, 4),
  288 MIX_NONE(SOUND_MIXER_OGAIN),
  289 MIX_ENT(SOUND_MIXER_LINE1,      16, 1, 1, 4,    17, 1, 1, 4),
  290 MIX_NONE(SOUND_MIXER_LINE2),
  291 MIX_NONE(SOUND_MIXER_LINE3),
  292 };
  293 
  294 #define OPTI931_MIXER_DEVICES   \
  295     (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
  296      SOUND_MASK_LINE   | SOUND_MASK_MIC   | SOUND_MASK_CD  | \
  297      SOUND_MASK_IGAIN  | SOUND_MASK_LINE1                    )
  298 
  299 /*
  300  * Register definitions for the Yamaha OPL3-SA[23x].
  301  */
  302 #define OPL3SAx_POWER   0x01            /* Power Management (R/W) */
  303 #define OPL3SAx_POWER_PDX       0x01    /* Set to 1 to halt oscillator */
  304 #define OPL3SAx_POWER_PDN       0x02    /* Set to 1 to power down */
  305 #define OPL3SAx_POWER_PSV       0x04    /* Set to 1 to power save */
  306 #define OPL3SAx_POWER_ADOWN     0x20    /* Analog power (?) */
  307 
  308 #define OPL3SAx_SYSTEM  0x02            /* System control (R/W) */
  309 #define OPL3SAx_SYSTEM_VZE      0x01    /* I2S audio routing */
  310 #define OPL3SAx_SYSTEM_IDSEL    0x03    /* SB compat version select */
  311 #define OPL3SAx_SYSTEM_SBHE     0x80    /* 0 for AT bus, 1 for XT bus */
  312 
  313 #define OPL3SAx_IRQCONF 0x03            /* Interrupt configuration (R/W */
  314 #define OPL3SAx_IRQCONF_WSSA    0x01    /* WSS interrupts through IRQA */
  315 #define OPL3SAx_IRQCONF_SBA     0x02    /* WSS interrupts through IRQA */
  316 #define OPL3SAx_IRQCONF_MPUA    0x04    /* WSS interrupts through IRQA */
  317 #define OPL3SAx_IRQCONF_OPL3A   0x08    /* WSS interrupts through IRQA */
  318 #define OPL3SAx_IRQCONF_WSSB    0x10    /* WSS interrupts through IRQB */
  319 #define OPL3SAx_IRQCONF_SBB     0x20    /* WSS interrupts through IRQB */
  320 #define OPL3SAx_IRQCONF_MPUB    0x40    /* WSS interrupts through IRQB */
  321 #define OPL3SAx_IRQCONF_OPL3B   0x80    /* WSS interrupts through IRQB */
  322 
  323 #define OPL3SAx_IRQSTATUSA 0x04         /* Interrupt (IRQ-A) Status (RO) */
  324 #define OPL3SAx_IRQSTATUSB 0x05         /* Interrupt (IRQ-B) Status (RO) */
  325 #define OPL3SAx_IRQSTATUS_PI    0x01    /* Playback Flag of CODEC */
  326 #define OPL3SAx_IRQSTATUS_CI    0x02    /* Recording Flag of CODEC */
  327 #define OPL3SAx_IRQSTATUS_TI    0x04    /* Timer Flag of CODEC */
  328 #define OPL3SAx_IRQSTATUS_SB    0x08    /* SB compat Playback Interrupt Flag */
  329 #define OPL3SAx_IRQSTATUS_MPU   0x10    /* MPU401 Interrupt Flag */
  330 #define OPL3SAx_IRQSTATUS_OPL3  0x20    /* Internal FM Timer Flag */
  331 #define OPL3SAx_IRQSTATUS_MV    0x40    /* HW Volume Interrupt Flag */
  332 #define OPL3SAx_IRQSTATUS_PI    0x01    /* Playback Flag of CODEC */
  333 #define OPL3SAx_IRQSTATUS_CI    0x02    /* Recording Flag of CODEC */
  334 #define OPL3SAx_IRQSTATUS_TI    0x04    /* Timer Flag of CODEC */
  335 #define OPL3SAx_IRQSTATUS_SB    0x08    /* SB compat Playback Interrupt Flag */
  336 #define OPL3SAx_IRQSTATUS_MPU   0x10    /* MPU401 Interrupt Flag */
  337 #define OPL3SAx_IRQSTATUS_OPL3  0x20    /* Internal FM Timer Flag */
  338 #define OPL3SAx_IRQSTATUS_MV    0x40    /* HW Volume Interrupt Flag */
  339 
  340 #define OPL3SAx_DMACONF 0x06            /* DMA configuration (R/W) */
  341 #define OPL3SAx_DMACONF_WSSPA   0x01    /* WSS Playback on DMA-A */
  342 #define OPL3SAx_DMACONF_WSSRA   0x02    /* WSS Recording on DMA-A */
  343 #define OPL3SAx_DMACONF_SBA     0x02    /* SB Playback on DMA-A */
  344 #define OPL3SAx_DMACONF_WSSPB   0x10    /* WSS Playback on DMA-A */
  345 #define OPL3SAx_DMACONF_WSSRB   0x20    /* WSS Recording on DMA-A */
  346 #define OPL3SAx_DMACONF_SBB     0x20    /* SB Playback on DMA-A */
  347 
  348 #define OPL3SAx_VOLUMEL 0x07            /* Master Volume Left (R/W) */
  349 #define OPL3SAx_VOLUMEL_MVL     0x0f    /* Attenuation level */
  350 #define OPL3SAx_VOLUMEL_MVLM    0x80    /* Mute */
  351 
  352 #define OPL3SAx_VOLUMER 0x08            /* Master Volume Right (R/W) */
  353 #define OPL3SAx_VOLUMER_MVR     0x0f    /* Attenuation level */
  354 #define OPL3SAx_VOLUMER_MVRM    0x80    /* Mute */
  355 
  356 #define OPL3SAx_MIC     0x09            /* MIC Volume (R/W) */
  357 #define OPL3SAx_VOLUMER_MCV     0x1f    /* Attenuation level */
  358 #define OPL3SAx_VOLUMER_MICM    0x80    /* Mute */
  359 
  360 #define OPL3SAx_MISC    0x0a            /* Miscellaneous */
  361 #define OPL3SAx_MISC_VER        0x07    /* Version */
  362 #define OPL3SAx_MISC_MODE       0x08    /* SB or WSS mode */
  363 #define OPL3SAx_MISC_MCSW       0x10    /*  */
  364 #define OPL3SAx_MISC_VEN        0x80    /* Enable hardware volume control */
  365 
  366 #define OPL3SAx_WSSDMA  0x0b            /* WSS DMA Counter (RW) (4 regs) */
  367 
  368 #define OPL3SAx_WSSIRQSCAN 0x0f         /* WSS Interrupt Scan out/in (R/W) */
  369 #define OPL3SAx_WSSIRQSCAN_SPI  0x01
  370 #define OPL3SAx_WSSIRQSCAN_SCI  0x02
  371 #define OPL3SAx_WSSIRQSCAN_STI  0x04
  372 
  373 #define OPL3SAx_SBSTATE 0x10            /* SB compat Internal State (R/W) */
  374 #define OPL3SAx_SBSTATE_SBPDR   0x01    /* SB Power Down Request */
  375 #define OPL3SAx_SBSTATE_SE      0x02    /* Scan Enable */
  376 #define OPL3SAx_SBSTATE_SM      0x04    /* Scan Mode */
  377 #define OPL3SAx_SBSTATE_SS      0x08    /* Scan Select */
  378 #define OPL3SAx_SBSTATE_SBPDA   0x80    /* SB Power Down Acknowledge */
  379 
  380 #define OPL3SAx_SBDATA 0x11             /* SB compat State Scan Data (R/W) */
  381 
  382 #define OPL3SAx_DIGITALPOWER 0x12       /* Digital Partial Power Down (R/W) */
  383 #define OPL3SAx_DIGITALPOWER_PnP  0x01
  384 #define OPL3SAx_DIGITALPOWER_SB   0x02
  385 #define OPL3SAx_DIGITALPOWER_WSSP 0x04
  386 #define OPL3SAx_DIGITALPOWER_WSSR 0x08
  387 #define OPL3SAx_DIGITALPOWER_FM   0x10
  388 #define OPL3SAx_DIGITALPOWER_MCLK0 0x20
  389 #define OPL3SAx_DIGITALPOWER_MPU  0x40
  390 #define OPL3SAx_DIGITALPOWER_JOY  0x80
  391 
  392 #define OPL3SAx_ANALOGPOWER 0x13        /* Analog Partial Power Down (R/W) */
  393 #define OPL3SAx_ANALOGPOWER_WIDE  0x01
  394 #define OPL3SAx_ANALOGPOWER_SBDAC 0x02
  395 #define OPL3SAx_ANALOGPOWER_DA    0x04
  396 #define OPL3SAx_ANALOGPOWER_AD    0x08
  397 #define OPL3SAx_ANALOGPOWER_FMDAC 0x10
  398 
  399 #define OPL3SAx_WIDE    0x14            /* Enhanced control(WIDE) (R/W) */
  400 #define OPL3SAx_WIDE_WIDEL      0x07    /* Wide level on Left Channel */
  401 #define OPL3SAx_WIDE_WIDER      0x70    /* Wide level on Right Channel */
  402 
  403 #define OPL3SAx_BASS    0x15            /* Enhanced control(BASS) (R/W) */
  404 #define OPL3SAx_BASS_BASSL      0x07    /* Bass level on Left Channel */
  405 #define OPL3SAx_BASS_BASSR      0x70    /* Bass level on Right Channel */
  406 
  407 #define OPL3SAx_TREBLE  0x16            /* Enhanced control(TREBLE) (R/W) */
  408 #define OPL3SAx_TREBLE_TREBLEL  0x07    /* Treble level on Left Channel */
  409 #define OPL3SAx_TREBLE_TREBLER  0x70    /* Treble level on Right Channel */
  410 
  411 #define OPL3SAx_HWVOL   0x17            /* HW Volume IRQ Configuration (R/W) */
  412 #define OPL3SAx_HWVOL_IRQA      0x10    /* HW Volume IRQ on IRQ-A */
  413 #define OPL3SAx_HWVOL_IRQB      0x20    /* HW Volume IRQ on IRQ-B */
  414 
  415 

Cache object: f8a5ee967e9c1dc13be8d1009acec3f6


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.