The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/isa/mss.h

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    1 /*
    2  * file: mss.h
    3  *
    4  * (C) 1997 Luigi Rizzo (luigi@iet.unipi.it)
    5  *
    6  * This file contains information and macro definitions for
    7  * AD1848-compatible devices, used in the MSS/WSS compatible boards.
    8  *
    9  */
   10 
   11 /*
   12  *
   13 
   14 The codec part of the board is seen as a set of 4 registers mapped
   15 at the base address for the board (default 0x534). Note that some
   16 (early) boards implemented 4 additional registers 4 location before
   17 (usually 0x530) to store configuration information. This is a source
   18 of confusion in that one never knows what address to specify. The
   19 (current) convention is to use the old address (0x530) in the kernel
   20 configuration file and consider MSS registers start four location
   21 ahead.
   22 
   23  *
   24  */
   25 
   26 struct mixer_def {
   27         u_int regno:7;
   28         u_int polarity:1;       /* 1 means reversed */
   29         u_int bitoffs:4;
   30         u_int nbits:4;
   31 };
   32 typedef struct mixer_def mixer_ent;
   33 typedef struct mixer_def mixer_tab[32][2];
   34 
   35 #define MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) \
   36         {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}}
   37 
   38 #define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \
   39         {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}}
   40 
   41 #define MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0)
   42 
   43 /*
   44  * The four visible registers of the MSS :
   45  *
   46  */
   47 
   48 #define MSS_INDEX        (0 + 4)
   49 #define MSS_IDXBUSY             0x80    /* readonly, set when busy */
   50 #define MSS_MCE                 0x40    /* the MCE bit. */
   51         /*
   52          * the MCE bit must be set whenever the current mode of the
   53          * codec is changed; this in particular is true for the
   54          * Data Format (I8, I28) and Interface Config(I9) registers.
   55          * Only exception are CEN and PEN which can be changed on the fly.
   56          * The DAC output is muted when MCE is set.
   57          */
   58 #define MSS_TRD                 0x20    /* Transfer request disable */
   59         /*
   60          * When TRD is set, DMA transfers cease when the INT bit in
   61          * the MSS status reg is set. Must be cleared for automode
   62          * DMA, set otherwise.
   63          */
   64 #define MSS_IDXMASK             0x1f    /* mask for indirect address */
   65 
   66 #define MSS_IDATA       (1 + 4)
   67         /*
   68          * data to be transferred to the indirect register addressed
   69          * by index addr. During init and sw. powerdown, cannot be
   70          * written to, and is always read as 0x80 (consistent with the
   71          * busy flag).
   72          */
   73 
   74 #define MSS_STATUS      (2 + 4)
   75 
   76 #define IS_CUL          0x80    /* capture upper/lower */
   77 #define IS_CLR          0x40    /* capture left/right */
   78 #define IS_CRDY         0x20    /* capture ready for programmed i/o */
   79 #define IS_SER          0x10    /* sample error (overrun/underrun) */
   80 #define IS_PUL          0x08    /* playback upper/lower */
   81 #define IS_PLR          0x04    /* playback left/right */
   82 #define IS_PRDY         0x02    /* playback ready for programmed i/o */
   83 #define IS_INT          0x01    /* int status (1 = active) */
   84         /*
   85          * IS_INT is clreared by any write to the status register.
   86          */
   87 #if 0
   88 #define io_Polled_IO(d)         ((d)->io_base+3+4)
   89         /*
   90          * this register is used in case of polled i/o
   91          */
   92 #endif
   93 
   94 /*
   95  * The MSS has a set of 16 (or 32 depending on the model) indirect
   96  * registers accessible through the data port by specifying the
   97  * appropriate address in the address register.
   98  *
   99  * The 16 low registers are uniformly handled in AD1848/CS4248 compatible
  100  * mode (often called MODE1). For the upper 16 registers there are
  101  * some differences among different products, mainly Crystal uses them
  102  * differently from OPTi.
  103  *
  104  */
  105 
  106 /*
  107  * volume registers
  108  */
  109 
  110 #define I6_MUTE         0x80
  111 
  112 /*
  113  * register I9 -- interface configuration.
  114  */
  115 
  116 #define I9_PEN          0x01    /* playback enable */
  117 #define I9_CEN          0x02    /* capture enable */
  118 
  119 /*
  120  * values used in bd_flags
  121  */
  122 #define BD_F_MCE_BIT    0x0001
  123 #define BD_F_IRQ_OK     0x0002
  124 #define BD_F_TMR_RUN    0x0004
  125 #define BD_F_MSS_OFFSET 0x0008  /* offset mss writes by -4 */
  126 #define BD_F_DUPLEX     0x0010
  127 #define BD_F_924PNP     0x0020  /* OPTi924 is in PNP mode */
  128 
  129 /*
  130  * sound/ad1848_mixer.h
  131  *
  132  * Definitions for the mixer of AD1848 and compatible codecs.
  133  *
  134  * Copyright by Hannu Savolainen 1994
  135  *
  136  * Redistribution and use in source and binary forms, with or without
  137  * modification, are permitted provided that the following conditions are
  138  * met: 1. Redistributions of source code must retain the above copyright
  139  * notice, this list of conditions and the following disclaimer. 2.
  140  * Redistributions in binary form must reproduce the above copyright notice,
  141  * this list of conditions and the following disclaimer in the documentation
  142  * and/or other materials provided with the distribution.
  143  *
  144  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  145  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  146  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  147  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  148  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  149  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  150  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  151  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  152  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  153  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  154  * SUCH DAMAGE.
  155  */
  156 /*
  157  * The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
  158  * Soundcard manufacturers have connected actual inputs (CD, synth, line,
  159  * etc) to these inputs in different order. Therefore it's difficult
  160  * to assign mixer channels to to these inputs correctly. The following
  161  * contains two alternative mappings. The first one is for GUS MAX and
  162  * the second is just a generic one (line1, line2 and line3).
  163  * (Actually this is not a mapping but rather some kind of interleaving
  164  * solution).
  165  */
  166 
  167 #define MSS_REC_DEVICES \
  168     (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
  169 
  170 
  171 /*
  172  * Table of mixer registers. There is a default table for the
  173  * AD1848/CS423x clones, one for the OPTI931 and one for the
  174  * OPTi930. As more MSS clones come out, there ought to be
  175  * more tables.
  176  *
  177  * Fields in the table are : polarity, register, offset, bits
  178  *
  179  * The channel numbering used by individual soundcards is not fixed.
  180  * Some cards have assigned different meanings for the AUX1, AUX2
  181  * and LINE inputs. Some have different features...
  182  *
  183  * Following there is a macro ...MIXER_DEVICES which is a bitmap
  184  * of all non-zero fields in the table.
  185  * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
  186  * registers I0..I15)
  187  *
  188  */
  189 
  190 mixer_ent mix_devices[32][2] = {
  191 MIX_NONE(SOUND_MIXER_VOLUME),
  192 MIX_NONE(SOUND_MIXER_BASS),
  193 MIX_NONE(SOUND_MIXER_TREBLE),
  194 #ifdef PC98     /* PC98's synth is assigned to AUX#2 */
  195 MIX_ENT(SOUND_MIXER_SYNTH,       4, 1, 0, 5,     5, 1, 0, 5),
  196 #else           /* AT386's synth is assigned to AUX#1 */
  197 MIX_ENT(SOUND_MIXER_SYNTH,       2, 1, 0, 5,     3, 1, 0, 5),
  198 #endif
  199 MIX_ENT(SOUND_MIXER_PCM,         6, 1, 0, 6,     7, 1, 0, 6),
  200 MIX_ENT(SOUND_MIXER_SPEAKER,    26, 1, 0, 4,     0, 0, 0, 0),
  201 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 0, 5,    19, 1, 0, 5),
  202 MIX_ENT(SOUND_MIXER_MIC,         0, 0, 5, 1,     1, 0, 5, 1),
  203 #ifdef PC98     /* PC98's cd-audio is assigned to AUX#1 */
  204 MIX_ENT(SOUND_MIXER_CD,          2, 1, 0, 5,     3, 1, 0, 5),
  205 #else           /* AT386's cd-audio is assigned to AUX#2 */
  206 MIX_ENT(SOUND_MIXER_CD,          4, 1, 0, 5,     5, 1, 0, 5),
  207 #endif
  208 MIX_ENT(SOUND_MIXER_IMIX,       13, 1, 2, 6,     0, 0, 0, 0),
  209 MIX_NONE(SOUND_MIXER_ALTPCM),
  210 MIX_NONE(SOUND_MIXER_RECLEV),
  211 MIX_ENT(SOUND_MIXER_IGAIN,       0, 0, 0, 4,     1, 0, 0, 4),
  212 MIX_NONE(SOUND_MIXER_OGAIN),
  213 MIX_NONE(SOUND_MIXER_LINE1),
  214 MIX_NONE(SOUND_MIXER_LINE2),
  215 MIX_NONE(SOUND_MIXER_LINE3),
  216 };
  217 
  218 #define MODE2_MIXER_DEVICES     \
  219     (SOUND_MASK_SYNTH | SOUND_MASK_PCM    | SOUND_MASK_SPEAKER | \
  220      SOUND_MASK_LINE  | SOUND_MASK_MIC    | SOUND_MASK_CD      | \
  221      SOUND_MASK_IMIX  | SOUND_MASK_IGAIN                         )
  222 
  223 #define MODE1_MIXER_DEVICES     \
  224     (SOUND_MASK_SYNTH | SOUND_MASK_PCM    | SOUND_MASK_MIC     | \
  225      SOUND_MASK_CD    | SOUND_MASK_IMIX   | SOUND_MASK_IGAIN     )
  226 
  227 
  228 mixer_ent opti930_devices[32][2] = {
  229 MIX_ENT(SOUND_MIXER_VOLUME,     22, 1, 0, 4,    23, 1, 0, 4),
  230 MIX_NONE(SOUND_MIXER_BASS),
  231 MIX_NONE(SOUND_MIXER_TREBLE),
  232 MIX_ENT(SOUND_MIXER_SYNTH,      4,  1, 0, 4,    5,  1, 0, 4),
  233 MIX_ENT(SOUND_MIXER_PCM,        6,  1, 1, 5,    7,  1, 1, 5),
  234 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 1, 4,    19, 1, 1, 4),
  235 MIX_NONE(SOUND_MIXER_SPEAKER),
  236 MIX_ENT(SOUND_MIXER_MIC,        21, 1, 0, 4,    22, 1, 0, 4),
  237 MIX_ENT(SOUND_MIXER_CD,         2,  1, 1, 4,    3,  1, 1, 4),
  238 MIX_NONE(SOUND_MIXER_IMIX),
  239 MIX_NONE(SOUND_MIXER_ALTPCM),
  240 MIX_NONE(SOUND_MIXER_RECLEV),
  241 MIX_NONE(SOUND_MIXER_IGAIN),
  242 MIX_NONE(SOUND_MIXER_OGAIN),
  243 MIX_NONE(SOUND_MIXER_LINE1),
  244 MIX_NONE(SOUND_MIXER_LINE2),
  245 MIX_NONE(SOUND_MIXER_LINE3),
  246 };
  247 
  248 #define OPTI930_MIXER_DEVICES   \
  249     (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
  250      SOUND_MASK_LINE   | SOUND_MASK_MIC   | SOUND_MASK_CD )
  251 
  252 /*
  253  * entries for the opti931...
  254  */
  255 
  256 mixer_ent opti931_devices[32][2] = {    /* for the opti931 */
  257 MIX_ENT(SOUND_MIXER_VOLUME,     22, 1, 1, 5,    23, 1, 1, 5),
  258 MIX_NONE(SOUND_MIXER_BASS),
  259 MIX_NONE(SOUND_MIXER_TREBLE),
  260 MIX_ENT(SOUND_MIXER_SYNTH,       4, 1, 1, 4,     5, 1, 1, 4),
  261 MIX_ENT(SOUND_MIXER_PCM,         6, 1, 0, 5,     7, 1, 0, 5),
  262 MIX_NONE(SOUND_MIXER_SPEAKER),
  263 MIX_ENT(SOUND_MIXER_LINE,       18, 1, 1, 4,    19, 1, 1, 4),
  264 MIX_ENT(SOUND_MIXER_MIC,         0, 0, 5, 1,     1, 0, 5, 1),
  265 MIX_ENT(SOUND_MIXER_CD,          2, 1, 1, 4,     3, 1, 1, 4),
  266 MIX_NONE(SOUND_MIXER_IMIX),
  267 MIX_NONE(SOUND_MIXER_ALTPCM),
  268 MIX_NONE(SOUND_MIXER_RECLEV),
  269 MIX_ENT(SOUND_MIXER_IGAIN,       0, 0, 0, 4,     1, 0, 0, 4),
  270 MIX_NONE(SOUND_MIXER_OGAIN),
  271 MIX_ENT(SOUND_MIXER_LINE1,      16, 1, 1, 4,    17, 1, 1, 4),
  272 MIX_NONE(SOUND_MIXER_LINE2),
  273 MIX_NONE(SOUND_MIXER_LINE3),
  274 };
  275 
  276 #define OPTI931_MIXER_DEVICES   \
  277     (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
  278      SOUND_MASK_LINE   | SOUND_MASK_MIC   | SOUND_MASK_CD  | \
  279      SOUND_MASK_IGAIN  | SOUND_MASK_LINE1                    )
  280 
  281 /*-
  282  * Copyright (c) 1999 Doug Rabson
  283  * All rights reserved.
  284  *
  285  * Redistribution and use in source and binary forms, with or without
  286  * modification, are permitted provided that the following conditions
  287  * are met:
  288  * 1. Redistributions of source code must retain the above copyright
  289  *    notice, this list of conditions and the following disclaimer.
  290  * 2. Redistributions in binary form must reproduce the above copyright
  291  *    notice, this list of conditions and the following disclaimer in the
  292  *    documentation and/or other materials provided with the distribution.
  293  *
  294  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  295  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  296  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  297  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  298  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  299  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  300  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  301  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  302  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  303  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  304  * SUCH DAMAGE.
  305  *
  306  * $FreeBSD: stable/4/sys/dev/sound/isa/mss.h 95264 2002-04-22 15:49:36Z cg $
  307  */
  308 
  309 /*
  310  * Register definitions for the Yamaha OPL3-SA[23x].
  311  */
  312 #define OPL3SAx_POWER   0x01            /* Power Management (R/W) */
  313 #define OPL3SAx_POWER_PDX       0x01    /* Set to 1 to halt oscillator */
  314 #define OPL3SAx_POWER_PDN       0x02    /* Set to 1 to power down */
  315 #define OPL3SAx_POWER_PSV       0x04    /* Set to 1 to power save */
  316 #define OPL3SAx_POWER_ADOWN     0x20    /* Analog power (?) */
  317 
  318 #define OPL3SAx_SYSTEM  0x02            /* System control (R/W) */
  319 #define OPL3SAx_SYSTEM_VZE      0x01    /* I2S audio routing */
  320 #define OPL3SAx_SYSTEM_IDSEL    0x03    /* SB compat version select */
  321 #define OPL3SAx_SYSTEM_SBHE     0x80    /* 0 for AT bus, 1 for XT bus */
  322 
  323 #define OPL3SAx_IRQCONF 0x03            /* Interrupt configuration (R/W */
  324 #define OPL3SAx_IRQCONF_WSSA    0x01    /* WSS interrupts through IRQA */
  325 #define OPL3SAx_IRQCONF_SBA     0x02    /* WSS interrupts through IRQA */
  326 #define OPL3SAx_IRQCONF_MPUA    0x04    /* WSS interrupts through IRQA */
  327 #define OPL3SAx_IRQCONF_OPL3A   0x08    /* WSS interrupts through IRQA */
  328 #define OPL3SAx_IRQCONF_WSSB    0x10    /* WSS interrupts through IRQB */
  329 #define OPL3SAx_IRQCONF_SBB     0x20    /* WSS interrupts through IRQB */
  330 #define OPL3SAx_IRQCONF_MPUB    0x40    /* WSS interrupts through IRQB */
  331 #define OPL3SAx_IRQCONF_OPL3B   0x80    /* WSS interrupts through IRQB */
  332 
  333 #define OPL3SAx_IRQSTATUSA 0x04         /* Interrupt (IRQ-A) Status (RO) */
  334 #define OPL3SAx_IRQSTATUSB 0x05         /* Interrupt (IRQ-B) Status (RO) */
  335 #define OPL3SAx_IRQSTATUS_PI    0x01    /* Playback Flag of CODEC */
  336 #define OPL3SAx_IRQSTATUS_CI    0x02    /* Recording Flag of CODEC */
  337 #define OPL3SAx_IRQSTATUS_TI    0x04    /* Timer Flag of CODEC */
  338 #define OPL3SAx_IRQSTATUS_SB    0x08    /* SB compat Playback Interrupt Flag */
  339 #define OPL3SAx_IRQSTATUS_MPU   0x10    /* MPU401 Interrupt Flag */
  340 #define OPL3SAx_IRQSTATUS_OPL3  0x20    /* Internal FM Timer Flag */
  341 #define OPL3SAx_IRQSTATUS_MV    0x40    /* HW Volume Interrupt Flag */
  342 #define OPL3SAx_IRQSTATUS_PI    0x01    /* Playback Flag of CODEC */
  343 #define OPL3SAx_IRQSTATUS_CI    0x02    /* Recording Flag of CODEC */
  344 #define OPL3SAx_IRQSTATUS_TI    0x04    /* Timer Flag of CODEC */
  345 #define OPL3SAx_IRQSTATUS_SB    0x08    /* SB compat Playback Interrupt Flag */
  346 #define OPL3SAx_IRQSTATUS_MPU   0x10    /* MPU401 Interrupt Flag */
  347 #define OPL3SAx_IRQSTATUS_OPL3  0x20    /* Internal FM Timer Flag */
  348 #define OPL3SAx_IRQSTATUS_MV    0x40    /* HW Volume Interrupt Flag */
  349 
  350 #define OPL3SAx_DMACONF 0x06            /* DMA configuration (R/W) */
  351 #define OPL3SAx_DMACONF_WSSPA   0x01    /* WSS Playback on DMA-A */
  352 #define OPL3SAx_DMACONF_WSSRA   0x02    /* WSS Recording on DMA-A */
  353 #define OPL3SAx_DMACONF_SBA     0x02    /* SB Playback on DMA-A */
  354 #define OPL3SAx_DMACONF_WSSPB   0x10    /* WSS Playback on DMA-A */
  355 #define OPL3SAx_DMACONF_WSSRB   0x20    /* WSS Recording on DMA-A */
  356 #define OPL3SAx_DMACONF_SBB     0x20    /* SB Playback on DMA-A */
  357 
  358 #define OPL3SAx_VOLUMEL 0x07            /* Master Volume Left (R/W) */
  359 #define OPL3SAx_VOLUMEL_MVL     0x0f    /* Attenuation level */
  360 #define OPL3SAx_VOLUMEL_MVLM    0x80    /* Mute */
  361 
  362 #define OPL3SAx_VOLUMER 0x08            /* Master Volume Right (R/W) */
  363 #define OPL3SAx_VOLUMER_MVR     0x0f    /* Attenuation level */
  364 #define OPL3SAx_VOLUMER_MVRM    0x80    /* Mute */
  365 
  366 #define OPL3SAx_MIC     0x09            /* MIC Volume (R/W) */
  367 #define OPL3SAx_VOLUMER_MCV     0x1f    /* Attenuation level */
  368 #define OPL3SAx_VOLUMER_MICM    0x80    /* Mute */
  369 
  370 #define OPL3SAx_MISC    0x0a            /* Miscellaneous */
  371 #define OPL3SAx_MISC_VER        0x07    /* Version */
  372 #define OPL3SAx_MISC_MODE       0x08    /* SB or WSS mode */
  373 #define OPL3SAx_MISC_MCSW       0x10    /*  */
  374 #define OPL3SAx_MISC_VEN        0x80    /* Enable hardware volume control */
  375 
  376 #define OPL3SAx_WSSDMA  0x0b            /* WSS DMA Counter (RW) (4 regs) */
  377 
  378 #define OPL3SAx_WSSIRQSCAN 0x0f         /* WSS Interrupt Scan out/in (R/W) */
  379 #define OPL3SAx_WSSIRQSCAN_SPI  0x01
  380 #define OPL3SAx_WSSIRQSCAN_SCI  0x02
  381 #define OPL3SAx_WSSIRQSCAN_STI  0x04
  382 
  383 #define OPL3SAx_SBSTATE 0x10            /* SB compat Internal State (R/W) */
  384 #define OPL3SAx_SBSTATE_SBPDR   0x01    /* SB Power Down Request */
  385 #define OPL3SAx_SBSTATE_SE      0x02    /* Scan Enable */
  386 #define OPL3SAx_SBSTATE_SM      0x04    /* Scan Mode */
  387 #define OPL3SAx_SBSTATE_SS      0x08    /* Scan Select */
  388 #define OPL3SAx_SBSTATE_SBPDA   0x80    /* SB Power Down Acknowledge */
  389 
  390 #define OPL3SAx_SBDATA 0x11             /* SB compat State Scan Data (R/W) */
  391 
  392 #define OPL3SAx_DIGITALPOWER 0x12       /* Digital Partial Power Down (R/W) */
  393 #define OPL3SAx_DIGITALPOWER_PnP  0x01
  394 #define OPL3SAx_DIGITALPOWER_SB   0x02
  395 #define OPL3SAx_DIGITALPOWER_WSSP 0x04
  396 #define OPL3SAx_DIGITALPOWER_WSSR 0x08
  397 #define OPL3SAx_DIGITALPOWER_FM   0x10
  398 #define OPL3SAx_DIGITALPOWER_MCLK0 0x20
  399 #define OPL3SAx_DIGITALPOWER_MPU  0x40
  400 #define OPL3SAx_DIGITALPOWER_JOY  0x80
  401 
  402 #define OPL3SAx_ANALOGPOWER 0x13        /* Analog Partial Power Down (R/W) */
  403 #define OPL3SAx_ANALOGPOWER_WIDE  0x01
  404 #define OPL3SAx_ANALOGPOWER_SBDAC 0x02
  405 #define OPL3SAx_ANALOGPOWER_DA    0x04
  406 #define OPL3SAx_ANALOGPOWER_AD    0x08
  407 #define OPL3SAx_ANALOGPOWER_FMDAC 0x10
  408 
  409 #define OPL3SAx_WIDE    0x14            /* Enhanced control(WIDE) (R/W) */
  410 #define OPL3SAx_WIDE_WIDEL      0x07    /* Wide level on Left Channel */
  411 #define OPL3SAx_WIDE_WIDER      0x70    /* Wide level on Right Channel */
  412 
  413 #define OPL3SAx_BASS    0x15            /* Enhanced control(BASS) (R/W) */
  414 #define OPL3SAx_BASS_BASSL      0x07    /* Bass level on Left Channel */
  415 #define OPL3SAx_BASS_BASSR      0x70    /* Bass level on Right Channel */
  416 
  417 #define OPL3SAx_TREBLE  0x16            /* Enhanced control(TREBLE) (R/W) */
  418 #define OPL3SAx_TREBLE_TREBLEL  0x07    /* Treble level on Left Channel */
  419 #define OPL3SAx_TREBLE_TREBLER  0x70    /* Treble level on Right Channel */
  420 
  421 #define OPL3SAx_HWVOL   0x17            /* HW Volume IRQ Configuration (R/W) */
  422 #define OPL3SAx_HWVOL_IRQA      0x10    /* HW Volume IRQ on IRQ-A */
  423 #define OPL3SAx_HWVOL_IRQB      0x20    /* HW Volume IRQ on IRQ-B */
  424 
  425 

Cache object: 287b72cdc1f4a0654ed0437f7b8b52ab


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