Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/sound/pci/au88x0.h
Version:
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1 /*- 2 * Copyright (c) 2003 Dag-Erling Coïdan Smørgrav 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer 10 * in this position and unchanged. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _AU88X0_H_INCLUDED 32 #define _AU88X0_H_INCLUDED 33 34 /* 35 * Chipset parameters 36 */ 37 struct au88x0_chipset { 38 const char *auc_name; 39 uint32_t auc_pci_id; 40 41 /* General control register */ 42 uint32_t auc_control; 43 #define AU88X0_CTL_MIDI_ENABLE 0x0001 44 #define AU88X0_CTL_GAME_ENABLE 0x0008 45 #define AU88X0_CTL_IRQ_ENABLE 0x4000 46 47 /* IRQ control register */ 48 uint32_t auc_irq_source; 49 #define AU88X0_IRQ_FATAL_ERR 0x0001 50 #define AU88X0_IRQ_PARITY_ERR 0x0002 51 #define AU88X0_IRQ_REG_ERR 0x0004 52 #define AU88X0_IRQ_FIFO_ERR 0x0008 53 #define AU88X0_IRQ_DMA_ERR 0x0010 54 #define AU88X0_IRQ_PCMOUT 0x0020 55 #define AU88X0_IRQ_TIMER 0x1000 56 #define AU88X0_IRQ_MIDI 0x2000 57 #define AU88X0_IRQ_MODEM 0x4000 58 uint32_t auc_irq_mask; 59 uint32_t auc_irq_control; 60 #define AU88X0_IRQ_PENDING_BIT 0x0001 61 uint32_t auc_irq_status; 62 63 /* DMA control registers */ 64 uint32_t auc_dma_control; 65 66 /* FIFOs */ 67 int auc_fifo_size; 68 int auc_wt_fifos; 69 uint32_t auc_wt_fifo_base; 70 uint32_t auc_wt_fifo_ctl; 71 uint32_t auc_wt_dma_ctl; 72 int auc_adb_fifos; 73 uint32_t auc_adb_fifo_base; 74 uint32_t auc_adb_fifo_ctl; 75 uint32_t auc_adb_dma_ctl; 76 77 /* Routing */ 78 uint32_t auc_adb_route_base; 79 int auc_adb_route_bits; 80 int auc_adb_codec_in; 81 int auc_adb_codec_out; 82 }; 83 84 /* 85 * Channel information 86 */ 87 struct au88x0_chan_info { 88 struct au88x0_info *auci_aui; 89 struct pcm_channel *auci_pcmchan; 90 struct snd_dbuf *auci_buf; 91 int auci_dir; 92 }; 93 94 /* 95 * Device information 96 */ 97 struct au88x0_info { 98 /* the device we're associated with */ 99 device_t aui_dev; 100 uint32_t aui_model; 101 struct au88x0_chipset *aui_chipset; 102 103 /* parameters */ 104 bus_size_t aui_bufsize; 105 int aui_wt_fifos; 106 int aui_wt_fifo_ctl; 107 int aui_adb_fifos; 108 int aui_adb_fifo_ctl; 109 int aui_fifo_size; 110 uint32_t aui_chanbase; 111 112 /* bus_space tag and handle */ 113 bus_space_tag_t aui_spct; 114 bus_space_handle_t aui_spch; 115 116 /* register space */ 117 int aui_regtype; 118 int aui_regid; 119 struct resource *aui_reg; 120 121 /* irq */ 122 int aui_irqtype; 123 int aui_irqid; 124 struct resource *aui_irq; 125 void *aui_irqh; 126 127 /* dma */ 128 bus_dma_tag_t aui_dmat; 129 130 /* codec */ 131 struct ac97_info *aui_ac97i; 132 133 /* channels */ 134 struct au88x0_chan_info aui_chan[2]; 135 }; 136 137 /* 138 * Common parameters 139 */ 140 #define AU88X0_SETTLE_DELAY 1000 141 #define AU88X0_RETRY_COUNT 10 142 #define AU88X0_BUFSIZE_MIN 0x1000 143 #define AU88X0_BUFSIZE_DFLT 0x4000 144 #define AU88X0_BUFSIZE_MAX 0x4000 145 146 /* 147 * Codec control registers 148 * 149 * AU88X0_CODEC_CHANNEL array of 32 32-bit words 150 * 151 * AU88X0_CODEC_CONTROL control register 152 * 153 * bit 16 ready 154 * 155 * AU88X0_CODEC_IO I/O register 156 * 157 * bits 0-15 contents of codec register 158 * bits 16-22 address of codec register 159 * bit 23 0 for read, 1 for write 160 */ 161 #define AU88X0_CODEC_CHANNEL 0x29080 162 #define AU88X0_CODEC_CONTROL 0x29184 163 #define AU88X0_CDCTL_WROK 0x00000100 164 #define AU88X0_CODEC_IO 0x29188 165 #define AU88X0_CDIO_DATA_SHIFT 0 166 #define AU88X0_CDIO_DATA_MASK 0x0000ffff 167 #define AU88X0_CDIO_ADDR_SHIFT 16 168 #define AU88X0_CDIO_ADDR_MASK 0x007f0000 169 #define AU88X0_CDIO_RDBIT 0x00000000 170 #define AU88X0_CDIO_WRBIT 0x00800000 171 #define AU88X0_CDIO_READ(a) (AU88X0_CDIO_RDBIT | \ 172 (((a) << AU88X0_CDIO_ADDR_SHIFT) & AU88X0_CDIO_ADDR_MASK)) 173 #define AU88X0_CDIO_WRITE(a, d) (AU88X0_CDIO_WRBIT | \ 174 (((a) << AU88X0_CDIO_ADDR_SHIFT) & AU88X0_CDIO_ADDR_MASK) | \ 175 (((d) << AU88X0_CDIO_DATA_SHIFT) & AU88X0_CDIO_DATA_MASK)) 176 #define AU88X0_CODEC_ENABLE 0x29190 177 178 #endif
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